From 96a170f49a937d2091c7afbc8c926e58b584db06 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 13 Nov 2024 09:15:58 +0100 Subject: [PATCH] chore: update to STM32CubeCLT version 1.16.0 Signed-off-by: Frederic Pillon --- svd/STM32C0xx/STM32C071.svd | 67357 ++++++++++++++++++++ svd/STM32CubeCLT.version | 2 +- svd/STM32G0xx/STM32G030.svd | 49 +- svd/STM32G0xx/STM32G031.svd | 4 +- svd/STM32G0xx/STM32G041.svd | 4 +- svd/STM32G0xx/STM32G050.svd | 49 +- svd/STM32G0xx/STM32G051.svd | 6 +- svd/STM32G0xx/STM32G061.svd | 4 +- svd/STM32G0xx/STM32G070.svd | 49 +- svd/STM32G0xx/STM32G071.svd | 4 +- svd/STM32G0xx/STM32G081.svd | 4 +- svd/STM32G0xx/STM32G0B0.svd | 51 +- svd/STM32G0xx/STM32G0B1.svd | 4 +- svd/STM32G0xx/STM32G0C1.svd | 4 +- svd/STM32G4xx/STM32G431.svd | 28 +- svd/STM32G4xx/STM32G441.svd | 28 +- svd/STM32G4xx/STM32G471.svd | 28 +- svd/STM32G4xx/STM32G473.svd | 28 +- svd/STM32G4xx/STM32G474.svd | 28 +- svd/STM32G4xx/STM32G483.svd | 28 +- svd/STM32G4xx/STM32G484.svd | 28 +- svd/STM32G4xx/STM32G491.svd | 28 +- svd/STM32G4xx/STM32G4A1.svd | 28 +- svd/STM32H7xx/STM32H723.svd | 153 +- svd/STM32H7xx/STM32H725.svd | 153 +- svd/STM32H7xx/STM32H730.svd | 153 +- svd/STM32H7xx/STM32H733.svd | 153 +- svd/STM32H7xx/STM32H735.svd | 153 +- svd/STM32H7xx/STM32H73x.svd | 404 +- svd/STM32H7xx/STM32H7A3.svd | 98 +- svd/STM32H7xx/STM32H7B0.svd | 98 +- svd/STM32H7xx/STM32H7B3.svd | 98 +- svd/STM32L4xx/STM32L412.svd | 4 +- svd/STM32L4xx/STM32L476.svd | 76 +- svd/STM32L4xx/STM32L496.svd | 76 +- svd/STM32L4xx/STM32L4x1.svd | 4 +- svd/STM32L4xx/STM32L4x2.svd | 4 +- svd/STM32L4xx/STM32L4x3.svd | 4 +- svd/STM32L4xx/STM32L4x5.svd | 18101 ++++-- svd/STM32L4xx/STM32L4x6.svd | 2413 +- svd/STM32U0xx/STM32U031.svd | 89540 ++++++++++++++++++++++++++ svd/STM32U0xx/STM32U073.svd | 97238 ++++++++++++++++++++++++++++ svd/STM32U0xx/STM32U083.svd | 98312 +++++++++++++++++++++++++++++ svd/STM32U0xx/STM32U0x.svd | 1583 + svd/STM32WBxx/STM32WB05.svd | 28044 ++++++++ svd/STM32WBxx/STM32WB06.svd | 32837 ++++++++++ svd/STM32WBxx/STM32WB07.svd | 32832 ++++++++++ svd/STM32WBxx/STM32WB09.svd | 28875 +++++++++ svd/STM32WLxx/STM32WL5x_CM0P.svd | 4 +- svd/STM32WLxx/STM32WL5x_CM4.svd | 6 +- svd/STM32WLxx/STM32WLE5_CM4.svd | 6004 +- 51 files changed, 494591 insertions(+), 10672 deletions(-) create mode 100644 svd/STM32C0xx/STM32C071.svd create mode 100644 svd/STM32U0xx/STM32U031.svd create mode 100644 svd/STM32U0xx/STM32U073.svd create mode 100644 svd/STM32U0xx/STM32U083.svd create mode 100644 svd/STM32U0xx/STM32U0x.svd create mode 100644 svd/STM32WBxx/STM32WB05.svd create mode 100644 svd/STM32WBxx/STM32WB06.svd create mode 100644 svd/STM32WBxx/STM32WB07.svd create mode 100644 svd/STM32WBxx/STM32WB09.svd diff --git a/svd/STM32C0xx/STM32C071.svd b/svd/STM32C0xx/STM32C071.svd new file mode 100644 index 0000000..2da88bf --- /dev/null +++ b/svd/STM32C0xx/STM32C071.svd @@ -0,0 +1,67357 @@ + + + + STM32C071 + 1.1 + STM32C071 + + CM0+ + r0p0 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x40012400 + + 0x0 + 0x30C + registers + + + ADC + ADC interrupt + 12 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready +This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. +It is cleared by software writing 1 to it. + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag +This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1 . + 1 + 1 + read-write + + + B_0x0 + Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag +This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. + 2 + 1 + read-write + + + B_0x0 + Channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Channel conversion complete + 0x1 + + + + + EOS + End of sequence flag +This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. + 3 + 1 + read-write + + + B_0x0 + Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Conversion sequence complete + 0x1 + + + + + OVR + ADC overrun +This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + AWD1 + Analog watchdog 1 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. + 7 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. + 8 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. + 9 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + EOCAL + End Of Calibration flag +This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. + 11 + 1 + read-write + + + B_0x0 + Calibration is not complete + 0x0 + + + B_0x1 + Calibration is complete + 0x1 + + + + + CCRDY + Channel Configuration Ready flag +This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. +Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. + 13 + 1 + read-write + + + B_0x0 + Channel configuration update not applied. + 0x0 + + + B_0x1 + Channel configuration update is applied. + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable +This bit is set and cleared by software to enable/disable the ADC Ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled. + 0x0 + + + B_0x1 + ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable +This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. + 0x1 + + + + + EOCIE + End of conversion interrupt enable +This bit is set and cleared by software to enable/disable the end of conversion interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled + 0x0 + + + B_0x1 + EOC interrupt enabled. An interrupt is generated when the EOC bit is set. + 0x1 + + + + + EOSIE + End of conversion sequence interrupt enable +This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. An interrupt is generated when the EOS bit is set. + 0x1 + + + + + OVRIE + Overrun interrupt enable +This bit is set and cleared by software to enable/disable the overrun interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + EOCALIE + End of calibration interrupt enable +This bit is set and cleared by software to enable/disable the end of calibration interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + End of calibration interrupt disabled + 0x0 + + + B_0x1 + End of calibration interrupt enabled + 0x1 + + + + + CCRDYIE + Channel Configuration Ready Interrupt enable +This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Channel configuration ready interrupt disabled + 0x0 + + + B_0x1 + Channel configuration ready interrupt enabled + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADEN + ADC enable command +This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. +It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. +Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0) + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command + 1 + 1 + read-write + + + B_0x0 + No ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. + 0x1 + + + + + ADSTART + ADC start conversion command +This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). +It is cleared by hardware: +In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. +In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. +In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. +Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). +Note: After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored. + 2 + 1 + read-write + + + B_0x0 + No ADC conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. + 0x1 + + + + + ADSTP + ADC stop conversion command + 4 + 1 + read-write + + + B_0x0 + No ADC stop conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. + 0x1 + + + + + ADVREGEN + ADC Voltage Regulator Enable +This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after t<sub>ADCVREG_STUP</sub>. +It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. +Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 28 + 1 + read-write + + + B_0x0 + ADC voltage regulator disabled + 0x0 + + + B_0x1 + ADC voltage regulator enabled + 0x1 + + + + + ADCAL + ADC calibration +This bit is set by software to start the calibration of the ADC. +It is cleared by hardware after calibration is complete. +Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0). +Note: The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing). + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. + 0x1 + + + + + + + ADC_CFGR1 + ADC_CFGR1 + ADC configuration register 1 + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable +This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section 16.6.5: Managing converted data using the DMA on page 325. + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration +This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. +For more details, refer to Section 16.6.5: Managing converted data using the DMA on page 325. + 1 + 1 + read-write + + + B_0x0 + DMA one shot mode selected + 0x0 + + + B_0x1 + DMA circular mode selected + 0x1 + + + + + SCANDIR + Scan sequence direction +This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Upward scan (from CHSEL0 to CHSEL22) + 0x0 + + + B_0x1 + Backward scan (from CHSEL22 to CHSEL0) + 0x1 + + + + + RES + Data resolution +These bits are written by software to select the resolution of the conversion. + 3 + 2 + read-write + + + B_0x0 + 12 bits + 0x0 + + + B_0x1 + 10 bits + 0x1 + + + B_0x2 + 8 bits + 0x2 + + + B_0x3 + 6 bits + 0x3 + + + + + ALIGN + Data alignment +This bit is set and cleared by software to select right or left alignment. Refer to Figure 43: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 323 + 5 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + EXTSEL + External trigger selection +These bits select the external event used to trigger the start of conversion (refer to Table 67: External triggers for details): + 6 + 3 + read-write + + + B_0x0 + TRG0 + 0x0 + + + B_0x1 + TRG1 + 0x1 + + + B_0x2 + TRG2 + 0x2 + + + B_0x3 + TRG3 + 0x3 + + + B_0x4 + TRG4 + 0x4 + + + B_0x5 + TRG5 + 0x5 + + + B_0x6 + TRG6 + 0x6 + + + B_0x7 + TRG7 + 0x7 + + + + + EXTEN + External trigger enable and polarity selection +These bits are set and cleared by software to select the external trigger polarity and enable the trigger. + 10 + 2 + read-write + + + B_0x0 + Hardware trigger detection disabled (conversions can be started by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + OVRMOD + Overrun management mode +This bit is set and cleared by software and configure the way data overruns are managed. + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / continuous conversion mode +This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + WAIT + Wait conversion mode +This bit is set and cleared by software to enable/disable wait conversion mode.<sup>.</sup> + 14 + 1 + read-write + + + B_0x0 + Wait conversion mode off + 0x0 + + + B_0x1 + Wait conversion mode on + 0x1 + + + + + AUTOFF + Auto-off mode +This bit is set and cleared by software to enable/disable auto-off mode.<sup>.</sup> + 15 + 1 + read-write + + + B_0x0 + Auto-off mode disabled + 0x0 + + + B_0x1 + Auto-off mode enabled + 0x1 + + + + + DISCEN + Discontinuous mode +This bit is set and cleared by software to enable/disable discontinuous mode. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode disabled + 0x0 + + + B_0x1 + Discontinuous mode enabled + 0x1 + + + + + CHSELRMOD + Mode selection of the ADC_CHSELR register +This bit is set and cleared by software to control the ADC_CHSELR feature: +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 21 + 1 + read-write + + + B_0x0 + Each bit of the ADC_CHSELR register enables an input + 0x0 + + + B_0x1 + ADC_CHSELR register is able to sequence up to 8 channels + 0x1 + + + + + AWD1SGL + Enable the watchdog on a single channel or on all channels +This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled + 0x0 + + + B_0x1 + Analog watchdog 1 enabled + 0x1 + + + + + AWD1CH + Analog watchdog channel selection +These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. +..... +Others: Reserved +Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. + 26 + 5 + read-write + + + B_0x0 + ADC analog input Channel 0 monitored by AWD + 0x0 + + + B_0x1 + ADC analog input Channel 1 monitored by AWD + 0x1 + + + B_0x16 + ADC analog input Channel 22 monitored by AWD + 0x16 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OVSE + Oversampler Enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 0 + 1 + read-write + + + B_0x0 + Oversampler disabled + 0x0 + + + B_0x1 + Oversampler enabled + 0x1 + + + + + OVSR + Oversampling ratio +This bit filed defines the number of oversampling ratio. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift +This bit is set and cleared by software. +Others: Reserved +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TOVS + Triggered Oversampling +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively after a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a trigger + 0x1 + + + + + LFTRIG + Low frequency trigger mode enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 29 + 1 + read-write + + + B_0x0 + Low Frequency Trigger Mode disabled + 0x0 + + + B_0x1 + Low Frequency Trigger Mode enabled + 0x1 + + + + + CKMODE + ADC clock mode +These bits are set and cleared by software to define how the analog ADC is clocked: +In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. +Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 30 + 2 + read-write + + + B_0x0 + ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) + 0x0 + + + B_0x1 + PCLK/2 (Synchronous clock mode) + 0x1 + + + B_0x2 + PCLK/4 (Synchronous clock mode) + 0x2 + + + B_0x3 + PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) + 0x3 + + + + + + + ADC_SMPR + ADC_SMPR + ADC sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMP1 + Sampling time selection 1 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMP2 + Sampling time selection 2 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 4 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMPSEL0 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 8 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL1 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 9 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL2 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 10 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL3 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 11 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL4 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 12 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL5 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 13 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL6 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 14 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL7 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 15 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL8 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 16 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL9 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 17 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL10 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 18 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL11 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 19 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL12 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 20 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL13 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 21 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL14 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 22 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL15 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 23 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL16 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 24 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL17 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 25 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL18 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 26 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL19 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 27 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL20 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 28 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL21 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 29 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL22 + Channel-x sampling time selection (x = 22 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: Refer to Section 16.3: ADC implementation for the maximum number of channels. + 30 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + + + ADC_AWD1TR + ADC_AWD1TR + ADC watchdog threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section 16.8: Analog window watchdogs on page 329. + 0 + 12 + read-write + + + HT1 + Analog watchdog 1 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section 16.8: Analog window watchdogs on page 329. + 16 + 12 + read-write + + + + + ADC_AWD2TR + ADC_AWD2TR + ADC watchdog threshold register + 0x24 + 0x20 + read-write + 0x0FFF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section 16.8: Analog window watchdogs on page 329. + 0 + 12 + read-write + + + HT2 + Analog watchdog 2 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section 16.8: Analog window watchdogs on page 329. + 16 + 12 + read-write + + + + + ADC_CHSELR + ADC_CHSELR + ADC channel selection register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CHSEL0 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 0 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL1 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 1 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL2 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL3 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 3 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL4 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 4 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL5 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 5 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL6 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 6 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL7 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 7 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL8 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 8 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL9 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 9 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL10 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 10 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL11 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 11 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL12 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 12 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL13 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 13 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL14 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 14 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL15 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 15 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL16 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 16 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL17 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 17 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL18 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 18 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL19 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 19 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL20 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 20 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL21 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 21 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL22 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 22 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + + + ADC_CHSELR_ALTERNATE1 + ADC_CHSELR_ALTERNATE1 + ADC channel selection register + ADC_CHSELR + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ1 + 1st conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 4 + read-write + + + SQ2 + 2nd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 4 + 4 + read-write + + + SQ3 + 3rd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 8 + 4 + read-write + + + SQ4 + 4th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 12 + 4 + read-write + + + SQ5 + 5th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 16 + 4 + read-write + + + SQ6 + 6th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 20 + 4 + read-write + + + SQ7 + 7th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 24 + 4 + read-write + + + SQ8 + 8th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +... +Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 28 + 4 + read-write + + + B_0x0 + CH0 + 0x0 + + + B_0x1 + CH1 + 0x1 + + + B_0xC + CH12 + 0xC + + + B_0xD + CH13 + 0xD + + + B_0xE + CH14 + 0xE + + + B_0xF + No channel selected (End of sequence) + 0xF + + + + + + + ADC_AWD3TR + ADC_AWD3TR + ADC watchdog threshold register + 0x2C + 0x20 + read-write + 0x0FFF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section 16.8: Analog window watchdogs on page 329. + 0 + 12 + read-write + + + HT3 + Analog watchdog 3 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section 16.8: Analog window watchdogs on page 329. + 16 + 12 + read-write + + + + + ADC_DR + ADC_DR + ADC data register + 0x40 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DATA + Converted data +These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 43: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 323. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AWD2CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH20 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 20 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH21 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 21 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH22 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC Analog Watchdog 3 Configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AWD3CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH20 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 20 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH21 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 21 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH22 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factor + 0xB4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CALFACT + Calibration factor +These bits are written by hardware or by software. +Once a calibration is complete, they are updated by hardware with the calibration factors. +Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new conversion is launched. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. +Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + 0 + 7 + read-write + + + + + ADC_CCR + ADC_CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESC + ADC prescaler +Set and cleared by software to select the frequency of the clock to the ADC. +Other: Reserved +Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + V<sub>REFINT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>REFINT</sub>. +Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + V<sub>REFINT</sub> disabled + 0x0 + + + B_0x1 + V<sub>REFINT</sub> enabled + 0x1 + + + + + TSEN + Temperature sensor enable +This bit is set and cleared by software to enable/disable the temperature sensor. +Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Temperature sensor disabled + 0x0 + + + B_0x1 + Temperature sensor enabled + 0x1 + + + + + + + + + CRC + CRC address block description + CRC + 0x40023000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + CRS + CRS address block description + CRS + 0x40006C00 + + 0x0 + 0x10 + registers + + + + CRS_CR + CRS_CR + CRS control register + 0x00 + 0x20 + read-write + 0x00004000 + 0xFFFFFFFF + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + B_0x0 + SYNC event OK (SYNCOKF) interrupt disabled + 0x0 + + + B_0x1 + SYNC event OK (SYNCOKF) interrupt enabled + 0x1 + + + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + B_0x0 + SYNC warning (SYNCWARNF) interrupt disabled + 0x0 + + + B_0x1 + SYNC warning (SYNCWARNF) interrupt enabled + 0x1 + + + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + B_0x0 + Synchronization or trimming error (ERRF) interrupt disabled + 0x0 + + + B_0x1 + Synchronization or trimming error (ERRF) interrupt enabled + 0x1 + + + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + B_0x0 + Expected SYNC (ESYNCF) interrupt disabled + 0x0 + + + B_0x1 + Expected SYNC (ESYNCF) interrupt enabled + 0x1 + + + + + CEN + Frequency error counter enable +This bit enables the oscillator clock for the frequency error counter. +When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + B_0x0 + Frequency error counter disabled + 0x0 + + + B_0x1 + Frequency error counter enabled + 0x1 + + + + + AUTOTRIMEN + Automatic trimming enable +This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section 7.4.4 for more details. + 6 + 1 + read-write + + + B_0x0 + Automatic trimming disabled, TRIM bits can be adjusted by the user. + 0x0 + + + B_0x1 + Automatic trimming enabled, TRIM bits are read-only and under hardware control. + 0x1 + + + + + SWSYNC + Generate software SYNC event +This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + A software SYNC event is generated. + 0x1 + + + + + TRIM + HSI48 oscillator smooth trimming +The default value of the HSI48 oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval. + 8 + 7 + read-write + + + + + CRS_CFGR + CRS_CFGR + CRS configuration register + 0x04 + 0x20 + read-write + 0x2022BB7F + 0xFFFFFFFF + + + RELOAD + Counter reload value +RELOAD is the value to be loaded in the frequency error counter with each SYNC event. +Refer to Section 7.4.3 for more details about counter behavior. + 0 + 16 + read-write + + + FELIM + Frequency error limit +FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 7.4.4 for more details about FECAP evaluation. + 16 + 8 + read-write + + + SYNCDIV + SYNC divider +These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + read-write + + + B_0x0 + SYNC not divided (default) + 0x0 + + + B_0x1 + SYNC divided by 2 + 0x1 + + + B_0x2 + SYNC divided by 4 + 0x2 + + + B_0x3 + SYNC divided by 8 + 0x3 + + + B_0x4 + SYNC divided by 16 + 0x4 + + + B_0x5 + SYNC divided by 32 + 0x5 + + + B_0x6 + SYNC divided by 64 + 0x6 + + + B_0x7 + SYNC divided by 128 + 0x7 + + + + + SYNCSRC + SYNC signal source selection +These bits are set and cleared by software to select the SYNC signal source (see Table 28): +Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF is not generated by the host. No SYNC signal is therefore provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs must be used as SYNC signal. + 28 + 2 + read-write + + + B_0x0 + crs_sync_in_1 selected as SYNC signal source + 0x0 + + + B_0x1 + crs_sync_in_2 selected as SYNC signal source + 0x1 + + + B_0x2 + crs_sync_in_3 selected as SYNC signal source + 0x2 + + + B_0x3 + crs_sync_in_4 selected as SYNC signal source + 0x3 + + + + + SYNCPOL + SYNC polarity selection +This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + read-write + + + B_0x0 + SYNC active on rising edge (default) + 0x0 + + + B_0x1 + SYNC active on falling edge + 0x1 + + + + + + + CRS_ISR + CRS_ISR + CRS interrupt and status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SYNCOKF + SYNC event OK flag +This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + read-only + + + B_0x0 + No SYNC event OK signaled + 0x0 + + + B_0x1 + SYNC event OK signaled + 0x1 + + + + + SYNCWARNF + SYNC warning flag +This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + read-only + + + B_0x0 + No SYNC warning signaled + 0x0 + + + B_0x1 + SYNC warning signaled + 0x1 + + + + + ERRF + Error flag +This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + read-only + + + B_0x0 + No synchronization or trimming error signaled + 0x0 + + + B_0x1 + Synchronization or trimming error signaled + 0x1 + + + + + ESYNCF + Expected SYNC flag +This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + read-only + + + B_0x0 + No expected SYNC signaled + 0x0 + + + B_0x1 + Expected SYNC signaled + 0x1 + + + + + SYNCERR + SYNC error +This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action has to be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + read-only + + + B_0x0 + No SYNC error signaled + 0x0 + + + B_0x1 + SYNC error signaled + 0x1 + + + + + SYNCMISS + SYNC missed +This flag is set by hardware when the frequency error counter reaches value FELIM * 128 and no SYNC is detected, meaning either that a SYNC pulse was missed, or the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, hence some other action must be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC), and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + read-only + + + B_0x0 + No SYNC missed error signaled + 0x0 + + + B_0x1 + SYNC missed error signaled + 0x1 + + + + + TRIMOVF + Trimming overflow or underflow +This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + read-only + + + B_0x0 + No trimming error signaled + 0x0 + + + B_0x1 + Trimming error signaled + 0x1 + + + + + FEDIR + Frequency error direction +FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + read-only + + + B_0x0 + Up-counting direction, the actual frequency is above the target + 0x0 + + + B_0x1 + Down-counting direction, the actual frequency is below the target + 0x1 + + + + + FECAP + Frequency error capture +FECAP is the frequency error counter value latched in the time of the last SYNC event. +Refer to Section 7.4.4 for more details about FECAP usage. + 16 + 16 + read-only + + + + + CRS_ICR + CRS_ICR + CRS interrupt flag clear register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNCOKC + SYNC event OK clear flag +Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + read-write + + + SYNCWARNC + SYNC warning clear flag +Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + read-write + + + ERRC + Error clear flag +Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + read-write + + + ESYNCC + Expected SYNC clear flag +Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + read-write + + + + + + + DBG + DBG address block description + DBG + 0x40015800 + + 0x0 + 0x10 + registers + + + + DBG_IDCODE + DBG_IDCODE + DBG device ID code register + 0x00 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + DEV_ID + Device identifier +This field indicates the device ID. Refer to Table 152. + 0 + 12 + read-only + + + REV_ID + Revision identifier +This field indicates the revision of the device. Refer to Table 152. + 16 + 16 + read-only + + + + + DBG_CR + DBG_CR + DBG configuration register + 0x00000004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_STOP + Debug Stop mode +Debug options in Stop mode. +Upon Stop mode exit, the software must re-establish the desired clock configuration. + 1 + 1 + read-write + + + B_0x0 + All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. + 0x0 + + + B_0x1 + FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events. + 0x1 + + + + + DBG_STANDBY + Debug Standby and Shutdown modes +Debug options in Standby or Shutdown mode. + 2 + 1 + read-write + + + B_0x0 + Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby) + 0x0 + + + B_0x1 + Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset. + 0x1 + + + + + + + DBG_APB_FZ1 + DBG_APB_FZ1 + DBG APB freeze register 1 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM2_STOP + Clocking of TIM2 counter when the core is halted +This bit enables/disables the clock to the counter of TIM2 when the core is halted: +This bit is only available on STM32C071xx. On the other devices, it is reserved. + 0 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_TIM3_STOP + Clocking of TIM3 counter when the core is halted +This bit enables/disables the clock to the counter of TIM3 when the core is halted: + 1 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_RTC_STOP + Clocking of RTC counter when the core is halted +This bit enables/disables the clock to the counter of RTC when the core is halted: + 10 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_WWDG_STOP + Clocking of WWDG counter when the core is halted +This bit enables/disables the clock to the counter of WWDG when the core is halted: + 11 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_IWDG_STOP + Clocking of IWDG counter when the core is halted +This bit enables/disables the clock to the counter of IWDG when the core is halted: + 12 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_I2C1_SMBUS_TIMEOUT + SMBUS timeout when core is halted + 21 + 1 + read-write + + + B_0x0 + Same behavior as in normal mode + 0x0 + + + B_0x1 + The SMBUS timeout is frozen + 0x1 + + + + + + + DBG_APB_FZ2 + DBG_APB_FZ2 + DBG APB freeze register 2 + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM1_STOP + Clocking of TIM1 counter when the core is halted +This bit enables/disables the clock to the counter of TIM1 when the core is halted: + 11 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_TIM14_STOP + Clocking of TIM14 counter when the core is halted +This bit enables/disables the clock to the counter of TIM14 when the core is halted: + 15 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_TIM16_STOP + Clocking of TIM16 counter when the core is halted +This bit enables/disables the clock to the counter of TIM16 when the core is halted: + 17 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + DBG_TIM17_STOP + Clocking of TIM17 counter when the core is halted +This bit enables/disables the clock to the counter of TIM17 when the core is halted: + 18 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + + + + + DMA + DMA register bank + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 channel 1 interrupt + 9 + + + DMA1_Channel2_3 + DMA1 channel 2 and 3 interrupts + 10 + + + + DMA_ISR + DMA_ISR + DMA interrupt status register + 0x00 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + GIF1 + Global interrupt flag for channel 1 + 0 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF1 + Transfer complete (TC) flag for channel 1 + 1 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF1 + Half transfer (HT) flag for channel 1 + 2 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF1 + Transfer error (TE) flag for channel 1 + 3 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF2 + Global interrupt flag for channel 2 + 4 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF2 + Transfer complete (TC) flag for channel 2 + 5 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF2 + Half transfer (HT) flag for channel 2 + 6 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF2 + Transfer error (TE) flag for channel 2 + 7 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF3 + Global interrupt flag for channel 3 + 8 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF3 + Transfer complete (TC) flag for channel 3 + 9 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF3 + Half transfer (HT) flag for channel 3 + 10 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF3 + Transfer error (TE) flag for channel 3 + 11 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF4 + global interrupt flag for channel 4 + 12 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF4 + Transfer complete (TC) flag for channel 4 + 13 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF4 + Half transfer (HT) flag for channel 4 + 14 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF4 + Transfer error (TE) flag for channel 4 + 15 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF5 + global interrupt flag for channel 5 + 16 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF5 + Transfer complete (TC) flag for channel 5 + 17 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF5 + Half transfer (HT) flag for channel 5 + 18 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF5 + Transfer error (TE) flag for channel 5 + 19 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + + + DMA_IFCR + DMA_IFCR + DMA interrupt flag clear register + 0x04 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CGIF1 + Global interrupt flag clear for channel 1 + 0 + 1 + write-only + + + CTCIF1 + Transfer complete flag clear for channel 1 + 1 + 1 + write-only + + + CHTIF1 + Half transfer flag clear for channel 1 + 2 + 1 + write-only + + + CTEIF1 + Transfer error flag clear for channel 1 + 3 + 1 + write-only + + + CGIF2 + Global interrupt flag clear for channel 2 + 4 + 1 + write-only + + + CTCIF2 + Transfer complete flag clear for channel 2 + 5 + 1 + write-only + + + CHTIF2 + Half transfer flag clear for channel 2 + 6 + 1 + write-only + + + CTEIF2 + Transfer error flag clear for channel 2 + 7 + 1 + write-only + + + CGIF3 + Global interrupt flag clear for channel 3 + 8 + 1 + write-only + + + CTCIF3 + Transfer complete flag clear for channel 3 + 9 + 1 + write-only + + + CHTIF3 + Half transfer flag clear for channel 3 + 10 + 1 + write-only + + + CTEIF3 + Transfer error flag clear for channel 3 + 11 + 1 + write-only + + + CGIF4 + Global interrupt flag clear for channel 4 + 12 + 1 + write-only + + + CTCIF4 + Transfer complete flag clear for channel 4 + 13 + 1 + write-only + + + CHTIF4 + Half transfer flag clear for channel 4 + 14 + 1 + write-only + + + CTEIF4 + Transfer error flag clear for channel 4 + 15 + 1 + write-only + + + CGIF5 + Global interrupt flag clear for channel 5 + 16 + 1 + write-only + + + CTCIF5 + Transfer complete flag clear for channel 5 + 17 + 1 + write-only + + + CHTIF5 + Half transfer flag clear for channel 5 + 18 + 1 + write-only + + + CTEIF5 + Transfer error flag clear for channel 5 + 19 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer (0 to 2<sup>16</sup> - 1) +This bitfield is updated by hardware when the channel is enabled: +It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. +It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). +It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). +If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA channel 1 peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA channel 1 memory address register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA channel 2 number of data to transfer register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer (0 to 2<sup>16</sup> - 1) +This bitfield is updated by hardware when the channel is enabled: +It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. +It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). +It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). +If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA channel 2 peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA channel 2 memory address register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer (0 to 2<sup>16</sup> - 1) +This bitfield is updated by hardware when the channel is enabled: +It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. +It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). +It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). +If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA channel 3 peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA channel 3 memory address register + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA channel 4 configuration register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer (0 to 2<sup>16</sup> - 1) +This bitfield is updated by hardware when the channel is enabled: +It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. +It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). +It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). +If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA channel 4 peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA channel 4 memory address register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA channel 5 configuration register + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer (0 to 2<sup>16</sup> - 1) +This bitfield is updated by hardware when the channel is enabled: +It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. +It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). +It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). +If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA channel 5 peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA channel 5 memory address register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x40020800 + + 0x0 + 0x148 + registers + + + DMAMUX_DMA1_Channel4_5 + DMAMUX and DMA1 channel 4 and 5 interrupts + 11 + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 6 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table 44: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 6 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table 44: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 6 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table 44: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 6 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table 44: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 6 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table 44: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x080 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SOF0 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 0 + 1 + read-only + + + SOF1 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 1 + 1 + read-only + + + SOF2 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 2 + 1 + read-only + + + SOF3 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 3 + 1 + read-only + + + SOF4 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 4 + 1 + read-only + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x084 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CSOF0 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 0 + 1 + write-only + + + CSOF1 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 1 + 1 + write-only + + + CSOF2 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 2 + 1 + write-only + + + CSOF3 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 3 + 1 + write-only + + + CSOF4 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 4 + 1 + write-only + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + OF0 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 0 + 1 + read-only + + + OF1 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 1 + 1 + read-only + + + OF2 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 2 + 1 + read-only + + + OF3 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 3 + 1 + read-only + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + COF0 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 0 + 1 + write-only + + + COF1 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 1 + 1 + write-only + + + COF2 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 2 + 1 + write-only + + + COF3 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 3 + 1 + write-only + + + + + + + EXTI + EXTI address block description + EXTI + 0x40021800 + + 0x0 + 0x98 + registers + + + PVM + VDDIO2 monitor interrupt (EXTI line 34) + 1 + + + EXTI0_1 + EXTI line 0 and 1 interrupt + 5 + + + EXTI2_3 + EXTI line 2 and 3 interrupt + 6 + + + EXTI4_15 + EXTI line 4 to 15 interrupt + 7 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register 1 + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable line x (x = 15 to 0) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Note: The configurable lines are edge triggered; no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register 1 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable line x (x = 15 to 0). +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register 1 + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI1 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI2 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI3 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI4 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI5 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI6 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI7 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI8 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI9 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI10 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI11 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI12 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI13 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI14 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI15 + Software rising edge event trigger on line x (x = 15 to 0) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register 1 + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + Rising edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register 1 + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + Falling edge event pending for configurable line x (x = 15 to 0) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_RTSR2 + EXTI_RTSR2 + EXTI rising trigger selection register 2 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RT34 + Rising trigger event configuration bit of configurable line 34 +Each bit enables/disables the rising edge trigger for the event and interrupt on the line 34. +This configurable line is edge triggered; no glitch must be generated on this inputs. +Note: If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_FTSR2 + EXTI_FTSR2 + EXTI falling trigger selection register 2 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FT34 + Falling trigger event configuration bit of configurable line 34. +Each bit enables/disables the falling edge trigger for the event and interrupt on the line 34. +The configurable lines are edge triggered; no glitch must be generated on these inputs. +Note: If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_SWIER2 + EXTI_SWIER2 + EXTI software interrupt event register 2 + 0x030 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWI34 + Software rising edge event trigger on line 34 +Setting of any bit by software triggers a rising edge event on the line 34, resulting in an interrupt, independently of EXTI_RTSR2 and EXTI_FTSR2 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + + + EXTI_RPR2 + EXTI_RPR2 + EXTI rising edge pending register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPIF34 + Rising edge event pending for configurable line 34 +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER2 register) on the line 34. Each bit is cleared by writing 1 into it. + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR2 + EXTI_FPR2 + EXTI falling edge pending register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FPIF34 + Falling edge event pending for configurable line 34 +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER2 register) on the line 34. Each bit is cleared by writing 1 into it. + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI0 GPIO port selection +These bits are written by software to select the source input for EXTI0 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[0] pin + 0x00 + + + B_0x01 + PB[0] pin + 0x01 + + + B_0x02 + PC[0] pin + 0x02 + + + B_0x03 + PD[0] pin + 0x03 + + + B_0x05 + PF[0] pin + 0x05 + + + + + EXTI1 + EXTI1 GPIO port selection +These bits are written by software to select the source input for EXTI1 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[1] pin + 0x00 + + + B_0x01 + PB[1] pin + 0x01 + + + B_0x02 + PC[1] pin + 0x02 + + + B_0x03 + PD[1] pin + 0x03 + + + B_0x05 + PF[1] pin + 0x05 + + + + + EXTI2 + EXTI2 GPIO port selection +These bits are written by software to select the source input for EXTI2 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[2] pin + 0x00 + + + B_0x01 + PB[2] pin + 0x01 + + + B_0x02 + PC[2] pin + 0x02 + + + B_0x03 + PD[2] pin + 0x03 + + + B_0x05 + PF[2] pin + 0x05 + + + + + EXTI3 + EXTI3 GPIO port selection +These bits are written by software to select the source input for EXTI3 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[3] pin + 0x00 + + + B_0x01 + PB[3] pin + 0x01 + + + B_0x02 + PC[3] pin + 0x02 + + + B_0x03 + PD[3] pin + 0x03 + + + B_0x05 + PF[3] pin + 0x05 + + + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI4 GPIO port selection +These bits are written by software to select the source input for EXTI4 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[4] pin + 0x00 + + + B_0x01 + PB[4] pin + 0x01 + + + B_0x02 + PC[4] pin + 0x02 + + + B_0x03 + PD[4] pin + 0x03 + + + B_0x05 + PF[4] pin + 0x05 + + + + + EXTI5 + EXTI5 GPIO port selection +These bits are written by software to select the source input for EXTI5 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[5] pin + 0x00 + + + B_0x01 + PB[5] pin + 0x01 + + + B_0x02 + PC[5] pin + 0x02 + + + B_0x03 + PD[5] pin + 0x03 + + + B_0x05 + PF[5] pin + 0x05 + + + + + EXTI6 + EXTI6 GPIO port selection +These bits are written by software to select the source input for EXTI6 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[6] pin + 0x00 + + + B_0x01 + PB[6] pin + 0x01 + + + B_0x02 + PC[6] pin + 0x02 + + + B_0x03 + PD[6] pin + 0x03 + + + B_0x05 + PF[6] pin + 0x05 + + + + + EXTI7 + EXTI7 GPIO port selection +These bits are written by software to select the source input for EXTI7 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[7] pin + 0x00 + + + B_0x01 + PB[7] pin + 0x01 + + + B_0x02 + PC[7] pin + 0x02 + + + B_0x03 + PD[7] pin + 0x03 + + + B_0x05 + PF[7] pin + 0x05 + + + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTI8 GPIO port selection +These bits are written by software to select the source input for EXTI8 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[8] pin + 0x00 + + + B_0x01 + PB[8] pin + 0x01 + + + B_0x02 + PC[8] pin + 0x02 + + + B_0x03 + PD[8] pin + 0x03 + + + B_0x05 + PF[8] pin + 0x05 + + + + + EXTI9 + EXTI9 GPIO port selection +These bits are written by software to select the source input for EXTI9 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[9] pin + 0x00 + + + B_0x01 + PB[9] pin + 0x01 + + + B_0x02 + PC[9] pin + 0x02 + + + B_0x03 + PD[9] pin + 0x03 + + + B_0x05 + PF[9] pin + 0x05 + + + + + EXTI10 + EXTI10 GPIO port selection +These bits are written by software to select the source input for EXTI10 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[10] pin + 0x00 + + + B_0x01 + PB[10] pin + 0x01 + + + B_0x02 + PC[10] pin + 0x02 + + + B_0x03 + PD[10] pin + 0x03 + + + B_0x05 + PF[10] pin + 0x05 + + + + + EXTI11 + EXTI11 GPIO port selection +These bits are written by software to select the source input for EXTI11 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[11] pin + 0x00 + + + B_0x01 + PB[11] pin + 0x01 + + + B_0x02 + PC[11] pin + 0x02 + + + B_0x03 + PD[11] pin + 0x03 + + + B_0x05 + PF[11] pin + 0x05 + + + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTI12 GPIO port selection +These bits are written by software to select the source input for EXTI12 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[12] pin + 0x00 + + + B_0x01 + PB[12] pin + 0x01 + + + B_0x02 + PC[12] pin + 0x02 + + + B_0x03 + PD[12] pin + 0x03 + + + B_0x05 + PF[12] pin + 0x05 + + + + + EXTI13 + EXTI13 GPIO port selection +These bits are written by software to select the source input for EXTI13 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[13] pin + 0x00 + + + B_0x01 + PB[13] pin + 0x01 + + + B_0x02 + PC[13] pin + 0x02 + + + B_0x03 + PD[13] pin + 0x03 + + + B_0x05 + PF[13] pin + 0x05 + + + + + EXTI14 + EXTI14 GPIO port selection +These bits are written by software to select the source input for EXTI14 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[14] pin + 0x00 + + + B_0x01 + PB[14] pin + 0x01 + + + B_0x02 + PC[14] pin + 0x02 + + + B_0x03 + PD[14] pin + 0x03 + + + B_0x05 + PF[14] pin + 0x05 + + + + + EXTI15 + EXTI15 GPIO port selection +These bits are written by software to select the source input for EXTI15 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[15] pin + 0x00 + + + B_0x01 + PB[15] pin + 0x01 + + + B_0x02 + PC[15] pin + 0x02 + + + B_0x03 + PD[15] pin + 0x03 + + + B_0x05 + PF[15] pin + 0x05 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wakeup with interrupt mask register 1 + 0x080 + 0x20 + read-write + 0xFFF80000 + 0xFFFFFFFF + + + IM0 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 0 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM1 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 1 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM2 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 2 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM3 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 3 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM4 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 4 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM5 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 5 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM6 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 6 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM7 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 7 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM8 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 8 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM9 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 9 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM10 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 10 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM11 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 11 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM12 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 12 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM13 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 13 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM14 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 14 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM15 + CPU wakeup with interrupt mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 15 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM19 + CPU wakeup with interrupt mask on line 19 +Setting/clearing this bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 19 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM23 + CPU wakeup with interrupt mask on line 23 +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 23 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM25 + CPU wakeup with interrupt mask on line 25 +Setting/clearing each bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 25 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM31 + CPU wakeup with interrupt mask on line 31 +Setting/clearing this bit unmasks/masks the CPU wakeup with interrupt, by an event on the corresponding line. + 31 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wakeup with event mask register + 0x084 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 0 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM1 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 1 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM2 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 2 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM3 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 3 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM4 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 4 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM5 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 5 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM6 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 6 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM7 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 7 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM8 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 8 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM9 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 9 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM10 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 10 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM11 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 11 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM12 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 12 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM13 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 13 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM14 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 14 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM15 + CPU wakeup with event generation mask on line x (x = 15 to 0) +Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 15 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM19 + CPU wakeup with event generation mask on line 19 +Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 19 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM23 + CPU wakeup with event generation mask on line 23 +Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 23 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM25 + CPU wakeup with event generation mask on line 25 +Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 25 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM31 + CPU wakeup with event generation mask on line 31 +Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the corresponding line. + 31 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + + + EXTI_IMR2 + EXTI_IMR2 + EXTI CPU wakeup with interrupt mask register 2 + 0x090 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IM34 + CPU wakeup with interrupt mask on line 34 +Setting/clearing the bit unmasks/masks the CPU wakeup with interrupt request from the line 34. + 2 + 1 + read-write + + + B_0x0 + wakeup with interrupt masked + 0x0 + + + B_0x1 + wakeup with interrupt unmasked + 0x1 + + + + + IM36 + CPU wake-up with interrupt mask on line 36 + + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unmasked + 0x1 + + + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wakeup with event mask register 2 + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EM34 + CPU wakeup with event generation mask on line 34 +Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the line 34. + 2 + 1 + read-write + + + B_0x0 + wakeup with event generation masked + 0x0 + + + B_0x1 + wakeup with event generation unmasked + 0x1 + + + + + EM36 + CPU wake-up with event generation mask on line 36 + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + + + FLASH + Spider_FLASH register block + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 3 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x000 + 0x20 + read-write + 0x40600 + 0xFFFEFFFF + + + LATENCY + Flash memory access latency +The value in this bitfield represents the number of CPU wait states when accessing the flash memory. +Other: Reserved +A new write into the bitfield becomes effective when it returns the same value upon read. + 0 + 3 + read-write + + + B_0x0 + Zero wait states + 0x0 + + + B_0x1 + One wait state + 0x1 + + + + + PRFTEN + CPU Prefetch enable + 8 + 1 + read-write + + + B_0x0 + CPU Prefetch disabled + 0x0 + + + B_0x1 + CPU Prefetch enabled + 0x1 + + + + + ICEN + CPU Instruction cache enable + 9 + 1 + read-write + + + B_0x0 + CPU Instruction cache is disabled + 0x0 + + + B_0x1 + CPU Instruction cache is enabled + 0x1 + + + + + ICRST + CPU Instruction cache reset +This bit can be written only when the instruction cache is disabled. + 11 + 1 + read-write + + + B_0x0 + CPU Instruction cache is not reset + 0x0 + + + B_0x1 + CPU Instruction cache is reset + 0x1 + + + + + EMPTY + Main flash memory area empty +This bit indicates whether the first location of the Main flash memory area was read as erased or as programmed during OBL. It is not affected by the system reset. Software may need to change this bit value after a flash memory program or erase operation. +The bit can be set and reset by software. + 16 + 1 + read-write + + + B_0x0 + Main flash memory area programmed + 0x0 + + + B_0x1 + Main flash memory area empty + 0x1 + + + + + DBG_SWEN + Debug access software enable +Software may use this bit to enable/disable the debugger read access. + 18 + 1 + read-write + + + B_0x0 + Debugger disabled + 0x0 + + + B_0x1 + Debugger enabled + 0x1 + + + + + + + FLASH_KEYR + FLASH_KEYR + FLASH key register + 0x008 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + FLASH key +The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: +KEY1: 0x4567 0123 +KEY2: 0xCDEF 89AB + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + Option byte key +The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: +KEY1: 0x0819 2A3B +KEY2: 0x4C5D 6E7F + 0 + 32 + write-only + + + + + FLASH_SR + FLASH_SR + FLASH status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFF0FFFF + + + EOP + End of operation +Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. +This bit is set only if the end of operation interrupts are enabled (EOPIE=1). +Cleared by writing 1. + 0 + 1 + read-write + + + OPERR + Operation error +Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. +This bit is set only if error interrupts are enabled (ERRIE=1). +Cleared by writing 1 . + 1 + 1 + read-write + + + PROGERR + Programming error +Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. +Cleared by writing 1. + 3 + 1 + read-write + + + WRPERR + Write protection error +Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. +Cleared by writing 1. + 4 + 1 + read-write + + + PGAERR + Programming alignment error +Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. +Cleared by writing 1. + 5 + 1 + read-write + + + SIZERR + Size error +Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). +Cleared by writing 1. + 6 + 1 + read-write + + + PGSERR + Programming sequence error +Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. +Cleared by writing 1. + 7 + 1 + read-write + + + MISSERR + Fast programming data miss error +In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. +Cleared by writing 1. + 8 + 1 + read-write + + + FASTERR + Fast programming error +Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. +Cleared by writing 1. + 9 + 1 + read-write + + + RDERR + PCROP read error +Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. +Cleared by writing 1. + 14 + 1 + read-write + + + OPTVERR + Option and Engineering bits loading validity error + 15 + 1 + read-write + + + BSY1 + Busy +This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. + 16 + 1 + read-only + + + CFGBSY + Programming or erase configuration busy. +This flag is set and reset by hardware. +For flash program operation, it is set when the first word is sent, and cleared after the second word is sent when the operation completes or ends with an error. +For flash erase operation, it is set when setting the STRT bit of the FLASH_CR register and cleared when the operation completes or ends with an error. +When set, a programming or erase operation is ongoing and the corresponding settings in the FLASH control register (FLASH_CR) are used (busy) and cannot be changed. Any other flash operation launch must be postponed. +When cleared, the programming and erase settings in the FLASH control register (FLASH_CR) can be modified. +Note: The CFGBSY bit is also set when attempting to write locked flash memory (with the first byte sent). When the CFGBSY bit is set, writing into the FLASH_CR register causes HardFault.To clear the CFGBSY bit, send a double word to the flash memory and wait until the access is finished (otherwise the CFGBSY bit remains set). + 18 + 1 + read-only + + + + + FLASH_CR + FLASH_CR + FLASH control register + 0x014 + 0x20 + read-write + 0xC0000000 + 0xFFFFFFFF + + + PG + Flash memory programming enable + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PER + Page erase enable + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MER1 + Mass erase +When set, this bit triggers the mass erase, that is, all user pages. + 2 + 1 + read-write + + + PNB + Page number selection +These bits select the page to erase: +... +Note: Values corresponding to addresses outside the Main memory are not allowed. See Table 6 and Table 7. + 3 + 6 + read-write + + + B_0x00 + page 0 + 0x00 + + + B_0x01 + page 1 + 0x01 + + + B_0x3F + page 63 + 0x3F + + + + + STRT + Start erase operation +This bit triggers an erase operation when set. +This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. + 16 + 1 + read-write + + + OPTSTRT + Start of modification of option bytes +This bit triggers an options operation when set. +This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. + 17 + 1 + read-write + + + FSTPG + Fast programming enable + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + EOPIE + End-of-operation interrupt enable +This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ERRIE + Error interrupt enable +This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RDERRIE + PCROP read error interrupt enable +This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OBL_LAUNCH + Option byte load launch +When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. +The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. + 27 + 1 + read-write + + + SEC_PROT + Securable memory area protection enable +This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. +This bit is possible to set only by software and to clear only through a system reset. + 28 + 1 + read-write + + + B_0x0 + Disable (securable area accessible) + 0x0 + + + B_0x1 + Enable (securable area not accessible) + 0x1 + + + + + OPTLOCK + Options Lock +This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. +In case of an unsuccessful unlock operation, this bit remains set until the next reset. + 30 + 1 + read-write + + + LOCK + FLASH_CR Lock +This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. +In case of an unsuccessful unlock operation, this bit remains set until the next system reset. + 31 + 1 + read-write + + + + + FLASH_OPTR + FLASH_OPTR + FLASH option register + 0x020 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + RDP + Read protection level +Other: Level 1, memories read protection active + 0 + 8 + read-write + + + B_0xAA + Level 0, read protection not active + 0xAA + + + B_0xCC + Level 2, chip read protection active + 0xCC + + + + + BOR_EN + Brown out reset enable + 8 + 1 + read-write + + + B_0x0 + Configurable brown out reset disabled, power-on reset defined by POR/PDR levels + 0x0 + + + B_0x1 + Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account + 0x1 + + + + + BORR_LEV + BOR threshold at rising V<sub>DD</sub> supply +Rising V<sub>DD</sub> crossings this threshold releases the reset signal. + 9 + 2 + read-write + + + B_0x0 + BOR rising level 1 with threshold around 2.1 V + 0x0 + + + B_0x1 + BOR rising level 2 with threshold around 2.3 V + 0x1 + + + B_0x2 + BOR rising level 3 with threshold around 2.6 V + 0x2 + + + B_0x3 + BOR rising level 4 with threshold around 2.9 V + 0x3 + + + + + BORF_LEV + BOR threshold at falling V<sub>DD</sub> supply +Falling V<sub>DD</sub> crossings this threshold activates the reset signal. + 11 + 2 + read-write + + + B_0x0 + BOR falling level 1 with threshold around 2.0 V + 0x0 + + + B_0x1 + BOR falling level 2 with threshold around 2.2 V + 0x1 + + + B_0x2 + BOR falling level 3 with threshold around 2.5 V + 0x2 + + + B_0x3 + BOR falling level 4 with threshold around 2.8 V + 0x3 + + + + + nRST_STOP + None + 13 + 1 + read-write + + + nRST_STDBY + None + 14 + 1 + read-write + + + nRST_SHDW + None + 15 + 1 + read-write + + + IWDG_SW + None + 16 + 1 + read-write + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Stop mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Stop mode + 0x1 + + + + + IWGD_STDBY + None + 18 + 1 + read-write + + + WWDG_SW + Window watchdog selection + 19 + 1 + read-write + + + B_0x0 + Hardware window watchdog + 0x0 + + + B_0x1 + Software window watchdog + 0x1 + + + + + HSE_NOT_REMAPPED + HSE remapping enable/disable +When cleared, the bit remaps the HSE clock source from PF0-OSC_IN/PF1-OSC_OUT pins to PC14-OSCX_IN/PC15-OSCX_OUT. Thus PC14-OSCX_IN/PC15-OSCX_OUT are shared by both LSE and HSE and the two clock sources cannot be use simultaneously. +On packages with less than 48 pins, the remapping is always enabled (PF0-OSC_IN/PF1-OSC_OUT are not available), regardless of this bit. As all STM32C011xx packages have less than 48 pins, this bit is only applicable to STM32C031xx. +Note: On 48 pins packages, when HSE_NOT_REMAPPED is reset, HSE cannot be used in bypass mode. Refer to product errata sheet for more details. + 21 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + RAM_PARITY_CHECK + SRAM parity check control enable/disable + 22 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + SECURE_MUXING_EN + Multiple-bonding security +The bit allows enabling automatic I/O configuration to prevent conflicts on I/Os connected (bonded) onto the same pin. +If the software sets one of the I/Os connected to the same pin as active by configuring the SYSCFG_CFGR3 register, enabling this bit automatically forces the other I/Os in digital input mode, regardless of their software configuration. +When the bit is disabled, the SYSCFG_CFGR3 register setting is ignored, all GPIOs linked to a given pin are active and can be set in the mode specified by the corresponding GPIOx_MODER register. The user software must ensure that there is no conflict between GPIOs. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + nBOOT_SEL + BOOT0 signal source selection +This option bit defines the source of the BOOT0 signal. + 24 + 1 + read-write + + + B_0x0 + BOOT0 pin (legacy mode) + 0x0 + + + B_0x1 + nBOOT0 option bit + 0x1 + + + + + nBOOT1 + Boot configuration +Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit configuration), this bit selects boot mode from the Main flash memory, SRAM or the System memory. Refer to Section 3: Boot configuration. + 25 + 1 + read-write + + + nBOOT0 + nBOOT0 option bit + 26 + 1 + read-write + + + B_0x0 + nBOOT0 = 0 + 0x0 + + + B_0x1 + nBOOT0 = 1 + 0x1 + + + + + NRST_MODE + NRST pin configuration + 27 + 2 + read-write + + + B_0x1 + Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. + 0x1 + + + B_0x2 + Standard GPIO: only internal RESET is possible + 0x2 + + + B_0x3 + Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode + 0x3 + + + + + IRHEN + Internal reset holder enable bit + 29 + 1 + read-write + + + B_0x0 + Internal resets are propagated as simple pulse on NRST pin + 0x0 + + + B_0x1 + Internal resets drives NRST pin low until it is seen as low level + 0x1 + + + + + + + FLASH_PCROP1ASR + FLASH_PCROP1ASR + FLASH PCROP area A start address register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFF00 + + + PCROP1A_STRT + PCROP1A area start offset +Contains the offset of the first subpage of the PCROP1A area. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 8 + read-write + + + + + FLASH_PCROP1AER + FLASH_PCROP1AER + FLASH PCROP area A end address register + 0x028 + 0x20 + read-write + 0x0 + 0x7FFFFF00 + + + PCROP1A_END + PCROP1A area end offset +Contains the offset of the last subpage of the PCROP1A area. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 8 + read-write + + + PCROP_RDP + PCROP area erase upon RDP level regression +This bit determines whether the PCROP area (and the totality of the PCROP area boundary pages) is erased by the mass erase triggered by the RDP level regression from Level 1 to Level 0: +The software can only set this bit. It is automatically reset upon mass erase following the RDP regression from Level 1 to Level 0. + 31 + 1 + read-write + + + B_0x0 + Not erased + 0x0 + + + B_0x1 + Erased + 0x1 + + + + + + + FLASH_WRP1AR + FLASH_WRP1AR + FLASH WRP area A address register + 0x02C + 0x20 + read-write + 0x0 + 0xFFC0FFC0 + + + WRP1A_STRT + WRP area A start offset +This bitfield contains the offset of the first page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 6 + read-write + + + WRP1A_END + WRP area A end offset +This bitfield contains the offset of the last page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 6 + read-write + + + + + FLASH_WRP1BR + FLASH_WRP1BR + FLASH WRP area B address register + 0x030 + 0x20 + read-write + 0x0 + 0xFFC0FFC0 + + + WRP1B_STRT + WRP area B start offset +This bitfield contains the offset of the first page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 6 + read-write + + + WRP1B_END + WRP area B end offset +This bitfield contains the offset of the last page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 6 + read-write + + + + + FLASH_PCROP1BSR + FLASH_PCROP1BSR + FLASH PCROP area B start address register + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFF00 + + + PCROP1B_STRT + PCROP1B area start offset +Contains the offset of the first subpage of the PCROP1B area. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 8 + read-write + + + + + FLASH_PCROP1BER + FLASH_PCROP1BER + FLASH PCROP area B end address register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFF00 + + + PCROP1B_END + PCROP1B area end offset +Contains the offset of the last subpage of the PCROP1B area. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 8 + read-write + + + + + FLASH_SECR + FLASH_SECR + FLASH security register + 0x080 + 0x20 + read-write + 0x0 + 0xFFFEFF00 + + + SEC_SIZE + Securable memory area size +Contains the number of securable flash memory pages. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 6 + read-write + + + BOOT_LOCK + used to force boot from user area +If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). + 16 + 1 + read-write + + + B_0x0 + Boot based on the pad/option bit configuration + 0x0 + + + B_0x1 + Boot forced from Main flash memory + 0x1 + + + + + + + + + GPIOA + GPIOA address block description + GPIOA + 0x50000000 + + 0x0 + 0x2C + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 0 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE1 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 2 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE2 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 4 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE3 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 6 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE4 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 8 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE5 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 10 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE6 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 12 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE7 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 14 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE8 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 16 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE9 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 18 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE10 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 20 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE11 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 22 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE12 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 24 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE13 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 26 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE14 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 28 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE15 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 30 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 0 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 2 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 4 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 6 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 8 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 10 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 12 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 14 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 16 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 18 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 20 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 22 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 24 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 26 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 28 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 30 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 0 + 1 + read-write + + + OD1 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 1 + 1 + read-write + + + OD2 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 2 + 1 + read-write + + + OD3 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 3 + 1 + read-write + + + OD4 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 4 + 1 + read-write + + + OD5 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 5 + 1 + read-write + + + OD6 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 6 + 1 + read-write + + + OD7 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 7 + 1 + read-write + + + OD8 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 8 + 1 + read-write + + + OD9 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 9 + 1 + read-write + + + OD10 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 10 + 1 + read-write + + + OD11 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 11 + 1 + read-write + + + OD12 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 12 + 1 + read-write + + + OD13 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 13 + 1 + read-write + + + OD14 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 14 + 1 + read-write + + + OD15 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOB + GPIOB address block description + GPIOB + 0x50000400 + + 0x0 + 0x2C + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 0 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE1 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 2 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE2 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 4 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE3 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 6 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE4 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 8 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE5 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 10 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE6 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 12 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE7 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 14 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE8 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 16 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE9 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 18 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE10 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 20 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE11 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 22 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE12 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 24 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE13 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 26 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE14 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 28 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE15 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 30 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 0 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 2 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 4 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 6 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 8 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 10 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 12 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 14 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 16 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 18 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 20 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 22 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 24 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 26 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 28 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 30 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 0 + 1 + read-write + + + OD1 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 1 + 1 + read-write + + + OD2 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 2 + 1 + read-write + + + OD3 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 3 + 1 + read-write + + + OD4 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 4 + 1 + read-write + + + OD5 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 5 + 1 + read-write + + + OD6 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 6 + 1 + read-write + + + OD7 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 7 + 1 + read-write + + + OD8 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 8 + 1 + read-write + + + OD9 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 9 + 1 + read-write + + + OD10 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 10 + 1 + read-write + + + OD11 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 11 + 1 + read-write + + + OD12 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 12 + 1 + read-write + + + OD13 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 13 + 1 + read-write + + + OD14 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 14 + 1 + read-write + + + OD15 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 15 + 1 + read-write + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOB_LCKR + GPIOB_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOC + GPIOC address block description + GPIOC + 0x50000800 + + 0x0 + 0x2C + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 0 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE1 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 2 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE2 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 4 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE3 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 6 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE4 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 8 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE5 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 10 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE6 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 12 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE7 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 14 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE8 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 16 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE9 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 18 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE10 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 20 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE11 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 22 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE12 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 24 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE13 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 26 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE14 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 28 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE15 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 30 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 0 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 2 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 4 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 6 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 8 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 10 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 12 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 14 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 16 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 18 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 20 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 22 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 24 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 26 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 28 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 30 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 0 + 1 + read-write + + + OD1 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 1 + 1 + read-write + + + OD2 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 2 + 1 + read-write + + + OD3 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 3 + 1 + read-write + + + OD4 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 4 + 1 + read-write + + + OD5 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 5 + 1 + read-write + + + OD6 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 6 + 1 + read-write + + + OD7 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 7 + 1 + read-write + + + OD8 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 8 + 1 + read-write + + + OD9 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 9 + 1 + read-write + + + OD10 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 10 + 1 + read-write + + + OD11 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 11 + 1 + read-write + + + OD12 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 12 + 1 + read-write + + + OD13 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 13 + 1 + read-write + + + OD14 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 14 + 1 + read-write + + + OD15 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 15 + 1 + read-write + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOC_LCKR + GPIOC_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOD + GPIOD address block description + GPIOD + 0x50000C00 + + 0x0 + 0x2C + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 0 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE1 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 2 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE2 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 4 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE3 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 6 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE4 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 8 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE5 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 10 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE6 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 12 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE7 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 14 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE8 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 16 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE9 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 18 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE10 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 20 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE11 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 22 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE12 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 24 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE13 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 26 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE14 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 28 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE15 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 30 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 0 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 2 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 4 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 6 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 8 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 10 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 12 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 14 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 16 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 18 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 20 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 22 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 24 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 26 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 28 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 30 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 0 + 1 + read-write + + + OD1 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 1 + 1 + read-write + + + OD2 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 2 + 1 + read-write + + + OD3 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 3 + 1 + read-write + + + OD4 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 4 + 1 + read-write + + + OD5 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 5 + 1 + read-write + + + OD6 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 6 + 1 + read-write + + + OD7 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 7 + 1 + read-write + + + OD8 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 8 + 1 + read-write + + + OD9 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 9 + 1 + read-write + + + OD10 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 10 + 1 + read-write + + + OD11 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 11 + 1 + read-write + + + OD12 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 12 + 1 + read-write + + + OD13 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 13 + 1 + read-write + + + OD14 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 14 + 1 + read-write + + + OD15 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 15 + 1 + read-write + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOD_LCKR + GPIOD_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOF + GPIOF address block description + GPIOF + 0x50001400 + + 0x0 + 0x2C + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 0 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE1 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 2 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE2 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 4 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE3 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 6 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE4 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 8 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE5 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 10 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE6 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 12 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE7 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 14 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE8 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 16 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE9 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 18 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE10 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 20 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE11 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 22 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE12 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 24 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE13 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 26 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE14 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 28 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + MODE15 + Port x configuration for I/O y +These bits are written by software to set the I/O to one of four operating modes. + 30 + 2 + read-write + + + B_0x0 + Input + 0x0 + + + B_0x1 + Output + 0x1 + + + B_0x2 + Alternate function + 0x2 + + + B_0x3 + Analog + 0x3 + + + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 0 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 2 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 4 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 6 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 8 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 10 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 12 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 14 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 16 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 18 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 20 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 22 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 24 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 26 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 28 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration for I/O y +These bits are written by software to configure the I/O output speed. +Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. +Note: The FT_c GPIOs cannot be set to high speed. + 30 + 2 + read-write + + + B_0x0 + Very low speed + 0x0 + + + B_0x1 + Low speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O y +These bits are written by software to configure the I/O pull-up or pull-down +Note: On the same pin, this pull up/down must not be activated when a pull down/up is set through the PWR_PDCRx/PWR_PUCRx registers. + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 0 + 1 + read-write + + + OD1 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 1 + 1 + read-write + + + OD2 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 2 + 1 + read-write + + + OD3 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 3 + 1 + read-write + + + OD4 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 4 + 1 + read-write + + + OD5 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 5 + 1 + read-write + + + OD6 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 6 + 1 + read-write + + + OD7 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 7 + 1 + read-write + + + OD8 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 8 + 1 + read-write + + + OD9 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 9 + 1 + read-write + + + OD10 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 10 + 1 + read-write + + + OD11 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 11 + 1 + read-write + + + OD12 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 12 + 1 + read-write + + + OD13 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 13 + 1 + read-write + + + OD14 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 14 + 1 + read-write + + + OD15 + Port output data I/O y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F). + 15 + 1 + read-write + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOF_LCKR + GPIOF_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x pin y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x, I/O y +These bits are written by software to configure alternate function I/Os + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O y +These bits are write-only. A read operation always returns 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + IWDG + IWDG address block description + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG key register + 0x00 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Key value (write only, read 0x0000) +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 22.3.4: Register access protection) +Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected) + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG prescaler register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PR + Prescaler divider +These bits are write access protected see Section 22.3.4: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset in order to be able to change the prescaler divider. +Note: Reading this register returns the prescaler value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 3 + read-write + + + B_0x0 + divider /4 + 0x0 + + + B_0x1 + divider /8 + 0x1 + + + B_0x2 + divider /16 + 0x2 + + + B_0x3 + divider /32 + 0x3 + + + B_0x4 + divider /64 + 0x4 + + + B_0x5 + divider /128 + 0x5 + + + B_0x6 + divider /256 + 0x6 + + + B_0x7 + divider /256 + 0x7 + + + + + + + IWDG_RLR + IWDG_RLR + IWDG reload register + 0x08 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + RL + Watchdog counter reload value +These bits are write access protected see Register access protection. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. +The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG status register + 0x0C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PVU + Watchdog prescaler value update +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the V<sub>DD</sub> voltage domain (takes up to five LSI cycles). +Prescaler value can be updated only when PVU bit is reset. + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to five LSI cycles). +Reload value can be updated only when RVU bit is reset. + 1 + 1 + read-only + + + WVU + Watchdog counter window value update +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to five LSI cycles). +Window value can be updated only when WVU bit is reset. + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG window register + 0x10 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + WIN + Watchdog counter window value +These bits are write access protected, see Section 22.3.4, they contain the high limit of the window value to be compared with the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG status register (IWDG_SR) must be reset in order to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + + + I2C1 + I2C address block description + I2C + 0x40005400 + + 0x0 + 0x2C + registers + + + I2C1 + I2C1 global interrupt (combined with EXTI 23) + 23 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + TXIE + TX interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: Any of these events generates an interrupt: +Note: Transfer complete (TC) +Note: Transfer complete reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer complete interrupt disabled + 0x0 + + + B_0x1 + Transfer complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generates an interrupt: +Note: Arbitration loss (ARLO) +Note: Bus error detection (BERR) +Note: Overrun/underrun (OVR) +Note: Timeout detection (TIMEOUT) +Note: PEC error detection (PECERR) +Note: Alert pin event detection (ALERT) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +... +Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to one t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to fifteen t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable +Note: If the wake-up from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. +Note: WUPEN can be set only when DNF = 0000. + 18 + 1 + read-write + + + B_0x0 + Wake-up from Stop mode disabled. + 0x0 + + + B_0x1 + Wake-up from Stop mode enabled. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus host address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 20 + 1 + read-write + + + B_0x0 + Host address disabled. Address 0b0001000x is NACKed. + 0x0 + + + B_0x1 + Host address enabled. Address 0b0001000x is ACKed. + 0x1 + + + + + SMBDEN + SMBus device default address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. Address 0b1100001x is NACKed. + 0x0 + + + B_0x1 + Device default address enabled. Address 0b1100001x is ACKed. + 0x1 + + + + + ALERTEN + SMBus alert enable +Note: When ALERTEN = 0, the SMBA pin can be used as a standard GPIO. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN = 1). In device mode (SMBHEN = 0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN = 1). In device mode (SMBHEN = 0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). + 0x1 + + + + + PECEN + PEC enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] must be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer + 0x0 + + + B_0x1 + Master requests a read transfer + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit address in write direction + restart + first seven bits of the 10-bit address in read direction. + 0x0 + + + B_0x1 + The master sends only the first seven bits of the 10-bit address, followed by read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer. +Otherwise, setting this bit generates a START condition once the bus is free. +Note: Writing 0 to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In master mode: +Note: Writing 0 to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation + 0x0 + + + B_0x1 + Stop generation after current byte transfer + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing 0 to this bit has no effect. +Note: This bit is used only in slave mode: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is don t care in slave mode with SBC = 0. +Note: Changing these bits when the START bit is set is not allowed. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. +Note: Writing 0 to this bit has no effect. +Note: This bit has no effect when RELOAD is set, and in slave mode when SBC = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 26 + 1 + read-write + + + B_0x0 + No PEC transfer + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN = 0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN = 0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN = 0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don t care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don t care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don t care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don t care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don t care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don t care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL + 1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH + 1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL</sub> = (SCLDEL + 1) x t<sub>PRESC</sub> between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings), and for SCL high and low level counters (refer to I2C master initialization). +t<sub>PRESC </sub>= (PRESC + 1) x t<sub>I2CCLK</sub> + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE = 0 +t<sub>TIMEOUT</sub>= (TIMEOUTA + 1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE = 1 +t<sub>IDLE</sub>= (TIMEOUTA + 1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN = 0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN = 0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled. hen SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE = 0) or high for more than t<sub>IDLE </sub>(TIDLE = 1), a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +Master mode: the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +Slave mode: the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT </sub>= (TIMEOUTB + TIDLE = 01) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN = 0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +as a master, provided that the STOP condition is generated by the peripheral. +as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer complete (master mode) +This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer complete reload +This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting the BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + PECERR + PEC error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 11 + 1 + read-only + + + TIMEOUT + Timeout or t<sub>LOW</sub> detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1 and an SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Note: Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + I2C2 + 0x40005800 + + I2C2 + I2C2 global interrupt + 24 + + + + PWR + PWR address block description + PWR + 0x40007000 + + 0x0 + 0x80 + registers + + + + PWR_CR1 + PWR_CR1 + PWR control register 1 + 0x00 + 0x20 + read-write + 0x00000208 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when CPU enters deepsleep mode. +1XX: Shutdown mode + 0 + 3 + read-write + + + B_0x0 + Stop mode + 0x0 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + Flash memory powered down during Stop mode +This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. + 3 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_SLP + Flash memory powered down during Sleep mode +This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode. + 5 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + + + PWR_CR2 + PWR_CR2 + PWR control register 1 + 0x04 + 0x20 + read-write + 0x00000100 + 0xFFFFFFFF + + + PVM_VDDIO2 + supply voltage monitoring + 8 + 2 + read-write + + + B_0x0 + Monitoring disabled; IOs in isolation mode + 0x0 + + + B_0x1 + Monitoring enabled; IOs enabled or in isolation mode according to V<sub>DDIO2</sub> level + 0x1 + + + B_0x2 + Monitoring bypassed; IOs enabled + 0x2 + + + + + + + PWR_CR3 + PWR_CR3 + PWR control register 3 + 0x08 + 0x20 + read-write + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable WKUP1 wakeup pin +When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register. + 0 + 1 + read-write + + + EWUP2 + Enable WKUP2 wakeup pin +When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register. + 1 + 1 + read-write + + + EWUP3 + Enable WKUP3 wakeup pin +When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register. + 2 + 1 + read-write + + + EWUP4 + Enable WKUP4 wakeup pin +When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + 3 + 1 + read-write + + + EWUP5 + Enable WKUP5 wakeup pin +When this bit is set, the WKUP5 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured through WP5 bit in the PWR_CR4 register. + 4 + 1 + read-write + + + EWUP6 + Enable WKUP6 wakeup pin +When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register. + 5 + 1 + read-write + + + APC + Apply pull-up and pull-down configuration +This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. + 10 + 1 + read-write + + + B_0x0 + Not applied + 0x0 + + + B_0x1 + Applied + 0x1 + + + + + EIWUL + Enable internal wakeup line +When set, a rising edge on the internal wakeup line triggers a wakeup event. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + PWR control register 4 + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WP1 + WKUP1 wakeup pin polarity +WKUP1 external wakeup signal polarity (level or edge) to generate wakeup condition: + 0 + 1 + read-write + + + B_0x0 + High level or rising edge + 0x0 + + + B_0x1 + Low level or falling edge + 0x1 + + + + + WP2 + WKUP2 wakeup pin polarity +WKUP2 external wakeup signal polarity (level or edge) to generate wakeup condition: + 1 + 1 + read-write + + + B_0x0 + High level or rising edge + 0x0 + + + B_0x1 + Low level or falling edge + 0x1 + + + + + WP3 + WKUP3 wakeup pin polarity +WKUP3 external wakeup signal polarity (level or edge) to generate wakeup condition: + 2 + 1 + read-write + + + B_0x0 + High level or rising edge + 0x0 + + + B_0x1 + Low level or falling edge + 0x1 + + + + + WP4 + WKUP4 wakeup pin polarity +WKUP4 external wakeup signal polarity (level or edge) to generate wakeup condition: + 3 + 1 + read-write + + + B_0x0 + High level or rising edge + 0x0 + + + B_0x1 + Low level or falling edge + 0x1 + + + + + WP5 + WKUP5 wakeup pin polarity +WKUP5 external wakeup signal polarity (level or edge) to generate wakeup condition: + 4 + 1 + read-write + + + B_0x0 + High level or rising edge + 0x0 + + + B_0x1 + Low level or falling edge + 0x1 + + + + + WP6 + WKUP6 wakeup pin polarity +WKUP6 external wakeup signal polarity (level or edge) to generate wakeup condition: + 5 + 1 + read-write + + + B_0x0 + High level or rising edge + 0x0 + + + B_0x1 + Low level or falling edge + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + PWR status register 1 + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wakeup flag 1 +This bit is set when a wakeup condition is detected on WKUP1 wakeup pin. It is cleared by setting the CWUF1 bit of the PWR_SCR register. + 0 + 1 + read-only + + + WUF2 + Wakeup flag 2 +This bit is set when a wakeup condition is detected on WKUP2 wakeup pin. It is cleared by setting the CWUF2 bit of the PWR_SCR register. + 1 + 1 + read-only + + + WUF3 + Wakeup flag 3 +This bit is set when a wakeup condition is detected on WKUP3 wakeup pin. It is cleared by setting the CWUF3 bit of the PWR_SCR register. + 2 + 1 + read-only + + + WUF4 + Wakeup flag 4 +This bit is set when a wakeup condition is detected on WKUP4 wakeup pin. It is cleared by setting the CWUF4 bit of the PWR_SCR register. + 3 + 1 + read-only + + + WUF5 + Wakeup flag 5 +This bit is set when a wakeup condition is detected on WKUP5 wakeup pin. It is cleared by setting the CWUF5 bit of the PWR_SCR register. + 4 + 1 + read-only + + + WUF6 + Wakeup flag 6 +This bit is set when a wakeup condition is detected on WKUP6 wakeup pin. It is cleared by setting the CWUF6 bit of the PWR_SCR register. + 5 + 1 + read-only + + + SBF + Standby flag +This bit is set by hardware when the device enters Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 8 + 1 + read-only + + + B_0x0 + The device did not enter Standby mode + 0x0 + + + B_0x1 + The device entered Standby mode + 0x1 + + + + + WUFI + Wakeup flag internal +This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + PWR status register 2 + 0x14 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FLASH_RDY + Flash ready flag +This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. +Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory. + 7 + 1 + read-only + + + B_0x0 + Flash memory in power-down + 0x0 + + + B_0x1 + Flash memory ready to be accessed + 0x1 + + + + + PVM_VDDIO2_OUT + V<sub>DDIO2</sub> supply voltage monitoring output flag +This flag indicates the readiness of the V<sub>DDIO2</sub> supply voltage (excess of 1.2 V). +The flag is cleared when the PVM of V<sub>DDIO2</sub> is disabled (PVM_VDDIO2[0] = 0). +Note: Only applicable on STM32C071xx, reserved on the other products. + 13 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + + + PWR_SCR + PWR_SCR + PWR status clear register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wakeup flag 1 +Setting this bit clears the WUF1 flag in the PWR_SR1 register. + 0 + 1 + write-only + + + CWUF2 + Clear wakeup flag 2 +Setting this bit clears the WUF2 flag in the PWR_SR1 register. + 1 + 1 + write-only + + + CWUF3 + Clear wakeup flag 3 +Setting this bit clears the WUF3 flag in the PWR_SR1 register. + 2 + 1 + write-only + + + CWUF4 + Clear wakeup flag 4 +Setting this bit clears the WUF4 flag in the PWR_SR1 register. + 3 + 1 + write-only + + + CWUF5 + Clear wakeup flag 5 +Setting this bit clears the WUF5 flag in the PWR_SR1 register. + 4 + 1 + write-only + + + CWUF6 + Clear wakeup flag 6 +Setting this bit clears the WUF6 flag in the PWR_SR1 register. + 5 + 1 + write-only + + + CSBF + Clear standby flag +Setting this bit clears the SBF flag in the PWR_SR1 register. + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + PWR Port A pull-up control register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PU1 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PU2 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PU3 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PU4 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PU5 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PU6 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PU7 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 7 + 1 + read-write + + + PU8 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PU9 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + PU10 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 10 + 1 + read-write + + + PU11 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 11 + 1 + read-write + + + PU12 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 12 + 1 + read-write + + + PU13 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 13 + 1 + read-write + + + PU14 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 14 + 1 + read-write + + + PU15 + Port A pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + PWR Port A pull-down control register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PD1 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PD2 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PD3 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PD4 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PD5 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PD6 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PD7 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 7 + 1 + read-write + + + PD8 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PD9 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + PD10 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 10 + 1 + read-write + + + PD11 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 11 + 1 + read-write + + + PD12 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 12 + 1 + read-write + + + PD13 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 13 + 1 + read-write + + + PD14 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 14 + 1 + read-write + + + PD15 + Port A pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 15 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + PWR Port B pull-up control register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PU1 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PU2 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PU3 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PU4 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PU5 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PU6 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PU7 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 7 + 1 + read-write + + + PU8 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PU9 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + PU10 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 10 + 1 + read-write + + + PU11 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 11 + 1 + read-write + + + PU12 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 12 + 1 + read-write + + + PU13 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 13 + 1 + read-write + + + PU14 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 14 + 1 + read-write + + + PU15 + Port B pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. +On STM32C011xx, only PU7 and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + PWR Port B pull-down control register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PD1 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PD2 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PD3 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PD4 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PD5 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PD6 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PD7 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 7 + 1 + read-write + + + PD8 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PD9 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + PD10 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 10 + 1 + read-write + + + PD11 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 11 + 1 + read-write + + + PD12 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 12 + 1 + read-write + + + PD13 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 13 + 1 + read-write + + + PD14 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 14 + 1 + read-write + + + PD15 + Port B pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. +On STM32C011xx, only PD7 and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + PWR Port C pull-up control register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PU1 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PU2 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PU3 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PU4 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PU5 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PU6 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PU7 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 7 + 1 + read-write + + + PU8 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PU9 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + PU10 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 10 + 1 + read-write + + + PU11 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 11 + 1 + read-write + + + PU12 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 12 + 1 + read-write + + + PU13 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 13 + 1 + read-write + + + PU14 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 14 + 1 + read-write + + + PU15 + Port C pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. +On STM32C011xx, only PU15 and PU14 are available. On STM32C031xx, only PU15 to PU13, PU7, and PU6 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + PWR Port C pull-down control register + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PD1 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PD2 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PD3 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PD4 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PD5 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PD6 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PD7 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 7 + 1 + read-write + + + PD8 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PD9 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + PD10 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 10 + 1 + read-write + + + PD11 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 11 + 1 + read-write + + + PD12 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 12 + 1 + read-write + + + PD13 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 13 + 1 + read-write + + + PD14 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 14 + 1 + read-write + + + PD15 + Port C pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. +On STM32C011xx, only PD15 and PD14 are available. On STM32C031xx, only PD15 to PD13, PD7, and PD6 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + PWR Port D pull-up control register + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PU1 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PU2 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PU3 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PU4 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PU5 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PU6 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PU3 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PU8 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Only available on STM32C071xx. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PU9 + Port D pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O. +Only available on STM32C071xx. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + PWR Port D pull-down control register + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PD1 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PD2 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PD3 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + PD4 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 4 + 1 + read-write + + + PD5 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 5 + 1 + read-write + + + PD6 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Not available on STM32C011xx. On STM32C031xx, only PD3 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 6 + 1 + read-write + + + PD8 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Only available on STM32C071xx. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 8 + 1 + read-write + + + PD9 + Port D pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O. +Only available on STM32C071xx. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 9 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + PWR Port F pull-up control register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. +On STM32C011xx, only PU2 is available. On STM32C031xx, only PU2 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PU1 + Port F pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. +On STM32C011xx, only PU2 is available. On STM32C031xx, only PU2 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PU2 + Port F pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. +On STM32C011xx, only PU2 is available. On STM32C031xx, only PU2 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PU3 + Port F pull-up bit i +Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. +On STM32C011xx, only PU2 is available. On STM32C031xx, only PU2 to PU0 are available. +Note: For the same pin, this pull-up device must not be activated when a pull-down device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + PWR Port F pull-down control register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. +On STM32C011xx, only PD2 is available. On STM32C031xx, only PD2 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 0 + 1 + read-write + + + PD1 + Port F pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. +On STM32C011xx, only PD2 is available. On STM32C031xx, only PD2 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 1 + 1 + read-write + + + PD2 + Port F pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. +On STM32C011xx, only PD2 is available. On STM32C031xx, only PD2 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 2 + 1 + read-write + + + PD3 + Port F pull-down bit i +Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. +On STM32C011xx, only PD2 is available. On STM32C031xx, only PD2 to PD0 are available. +Note: For the same pin, this pull-down device must not be activated when a pull-up device is set through the GPIOx_PUPDR register. + 3 + 1 + read-write + + + + + PWR_BKP0R + PWR_BKP0R + PWR backup 0 register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + Backup bitfield +This bitfield retains information when the device is in Standby. + 0 + 16 + read-write + + + + + PWR_BKP1R + PWR_BKP1R + PWR backup 1 register + 0x74 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + Backup bitfield +This bitfield retains information when the device is in Standby. + 0 + 16 + read-write + + + + + PWR_BKP2R + PWR_BKP2R + PWR backup 2 register + 0x78 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + Backup bitfield +This bitfield retains information when the device is in Standby. + 0 + 16 + read-write + + + + + PWR_BKP3R + PWR_BKP3R + PWR backup 3 register + 0x7C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + Backup bitfield +This bitfield retains information when the device is in Standby. + 0 + 16 + read-write + + + + + + + RCC + RCC address block description + RCC + 0x40021000 + + 0x0 + 0x64 + registers + + + RCC_CRS + RCC/CRS global interrupt + 4 + + + + RCC_CR + RCC_CR + RCC clock control register + 0x00 + 0x20 + read-write + 0x00001540 + 0xFFFFFFFF + + + SYSDIV + Clock division factor for system clock +Set and cleared by software. SYSCLK is result of the division by: +Note: This bitfield is only available on STM32C071xx. + 2 + 3 + read-write + + + B_0x0 + 1 (no division, reset value) + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + HSIKERDIV + HSI48 kernel clock division factor +This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock: + 5 + 3 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 (reset value) + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + HSION + HSI48 clock enable +Set and cleared by software and hardware, with hardware taking priority. +Kept low by hardware as long as the device is in a low-power mode. +Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSIKERON + HSI48 always-enable for peripheral kernels. +Set and cleared by software. +Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock. +Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode. + 9 + 1 + read-write + + + B_0x0 + HSI48 oscillator enable depends on the HSION bit + 0x0 + + + B_0x1 + HSI48 oscillator is active in Run and Stop modes + 0x1 + + + + + HSIRDY + HSI48 clock ready flag +Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable). +Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles. + 10 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + HSIDIV + HSI48 clock division factor +This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock: + 11 + 3 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 (reset value) + 0x2 + + + B_0x3 + 8 + 0x3 + + + B_0x4 + 16 + 0x4 + + + B_0x5 + 32 + 0x5 + + + B_0x6 + 64 + 0x6 + + + B_0x7 + 128 + 0x7 + + + + + HSEON + HSE clock enable +Set and cleared by software. +Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable and ready for use. +Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +Set and cleared by software. +When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + No bypass + 0x0 + + + B_0x1 + Bypass + 0x1 + + + + + CSSON + Clock security system enable +Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSIUSB48ON + HSIUSB48 clock enable +Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked from HSIUSB48. +Note: Only applicable on STM32C071xx, reserved on other devices. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSIUSB48RDY + HSIUSB48 clock ready flag +Set by hardware when the HSIUSB48 oscillator is enabled through HSIUSB48ON and ready to use (stable). +Note: Only applicable on STM32C071xx, reserved on other devices. + 23 + 1 + read-write + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + RCC internal clock source calibration register + 0x04 + 0x20 + read-write + 0x00004000 + 0xFFFFFF00 + + + HSICAL + HSI48 clock calibration +This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity. +Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64. + 0 + 8 + read-only + + + HSITRIM + HSI48 clock trimming +The value of this bitfield contributes to the HSICAL[7:0] bitfield value. +It allows HSI48 clock frequency user trimming. +The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value. + 8 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + RCC clock configuration register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SW + System clock switch +This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: +Others: Reserved +The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + 0 + 3 + read-write + + + B_0x0 + HSISYS + 0x0 + + + B_0x1 + HSE + 0x1 + + + B_0x3 + LSI + 0x3 + + + B_0x4 + LSE + 0x4 + + + + + SWS + System clock switch status +This bitfield is controlled by hardware to indicate the clock source used as system clock: +Others: Reserved + 3 + 3 + read-only + + + B_0x0 + HSISYS + 0x0 + + + B_0x1 + HSE + 0x1 + + + B_0x3 + LSI + 0x3 + + + B_0x4 + LSE + 0x4 + + + + + HPRE + AHB prescaler +This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: +0xxx: 1 + 8 + 4 + read-write + + + B_0x8 + 2 + 0x8 + + + B_0x9 + 4 + 0x9 + + + B_0xA + 8 + 0xA + + + B_0xB + 16 + 0xB + + + B_0xC + 64 + 0xC + + + B_0xD + 128 + 0xD + + + B_0xE + 256 + 0xE + + + B_0xF + 512 + 0xF + + + + + PPRE + APB prescaler +This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: +0xx: 1 + 12 + 3 + read-write + + + B_0x4 + 2 + 0x4 + + + B_0x5 + 4 + 0x5 + + + B_0x6 + 8 + 0x6 + + + B_0x7 + 16 + 0x7 + + + + + MCO2SEL + Microcontroller clock output 2 clock selector +This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: +Other: reserved, must not be used +Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. On STM32C011xx and STM32C031xx, MCOSEL[3] is reserved. + 16 + 4 + read-write + + + B_0x0 + no clock + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x3 + HSI48 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSIUSB48 + 0x8 + + + + + MCO2PRE + Microcontroller clock output 2 prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: +... +Other: Reserved +It is highly recommended to set this field before the MCO2 output is enabled. +Note: Values above 0111 are only significant for STM32C071xx. On STM32C011xx and STM32C031xx devices, MCOPRE[3] is reserved. + 20 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + MCOSEL + Microcontroller clock output clock selector +This bitfield is controlled by software. It sets the clock selector for MCO output as follows: +Other: reserved, must not be used +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. On STM32C011xx and STM32C031xx, MCOSEL[3] is reserved. + 24 + 4 + read-write + + + B_0x0 + no clock + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x3 + HSI48 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSIUSB48 + 0x8 + + + + + MCOPRE + Microcontroller clock output prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: +... +Other: Reserved +It is highly recommended to set this field before the MCO output is enabled. +Note: Values above 0111 are only significant for STM32C071xx. On STM32C011xx and STM32C031xx devices, MCOPRE[3] is reserved. + 28 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x14 + 0x20 + read-only + 0x0 + 0xFFFFFE00 + + + HSIUSB48CAL + HSIUSB48 clock calibration +These bits are initialized at startup with the factory-programmed HSIUSB48 calibration trim +value. + 0 + 9 + read-only + + + + + RCC_CIER + RCC_CIER + RCC clock interrupt enable register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSIUSB48RDYIE + HSIUSB48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSIUSB48 oscillator stabilization: +Note: Only applicable on STM32C071xx, reserved on other devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSIRDYIE + HSI48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization: + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + RCC clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +This flag indicates a pending interrupt upon LSE clock getting ready. +Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. +Cleared by software setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +This flag indicates a pending interrupt upon LSE clock getting ready. +Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. +Cleared by software setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + HSIUSB48RDYF + HSIUSB48 ready interrupt flag +Set by hardware when the HSIUSB48 clock becomes stable and HSIUSB48RDYIE is set as a response to setting HSIUSB48ON (refer to RCC clock control register (RCC_CR)). When HSIUSB48ON is not set but the HSIUSB48 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIUSB48RDYC bit. +Note: Only applicable on STM32C071xx, reserved on other devices. + 2 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + HSIRDYF + HSI48 ready interrupt flag +This flag indicates a pending interrupt upon HSI48 clock getting ready. +Set by hardware when the HSI48 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to RCC clock control register (RCC_CR)). When HSION is not set but the HSI48 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +This flag indicates a pending interrupt upon HSE clock getting ready. +Set by hardware when the HSE clock becomes stable and HSERDYIE is set. +Cleared by software setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + CSSF + HSE clock security system interrupt flag +This flag indicates a pending interrupt upon HSE clock failure. +Set by hardware when a failure is detected in the HSE oscillator. +Cleared by software setting the CSSC bit. + 8 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + LSECSSF + LSE clock security system interrupt flag +This flag indicates a pending interrupt upon LSE clock failure. +Set by hardware when a failure is detected in the LSE oscillator. +Cleared by software by setting the LSECSSC bit. + 9 + 1 + read-only + + + B_0x0 + Interrupt not pending + 0x0 + + + B_0x1 + Interrupt pending + 0x1 + + + + + + + RCC_CICR + RCC_CICR + RCC clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +This bit is set by software to clear the LSIRDYF flag. + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSIRDYF flag + 0x1 + + + + + LSERDYC + LSE ready interrupt clear +This bit is set by software to clear the LSERDYF flag. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSERDYF flag + 0x1 + + + + + HSIUSB48RDYC + HSIUSB48 ready interrupt clear +This bit is set software to clear the HSIUSB48RDYF flag. +Note: Only applicable on STM32C071xx, reserved on other devices. + 2 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIUSB48RDYF flag + 0x1 + + + + + HSIRDYC + HSI48 ready interrupt clear +This bit is set software to clear the HSIRDYF flag. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear +This bit is set by software to clear the HSERDYF flag. + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear +This bit is set by software to clear the HSECSSF flag. + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear +This bit is set by software to clear the LSECSSF flag. + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + + + RCC_IOPRSTR + RCC_IOPRSTR + RCC I/O port reset register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + I/O port A reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port A + 0x1 + + + + + GPIOBRST + I/O port B reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port B + 0x1 + + + + + GPIOCRST + I/O port C reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port C + 0x1 + + + + + GPIODRST + I/O port D reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port D + 0x1 + + + + + GPIOFRST + I/O port F reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port F + 0x1 + + + + + + + RCC_AHBRSTR + RCC_AHBRSTR + RCC AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 and DMAMUX reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 and DMAMUX + 0x1 + + + + + FLASHRST + Flash memory interface reset +Set and cleared by software. +This bit can only be set when the Flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset Flash memory interface + 0x1 + + + + + CRCRST + CRC reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + + + RCC_APBRSTR1 + RCC_APBRSTR1 + RCC APB peripheral reset register 1 + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + USBRST + USB reset +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB + 0x1 + + + + + SPI2RST + SPI2 reset +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + CRSRST + CRS reset +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRS + 0x1 + + + + + USART2RST + USART2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + I2C1RST + I2C1 reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + DBGRST + Debug support reset +Set and cleared by software. + 27 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DBG + 0x1 + + + + + PWRRST + Power interface reset +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + + + RCC_APBRSTR2 + RCC_APBRSTR2 + RCC APB peripheral reset register 2 + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + 0x1 + + + + + TIM1RST + TIM1 timer reset +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + USART1RST + USART1 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + TIM14RST + TIM14 timer reset +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM14 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + TIM17RST + TIM16 timer reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM17 timer + 0x1 + + + + + ADCRST + ADC reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC + 0x1 + + + + + + + RCC_IOPENR + RCC_IOPENR + RCC I/O port clock enable register + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + I/O port A clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBEN + I/O port B clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCEN + I/O port C clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODEN + I/O port D clock enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFEN + I/O port F clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_AHBENR + RCC_AHBENR + RCC AHB peripheral clock enable register + 0x38 + 0x20 + read-write + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHEN + Flash memory interface clock enable +Set and cleared by software. +This bit can only be cleared when the Flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCEN + CRC clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBENR1 + RCC_APBENR1 + RCC APB peripheral clock enable register 1 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3EN + TIM3 timer clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBEN + RTC APB clock enable +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGEN + WWDG clock enable +Set by software to enable the window watchdog clock. Cleared by hardware system reset +This bit can also be set by hardware if the WWDG_SW option bit is 0. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBEN + USB clock enable +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2EN + SPI2 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRSEN + CRS clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2EN + USART2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2EN + I2C2 clock enable +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DBGEN + Debug support clock enable +Set and cleared by software. + 27 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWREN + Power interface clock enable +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBENR2 + RCC_APBENR2 + RCC APB peripheral clock enable register 2 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1EN + TIM1 timer clock enable +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1EN + SPI1 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1EN + USART1 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM14EN + TIM14 timer clock enable +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16EN + TIM16 timer clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM17EN + TIM16 timer clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCEN + ADC clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_IOPSMENR + RCC_IOPSMENR + RCC I/O port in Sleep mode clock enable register + 0x44 + 0x20 + read-write + 0x0000002F + 0xFFFFFFFF + + + GPIOASMEN + I/O port A clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBSMEN + I/O port B clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCSMEN + I/O port C clock enable during Sleep mode +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODSMEN + I/O port D clock enable during Sleep mode +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFSMEN + I/O port F clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_AHBSMENR + RCC_AHBSMENR + RCC AHB peripheral clock enable in Sleep/Stop mode register + 0x48 + 0x20 + read-write + 0x00001301 + 0xFFFFFFFF + + + DMA1SMEN + DMA1 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHSMEN + Flash memory interface clock enable during Sleep mode +Set and cleared by software. +This bit can be activated only when the Flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SRAMSMEN + SRAM clock enable during Sleep mode +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCSMEN + CRC clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR1 + RCC_APBSMENR1 + RCC APB peripheral clock enable in Sleep/Stop mode register 1 + 0x4C + 0x20 + read-write + 0x18636C03 + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clock enable during Sleep mode +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3SMEN + TIM3 timer clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep mode +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGSMEN + WWDG clock enable during Sleep and Stop modes +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBSMEN + USB clock enable during Sleep and Stop modes +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2SMEN + SPI2 clock enable during Sleep and Stop modes +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRSSMEN + CRS clock enable during Sleep and Stop modes +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2SMEN + USART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1SMEN + I2C1 clock enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2SMEN + I2C2 clock enable during Sleep and Stop modes +Set and cleared by software. +Note: Only applicable on STM32C071xx, reserved on other devices. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DBGSMEN + Debug support clock enable during Sleep mode +Set and cleared by software. + 27 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWRSMEN + Power interface clock enable during Sleep mode +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR2 + RCC_APBSMENR2 + RCC APB peripheral clock enable in Sleep/Stop mode register 2 + 0x50 + 0x20 + read-write + 0x0016D801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG clock enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1SMEN + TIM1 timer clock enable during Sleep mode +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1SMEN + SPI1 clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1SMEN + USART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM14SMEN + TIM14 timer clock enable during Sleep mode +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16SMEN + TIM16 timer clock enable during Sleep mode +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM17SMEN + TIM16 timer clock enable during Sleep mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCSMEN + ADC clock enable during Sleep mode +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_CCIPR1 + RCC_CCIPR1 + RCC peripherals independent clock configuration register 1 + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection +This bitfield is controlled by software to select USART1 clock source as follows: + 0 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSIKER + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + I2C1SEL + I2C1 clock source selection +This bitfield is controlled by software to select I2C1 clock source as follows: + 12 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSIKER + 0x2 + + + + + I2S1SEL + I2S1 clock source selection +This bitfield is controlled by software to select I2S1 clock source as follows: + 14 + 2 + read-write + + + B_0x0 + SYSCLK + 0x0 + + + B_0x2 + HSIKER + 0x2 + + + B_0x3 + I2S_CKIN + 0x3 + + + + + ADCSEL + ADCs clock source selection +This bitfield is controlled by software to select the asynchronous clock source for ADC: + 30 + 2 + read-write + + + B_0x0 + System clock + 0x0 + + + B_0x2 + HSIKER + 0x2 + + + + + + + RCC_CCIPR2 + RCC_CCIPR2 + RCC peripherals independent clock configuration register 2 + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USBSEL + USB clock source selection +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + HSIUSB48 + 0x0 + + + B_0x1 + HSE + 0x1 + + + + + + + RCC_CSR1 + RCC_CSR1 + RCC control/status register 1 + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +Set and cleared by software to enable LSE oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): +After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and cleared by software to bypass the LSE oscillator (in debug mode). +This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). + 2 + 1 + read-write + + + B_0x0 + Not bypassed + 0x0 + + + B_0x1 + Bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +Set by software to select the LSE oscillator drive capability as follows: +Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. + 3 + 1 + read-write + + + B_0x0 + medium-high driving capability + 0x0 + + + B_0x1 + high driving capability + 0x1 + + + + + LSECSSON + CSS on LSE enable +Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: +LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD +=1). In that case the software must disable the LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection +Set by hardware to indicate when a failure is detected by the clock security system +on the external 32 kHz oscillator (LSE): + 6 + 1 + read-only + + + B_0x0 + No failure detected + 0x0 + + + B_0x1 + Failure detected + 0x1 + + + + + RTCSEL + RTC clock source selection +Set by software to select the clock source for the RTC as follows: +Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00. + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE + 0x1 + + + B_0x2 + LSI + 0x2 + + + B_0x3 + HSE divided by 32 + 0x3 + + + + + RTCEN + RTC clock enable +Set and cleared by software. The bit enables clock to RTC and TAMP. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCRST + RTC domain software reset +Set and cleared by software to reset the RTC domain: + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSCOSEL + Low-speed clock output selection +Set and cleared by software to select the low-speed output clock: + 25 + 1 + read-write + + + B_0x0 + LSI + 0x0 + + + B_0x1 + LSE + 0x1 + + + + + + + RCC_CSR2 + RCC_CSR2 + RCC control/status register 2 + 0x60 + 0x20 + read-write + 0x00000000 + 0x00FFFFFF + + + LSION + LSI oscillator enable +Set and cleared by software to enable/disable the LSI oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): +After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + RMVF + Remove reset flags +Set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag +Set by hardware when a reset from the Option byte loading occurs. +Cleared by setting the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from Option byte loading occurred + 0x0 + + + B_0x1 + Reset from Option byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag +Set by hardware when a reset from the NRST pin occurs. +Cleared by setting the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + PWRRSTF + BOR or POR/PDR flag +Set by hardware when a BOR or POR/PDR occurs. +Cleared by setting the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR or POR occurred + 0x0 + + + B_0x1 + BOR or POR occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Set by hardware when a software reset occurs. +Cleared by setting the RMVF bit. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag +Set by hardware when an independent watchdog reset domain occurs. +Cleared by setting the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +Set by hardware when a window watchdog reset occurs. +Cleared by setting the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. +Cleared by setting the RMVF bit. +This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared. + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + + + RTC + RTC address block description + RTC + 0x40002800 + + 0x0 + 0x60 + registers + + + RTC + RTC interrupts (EXTI lines 19) + 2 + + + + RTC_TR + RTC_TR + RTC time register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_DR + RTC_DR + RTC date register + 0x04 + 0x20 + read-write + 0x00002101 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-write + + + DT + Date tens in BCD format + 4 + 2 + read-write + + + MU + Month units in BCD format + 8 + 4 + read-write + + + MT + Month tens in BCD format + 12 + 1 + read-write + + + WDU + Week day units +... + 13 + 3 + read-write + + + B_0x0 + forbidden + 0x0 + + + B_0x1 + Monday + 0x1 + + + B_0x7 + Sunday + 0x7 + + + + + YU + Year units in BCD format + 16 + 4 + read-write + + + YT + Year tens in BCD format + 20 + 4 + read-write + + + + + RTC_SSR + RTC_SSR + RTC sub second register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: +Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) +Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. + 0 + 16 + read-only + + + + + RTC_ICSR + RTC_ICSR + RTC initialization control and status register + 0x0C + 0x20 + read-write + 0x00000007 + 0xFFFFFFFF + + + ALRAWF + Alarm A write flag +This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. + 0 + 1 + read-only + + + B_0x0 + Alarm A update not allowed + 0x0 + + + B_0x1 + Alarm A update allowed + 0x1 + + + + + SHPF + Shift operation pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-only + + + B_0x0 + No shift operation is pending + 0x0 + + + B_0x1 + A shift operation is pending + 0x1 + + + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (Power-on reset state). + 4 + 1 + read-only + + + B_0x0 + Calendar has not been initialized + 0x0 + + + B_0x1 + Calendar has been initialized + 0x1 + + + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. + 5 + 1 + read-write + + + B_0x0 + Calendar shadow registers not yet synchronized + 0x0 + + + B_0x1 + Calendar shadow registers synchronized + 0x1 + + + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. + 6 + 1 + read-only + + + B_0x0 + Calendar registers update is not allowed + 0x0 + + + B_0x1 + Calendar registers update is allowed + 0x1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + + B_0x0 + Free running mode + 0x0 + + + B_0x1 + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 0x1 + + + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + RTC prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + 0xFFFFFFFF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_CR + RTC_CR + RTC control register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSEDGE + Timestamp event active edge +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + B_0x0 + RTC_TS input rising edge generates a timestamp event + 0x0 + + + B_0x1 + RTC_TS input falling edge generates a timestamp event + 0x1 + + + + + REFCKON + RTC_REFIN reference clock detection enable (50 or 60 Hz) +Note: PREDIV_S must be 0x00FF. + 4 + 1 + read-write + + + B_0x0 + RTC_REFIN detection disabled + 0x0 + + + B_0x1 + RTC_REFIN detection enabled + 0x1 + + + + + BYPSHAD + Bypass the shadow registers +Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. + 5 + 1 + read-write + + + B_0x0 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. + 0x0 + + + B_0x1 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 0x1 + + + + + FMT + Hour format + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + B_0x0 + Alarm A disabled + 0x0 + + + B_0x1 + Alarm A enabled + 0x1 + + + + + TSE + timestamp enable + 11 + 1 + read-write + + + B_0x0 + timestamp disable + 0x0 + + + B_0x1 + timestamp enable + 0x1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + B_0x0 + Alarm A interrupt disabled + 0x0 + + + B_0x1 + Alarm A interrupt enabled + 0x1 + + + + + TSIE + Timestamp interrupt enable + 15 + 1 + read-write + + + B_0x0 + Timestamp interrupt disable + 0x0 + + + B_0x1 + Timestamp interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. + 16 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Adds 1 hour to the current time. This can be used for summer time change + 0x1 + + + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. + 17 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Subtracts 1 hour to the current time. This can be used for winter time change. + 0x1 + + + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE = 1, this bit selects which signal is output on CALIB. +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section 24.3.14: Calibration clock output. + 19 + 1 + read-write + + + B_0x0 + Calibration output is 512 Hz + 0x0 + + + B_0x1 + Calibration output is 1 Hz + 0x1 + + + + + POL + Output polarity +This bit is used to configure the polarity of TAMPALRM output. + 20 + 1 + read-write + + + B_0x0 + The pin is high when ALRAF is asserted (depending on OSEL[1:0]). + 0x0 + + + B_0x1 + The pin is low when ALRAF is asserted (depending on OSEL[1:0]). + 0x1 + + + + + OSEL + Output selection +These bits are used to select the flag to be routed to TAMPALRM output. + 21 + 2 + read-write + + + B_0x0 + Output disabled + 0x0 + + + B_0x1 + Alarm A output enabled + 0x1 + + + + + COE + Calibration output enable +This bit enables the CALIB output + 23 + 1 + read-write + + + B_0x0 + Calibration output disabled + 0x0 + + + B_0x1 + Calibration output enabled + 0x1 + + + + + TAMPALRM_PU + TAMPALRM pull-up enable + 29 + 1 + read-write + + + B_0x0 + No pull-up is applied on TAMPALRM output + 0x0 + + + B_0x1 + A pull-up is applied on TAMPALRM output + 0x1 + + + + + TAMPALRM_TYPE + TAMPALRM output type + 30 + 1 + read-write + + + B_0x0 + TAMPALRM is push-pull output + 0x0 + + + B_0x1 + TAMPALRM is open-drain output + 0x1 + + + + + OUT2EN + RTC_OUT2 output enable + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00. +Refer to RTC register write protection for a description of how to unlock RTC register write protection. + 0 + 8 + write-only + + + + + RTC_CALR + RTC_CALR + RTC calibration register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 2<sup>20</sup> RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 24.3.12: RTC smooth digital calibration on page 606. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. +Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 24.3.12: RTC smooth digital calibration. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1, the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 24.3.12: RTC smooth digital calibration. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 CALP) - CALM. +Refer to Section 24.3.12: RTC smooth digital calibration. + 15 + 1 + read-write + + + B_0x0 + No RTCCLK pulses are added. + 0x0 + + + B_0x1 + One RTCCLK pulse is effectively inserted every 2<sup>11</sup> pulses (frequency increased by 488.5 ppm). + 0x1 + + + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC shift control register + 0x2C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / (PREDIV_S + 1) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: +Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). +Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. + 0 + 15 + write-only + + + ADD1S + Add one second +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Add one second to the clock/calendar + 0x1 + + + + + + + RTC_TSTR + RTC_TSTR + RTC timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-only + + + ST + Second tens in BCD format. + 4 + 3 + read-only + + + MNU + Minute units in BCD format. + 8 + 4 + read-only + + + MNT + Minute tens in BCD format. + 12 + 3 + read-only + + + HU + Hour units in BCD format. + 16 + 4 + read-only + + + HT + Hour tens in BCD format. + 20 + 2 + read-only + + + PM + AM/PM notation + 22 + 1 + read-only + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_TSDR + RTC_TSDR + RTC timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-only + + + DT + Date tens in BCD format + 4 + 2 + read-only + + + MU + Month units in BCD format + 8 + 4 + read-only + + + MT + Month tens in BCD format + 12 + 1 + read-only + + + WDU + Week day units + 13 + 3 + read-only + + + + + RTC_TSSSR + RTC_TSSSR + RTC timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SS + Sub second value +SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred. + 0 + 16 + read-only + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm A set if the seconds match + 0x0 + + + B_0x1 + Seconds don t care in alarm A comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm A set if the minutes match + 0x0 + + + B_0x1 + Minutes don t care in alarm A comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm A hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm A set if the hours match + 0x0 + + + B_0x1 + Hours don t care in alarm A comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is don t care. + 0x1 + + + + + MSK4 + Alarm A date mask + 31 + 1 + read-write + + + B_0x0 + Alarm A set if the date/day match + 0x0 + + + B_0x1 + Date/day don t care in alarm A comparison + 0x1 + + + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. +Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + B_0x0 + No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[14:1] are don t care in alarm A comparison. Only SS[0] is compared. + 0x1 + + + + + + + RTC_SR + RTC_SR + RTC status register + 0x50 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). + 0 + 1 + read-only + + + TSF + Timestamp flag +This flag is set by hardware when a timestamp event occurs. + 3 + 1 + read-only + + + TSOVF + Timestamp overflow flag +This flag is set by hardware when a timestamp event occurs while TSF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + + + RTC_MISR + RTC_MISR + RTC masked interrupt status register + 0x54 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A masked flag +This flag is set by hardware when the alarm A interrupt occurs. + 0 + 1 + read-only + + + TSMF + Timestamp masked flag +This flag is set by hardware when a timestamp interrupt occurs. + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow masked flag +This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + + + RTC_SCR + RTC_SCR + RTC status clear register + 0x5C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CALRAF + Clear alarm A flag +Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. + 0 + 1 + write-only + + + CTSF + Clear timestamp flag +Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. + 3 + 1 + write-only + + + CTSOVF + Clear timestamp overflow flag +Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + write-only + + + + + + + SPI1 + SPI address block description + SPI + 0x40013000 + + 0x0 + 0x24 + registers + + + SPI2S1 + SPI2S1 global interrupt + 25 + + + + SPI1_CR1 + SPI1_CR1 + SPI control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. +Note: These bits are not used in I<sup>2</sup>S mode. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. +Note: This bit is not used in I<sup>2</sup>S mode. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +Note: This bit is not used in I<sup>2</sup>S mode. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPI1_DR register. +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. +Note: This bit is not used in I<sup>2</sup>S mode. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. +Note: This bit is not used in I<sup>2</sup>S mode. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPI1_CR2 + SPI1_CR2 + SPI control register 2 + 0x04 + 16 + read-write + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1 , or FRF = 1 . +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I<sup>2</sup>S mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) +Note: These bits are not used in I<sup>2</sup>S mode. + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI1_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI1_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI1_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI1_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI1_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI1_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPI1_SR + SPI1_SR + SPI status register + 0x08 + 16 + read-write + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CHSIDE + Channel side +Note: This bit is not used in SPI mode. It has no significance in PCM mode. + 2 + 1 + read-only + + + B_0x0 + Channel Left has to be transmitted or has been received + 0x0 + + + B_0x1 + Channel Right has to be transmitted or has been received + 0x1 + + + + + UDR + Underrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. +Note: This bit is not used in SPI mode. + 3 + 1 + read-only + + + B_0x0 + No underrun occurred + 0x0 + + + B_0x1 + Underrun occurred + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPI1_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPI1_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. +Note: This bit is not used in I<sup>2</sup>S mode. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. + 7 + 1 + read-only + + + B_0x0 + SPI (or I2S) not busy + 0x0 + + + B_0x1 + SPI (or I2S) is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I<sup>2</sup>S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. +This flag is set by hardware and reset when SPI1_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPI1_DR + SPI1_DR + SPI data register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI1_CRCPR + SPI1_CRCPR + SPI CRC polynomial register + 0x10 + 16 + read-write + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI1_RXCRCR + SPI1_RXCRCR + SPI Rx CRC register + 0x14 + 16 + read-only + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI1_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI1_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI1_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI1_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPI1_TXCRCR + SPI1_TXCRCR + SPI Tx CRC register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI1_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI1_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI1_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI1_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPI1_I2SCFGR + SPI1_I2SCFGR + SPI1_I2S configuration register + 0x1C + 16 + read-write + 0x0000 + 0xFFFF + + + CHLEN + Channel length (number of bits per audio channel) +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. + 0 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + DATLEN + Data length to be transferred +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 1 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CKPOL + Inactive state clock polarity +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. +Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. + 3 + 1 + read-write + + + B_0x0 + I2S clock inactive state is low level + 0x0 + + + B_0x1 + I2S clock inactive state is high level + 0x1 + + + + + I2SSTD + I2S standard selection +For more details on I<sup>2</sup>S standards, refer to Section 27.7.2 on page 805 +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 4 + 2 + read-write + + + B_0x0 + I<sup>2</sup>S Philips standard + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). +Note: It is not used in SPI mode. + 7 + 1 + read-write + + + B_0x0 + Short frame synchronization + 0x0 + + + B_0x1 + Long frame synchronization + 0x1 + + + + + I2SCFG + I2S configuration mode +Note: These bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 8 + 2 + read-write + + + B_0x0 + Slave - transmit + 0x0 + + + B_0x1 + Slave - receive + 0x1 + + + B_0x2 + Master - transmit + 0x2 + + + B_0x3 + Master - receive + 0x3 + + + + + I2SE + I2S enable +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + B_0x0 + I2S peripheral is disabled + 0x0 + + + B_0x1 + I2S peripheral is enabled + 0x1 + + + + + I2SMOD + I2S mode selection +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S mode is selected + 0x1 + + + + + ASTRTEN + Asynchronous start enable. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. +Note: The appropriate transition is a falling edge on WS signal when I<sup>2</sup>S Philips Standard is used, or a rising edge for other standards. +Note: The appropriate level is a low level on WS signal when I<sup>2</sup>S Philips Standard is used, or a high level for other standards. +Note: Please refer to Section 27.7.3: Start-up description for additional information. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. + 0x0 + + + B_0x1 + The Asynchronous start is enabled. + 0x1 + + + + + + + SPI1_I2SPR + SPI1_I2SPR + SPI1_I2S prescaler register + 0x20 + 16 + read-write + 0x0002 + 0xFFFF + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. +Refer to Section 27.7.3 on page 812. +Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. +Note: They are not used in SPI mode. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +Refer to Section 27.7.3 on page 812. +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 8 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + Master clock output enable +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 9 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + SYSCFG + Spider_SYSCFG register block + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + SYSCFG configuration register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + MEM_MODE + Memory mapping selection bits +This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to Section 3: Boot configuration for more details. +x0: Main Flash memory + 0 + 2 + read-write + + + B_0x1 + System Flash memory + 0x1 + + + B_0x3 + Embedded SRAM + 0x3 + + + + + PA11_RMP + PA11 pin remapping +This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. +Note: If the PINMUX2[1:0] bitfield of the SYSCFG_CFGR3 register is at 00, PA11_RMP must be kept at 0 to prevent conflict due to two GPIO outputs with different output levels connected to the same pin. + 3 + 1 + read-write + + + B_0x0 + No remap (PA11) + 0x0 + + + B_0x1 + Remap (PA9) + 0x1 + + + + + PA12_RMP + PA12 pin remapping +This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. +Note: If the PINMUX4[1:0] bitfield of the SYSCFG_CFGR3 register is at 00, PA12_RMP must be kept at 0 to prevent conflict due to two GPIO outputs with different output levels connected to the same pin. + 4 + 1 + read-write + + + B_0x0 + No remap (PA12) + 0x0 + + + B_0x1 + Remap (PA10) + 0x1 + + + + + IR_POL + IR output polarity selection + 5 + 1 + read-write + + + B_0x0 + Output of IRTIM (IR_OUT) is not inverted + 0x0 + + + B_0x1 + Output of IRTIM (IR_OUT) is inverted + 0x1 + + + + + IR_MOD + IR Modulation Envelope signal selection +This bitfield selects the signal for IR modulation envelope: + 6 + 2 + read-write + + + B_0x0 + TIM16 + 0x0 + + + B_0x1 + USART1 + 0x1 + + + B_0x2 + USART2 + 0x2 + + + + + I2C_PB6_FMP + Fast Mode Plus (FM+) enable for PB6 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB6 I/O port. + 16 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB7_FMP + Fast Mode Plus (FM+) enable for PB7 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB7 I/O port. + 17 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB8_FMP + Fast Mode Plus (FM+) enable for PB8 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB8 I/O port. +Note: Not available on STM32C011xx. + 18 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB9_FMP + Fast Mode Plus (FM+) enable for PB9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB9 I/O port. +Note: Not available on STM32C011xx. + 19 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1_FMP + Fast Mode Plus (FM+) enable for I2C1 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. + 20 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2C_y_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2_FMP + Fast Mode Plus (FM+) enable for I2C2 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C2 through GPIOx_AFR registers. +Note: Only applicable to STM32C071xx. Reserved on the other products. + 21 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2C_y_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA9_FMP + Fast Mode Plus (FM+) enable for PA9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA9 I/O port. + 22 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA10_FMP + Fast Mode Plus (FM+) enable for PA10 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA10 I/O port. + 23 + 1 + read-write + + + B_0x0 + Disable disabled if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PC14_FMP + Fast Mode Plus (FM+) enable for PC14 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PC14 I/O port. +Note: Not available on STM32C011xx. + 24 + 1 + read-write + + + B_0x0 + Disable if not enabled through I2Cx_FMP + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + SYSCFG configuration register 2 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCKUP_LOCK + Cortex<Superscript> <Default Font>-M0+ LOCKUP enable +This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript> <Default Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + SYSCFG_CFGR3 + SYSCFG_CFGR3 + SYSCFG configuration register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PINMUX0 + Pin GPIO multiplexer 0 +This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. +1x: Reserved +1x: Reserved + 0 + 2 + read-write + + + B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1 + PB7 + 0x0 + + + + + PINMUX1 + Pin GPIO multiplexer 1 +This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. +1x: Reserved + 2 + 2 + read-write + + + B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + PF2 + 0x0 + + + B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + PA0 + 0x1 + + + B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + PA1 + 0x2 + + + B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4 + PA2 + 0x3 + + + + + PINMUX2 + Pin GPIO multiplexer 2 +This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. +1x: Reserved +Note: The PA11_RMP bit of the SYSCFG_CFGR1 takes priority over the selection through this bitfield. Refer to the description of the SYSCFG_CFGR1 register for more details. + 4 + 2 + read-write + + + B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 + PA8 + 0x0 + + + B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5 + PA11 + 0x1 + + + + + PINMUX3 + Pin GPIO multiplexer 3 +This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. +1x: Reserved + 6 + 2 + read-write + + + B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + PA14 + 0x0 + + + B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + PB6 + 0x1 + + + B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8 + PC15 + 0x2 + + + + + PINMUX4 + Pin GPIO multiplexer 4 +This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. +1x: Reserved +Note: The PA12_RMP bit of the SYSCFG_CFGR1 takes priority over the selection through this bitfield. Refer to the description of the SYSCFG_CFGR1 register for more details. + 8 + 2 + read-write + + + B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 + PA7 + 0x0 + + + B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2 + PA12 + 0x1 + + + + + PINMUX5 + Pin GPIO multiplexer 5 +This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. + 10 + 2 + read-write + + + B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + PA3 + 0x0 + + + B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + PA4 + 0x1 + + + B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + PA5 + 0x2 + + + B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1 + PA6 + 0x3 + + + + + + + SYSCFG_ITLINE0 + SYSCFG_ITLINE0 + SYSCFG interrupt line 0 status register + 0x80 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WWDG + Window watchdog interrupt pending flag + 0 + 1 + read-only + + + + + SYSCFG_ITLINE1 + SYSCFG_ITLINE1 + SYSCFG interrupt line 1 status register + 0x84 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PVM_VDDIO2_OUT + V<sub>DDIO2</sub> supply monitoring interrupt request pending (EXTI line 34) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE2 + SYSCFG_ITLINE2 + SYSCFG interrupt line 2 status register + 0x88 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RTC + RTC interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE3 + SYSCFG_ITLINE3 + SYSCFG interrupt line 3 status register + 0x8C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FLASH_ITF + Flash interface interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE4 + SYSCFG_ITLINE4 + SYSCFG interrupt line 4 status register + 0x90 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RCC + Reset and clock control interrupt request pending + 0 + 1 + read-only + + + CRS + CRS interrupt request pending +Note: Only applicable on STM32C071xx, reserved on other products. + 1 + 1 + read-only + + + + + SYSCFG_ITLINE5 + SYSCFG_ITLINE5 + SYSCFG interrupt line 5 status register + 0x94 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI line 0 interrupt request pending + 0 + 1 + read-only + + + EXTI1 + EXTI line 1 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE6 + SYSCFG_ITLINE6 + SYSCFG interrupt line 6 status register + 0x98 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EXTI2 + EXTI line 2 interrupt request pending + 0 + 1 + read-only + + + EXTI3 + EXTI line 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE7 + SYSCFG_ITLINE7 + SYSCFG interrupt line 7 status register + 0x9C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI line 4 interrupt request pending + 0 + 1 + read-only + + + EXTI5 + EXTI line 5 interrupt request pending + 1 + 1 + read-only + + + EXTI6 + EXTI line 6 interrupt request pending + 2 + 1 + read-only + + + EXTI7 + EXTI line 7 interrupt request pending + 3 + 1 + read-only + + + EXTI8 + EXTI line 8 interrupt request pending + 4 + 1 + read-only + + + EXTI9 + EXTI line 9 interrupt request pending + 5 + 1 + read-only + + + EXTI10 + EXTI line 10 interrupt request pending + 6 + 1 + read-only + + + EXTI11 + EXTI line 11 interrupt request pending + 7 + 1 + read-only + + + EXTI12 + EXTI line 12 interrupt request pending + 8 + 1 + read-only + + + EXTI13 + EXTI line 13 interrupt request pending + 9 + 1 + read-only + + + EXTI14 + EXTI line 14 interrupt request pending + 10 + 1 + read-only + + + EXTI15 + EXTI line 15 interrupt request pending + 11 + 1 + read-only + + + + + SYSCFG_ITLINE8 + SYSCFG_ITLINE8 + SYSCFG interrupt line 8 status register + 0xA0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + USB + USB interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE9 + SYSCFG_ITLINE9 + SYSCFG interrupt line 9 status register + 0xA4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH1 + DMA1 channel 1interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE10 + SYSCFG_ITLINE10 + SYSCFG interrupt line 10 status register + 0xA8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH2 + DMA1 channel 2 interrupt request pending + 0 + 1 + read-only + + + DMA1_CH3 + DMA1 channel 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE11 + SYSCFG_ITLINE11 + SYSCFG interrupt line 11 status register + 0xAC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DMAMUX + DMAMUX interrupt request pending + 0 + 1 + read-only + + + DMA_CH4 + DMA channel 5 interrupt request pending +Note: Only applicable on STM32C071xx, reserved on the other products. + 1 + 1 + read-only + + + DMA_CH5 + DMA channel 5 interrupt request pending +Note: Only applicable on STM32C071xx, reserved on the other products. + 2 + 1 + read-only + + + + + SYSCFG_ITLINE12 + SYSCFG_ITLINE12 + SYSCFG interrupt line 12 status register + 0xB0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE13 + SYSCFG_ITLINE13 + SYSCFG interrupt line 13 status register + 0xB4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM1_CCU + Timer 1 commutation interrupt request pending + 0 + 1 + read-only + + + TIM1_TRG + Timer 1 trigger interrupt request pending + 1 + 1 + read-only + + + TIM1_UPD + Timer 1 update interrupt request pending + 2 + 1 + read-only + + + TIM1_BRK + Timer 1 break interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE14 + SYSCFG_ITLINE14 + SYSCFG interrupt line 14 status register + 0xB8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM1_CC + Timer 1 capture compare interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE15 + SYSCFG_ITLINE15 + SYSCFG interrupt line 15 status register + 0xBC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM2 + TIM2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE16 + SYSCFG_ITLINE16 + SYSCFG interrupt line 16 status register + 0xC0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM3 + Timer 3 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE19 + SYSCFG_ITLINE19 + SYSCFG interrupt line 19 status register + 0xCC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM14 + Timer 14 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE21 + SYSCFG_ITLINE21 + SYSCFG interrupt line 21 status register + 0xD4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM16 + Timer 16 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE22 + SYSCFG_ITLINE22 + SYSCFG interrupt line 22 status register + 0xD8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM17 + Timer 17 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE23 + SYSCFG_ITLINE23 + SYSCFG interrupt line 23 status register + 0xDC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + I2C1 + I2C1 interrupt request pending, combined with EXTI line 23 + 0 + 1 + read-only + + + + + SYSCFG_ITLINE24 + SYSCFG_ITLINE24 + SYSCFG interrupt line 24 status register + 0xE0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + I2C2 + I2C2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE25 + SYSCFG_ITLINE25 + SYSCFG interrupt line 25 status register + 0xE4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SPI1 + SPI1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE26 + SYSCFG_ITLINE26 + SYSCFG interrupt line 26 status register + 0xE8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SPI2 + SPI2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE27 + SYSCFG_ITLINE27 + SYSCFG interrupt line 27 status register + 0xEC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + USART1 + USART1 interrupt request pending, combined with EXTI line 25 + 0 + 1 + read-only + + + + + SYSCFG_ITLINE28 + SYSCFG_ITLINE28 + SYSCFG interrupt line 28 status register + 0xF0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + USART2 + USART2 interrupt request pending (EXTI line 26) + 0 + 1 + read-only + + + + + + + TIM1 + TIM1 address block description + TIM1 + 0x40012C00 + + 0x0 + 0x6C + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 break, update, trigger and commutation interrupts + 13 + + + TIM1_CC + TIM1 Capture Compare interrupt + 14 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (ETR, TIx): +Note: t<sub>DTS</sub> = 1/f<sub>DTS</sub>, t<sub>CK_INT</sub> = 1/f<sub>CK_INT</sub>. + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub>=t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub>=2*t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub>=4*t<sub>CK_INT</sub> + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output Idle state 2 (OC2 output) +Refer to OIS1 bit + 10 + 1 + read-write + + + OIS2N + Output Idle state 2 (OC2N output) +Refer to OIS1N bit + 11 + 1 + read-write + + + OIS3 + Output Idle state 3 (OC3 output) +Refer to OIS1 bit + 12 + 1 + read-write + + + OIS3N + Output Idle state 3 (OC3N output) +Refer to OIS1N bit + 13 + 1 + read-write + + + OIS4 + Output Idle state 4 (OC4 output) +Refer to OIS1 bit + 14 + 1 + read-write + + + OIS5 + Output Idle state 5 (OC5 output) +Refer to OIS1 bit + 16 + 1 + read-write + + + OIS6 + Output Idle state 6 (OC6 output) +Refer to OIS1 bit + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 +These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO2) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO2) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO2) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO2) + 0x7 + + + B_0x8 + Compare - OC5REFC signal is used as trigger output (TRGO2) + 0x8 + + + B_0x9 + Compare - OC6REFC signal is used as trigger output (TRGO2) + 0x9 + + + B_0xA + Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 + 0xA + + + B_0xB + Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 + 0xB + + + B_0xC + Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xC + + + B_0xD + Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xD + + + B_0xE + Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xE + + + B_0xF + Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xF + + + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Codes above 1000: Reserved. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection +This bit is used to select the OCREF clear source. + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is not connected (reserved configuration) + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See Table 73: TIM1 internal trigger connection on page 395 for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of f<sub>CK_INT</sub> frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to Section 17.4.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag +This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + B2IF + Break 2 interrupt flag +This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 . + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag +Refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +Refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +Refer to CC1OF description + 12 + 1 + read-write + + + SBIF + System Break interrupt flag +This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. +This flag must be reset to re-start PWM operation. + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag +Refer to CC1IF description (Note: Channel 5 can only be configured as output) + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag +Refer to CC1IF description (Note: Channel 6 can only be configured as output) + 17 + 1 + read-write + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/Compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/Compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware +Note: This bit acts only on channels having a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. + 0x1 + + + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + B2G + Break 2 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. + 0x1 + + + + + + + TIM1_CCMR1 + TIM1_CCMR1 + TIM1 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC2F + Input capture 2 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR1_ALTERNATE1 + TIM1_CCMR1_ALTERNATE1 + TIM1 capture/compare mode register 1 + TIM1_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF= 0 ) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF= 1 ). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ocref_clr_int signal + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input) + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output Compare 2 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode +Refer to OC1M[3:0] description. + 12 + 3 + read-write + + + OC2CE + Output Compare 2 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2 + TIM1_CCMR2 + TIM1 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +Refer to IC1PSC[1:0] description. + 2 + 2 + read-write + + + IC3F + Input capture 3 filter +Refer to IC1F[3:0] description. + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC4F + Input capture 4 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR2_ALTERNATE1 + TIM1_CCMR2_ALTERNATE1 + TIM1 capture/compare mode register 2 + TIM1_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode +Refer to OC1M[3:0] description. + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode +Refer to OC3M[3:0] description. + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 74 for details. +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (channel configured as output). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/Compare 2 complementary output enable +Refer to CC1NE description + 6 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output polarity +Refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/Compare 3 complementary output enable +Refer to CC1NE description + 10 + 1 + read-write + + + CC3NP + Capture/Compare 3 complementary output polarity +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable +Refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output polarity +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 complementary output polarity +Refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/Compare 5 output enable +Refer to CC1E description + 16 + 1 + read-write + + + CC5P + Capture/Compare 5 output polarity +Refer to CC1P description + 17 + 1 + read-write + + + CC6E + Capture/Compare 6 output enable +Refer to CC1E description + 20 + 1 + read-write + + + CC6P + Capture/Compare 6 output polarity +Refer to CC1P description + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section 17.3.1: Time-base unit on page 331 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to: +the number of PWM periods in edge-aligned mode +the number of half PWM period in center-aligned mode. + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x38 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. +If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x3C + 16 + read-write + 0x0000 + 0xFFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x40 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR4 + Capture/Compare value +If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. +See OC/OCN enable description for more details (Section 17.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (Section 17.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +This bit enables the complete break protection (including all sources connected to bk_acth and BRK sources, as per Figure 100: Break and Break2 circuitry overview). +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. +See OC/OCN enable description for more details (Section 17.4.11: TIM1 capture/compare enable register (TIM1_CCER)). + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. OC and OCN outputs are disabled + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter +This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 20 + 4 + read-write + + + B_0x0 + No filter, BRK2 acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable +Note: The BRK2 must only be used with OSSR = OSSI = 1. +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 24 + 1 + read-write + + + B_0x0 + Break input BRK2 disabled + 0x0 + + + B_0x1 + Break input BRK2 enabled + 0x1 + + + + + BK2P + Break 2 polarity +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 25 + 1 + read-write + + + B_0x0 + Break input BRK2 is active low + 0x0 + + + B_0x1 + Break input BRK2 is active high + 0x1 + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BK2DSRM + Break2 Disarm +Refer to BKDSRM description + 27 + 1 + read-write + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional +Refer to BKBID description + 29 + 1 + read-write + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... +Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. +If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: +(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL +In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA +According to the configuration of the DMA Data Size, several cases may occur: +If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. +If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x11 + 18 transfers + 0x11 + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 32 + read-write + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC5M + OC5M[2:0]: Output compare 5 mode +Refer to OC1M description. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC6M + OC6M[2:0]: Output compare 6 mode +Refer to OC1M description. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/Compare 5 value +CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. + 0 + 16 + read-write + + + GC5C1 + Group Channel 5 and Channel 1 +Distortion on Channel 1 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC1REFC5 + 0x0 + + + B_0x1 + OC1REFC is the logical AND of OC1REFC and OC5REF + 0x1 + + + + + GC5C2 + Group Channel 5 and Channel 2 +Distortion on Channel 2 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC2REFC + 0x0 + + + B_0x1 + OC2REFC is the logical AND of OC2REFC and OC5REF + 0x1 + + + + + GC5C3 + Group Channel 5 and Channel 3 +Distortion on Channel 3 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). +Note: it is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC3REFC + 0x0 + + + B_0x1 + OC3REFC is the logical AND of OC3REFC and OC5REF + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x5C + 16 + read-write + 0x0000 + 0xFFFF + + + CCR6 + Capture/Compare 6 value +CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. + 0 + 16 + read-write + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 Alternate function register 2 + 0x64 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BK2INE + BRK2 BKIN input enable +This bit enables the BKIN2 alternate function input for the timer s BRK2 input. BKIN2 input is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN2 input disabled + 0x0 + + + B_0x1 + BKIN2 input enabled + 0x1 + + + + + BK2INP + BRK2 BKIN2 input polarity +This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM1_CH1 input + 0x0 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM1_CH2 input + 0x0 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM1_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM1_CH4 input + 0x0 + + + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40000000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 gloabal interrupt + 15 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub> = t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub> = 2 t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub> = 4 t<sub>CK_INT</sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section17. + 0x1 + + + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is unconnected. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF= 0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM2_CNT_ALTERNATE1 + TIM2_CNT_ALTERNATE1 + TIM2_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x3 + LSE + 0x3 + + + B_0x4 + MCO + 0x4 + + + B_0x5 + MCO2 + 0x5 + + + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM2_CH1 input + 0x0 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM2_CH2 input + 0x0 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM2_CH3 input + 0x0 + + + + + + + + + TIM3 + TIM3 address block description + TIM3 + 0x40000400 + + 0x0 + 0x6C + registers + + + TIM3 + TIM3 gloabal interrupt + 16 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. +CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub> = t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub> = 2 t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub> = 4 t<sub>CK_INT</sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 17.3.25: Interfacing with Hall sensors on page 380 + 0x1 + + + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +reinitializes the counter, generates an update of the registers and starts the counter. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection +This bit is used to select the OCREF clear source + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is unconnected. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See Table 77: TIM3 internal trigger connection on page 478 for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 . + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +refer to CC1OF description + 12 + 1 + read-write + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f <sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_ALTERNATE1 + TIM3_CCMR1_ALTERNATE1 + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF= 0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode +refer to OC1M description on bits 6:4 + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_ALTERNATE1 + TIM3_CCMR2_ALTERNATE1 + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode +Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode +Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: This configuration is reserved, it must not be used. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. +CC1 channel configured as output: CC1NP must be kept cleared in this case. +CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. +refer to CC1P description + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. +Refer to CC1P description + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. +refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. +Refer to CC1NP description + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + counter value + 0 + 32 + read-write + + + + + TIM3_CNT_ALTERNATE1 + TIM3_CNT_ALTERNATE1 + TIM3 counter + TIM3_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section 18.3.1: Time-base unit on page 429 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 32 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1is configured as input: +CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 32 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. +If channel CC2 is configured as input: +CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 32 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3is configured as input: +CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 32 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/Compare value +if CC4 channel is configured as output (CC4S bits): +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): +CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 32 + read-write + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... +Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). +... + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address +(TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection +These bits select the TI1[0] to TI1[15] input source. +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM3_CH1 input + 0x0 + + + + + TI2SEL + TI2[0] to TI2[15] input selection +These bits select the TI2[0] to TI2[15] input source. +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM3_CH2 input + 0x0 + + + + + TI3SEL + TI3[0] to TI3[15] input selection +These bits select the TI3[0] to TI3[15] input source. +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM3_CH3 input + 0x0 + + + + + + + + + TIM14 + TIM14 address block description + TIM14 + 0x40002000 + + 0x0 + 0x6C + registers + + + TIM14 + TIM14 gloabal interrupt + 19 + + + + TIM14_CR1 + TIM14_CR1 + TIM14 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock and gated mode can work only if the CEN bit has been previously set by +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. +Counter overflow +Setting the UG bit. +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. An UEV is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the update interrupt (UEV) sources. +Counter overflow +Setting the UG bit + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an UEV if enabled: + 0x0 + + + B_0x1 + Only counter overflow generates an UEV if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped on the update event + 0x0 + + + B_0x1 + Counter stops counting on the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub> = t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub> = 2 t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub> = 4 t<sub>CK_INT</sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM14_DIER + TIM14_DIER + TIM14 Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + + + TIM14_SR + TIM14_SR + TIM14 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow and if UDIS= 0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS= 0 and UDIS= 0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 . + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM14_EGR + TIM14_EGR + TIM14 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. + 0x1 + + + + + CC1G + Capture/compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + + + TIM14_CCMR1 + TIM14_CCMR1 + TIM14 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). +The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f <sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + + + TIM14_CCMR1_ALTERNATE1 + TIM14_CCMR1_ALTERNATE1 + TIM14 capture/compare mode register 1 + TIM14_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + Reserved. + 0x2 + + + B_0x3 + Reserved. + 0x3 + + + + + OC1FE + Output compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) +These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. +Others: Reserved +Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active + 0x7 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM14_CCER + TIM14_CCER + TIM14 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: This configuration is reserved, it must not be used. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output Polarity. +CC1 channel configured as output: CC1NP must be kept cleared. +CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description). + 3 + 1 + read-write + + + + + TIM14_CNT + TIM14_CNT + TIM14 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit in the TIMx_ISR register. + 31 + 1 + read-write + + + + + TIM14_PSC + TIM14_PSC + TIM14 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event. +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). + 0 + 16 + read-write + + + + + TIM14_ARR + TIM14_ARR + TIM14 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to Section 19.3.1: Time-base unit on page 517 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM14_CCR1 + TIM14_CCR1 + TIM14 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1is configured as input: +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + TIM14_TISEL + TIM14_TISEL + TIM14 timer input selection register + 0x68 + 16 + read-write + 0x0000 + 0xFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM14_CH1 input + 0x0 + + + B_0x1 + RTC CLK + 0x1 + + + B_0x2 + HSE/32 + 0x2 + + + B_0x3 + MCO + 0x3 + + + B_0x4 + MCO2 + 0x4 + + + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40014400 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 global interrupt + 21 + + + + TIM16_CR1 + TIM16_CR1 + TIM16 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (TIx), + 8 + 2 + read-write + + + B_0x0 + t <sub>DTS</sub>= t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t <sub>DTS</sub>= 2 * t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub> = 4 * t<sub>CK_INT</sub> + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM16_CR2 + TIM16_CR2 + TIM16 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + + + TIM16_DIER + TIM16_DIER + TIM16 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + + + TIM16_SR + TIM16_SR + TIM16 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + COMIF + COM interrupt flag + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 . + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM16_EGR + TIM16_EGR + TIM16 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware. +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + + + TIM16_CCMR1 + TIM16_CCMR1 + TIM16 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Others: Reserved +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). +The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input. + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N= + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + + + TIM16_CCMR1_ALTERNATE1 + TIM16_CCMR1_ALTERNATE1 + TIM16 capture/compare mode register 1 + TIM16_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Others: Reserved +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +All other values: Reserved +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). +Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. + 0x7 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM16_CCER + TIM16_CCER + TIM16 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 83 for details. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +Note: On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer +to the description of CC1P. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). +Note: On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + + + TIM16_CNT + TIM16_CNT + TIM16 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM16_PSC + TIM16_PSC + TIM16 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). + 0 + 16 + read-write + + + + + TIM16_ARR + TIM16_ARR + TIM16 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section 20.3.1: Time-base unit on page 526 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM16_RCR + TIM16_RCR + TIM16 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. + 0 + 8 + read-write + + + + + TIM16_CCR1 + TIM16_CCR1 + TIM16 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + TIM16_BDTR + TIM16_BDTR + TIM16 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup +This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. +DTG[7:5] = 0xx => DT = DTG[7:0] x t<sub>dtg</sub> with t <sub>dtg</sub>= t<sub>DTS</sub> +DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x t<sub>dtg</sub> with t <sub>dtg</sub>= 2 x t<sub>DTS</sub> +DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x t<sub>dtg</sub> with t <sub>dtg</sub>= 8 x t<sub>DTS</sub> +DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x t<sub>dtg</sub> with t <sub>dtg</sub>= 16 x t<sub>DTS</sub> +Example if t <sub>DTS</sub>= 125 ns (8 MHz), dead-time possible values are: +0 to 15875 ns by 125 ns steps, +16 s to 31750 ns by 250 ns steps, +32 s to 63 s by 1 s steps, +64 s to 126 s by 2 s steps +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 on channels configured as outputs. +See OC/OCN enable description for more details (Section 20.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 563). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (Section 20.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 563). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +1; Break inputs (BRK and CCS clock failure event) enabled +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +See OC/OCN enable description for more details (Section 20.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 563). + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: +This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM16_DCR + TIM16_DCR + TIM16 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM16_DMAR + TIM16_DMAR + TIM16 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address +(TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM16_CH1 input + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + LSE + 0x2 + + + B_0x4 + MCO2 + 0x4 + + + + + + + + + TIM17 + TIM17 address block description + TIM17 + 0x40014800 + + 0x0 + 0x6C + registers + + + TIM17 + TIM17 global interrupt + 22 + + + + TIM17_CR1 + TIM17_CR1 + TIM17 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (TIx), + 8 + 2 + read-write + + + B_0x0 + t <sub>DTS</sub>= t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t <sub>DTS</sub>= 2 * t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub> = 4 * t<sub>CK_INT</sub> + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM17_CR2 + TIM17_CR2 + TIM17 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + + + TIM17_DIER + TIM17_DIER + TIM17 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + + + TIM17_SR + TIM17_SR + TIM17 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + COMIF + COM interrupt flag + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 . + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM17_EGR + TIM17_EGR + TIM17 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware. +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + + + TIM17_CCMR1 + TIM17_CCMR1 + TIM17 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Others: Reserved +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). +The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input. + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N= + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + + + TIM17_CCMR1_ALTERNATE1 + TIM17_CCMR1_ALTERNATE1 + TIM17 capture/compare mode register 1 + TIM17_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Others: Reserved +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +All other values: Reserved +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). +Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. + 0x7 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM17_CCER + TIM17_CCER + TIM17 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 83 for details. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +Note: On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer +to the description of CC1P. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S= 00 (the channel is configured in output). +Note: On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + + + TIM17_CNT + TIM17_CNT + TIM17 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM17_PSC + TIM17_PSC + TIM17 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ). + 0 + 16 + read-write + + + + + TIM17_ARR + TIM17_ARR + TIM17 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section 20.3.1: Time-base unit on page 526 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM17_RCR + TIM17_RCR + TIM17 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. + 0 + 8 + read-write + + + + + TIM17_CCR1 + TIM17_CCR1 + TIM17 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + TIM17_BDTR + TIM17_BDTR + TIM17 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup +This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. +DTG[7:5] = 0xx => DT = DTG[7:0] x t<sub>dtg</sub> with t <sub>dtg</sub>= t<sub>DTS</sub> +DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x t<sub>dtg</sub> with t <sub>dtg</sub>= 2 x t<sub>DTS</sub> +DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x t<sub>dtg</sub> with t <sub>dtg</sub>= 8 x t<sub>DTS</sub> +DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x t<sub>dtg</sub> with t <sub>dtg</sub>= 16 x t<sub>DTS</sub> +Example if t <sub>DTS</sub>= 125 ns (8 MHz), dead-time possible values are: +0 to 15875 ns by 125 ns steps, +16 s to 31750 ns by 250 ns steps, +32 s to 63 s by 1 s steps, +64 s to 126 s by 2 s steps +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 on channels configured as outputs. +See OC/OCN enable description for more details (Section 20.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 563). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (Section 20.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 563). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +1; Break inputs (BRK and CCS clock failure event) enabled +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +See OC/OCN enable description for more details (Section 20.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 563). + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: +This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM17_DCR + TIM17_DCR + TIM17 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM17_DMAR + TIM17_DMAR + TIM17 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address +(TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + TIM17_AF1 + TIM17_AF1 + TIM17 alternate function register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + + + TIM17_TISEL + TIM17_TISEL + TIM17 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM17_CH1 input + 0x0 + + + B_0x2 + HSE/32 + 0x2 + + + B_0x3 + MCO + 0x3 + + + B_0x4 + MCO2 + 0x4 + + + + + + + + + USART1 + USART address block description + USART + 0x40013800 + + 0x0 + 0x30 + registers + + + USART1 + USART1 global interrupt (combined with EXTI 25) + 27 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE = 1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC = 1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not-full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE = 1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE = 0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE = 0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE = 0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE = 0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 16 + 5 + read-write + + + DEAT + Driver enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 26.4: USART implementation on page 691. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End-of-block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE = 0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE = 1 in the USART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO full interrupt enable +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when RXFF = 1 in the USART_ISR register + 0x1 + + + + + + + USART_CR1_ALTERNATE1 + USART_CR1_ALTERNATE1 + USART control register 1 + USART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE = 1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC = 1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE = 1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE = 0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE = 0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE = 0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE = 0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 16 + 5 + read-write + + + DEAT + Driver enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 26.4: USART implementation on page 691. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Bbock interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE = 0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + NSS pin enable +When the DIS_NSS bit is set, the NSS pin input is ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit address detection/4-bit address detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the USART is disabled (UE = 0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +This bit can only be written when the USART is disabled (UE = 0). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF = 1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. +The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE = 0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase +This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 249 and Figure 250) +This bit can only be written when the USART is disabled (UE = 0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +This bit can only be written when the USART is disabled (UE = 0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable +This bit enables the user to enable the CK pin. +This bit can only be written when the USART is disabled (UE = 0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. +In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +Note: UE = 1 + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + Stop bits +These bits are used for programming the stop bits. +This bitfield can only be written when the USART is disabled (UE = 0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0.5 stop bit. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1.5 stop bits + 0x3 + + + + + LINEN + LIN mode enable +This bit is set and cleared by software. +The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the USART is disabled (UE = 0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd = 0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted (V<sub>DD</sub> =0/mark, Gnd = 1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the USART is disabled (UE = 0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd = 0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted (V<sub>DD</sub> =0/mark, Gnd = 1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE = 0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable +This bit is set and cleared by software. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode +These bits are set and cleared by software. +This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). +Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable +This bit is set and cleared by software. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node +These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0). + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable +This bit is set and cleared by software. +This bit can only be written when the USART is disabled (UE = 0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +This bit can only be written when the USART is disabled (UE = 0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the USART is disabled (UE = 0). + 3 + 1 + read-write + + + B_0x0 + Half duplex mode is not selected + 0x0 + + + B_0x1 + Half duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable +This bit is used for enabling Smartcard mode. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 5 + 1 + read-write + + + B_0x0 + Smartcard Mode disabled + 0x0 + + + B_0x1 + Smartcard Mode enabled + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the USART is disabled (UE = 0). +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the USART is disabled (UE = 0) +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF = 1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable +This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. +This bit can only be written when the USART is disabled (UE = 0). + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE = 0). +Note: This control bit enables checking the communication flow w/o reading the data + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on reception error +This bit can only be written when the USART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode). + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the USART is disabled (UE = 0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 26.4: USART implementation on page 691. + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the USART is disabled (UE = 0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count +This bitfield specifies the number of retries for transmission and reception in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). +This bitfield must be programmed only when the USART is disabled (UE = 0). +When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. +0x1 to 0x7: number of automatic retransmission attempts (before signaling error) +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmit mode. + 0x0 + + + + + WUS + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 20 + 2 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + WUF active on start bit detection + 0x2 + + + B_0x3 + WUF active on RXNE/RXFNE. + 0x3 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF = 1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission complete before guard time, interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate +BRR[15:4] +BRR[15:4] = USARTDIV[15:4] +BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared. + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value + 0 + 8 + read-write + + + B_0x0 + Reserved - do not program this value + 0x0 + + + B_0x1 + Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode) + 0x1 + + + B_0x2 + Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode) + 0x2 + + + B_0x3 + Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode) + 0x3 + + + B_0x1F + Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode) + 0x1F + + + B_0x20 + Divides the source clock by 32 (IrDA mode) + 0x20 + + + B_0xFF + Divides the source clock by 255 (IrDA mode) + 0xFF + + + + + GT + Guard time value +This bitfield is used to program the Guard time value in terms of number of baud clock periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. +This bitfield can only be written when the USART is disabled (UE = 0). +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value +This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. +Note: This value must only be programmed once per received character. + 0 + 24 + read-write + + + BLEN + Block length +This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0: 0 information characters + LEC +BLEN = 1: 0 information characters + CRC +BLEN = 255: 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). +This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. +Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request +Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 0 + 1 + write-only + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This enables to discard the received data without reading them, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + read-only + 0x008000C0 + 0xF0FFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 26.5.8: Tolerance of the USART receiver to clock deviation on page 709). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. +RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. +It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. +An interrupt is generated if TCIE = 1 in the USART_CR1 register. +TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set. + 6 + 1 + read-only + + + B_0x0 + Transmission is not complete + 0x0 + + + B_0x1 + Transmission is complete + 0x1 + + + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. +An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE = 1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE = 1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE = 1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character Match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + Break character transmitted + 0x0 + + + B_0x1 + Break character requested by setting SBKRQ bit in USART_RQR register + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE = 1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 22 + 1 + read-only + + + TXFE + TXFIFO empty +This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. +An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO full +This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. +An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. +Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE1 + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR3 register. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 26.5.8: Tolerance of the USART receiver to clock deviation on page 709). + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXNEIE = 1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXNEIE = 1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. +It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE = 1 in the USART_CR1 register. +TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately. + 6 + 1 + read-only + + + B_0x0 + Transmission is not complete + 0x0 + + + B_0x1 + Transmission is complete + 0x1 + + + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). +An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register. + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE = 1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE = 1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE = 1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character Match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + Break character transmitted + 0x0 + + + B_0x1 + Break character requested by setting SBKRQ bit in USART_RQR register + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE = 1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register. + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register. + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 8 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 11 + 1 + write-only + + + EOBCF + End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register. +Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691 + 13 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 243). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 243). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF = 1. + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The USART input clock can be divided by a prescaler factor: +Remaining combinations: Reserved +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 28 + + + + USB + USB address block description + USB + 0x40005C00 + + 0x0 + 0x5C + registers + + + USB + USB global interrupt + 8 + + + + USB_CHEP0R + USB_CHEP0R + USB endpoint/channel 0 register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP1R + USB_CHEP1R + USB endpoint/channel 1 register + 0x4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP2R + USB_CHEP2R + USB endpoint/channel 2 register + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP3R + USB_CHEP3R + USB endpoint/channel 3 register + 0xC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP4R + USB_CHEP4R + USB endpoint/channel 4 register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP5R + USB_CHEP5R + USB endpoint/channel 5 register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP6R + USB_CHEP6R + USB endpoint/channel 6 register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP7R + USB_CHEP7R + USB endpoint/channel 7 register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + Device mode + Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. + Host mode + Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). + If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + Device mode + This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written. + Host mode + Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. + DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. + STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction + These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. + Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. + The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed + Device mode + This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. + Host mode + This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + Device mode + These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. + Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. + Host mode + These bits are the host application controls to start, retry, or abort host transactions driven by the channel. + These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: + - DISABLE + DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. + - VALID + A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. + VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. + - NAK + NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE + - STALL + STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). + If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). + If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. + This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received + Device mode + This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. + A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. + This bit is read/write but only 0 can be written, writing 1 has no effect. + Host mode + This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. + - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. + - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. + - A transaction ended with ACK handshake sets this bit + If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. + If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. + - A transaction ended with error sets this bit. + Errors can be seen via the bits ERR_RX (host mode only). + This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode + Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode + This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + Host mode + This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + Host mode + This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. + Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CNTR + USB_CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000003 + 0xFFFFFFFF + + + USBRST + USB Reset + Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. + Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software. + 0 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + USB core is under reset + 0x1 + + + + + PDWN + Power down + This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. + 1 + 1 + read-write + + + B_0x0 + Exit power down + 0x0 + + + B_0x1 + Enter power down mode + 0x1 + + + + + SUSPRDY + Suspend state effective + This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wake-up logic and single ended receiver is kept alive to detect remote wake-up or resume events. + Software must poll this bit to confirm it to be set before any STOP mode entry. + This bit is cleared by hardware simultaneously to the WAKEUP flag being set. + 2 + 1 + read-only + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Suspend state + 0x1 + + + + + SUSPEN + Suspend state enable + Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. + As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY = 1 acknowledge the suspend request. + This bit is cleared by hardware simultaneous with the WAKEUP flag set. + Software can set this bit when host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. + As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. + This bit is cleared by hardware simultaneous with the WAKEUP flag set. + 3 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + Enter L1/L2 suspend + 0x1 + + + + + L2RES + L2 remote wake-up / resume driver + Device mode + The microcontroller can set this bit to send remote wake-up signaling to the host. It must be activated, according to USB specifications, for no less than 1 ms and no more than 15 ms after which the host PC is ready to drive the resume sequence up to its end. + Host mode + Software sets this bit to send resume signaling to the device. + Software clears this bit to send end of resume to device and restart SOF generation. + In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send L2 resume signaling to device + 0x1 + + + + + L1RES + L1 remote wake-up / resume driver + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + send signal to host + 0x1 + + + + + L1REQM + LPM L1 state request interrupt mask + 7 + 1 + read-write + + + B_0x0 + LPM L1 state request (L1REQ) interrupt disabled. + 0x0 + + + B_0x1 + L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ESOFM + Expected start of frame interrupt mask + 8 + 1 + read-write + + + B_0x0 + Expected start of frame (ESOF) interrupt disabled. + 0x0 + + + B_0x1 + ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SOFM + Start of frame interrupt mask + 9 + 1 + read-write + + + B_0x0 + SOF interrupt disabled. + 0x0 + + + B_0x1 + SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + RST_DCONM + USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask + 10 + 1 + read-write + + + B_0x0 + RESET interrupt disabled. + 0x0 + + + B_0x1 + RESET interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SUSPM + Suspend mode interrupt mask + 11 + 1 + read-write + + + B_0x0 + Suspend mode request (SUSP) interrupt disabled. + 0x0 + + + B_0x1 + SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + WKUPM + Wake-up interrupt mask + 12 + 1 + read-write + + + B_0x0 + WKUP interrupt disabled. + 0x0 + + + B_0x1 + WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ERRM + Error interrupt mask + 13 + 1 + read-write + + + B_0x0 + ERR interrupt disabled. + 0x0 + + + B_0x1 + ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + PMAOVRM + Packet memory area over / underrun interrupt mask + 14 + 1 + read-write + + + B_0x0 + PMAOVR interrupt disabled. + 0x0 + + + B_0x1 + PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + CTRM + Correct transfer interrupt mask + 15 + 1 + read-write + + + B_0x0 + Correct transfer (CTR) interrupt disabled. + 0x0 + + + B_0x1 + CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + THR512M + 512 byte threshold interrupt mask + 16 + 1 + read-write + + + B_0x0 + 512 byte threshold interrupt disabled + 0x0 + + + B_0x1 + 512 byte threshold interrupt enabled + 0x1 + + + + + DDISCM + Device disconnection mask + Host mode + 17 + 1 + read-write + + + B_0x0 + Device disconnection interrupt disabled + 0x0 + + + B_0x1 + Device disconnection interrupt enabled + 0x1 + + + + + HOST + HOST mode + HOST bit selects betweens host or device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. + 31 + 1 + read-write + + + B_0x0 + USB Device function + 0x0 + + + B_0x1 + USB host function + 0x1 + + + + + + + USB_ISTR + USB_ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDN + Device Endpoint / host channel identification number + These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: two levels are defined, in order of priority: isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only. + 0 + 4 + read-only + + + DIR + Direction of transaction + This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. + If DIR bit = 0, VTTX bit is set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). + If DIR bit = 1, VTRX bit or both VTTX/VTRX are set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. + This information can be used by the application software to access the USB_CHEPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + Device mode + This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only 0 can be written and writing 1 has no effect. + 7 + 1 + read-write + + + ESOF + Expected start of frame + Device mode + This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1 ms, but if the device does not receive it properly, the suspend timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the suspend timer is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect. + 8 + 1 + read-write + + + SOF + Start of frame + This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this can be useful for isochronous applications). This bit is read/write but only 0 can be written and writing 1 has no effect. + 9 + 1 + read-write + + + RST_DCON + USB reset request (Device mode) or device connect/disconnect (Host mode) + Device mode + This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. + Host mode + This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22 cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times consecutively from connected state. + 10 + 1 + read-write + + + SUSP + Suspend mode request + Device mode + This bit is set by the hardware when no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can be written and writing 1 has no effect. + 11 + 1 + read-write + + + WKUP + Wake-up + This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (for example wake-up unit) about the start of the resume process. This bit is read/write but only 0 can be written and writing 1 has no effect. + 12 + 1 + read-write + + + ERR + Error + This flag is set whenever one of the errors listed below has occurred: + NANS: No ANSwer. The timeout for a host response has expired. + CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in the data, was wrong. + BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. + FVIO: Framing format violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). + The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (for example loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only 0 can be written and writing 1 has no effect. + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / underrun + This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host retries the transaction. The PMAOVR interrupt must never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only 0 can be written and writing 1 has no effect. + 14 + 1 + read-write + + + CTR + Completed transfer in host mode + This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and IDN bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. + 15 + 1 + read-only + + + THR512 + 512 byte threshold interrupt + This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. + 16 + 1 + read-write + + + DDISC + Device connection + Host mode + This bit is set when a device connection is detected. This bit is read/write but only 0 can be written and writing 1 has no effect. + 17 + 1 + read-write + + + DCON_STAT + Device connection status + Host mode: + This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected. + 29 + 1 + read-only + + + B_0x0 + No device connected + 0x0 + + + B_0x1 + FS or LS device connected to the host + 0x1 + + + + + LS_DCON + Low speed device connected + Host mode: + This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (48 MHz) from the unconnected state. + 30 + 1 + read-only + + + + + USB_FNR + USB_FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFF000 + + + FN + Frame number + This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for isochronous transfers. This bit field is updated on the generation of an SOF interrupt. + 0 + 11 + read-only + + + LSOF + Lost SOF + Device mode + These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. + 11 + 2 + read-only + + + LCK + Locked + Device mode + This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. + 13 + 1 + read-only + + + RXDM + Receive data - line status + This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wake-up event. + 14 + 1 + read-only + + + RXDP + Receive data + line status + This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wake-up event. + 15 + 1 + read-only + + + + + USB_DADDR + USB_DADDR + USB Device address + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADD + Device address + Device mode + These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel address (EA) field in the associated USB_CHEPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. + Host mode + These bits contain the address transmitted with the LPM transaction + 0 + 7 + read-write + + + EF + Enable function + This bit is set by the software to enable the USB Device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at 0 no transactions are handled, irrespective of the settings of USB_CHEPnR registers. + 7 + 1 + read-write + + + + + USB_LPMCSR + USB_LPMCSR + LPM control and status register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPMEN + LPM support enable + Device mode + This bit is set by the software to enable the LPM support within the USB Device. If this bit is at 0 no LPM transactions are handled. + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable + Device mode: + The NYET/ACK is returned only on a successful LPM transaction: + No errors in both the EXT token and the LPM token (else ERROR) + A valid bLinkState = 0001B (L1) is received (else STALL) + 1 + 1 + read-write + + + B_0x0 + the valid LPM token is NYET. + 0x0 + + + B_0x1 + the valid LPM token is ACK. + 0x1 + + + + + REMWAKE + bRemoteWake value + Device mode + This bit contains the bRemoteWake value received with last ACKed LPM Token + 3 + 1 + read-only + + + BESL + BESL value + Device mode + These bits contain the BESL value received with last ACKed LPM Token + 4 + 4 + read-only + + + + + USB_BCDR + USB_BCDR + Battery charging detector + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCDEN + Battery charging detector (BCD) enable + Device mode + This bit is set by the software to enable the BCD support within the USB Device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD must be placed in OFF mode by clearing this bit to 0 in order to allow the normal USB operation. + 0 + 1 + read-write + + + PDEN + Primary detection (PD) mode enable + Device mode + This bit is set by the software to put the BCD into PD mode. Only one detection mode (PD, SD or OFF) must be selected to work correctly. + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode enable + Device mode + This bit is set by the software to put the BCD into SD mode. Only one detection mode (PD, SD or OFF) must be selected to work correctly. + 3 + 1 + read-write + + + PDET + Primary detection (PD) status + Device mode + This bit gives the result of PD. + 5 + 1 + read-only + + + B_0x0 + no BCD support detected (connected to SDP or proprietary device). + 0x0 + + + B_0x1 + BCD support detected (connected to ACA, CDP or DCP). + 0x1 + + + + + SDET + Secondary detection (SD) status + Device mode + This bit gives the result of SD. + 6 + 1 + read-only + + + B_0x0 + CDP detected. + 0x0 + + + B_0x1 + DCP detected. + 0x1 + + + + + PS2DET + DM pull-up detection status + Device mode + This bit is active only during PD and gives the result of comparison between DM voltage level and V<sub>LGC</sub> threshold. In normal situation, the DM level must be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. + 7 + 1 + read-only + + + B_0x0 + Normal port detected (connected to SDP, ACA, CDP or DCP). + 0x0 + + + B_0x1 + PS2 port or proprietary charger detected. + 0x1 + + + + + DPPU_DPD + DP pull-up / DPDM pull-down + Device mode + This bit is set by software to enable the embedded pull-up on DP line. Clearing it to 0 can be used to signal disconnect to the host when needed by the user software. + Host mode + This bit is set by software to enable the embedded pull-down on DP and DM lines. + 15 + 1 + read-write + + + + + + + WWDG + WWDG address block description + WWDG + 0x40002C00 + + 0x0 + 0xC + registers + + + WWDG + Window watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + WWDG control register + 0x000 + 0x20 + read-write + 0x0000007F + 0xFFFFFFFF + + + T + 7-bit counter (MSB to LSB) +These bits contain the value of the watchdog counter, decremented every +(4096 x 2<sup>WDGTB[2:0]</sup>) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). + 0 + 7 + read-write + + + WDGA + Activation bit +This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. + 7 + 1 + read-write + + + B_0x0 + Watchdog disabled + 0x0 + + + B_0x1 + Watchdog enabled + 0x1 + + + + + + + WWDG_CFR + WWDG_CFR + WWDG configuration register + 0x004 + 0x20 + read-write + 0x0000007F + 0xFFFFFFFF + + + W + 7-bit window value +These bits contain the window value to be compared with the down-counter. + 0 + 7 + read-write + + + EWI + Early wake-up interrupt enable +Set by software and cleared by hardware after a reset. When set, an interrupt occurs whenever the counter reaches the value 0x40. + 9 + 1 + read-write + + + WDGTB + Timer base +The timebase of the prescaler can be modified as follows: + 11 + 3 + read-write + + + B_0x0 + CK counter clock (PCLK div 4096) div 1 + 0x0 + + + B_0x1 + CK counter clock (PCLK div 4096) div 2 + 0x1 + + + B_0x2 + CK counter clock (PCLK div 4096) div 4 + 0x2 + + + B_0x3 + CK counter clock (PCLK div 4096) div 8 + 0x3 + + + B_0x4 + CK counter clock (PCLK div 4096) div 16 + 0x4 + + + B_0x5 + CK counter clock (PCLK div 4096) div 32 + 0x5 + + + B_0x6 + CK counter clock (PCLK div 4096) div 64 + 0x6 + + + B_0x7 + CK counter clock (PCLK div 4096) div 128 + 0x7 + + + + + + + WWDG_SR + WWDG_SR + WWDG status register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EWIF + Early wake-up interrupt flag +This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled. + 0 + 1 + read-write + + + + + + + diff --git a/svd/STM32CubeCLT.version b/svd/STM32CubeCLT.version index ace4423..15b989e 100644 --- a/svd/STM32CubeCLT.version +++ b/svd/STM32CubeCLT.version @@ -1 +1 @@ -1.15.1 +1.16.0 diff --git a/svd/STM32G0xx/STM32G030.svd b/svd/STM32G0xx/STM32G030.svd index baad197..f8ec0ec 100644 --- a/svd/STM32G0xx/STM32G030.svd +++ b/svd/STM32G0xx/STM32G030.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G030 - 1.6 + 1.7 STM32G030 CM0 @@ -3968,6 +3968,53 @@ Note: The software is allowed to write this bit only when ADSTART=0 (which ensur + + ECCR2 + ECCR2 + Flash ECC register 2 + 0x01C + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 14 + read-only + + + SYSF_ECC + ECC fail for Corrected ECC Error or + Double ECC Error in info block + 20 + 1 + read-only + + + ECCIE + ECC correction interrupt + enable + 24 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + OPTR OPTR diff --git a/svd/STM32G0xx/STM32G031.svd b/svd/STM32G0xx/STM32G031.svd index 042912b..dadc010 100644 --- a/svd/STM32G0xx/STM32G031.svd +++ b/svd/STM32G0xx/STM32G031.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G031 - 1.6 + 1.7 STM32G031 CM0 @@ -608,7 +608,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G041.svd b/svd/STM32G0xx/STM32G041.svd index 832b203..f359072 100644 --- a/svd/STM32G0xx/STM32G041.svd +++ b/svd/STM32G0xx/STM32G041.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G041 - 1.5 + 1.6 STM32G041 CM0 @@ -608,7 +608,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G050.svd b/svd/STM32G0xx/STM32G050.svd index 1d188f5..010f882 100644 --- a/svd/STM32G0xx/STM32G050.svd +++ b/svd/STM32G0xx/STM32G050.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G050 - 1.3 + 1.4 STM32G050 CM0 @@ -11076,6 +11076,53 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG + + ECCR2 + ECCR2 + Flash ECC register 2 + 0x01C + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 14 + read-only + + + SYSF_ECC + ECC fail for Corrected ECC Error or + Double ECC Error in info block + 20 + 1 + read-only + + + ECCIE + ECC correction interrupt + enable + 24 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + OPTR OPTR diff --git a/svd/STM32G0xx/STM32G051.svd b/svd/STM32G0xx/STM32G051.svd index 58f207e..aac7f04 100644 --- a/svd/STM32G0xx/STM32G051.svd +++ b/svd/STM32G0xx/STM32G051.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G051 - 1.4 + 1.5 STM32G051 CM0 @@ -4074,7 +4074,7 @@ This bit is set by software and cleared by a system reset. It locks the whole co COMP3_CSR - COMP2_CSR + COMP3_CSR Comparator 2 control and status register 0x8 0x20 @@ -12706,7 +12706,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G061.svd b/svd/STM32G0xx/STM32G061.svd index 03d1ea0..a12e766 100644 --- a/svd/STM32G0xx/STM32G061.svd +++ b/svd/STM32G0xx/STM32G061.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G061 - 1.4 + 1.5 STM32G061 CM0 @@ -12772,7 +12772,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G070.svd b/svd/STM32G0xx/STM32G070.svd index 33fbad3..9b00b03 100644 --- a/svd/STM32G0xx/STM32G070.svd +++ b/svd/STM32G0xx/STM32G070.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G070 - 1.9 + 2.0 STM32G070 CM0 @@ -4049,6 +4049,53 @@ Note: The software is allowed to write this bit only when ADSTART=0 (which ensur + + ECCR2 + ECCR2 + Flash ECC register 2 + 0x01C + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 14 + read-only + + + SYSF_ECC + ECC fail for Corrected ECC Error or + Double ECC Error in info block + 20 + 1 + read-only + + + ECCIE + ECC correction interrupt + enable + 24 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + OPTR OPTR diff --git a/svd/STM32G0xx/STM32G071.svd b/svd/STM32G0xx/STM32G071.svd index ef656be..5695d63 100644 --- a/svd/STM32G0xx/STM32G071.svd +++ b/svd/STM32G0xx/STM32G071.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G071 - 2.5 + 2.6 STM32G071 CM0 @@ -689,7 +689,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G081.svd b/svd/STM32G0xx/STM32G081.svd index 33c9d63..b8ea0cf 100644 --- a/svd/STM32G0xx/STM32G081.svd +++ b/svd/STM32G0xx/STM32G081.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G081 - 1.8 + 1.9 STM32G081 CM0 @@ -689,7 +689,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G0B0.svd b/svd/STM32G0xx/STM32G0B0.svd index 0c78de3..254bcbf 100644 --- a/svd/STM32G0xx/STM32G0B0.svd +++ b/svd/STM32G0xx/STM32G0B0.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G0B0 - 1.6 + 1.7 STM32G0B0 CM0 @@ -10441,6 +10441,53 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG + + ECCR2 + ECCR2 + Flash ECC register 2 + 0x01C + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 14 + read-only + + + SYSF_ECC + ECC fail for Corrected ECC Error or + Double ECC Error in info block + 20 + 1 + read-only + + + ECCIE + ECC correction interrupt + enable + 24 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + OPTR OPTR @@ -10532,7 +10579,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG 1 - + WRP1AR WRP1AR diff --git a/svd/STM32G0xx/STM32G0B1.svd b/svd/STM32G0xx/STM32G0B1.svd index 23f786f..67fc76b 100644 --- a/svd/STM32G0xx/STM32G0B1.svd +++ b/svd/STM32G0xx/STM32G0B1.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G0B1 - 1.8 + 1.9 STM32G0B1 CM0 @@ -16111,7 +16111,7 @@ These are protected write (P) bits, which means that write access by the bits is ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G0xx/STM32G0C1.svd b/svd/STM32G0xx/STM32G0C1.svd index 0f7e07a..5a58360 100644 --- a/svd/STM32G0xx/STM32G0C1.svd +++ b/svd/STM32G0xx/STM32G0C1.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32G0C1 - 1.8 + 1.9 STM32G0C1 CM0 @@ -17012,7 +17012,7 @@ These are protected write (P) bits, which means that write access by the bits is ADDR_ECC ECC fail address 0 - 15 + 14 read-only diff --git a/svd/STM32G4xx/STM32G431.svd b/svd/STM32G4xx/STM32G431.svd index 1af6c54..89e2e13 100644 --- a/svd/STM32G4xx/STM32G431.svd +++ b/svd/STM32G4xx/STM32G431.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G431 - 2.2 + 2.4 STM32G431 CM4 @@ -1594,7 +1594,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -24863,6 +24863,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -24893,6 +24899,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G441.svd b/svd/STM32G4xx/STM32G441.svd index eec1dea..31339a1 100644 --- a/svd/STM32G4xx/STM32G441.svd +++ b/svd/STM32G4xx/STM32G441.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G441 - 2.2 + 2.4 STM32G441 CM4 @@ -1594,7 +1594,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -24863,6 +24863,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -24893,6 +24899,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G471.svd b/svd/STM32G4xx/STM32G471.svd index a994cc3..c387e2d 100644 --- a/svd/STM32G4xx/STM32G471.svd +++ b/svd/STM32G4xx/STM32G471.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G471 - 2.2 + 2.4 STM32G471 CM4 @@ -1608,7 +1608,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -25320,6 +25320,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -25350,6 +25356,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G473.svd b/svd/STM32G4xx/STM32G473.svd index 2d4643a..f5d9201 100644 --- a/svd/STM32G4xx/STM32G473.svd +++ b/svd/STM32G4xx/STM32G473.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G473 - 2.3 + 2.5 STM32G473 CM4 @@ -1620,7 +1620,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -25332,6 +25332,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -25362,6 +25368,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G474.svd b/svd/STM32G4xx/STM32G474.svd index d845449..db065b0 100644 --- a/svd/STM32G4xx/STM32G474.svd +++ b/svd/STM32G4xx/STM32G474.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G474 - 2.2 + 2.4 STM32G474 CM4 @@ -1608,7 +1608,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -24798,6 +24798,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -24828,6 +24834,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G483.svd b/svd/STM32G4xx/STM32G483.svd index 7be9d74..e3980e8 100644 --- a/svd/STM32G4xx/STM32G483.svd +++ b/svd/STM32G4xx/STM32G483.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G483 - 2.2 + 2.4 STM32G483 CM4 @@ -1608,7 +1608,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -25320,6 +25320,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -25350,6 +25356,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G484.svd b/svd/STM32G4xx/STM32G484.svd index 03c4b42..e95f47b 100644 --- a/svd/STM32G4xx/STM32G484.svd +++ b/svd/STM32G4xx/STM32G484.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G484 - 2.2 + 2.4 STM32G484 CM4 @@ -1608,7 +1608,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -25320,6 +25320,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -25350,6 +25356,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G491.svd b/svd/STM32G4xx/STM32G491.svd index 5787861..dba57c5 100644 --- a/svd/STM32G4xx/STM32G491.svd +++ b/svd/STM32G4xx/STM32G491.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G491 - 2.0 + 2.2 STM32G491 CM4 @@ -1594,7 +1594,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -24350,6 +24350,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -24380,6 +24386,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32G4xx/STM32G4A1.svd b/svd/STM32G4xx/STM32G4A1.svd index cf0b7e9..de1233c 100644 --- a/svd/STM32G4xx/STM32G4A1.svd +++ b/svd/STM32G4xx/STM32G4A1.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32G4A1 - 2.0 + 2.2 STM32G4A1 CM4 @@ -1594,7 +1594,7 @@ Copyright (c) 2024 STMicroelectronics. SEC_SIZE1 SEC_SIZE1 0 - 8 + 7 @@ -24872,6 +24872,12 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 16 1 + + PIF17 + Pending bit 17 + 17 + 1 + PIF18 Pending bit 18 @@ -24902,6 +24908,24 @@ This bit is only valid for the main regulator in range 1 and has no effect on ra 22 1 + + PIF29 + Pending bit 29 + 29 + 1 + + + PIF30 + Pending bit 30 + 30 + 1 + + + PIF31 + Pending bit 31 + 31 + 1 + diff --git a/svd/STM32H7xx/STM32H723.svd b/svd/STM32H7xx/STM32H723.svd index 402b684..3830d36 100644 --- a/svd/STM32H7xx/STM32H723.svd +++ b/svd/STM32H7xx/STM32H723.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H723 - 1.7 + 1.8 STM32H723 CM7 @@ -5248,114 +5248,61 @@ Note: The software is allowed to write these bits only when ADSTART = 0 and JADS - EXTSEL0 + EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL1 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 6 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL2 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 7 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL3 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 8 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL4 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 9 - 1 + 5 read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x1F + adc_ext_trg31 + 0x1F + + EXTEN diff --git a/svd/STM32H7xx/STM32H725.svd b/svd/STM32H7xx/STM32H725.svd index 635a76b..2777167 100644 --- a/svd/STM32H7xx/STM32H725.svd +++ b/svd/STM32H7xx/STM32H725.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H725 - 1.6 + 1.7 STM32H725 CM7 @@ -5248,114 +5248,61 @@ Note: The software is allowed to write these bits only when ADSTART = 0 and JADS - EXTSEL0 + EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL1 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 6 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL2 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 7 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL3 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 8 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL4 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 9 - 1 + 5 read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x1F + adc_ext_trg31 + 0x1F + + EXTEN diff --git a/svd/STM32H7xx/STM32H730.svd b/svd/STM32H7xx/STM32H730.svd index e3df811..e515125 100644 --- a/svd/STM32H7xx/STM32H730.svd +++ b/svd/STM32H7xx/STM32H730.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H730 - 1.3 + 1.4 STM32H730 CM7 @@ -5248,114 +5248,61 @@ Note: The software is allowed to write these bits only when ADSTART = 0 and JADS - EXTSEL0 + EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL1 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 6 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL2 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 7 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL3 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 8 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL4 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 9 - 1 + 5 read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x1F + adc_ext_trg31 + 0x1F + + EXTEN diff --git a/svd/STM32H7xx/STM32H733.svd b/svd/STM32H7xx/STM32H733.svd index 4f52c22..f56aa8c 100644 --- a/svd/STM32H7xx/STM32H733.svd +++ b/svd/STM32H7xx/STM32H733.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H733 - 1.3 + 1.4 STM32H733 CM7 @@ -5248,114 +5248,61 @@ Note: The software is allowed to write these bits only when ADSTART = 0 and JADS - EXTSEL0 + EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL1 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 6 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL2 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 7 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL3 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 8 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL4 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 9 - 1 + 5 read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x1F + adc_ext_trg31 + 0x1F + + EXTEN diff --git a/svd/STM32H7xx/STM32H735.svd b/svd/STM32H7xx/STM32H735.svd index 7b365af..4fb80b6 100644 --- a/svd/STM32H7xx/STM32H735.svd +++ b/svd/STM32H7xx/STM32H735.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H735 - 1.3 + 1.4 STM32H735 CM7 @@ -5248,114 +5248,61 @@ Note: The software is allowed to write these bits only when ADSTART = 0 and JADS - EXTSEL0 + EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL1 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 6 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL2 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 7 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL3 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 8 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - - - EXTSEL4 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 9 - 1 + 5 read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x1F + adc_ext_trg31 + 0x1F + + EXTEN diff --git a/svd/STM32H7xx/STM32H73x.svd b/svd/STM32H7xx/STM32H73x.svd index aa8ae2a..9de0d5c 100644 --- a/svd/STM32H7xx/STM32H73x.svd +++ b/svd/STM32H7xx/STM32H73x.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H73x - 1.7 + 1.8 STM32H73x CM7 @@ -704,22 +704,22 @@ When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero B_0x0 - used when ADC clock ≤ 6.25 MHz + used when ADC clock less than or equal 6.25 MHz 0x0 B_0x1 - used when 6.25 MHz < ADC clock frequency≤ 12.5 MHz + used when 6.25 MHz < ADC clock frequencyless than or equal 12.5 MHz 0x1 B_0x2 - used when 12.5 MHz < ADC clock ≤25.0 MHz + used when 12.5 MHz < ADC clock less than or equal25.0 MHz 0x2 B_0x3 - used when 25.0 MHz < ADC clock ≤ 50.0 MHz + used when 25.0 MHz < ADC clock less than or equal 50.0 MHz 0x3 @@ -5248,289 +5248,61 @@ Note: The software is allowed to write these bits only when ADSTART = 0 and JADS - EXTSEL0 + EXTSEL External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 5 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - B_0x2 - adc_ext_trg2 - 0x2 - - - B_0x3 - adc_ext_trg3 - 0x3 - - - B_0x4 - adc_ext_trg4 - 0x4 - - - B_0x5 - adc_ext_trg5 - 0x5 - - - B_0x6 - adc_ext_trg6 - 0x6 - - - B_0x7 - adc_ext_trg7 - 0x7 - - - B_0x1F - adc_ext_trg31 - 0x1F - - - - - EXTSEL1 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 6 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - B_0x2 - adc_ext_trg2 - 0x2 - - - B_0x3 - adc_ext_trg3 - 0x3 - - - B_0x4 - adc_ext_trg4 - 0x4 - - - B_0x5 - adc_ext_trg5 - 0x5 - - - B_0x6 - adc_ext_trg6 - 0x6 - - - B_0x7 - adc_ext_trg7 - 0x7 - - - B_0x1F - adc_ext_trg31 - 0x1F - - - - - EXTSEL2 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 7 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - B_0x2 - adc_ext_trg2 - 0x2 - - - B_0x3 - adc_ext_trg3 - 0x3 - - - B_0x4 - adc_ext_trg4 - 0x4 - - - B_0x5 - adc_ext_trg5 - 0x5 - - - B_0x6 - adc_ext_trg6 - 0x6 - - - B_0x7 - adc_ext_trg7 - 0x7 - - - B_0x1F - adc_ext_trg31 - 0x1F - - - - - EXTSEL3 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 8 - 1 - read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - B_0x2 - adc_ext_trg2 - 0x2 - - - B_0x3 - adc_ext_trg3 - 0x3 - - - B_0x4 - adc_ext_trg4 - 0x4 - - - B_0x5 - adc_ext_trg5 - 0x5 - - - B_0x6 - adc_ext_trg6 - 0x6 - - - B_0x7 - adc_ext_trg7 - 0x7 - - - B_0x1F - adc_ext_trg31 - 0x1F - - - - - EXTSEL4 - External trigger selection for regular group -These bits select the external event used to trigger the start of conversion of a regular group: -... -Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). - 9 - 1 + 5 read-write - - - B_0x0 - adc_ext_trg0 - 0x0 - - - B_0x1 - adc_ext_trg1 - 0x1 - - - B_0x2 - adc_ext_trg2 - 0x2 - - - B_0x3 - adc_ext_trg3 - 0x3 - - - B_0x4 - adc_ext_trg4 - 0x4 - - - B_0x5 - adc_ext_trg5 - 0x5 - - - B_0x6 - adc_ext_trg6 - 0x6 - - - B_0x7 - adc_ext_trg7 - 0x7 - - - B_0x1F - adc_ext_trg31 - 0x1F - - + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x1F + adc_ext_trg31 + 0x1F + + EXTEN @@ -10856,7 +10628,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -11313,7 +11085,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -11770,7 +11542,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -12227,7 +11999,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -12684,7 +12456,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -13141,7 +12913,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -13598,7 +13370,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -14055,7 +13827,7 @@ It is read-only when the channel is enabled (EN = 1). NDT number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: -It is decremented after each single BDMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. +It is decremented after each single BDMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the BDMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). @@ -73563,12 +73335,12 @@ Note: Only accessible in host mode. B_0x0 - Long debounce time, used for physical connections (100 ms + 2.5 µs) + Long debounce time, used for physical connections (100 ms + 2.5 us) 0x0 B_0x1 - Short debounce time, used for soft connections (2.5 µs) + Short debounce time, used for soft connections (2.5 us) 0x1 @@ -74145,7 +73917,7 @@ Disables IN endpoints Flushes the FIFO Determines the token sequence from the IN token sequence learning queue Re-enables the endpoints -Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an “IN token received when FIFO empty” interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the “IN token received when FIFO empty” interrupt when clearing a global IN NAK handshake. +Clears the global nonperiodic IN NAK handshake If the global nonperiodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an IN token received when FIFO empty interrupt. The OTG then sends a NAK response to the host. To avoid this scenario, the application can check the FetSusp interrupt in OTG_GINTSTS, which ensures that the FIFO is full before clearing a global NAK handshake. Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a global IN NAK handshake. 22 1 read-write @@ -81255,8 +81027,8 @@ Note: When this bit is set region context (version, key, nonce) must be valid or CONFIGLOCK region config lock -This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. -Setting this bit forces KEYLOCK bit to “1”. +This bit-field is set once, i.e. if this bit is set it can only be reset to '0' if OTFDEC is reset. +Setting this bit forces KEYLOCK bit to '1'. 1 1 read-write @@ -81276,7 +81048,7 @@ Setting this bit forces KEYLOCK bit to “1”. KEYLOCK region key lock -This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset. +This bitfield is set once, i.e. if this bit is set it can only be reset to '0' if the OTFDEC is reset. 2 1 read-write @@ -81298,7 +81070,7 @@ This bitfield is set once, i.e. if this bit is set it can only be reset to “0 operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. -When either of the MODE bits are changed the region’s key and associated CRC are zeroed. +When either of the MODE bits are changed the region's key and associated CRC are zeroed. 4 2 read-write @@ -81540,8 +81312,8 @@ Note: When this bit is set region context (version, key, nonce) must be valid or CONFIGLOCK region config lock -This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. -Setting this bit forces KEYLOCK bit to “1”. +This bit-field is set once, i.e. if this bit is set it can only be reset to '0' if OTFDEC is reset. +Setting this bit forces KEYLOCK bit to '1'. 1 1 read-write @@ -81561,7 +81333,7 @@ Setting this bit forces KEYLOCK bit to “1”. KEYLOCK region key lock -This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset. +This bitfield is set once, i.e. if this bit is set it can only be reset to '0' if the OTFDEC is reset. 2 1 read-write @@ -81583,7 +81355,7 @@ This bitfield is set once, i.e. if this bit is set it can only be reset to “0 operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. -When either of the MODE bits are changed the region’s key and associated CRC are zeroed. +When either of the MODE bits are changed the region's key and associated CRC are zeroed. 4 2 read-write @@ -81825,8 +81597,8 @@ Note: When this bit is set region context (version, key, nonce) must be valid or CONFIGLOCK region config lock -This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. -Setting this bit forces KEYLOCK bit to “1”. +This bit-field is set once, i.e. if this bit is set it can only be reset to '0' if OTFDEC is reset. +Setting this bit forces KEYLOCK bit to '1'. 1 1 read-write @@ -81846,7 +81618,7 @@ Setting this bit forces KEYLOCK bit to “1”. KEYLOCK region key lock -This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset. +This bitfield is set once, i.e. if this bit is set it can only be reset to '0' if the OTFDEC is reset. 2 1 read-write @@ -81868,7 +81640,7 @@ This bitfield is set once, i.e. if this bit is set it can only be reset to “0 operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. -When either of the MODE bits are changed the region’s key and associated CRC are zeroed. +When either of the MODE bits are changed the region's key and associated CRC are zeroed. 4 2 read-write @@ -82110,8 +81882,8 @@ Note: When this bit is set region context (version, key, nonce) must be valid or CONFIGLOCK region config lock -This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. -Setting this bit forces KEYLOCK bit to “1”. +This bit-field is set once, i.e. if this bit is set it can only be reset to '0' if OTFDEC is reset. +Setting this bit forces KEYLOCK bit to '1'. 1 1 read-write @@ -82131,7 +81903,7 @@ Setting this bit forces KEYLOCK bit to “1”. KEYLOCK region key lock -This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset. +This bitfield is set once, i.e. if this bit is set it can only be reset to '0' if the OTFDEC is reset. 2 1 read-write @@ -82153,7 +81925,7 @@ This bitfield is set once, i.e. if this bit is set it can only be reset to “0 operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. -When either of the MODE bits are changed the region’s key and associated CRC are zeroed. +When either of the MODE bits are changed the region's key and associated CRC are zeroed. 4 2 read-write @@ -82376,7 +82148,7 @@ Refer to the OTFDEC_RxKEYR0 register for description of the KEY[127:0] bitfield. SEIF Security Error Interrupt Flag status This bit is set by hardware and read only by application. Bit is set when at least one security error has been detected (illegal access to keys, illegal write on locked configuration). -Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1”. +Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to '1'. 0 1 read-only @@ -82397,7 +82169,7 @@ Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1 XONEIF Execute-only execute-Never Error Interrupt Flag status This bit is set by hardware and read only by application. Bit is set when a read access and not an instruction fetch is detected on any encrypted region with MODE bits set to 00 or 11. It is also set when an instruction fetch and not a read access is detected on any encrypted region with MODE bits set to 01. -Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1”. +Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to '1'. 1 1 read-only @@ -82409,7 +82181,7 @@ Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1 B_0x1 - Read access detected on one region with MODE bits set to 00 or 11, or execute access detected on one region with MODE bits set to 01. OTFDEC returns a zeroed value for the illegal access, and an optional interrupt is generated if bit XONEIE is set to “1” in OTFDEC_IER register. + Read access detected on one region with MODE bits set to 00 or 11, or execute access detected on one region with MODE bits set to 01. OTFDEC returns a zeroed value for the illegal access, and an optional interrupt is generated if bit XONEIE is set to '1' in OTFDEC_IER register. 0x1 @@ -82418,7 +82190,7 @@ Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1 KEIF Key Error Interrupt Flag status This bit is set by hardware and read only by application. Bit is set when a read access occurs on any encrypted region following the reset of the key registers by an abort event (tamper detection, unauthorized debugger connection, untrusted boot, RDP level regression). -Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to “1”. +Bit is cleared when application sets in OTFDEC_ICR the corresponding bit to '1'. After KEIF is set any subsequent read to any enabled encrypted region returns a zeroed value. This state remains until OTFDEC keys are initialized again. 2 1 @@ -82431,7 +82203,7 @@ After KEIF is set any subsequent read to any enabled encrypted region returns a B_0x1 - Read access detected on an enabled encrypted region following an abort event. OTFDEC returns a zeroed value for the read, and an optional interrupt is generated if bit KEIE is set to “1” in OTFDEC_IER register. + Read access detected on an enabled encrypted region following an abort event. OTFDEC returns a zeroed value for the read, and an optional interrupt is generated if bit KEIE is set to '1' in OTFDEC_IER register. 0x1 @@ -85815,7 +85587,7 @@ This field represents the sum of engineering option byte calibration value and H HSITRIM HSI clock trimming Set by software to adjust calibration. -HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. +HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40. 24 7 @@ -85867,7 +85639,7 @@ This field represents the sum of engineering option byte calibration value and C CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. -CSICAL = CSITRIM + FLASH_CSI_opt. +CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20. 24 6 diff --git a/svd/STM32H7xx/STM32H7A3.svd b/svd/STM32H7xx/STM32H7A3.svd index a605dbe..6469f24 100644 --- a/svd/STM32H7xx/STM32H7A3.svd +++ b/svd/STM32H7xx/STM32H7A3.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H7A3 - 2.8 + 2.9 STM32H7A3 CM7 @@ -4740,6 +4740,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -4913,6 +4925,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5086,6 +5110,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5259,6 +5295,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5432,6 +5480,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5605,6 +5665,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5778,6 +5850,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5951,6 +6035,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + diff --git a/svd/STM32H7xx/STM32H7B0.svd b/svd/STM32H7xx/STM32H7B0.svd index b2ebada..08802ba 100644 --- a/svd/STM32H7xx/STM32H7B0.svd +++ b/svd/STM32H7xx/STM32H7B0.svd @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32H7B0 - 1.8 + 1.9 STM32H7B0 CM7 @@ -110574,6 +110574,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -110747,6 +110759,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -110920,6 +110944,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -111093,6 +111129,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -111266,6 +111314,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -111439,6 +111499,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -111612,6 +111684,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -111785,6 +111869,18 @@ In the default configuration this register is reset on a tamper detection event. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + diff --git a/svd/STM32H7xx/STM32H7B3.svd b/svd/STM32H7xx/STM32H7B3.svd index f98998d..1c94ad3 100644 --- a/svd/STM32H7xx/STM32H7B3.svd +++ b/svd/STM32H7xx/STM32H7B3.svd @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics. --> STM32H7B3 - 2.8 + 2.9 STM32H7B3 CM7 @@ -4740,6 +4740,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -4913,6 +4925,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5086,6 +5110,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5259,6 +5295,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5432,6 +5480,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5605,6 +5665,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5778,6 +5850,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + @@ -5951,6 +6035,18 @@ Copyright (c) 2024 STMicroelectronics. 14 1 + + DBM + double-buffer mode + 15 + 1 + + + CT + current target memory of DMA transfer in double-buffer mode. + 16 + 1 + diff --git a/svd/STM32L4xx/STM32L412.svd b/svd/STM32L4xx/STM32L412.svd index 961c632..aaf05f2 100644 --- a/svd/STM32L4xx/STM32L412.svd +++ b/svd/STM32L4xx/STM32L412.svd @@ -1,6 +1,6 @@ STM32L476 - 1.4 + 1.6 STM32L476 CM4 @@ -22474,6 +22474,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + OC2CE Output compare 2 clear enable @@ -22593,6 +22605,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + OC4CE Output compare 4 clear enable @@ -24714,6 +24738,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + OC2CE Output Compare 2 clear enable @@ -24833,6 +24869,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + OC4CE Output compare 4 clear enable @@ -26018,6 +26066,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + OC2CE Output Compare 2 clear enable @@ -26137,6 +26197,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + OC4CE Output compare 4 clear enable diff --git a/svd/STM32L4xx/STM32L496.svd b/svd/STM32L4xx/STM32L496.svd index 23888f9..3e8f57c 100644 --- a/svd/STM32L4xx/STM32L496.svd +++ b/svd/STM32L4xx/STM32L496.svd @@ -1,6 +1,6 @@ STM32L496 - 1.4 + 1.6 STM32L496 CM4 @@ -22864,6 +22864,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + OC2CE Output compare 2 clear enable @@ -22983,6 +22995,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + OC4CE Output compare 4 clear enable @@ -25104,6 +25128,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + OC2CE Output Compare 2 clear enable @@ -25223,6 +25259,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + OC4CE Output compare 4 clear enable @@ -26408,6 +26456,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC2M_bit3 + Output Compare 2 mode + 24 + 1 + + + OC1M_bit3 + Output Compare 1 mode + 16 + 1 + OC2CE Output Compare 2 clear enable @@ -26527,6 +26587,18 @@ This bit is written by software to clear the UDD flag in the LCD_SR register.read-write 0x00000000 + + OC4M_bit3 + Output Compare 4 mode + 24 + 1 + + + OC3M_bit3 + Output Compare 3 mode + 16 + 1 + OC4CE Output compare 4 clear enable diff --git a/svd/STM32L4xx/STM32L4x1.svd b/svd/STM32L4xx/STM32L4x1.svd index 102ef5f..5f852ae 100644 --- a/svd/STM32L4xx/STM32L4x1.svd +++ b/svd/STM32L4xx/STM32L4x1.svd @@ -1,6 +1,6 @@ STM32L4x3 - 2.0 + 2.1 STM32L4x3 CM4 diff --git a/svd/STM32L4xx/STM32L4x5.svd b/svd/STM32L4xx/STM32L4x5.svd index a27e199..4559343 100644 --- a/svd/STM32L4xx/STM32L4x5.svd +++ b/svd/STM32L4xx/STM32L4x5.svd @@ -1,6 +1,6 @@ + + STM32U031 + 1.0 + STM32U031 + + CM0+ + r0p1 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x40012400 + + 0x0 + 0x30C + registers + + + ADC_COMP + ADC and COMP interrupts (ADC combined with EXTI lines 17 and 18) + 12 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready +This bit is set by hardware after the ADC has been enabled (ADEN+1) and when the ADC reaches a state where it is ready to accept conversion requests. +It is cleared by software writing 1 to it. + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag +This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1. + 1 + 1 + read-write + + + B_0x0 + Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag +This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. + 2 + 1 + read-write + + + B_0x0 + Channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Channel conversion complete + 0x1 + + + + + EOS + End of sequence flag +This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. + 3 + 1 + read-write + + + B_0x0 + Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Conversion sequence complete + 0x1 + + + + + OVR + ADC overrun +This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + AWD1 + Analog watchdog 1 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. + 7 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. + 8 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. + 9 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + EOCAL + End Of Calibration flag +This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. + 11 + 1 + read-write + + + B_0x0 + Calibration is not complete + 0x0 + + + B_0x1 + Calibration is complete + 0x1 + + + + + CCRDY + Channel Configuration Ready flag +This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. +Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. + 13 + 1 + read-write + + + B_0x0 + Channel configuration update not applied. + 0x0 + + + B_0x1 + Channel configuration update is applied. + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable +This bit is set and cleared by software to enable/disable the ADC Ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled. + 0x0 + + + B_0x1 + ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable +This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. + 0x1 + + + + + EOCIE + End of conversion interrupt enable +This bit is set and cleared by software to enable/disable the end of conversion interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled + 0x0 + + + B_0x1 + EOC interrupt enabled. An interrupt is generated when the EOC bit is set. + 0x1 + + + + + EOSIE + End of conversion sequence interrupt enable +This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. An interrupt is generated when the EOS bit is set. + 0x1 + + + + + OVRIE + Overrun interrupt enable +This bit is set and cleared by software to enable/disable the overrun interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + EOCALIE + End of calibration interrupt enable +This bit is set and cleared by software to enable/disable the end of calibration interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + End of calibration interrupt disabled + 0x0 + + + B_0x1 + End of calibration interrupt enabled + 0x1 + + + + + CCRDYIE + Channel Configuration Ready Interrupt enable +This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Channel configuration ready interrupt disabled + 0x0 + + + B_0x1 + Channel configuration ready interrupt enabled + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADEN + ADC enable command +This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. +It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command + 1 + 1 + read-write + + + B_0x0 + No ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. + 0x1 + + + + + ADSTART + ADC start conversion command + 2 + 1 + read-write + + + B_0x0 + No ADC conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. + 0x1 + + + + + ADSTP + ADC stop conversion command + 4 + 1 + read-write + + + B_0x0 + No ADC stop conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. + 0x1 + + + + + ADVREGEN + ADC Voltage Regulator Enable + 28 + 1 + read-write + + + B_0x0 + ADC voltage regulator disabled + 0x0 + + + B_0x1 + ADC voltage regulator enabled + 0x1 + + + + + ADCAL + ADC calibration +This bit is set by software to start the calibration of the ADC. + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. + 0x1 + + + + + + + ADC_CFGR1 + ADC_CFGR1 + ADC configuration register 1 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable +This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration +This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN1=11. +For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. + 1 + 1 + read-write + + + B_0x0 + DMA one shot mode selected + 0x0 + + + B_0x1 + DMA circular mode selected + 0x1 + + + + + SCANDIR + Scan sequence direction +This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Upward scan (from CHSEL0 to CHSEL) + 0x0 + + + B_0x1 + Backward scan (from CHSEL to CHSEL0) + 0x1 + + + + + RES + Data resolution +These bits are written by software to select the resolution of the conversion. + 3 + 2 + read-write + + + B_0x0 + 12 bits + 0x0 + + + B_0x1 + 10 bits + 0x1 + + + B_0x2 + 8 bits + 0x2 + + + B_0x3 + 6 bits + 0x3 + + + + + ALIGN + Data alignment +This bit is set and cleared by software to select right or left alignment. Refer to Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332 + 5 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + EXTSEL + External trigger selection +These bits select the external event used to trigger the start of conversion (refer to Table160: External triggers for details): + 6 + 3 + read-write + + + B_0x0 + TRG0 + 0x0 + + + B_0x1 + TRG1 + 0x1 + + + B_0x2 + TRG2 + 0x2 + + + B_0x3 + TRG3 + 0x3 + + + B_0x4 + TRG4 + 0x4 + + + B_0x5 + TRG5 + 0x5 + + + B_0x6 + TRG6 + 0x6 + + + B_0x7 + TRG7 + 0x7 + + + + + EXTEN + External trigger enable and polarity selection +These bits are set and cleared by software to select the external trigger polarity and enable the trigger. + 10 + 2 + read-write + + + B_0x0 + Hardware trigger detection disabled (conversions can be started by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + OVRMOD + Overrun management mode +This bit is set and cleared by software and configure the way data overruns are managed. + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / continuous conversion mode +This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + WAIT + Wait conversion mode +This bit is set and cleared by software to enable/disable wait conversion mode.<sup>.</sup> + 14 + 1 + read-write + + + B_0x0 + Wait conversion mode off + 0x0 + + + B_0x1 + Wait conversion mode on + 0x1 + + + + + AUTOFF + Auto-off mode +This bit is set and cleared by software to enable/disable auto-off mode.<sup>.</sup> + 15 + 1 + read-write + + + B_0x0 + Auto-off mode disabled + 0x0 + + + B_0x1 + Auto-off mode enabled + 0x1 + + + + + DISCEN + Discontinuous mode +This bit is set and cleared by software to enable/disable discontinuous mode. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode disabled + 0x0 + + + B_0x1 + Discontinuous mode enabled + 0x1 + + + + + CHSELRMOD + Mode selection of the ADC_CHSELR register +This bit is set and cleared by software to control the ADC_CHSELR feature: +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 21 + 1 + read-write + + + B_0x0 + Each bit of the ADC_CHSELR register enables an input + 0x0 + + + B_0x1 + ADC_CHSELR register is able to sequence up to 8 channels + 0x1 + + + + + AWD1SGL + Enable the watchdog on a single channel or on all channels +This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled + 0x0 + + + B_0x1 + Analog watchdog 1 enabled + 0x1 + + + + + AWD1CH + Analog watchdog channel selection +These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. +..... +Others: Reserved +Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. + 26 + 5 + read-write + + + B_0x0 + ADC analog input Channel 0 monitored by AWD + 0x0 + + + B_0x1 + ADC analog input Channel 1 monitored by AWD + 0x1 + + + B_0x13 + ADC analog input Channel 19 monitored by AWD + 0x13 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVSE + Oversampler Enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 0 + 1 + read-write + + + B_0x0 + Oversampler disabled + 0x0 + + + B_0x1 + Oversampler enabled + 0x1 + + + + + OVSR + Oversampling ratio +This bit filed defines the number of oversampling ratio. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift +This bit is set and cleared by software. +Others: Reserved +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TOVS + Triggered Oversampling +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively after a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a trigger + 0x1 + + + + + LFTRIG + Low frequency trigger mode enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 29 + 1 + read-write + + + B_0x0 + Low Frequency Trigger Mode disabled + 0x0 + + + B_0x1 + Low Frequency Trigger Mode enabled + 0x1 + + + + + CKMODE + ADC clock mode +These bits are set and cleared by software to define how the analog ADC is clocked: +In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. +Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10). + 30 + 2 + read-write + + + B_0x0 + ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) + 0x0 + + + B_0x1 + PCLK/2 (Synchronous clock mode) + 0x1 + + + B_0x2 + PCLK/4 (Synchronous clock mode) + 0x2 + + + + + + + ADC_SMPR + ADC_SMPR + ADC sampling time register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMP1 + Sampling time selection 1 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMP2 + Sampling time selection 2 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMPSEL0 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL1 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL2 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL3 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL4 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL5 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL6 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL7 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL8 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL9 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL10 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL11 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL12 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 20 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL13 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 21 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL14 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL15 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL16 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL17 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL18 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 26 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL19 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 27 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + + + ADC_AWD1TR + ADC_AWD1TR + ADC watchdog threshold register + 0x20 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT1 + Analog watchdog 1 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_AWD2TR + ADC_AWD2TR + ADC watchdog threshold register + 0x24 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT2 + Analog watchdog 2 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_CHSELR + ADC_CHSELR + ADC channel selection register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CHSEL0 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 0 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL1 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 1 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL2 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL3 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 3 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL4 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 4 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL5 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 5 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL6 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 6 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL7 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 7 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL8 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 8 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL9 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 9 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL10 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 10 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL11 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 11 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL12 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 12 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL13 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 13 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL14 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 14 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL15 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 15 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL16 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 16 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL17 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 17 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL18 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 18 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL19 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 19 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + + + ADC_CHSELR_ALTERNATE + ADC_CHSELR_ALTERNATE + ADC channel selection register + ADC_CHSELR + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SQ1 + 1st conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 0 + 4 + read-write + + + SQ2 + 2nd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 4 + 4 + read-write + + + SQ3 + 3rd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 4 + read-write + + + SQ4 + 4th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 4 + read-write + + + SQ5 + 5th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 4 + read-write + + + SQ6 + 6th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 20 + 4 + read-write + + + SQ7 + 7th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 24 + 4 + read-write + + + SQ8 + 8th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +... +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 28 + 4 + read-write + + + B_0x0 + CH0 + 0x0 + + + B_0x1 + CH1 + 0x1 + + + B_0xC + CH12 + 0xC + + + B_0xD + CH13 + 0xD + + + B_0xE + CH14 + 0xE + + + B_0xF + No channel selected (End of sequence) + 0xF + + + + + + + ADC_AWD3TR + ADC_AWD3TR + ADC watchdog threshold register + 0x2C + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT3 + Analog watchdog 3 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_DR + ADC_DR + ADC data register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + Converted data +These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD2CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC Analog Watchdog 3 Configuration register + 0xA4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD3CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factor + 0xB4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALFACT + Calibration factor +These bits are written by hardware or by software. +Once a calibration is complete,1they are updated by hardware with the calibration factors. +Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new conversion is launched. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. +Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + 0 + 7 + read-write + + + + + ADC_CCR + ADC_CCR + ADC common configuration register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESC + ADC prescaler +Set and cleared by software to select the frequency of the clock to the ADC. +Other: Reserved +Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10). + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + V<sub>REFINT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>REFINT</sub>. +Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + V<sub>REFINT</sub> disabled + 0x0 + + + B_0x1 + V<sub>REFINT</sub> enabled + 0x1 + + + + + TSEN + Temperature sensor enable +This bit is set and cleared by software to enable/disable the temperature sensor. +Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Temperature sensor disabled + 0x0 + + + B_0x1 + Temperature sensor enabled + 0x1 + + + + + VBATEN + V<sub>BAT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>BAT</sub> channel. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing) + 24 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> channel disabled + 0x0 + + + B_0x1 + V<sub>BAT</sub> channel enabled + 0x1 + + + + + + + + + COMP1 + COMP address block description + COMP + 0x40010200 + + 0x0 + 0x8 + registers + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Comparator 1 enable bit +This bit is controlled by software (if not locked). It enables the comparator 1: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + INMSEL + Comparator 1 signal selector for inverting input INM +This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 1: +Refer to Table176: COMP1 inverting input assignment. + 4 + 4 + read-write + + + INPSEL + Comparator 1 signal selector for noninverting input +This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 1 (also see the WINMODE bit): +Refer to Table175: COMP1 noninverting input assignment. + 8 + 3 + read-write + + + WINMODE + Comparator 1 noninverting input selector for window mode +This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 1: + 11 + 1 + read-write + + + B_0x0 + Signal selected with INPSEL[2:0] bitfield of this register + 0x0 + + + B_0x1 + COMP_INP signal of the comparator 2 (required for window mode, see Figure164) + 0x1 + + + + + WINOUT + Comparator 1 output selector +This bit is controlled by software (if not locked). It selects the comparator 1 output: + 14 + 1 + read-write + + + B_0x0 + COMP_VALUE + 0x0 + + + B_0x1 + COMP_VALUE XOR COMP_VALUE (required for window mode, see Figure164) + 0x1 + + + + + POLARITY + Comparator 1 polarity selector +This bit is controlled by software (if not locked). It selects the comparator 1 output polarity: + 15 + 1 + read-write + + + B_0x0 + Non-inverted + 0x0 + + + B_0x1 + Inverted + 0x1 + + + + + HYST + Comparator 1 hysteresis selector +This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1: + 16 + 2 + read-write + + + B_0x0 + No hysteresis + 0x0 + + + B_0x1 + Low hysteresis + 0x1 + + + B_0x2 + Medium hysteresis + 0x2 + + + B_0x3 + High hysteresis + 0x3 + + + + + PWRMODE + Comparator 1 power mode selector +This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1: + 18 + 2 + read-write + + + B_0x0 + High speed/high power + 0x0 + + + B_0x1 + Medium speed/medium power + 0x1 + + + B_0x2 + Medium speed/medium power + 0x2 + + + B_0x3 + Low speed/low power + 0x3 + + + + + BLANKSEL + Comparator 1 blanking source selector +This bitfield is controlled by software (if not locked). It selects the blanking source: +Others: Reserved, must not be used + 20 + 5 + read-write + + + B_0x0 + No blanking + 0x0 + + + B_0x1 + TIM1 OC4 enabled as blanking source + 0x1 + + + B_0x2 + TIM1 OC5 enabled as blanking source + 0x2 + + + B_0x4 + TIM2 OC3 enabled as blanking source + 0x4 + + + B_0x8 + TIM3 OC3 enabled as blanking source + 0x8 + + + B_0x10 + TIM15 OC2 enabled as blanking source + 0x10 + + + + + VALUE + Comparator 1 output status +This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in Figure163. + 30 + 1 + read-only + + + LOCK + COMP_CSR register lock +This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. + 31 + 1 + read-write + + + B_0x0 + Not locked + 0x0 + + + B_0x1 + Locked + 0x1 + + + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Comparator 2 enable bit +This bit is controlled by software (if not locked). It enables the comparator 2: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + INMSEL + Comparator 2 signal selector for inverting input INM +This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 2: +Refer to Table178: COMP2 inverting input assignment. + 4 + 4 + read-write + + + INPSEL + Comparator 2 signal selector for noninverting input +This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 2 (also see the WINMODE bit): +Refer to Table177: COMP2 noninverting input assignment. + 8 + 2 + read-write + + + WINMODE + Comparator 2 noninverting input selector for window mode +This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 2: + 11 + 1 + read-write + + + B_0x0 + Signal selected with INPSEL[1:0] bitfield of this register + 0x0 + + + B_0x1 + COMP_INP signal of the comparator 1 (required for window mode, see Figure164) + 0x1 + + + + + WINOUT + Comparator 2 output selector +This bit is controlled by software (if not locked). It selects the comparator 2 output: + 14 + 1 + read-write + + + B_0x0 + COMP_VALUE + 0x0 + + + B_0x1 + COMP_VALUE XOR COMP_VALUE (required for window mode, see Figure164) + 0x1 + + + + + POLARITY + Comparator 2 polarity selector +This bit is controlled by software (if not locked). It selects the comparator 2 output polarity: + 15 + 1 + read-write + + + B_0x0 + Non-inverted + 0x0 + + + B_0x1 + Inverted + 0x1 + + + + + HYST + Comparator 2 hysteresis selector +This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2: + 16 + 2 + read-write + + + B_0x0 + No hysteresis + 0x0 + + + B_0x1 + Low hysteresis + 0x1 + + + B_0x2 + Medium hysteresis + 0x2 + + + B_0x3 + High hysteresis + 0x3 + + + + + PWRMODE + Comparator 2 power mode selector +This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2: + 18 + 2 + read-write + + + B_0x0 + High speed/high power + 0x0 + + + B_0x1 + Medium speed/medium power + 0x1 + + + B_0x2 + Medium speed/medium power + 0x2 + + + B_0x3 + Low speed/low power + 0x3 + + + + + BLANKSEL + Comparator 2 blanking source selector +This bitfield is controlled by software (if not locked). It selects the blanking source: +Others: Reserved, must not be used + 20 + 5 + read-write + + + B_0x0 + No blanking + 0x0 + + + B_0x1 + TIM1 OC4 enabled as blanking source + 0x1 + + + B_0x2 + TIM1 OC5 enabled as blanking source + 0x2 + + + B_0x4 + TIM2 OC3 enabled as blanking source + 0x4 + + + B_0x8 + TIM3 OC3 enabled as blanking source + 0x8 + + + B_0x10 + TIM15 OC2 enabled as blanking source + 0x10 + + + + + VALUE + Comparator 2 output status +This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in Figure163. + 30 + 1 + read-only + + + LOCK + COMP_CSR register lock +This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. + 31 + 1 + read-write + + + B_0x0 + Not locked + 0x0 + + + B_0x1 + Locked + 0x1 + + + + + + + + + CRC + CRC address block description + CRC + 0x40023000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected (RTYPE_IN1=10 or 1) + 0x0 + + + B_0x1 + Bit reversal done by byte (RTYPE_IN1=10) or half-word reversal done by word (RTYPE_IN1=11) + 0x1 + + + B_0x2 + Bit reversal done by half-word (RTYPE_IN1=10) or byte reversal done by word (RTYPE_IN1=11) + 0x2 + + + B_0x3 + Bit reversal done by word (RTYPE_IN1=10) or bit order is not affected (RTYPE_IN1=11) + 0x3 + + + + + REV_OUT + Reverse output data +This bitfield controls the reversal of the bit order of the output data. + 7 + 2 + read-write + + + B_0x0 + Bit order not affected (RTYPE_OUT1=10 or 1) + 0x0 + + + B_0x1 + Bit-reversed output format (RTYPE_OUT1=10) or half-word reversal done by word (RTYPE_OUT1=11) + 0x1 + + + B_0x2 + Bit order not affected (RTYPE_OUT1=10) or byte reversal done by word (RTYPE_OUT1=11) + 0x2 + + + B_0x3 + Bit order not affected (RTYPE_OUT1=10 or 1) + 0x3 + + + + + RTYPE_IN + Reverse type input +This bit controls the reversal granularity of the input data. + 9 + 1 + read-write + + + B_0x0 + Bit level input + 0x0 + + + B_0x1 + Byte or half-word level input + 0x1 + + + + + RTYPE_OUT + Reverse type output +This bit controls the reversal granularity of the output data. + 10 + 1 + read-write + + + B_0x0 + Bit level output + 0x0 + + + B_0x1 + Byte or half-word level output + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + DAC + DAC address block description + DAC + 0x40007400 + + 0x0 + 0x50 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN1 + DAC channel1 enable +This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + read-write + + + B_0x0 + DAC channel1 disabled + 0x0 + + + B_0x1 + DAC channel1 enabled + 0x1 + + + + + TEN1 + DAC channel1 trigger enable +This bit is set and cleared by software to enable/disable DAC channel1 trigger. +Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle. + 1 + 1 + read-write + + + B_0x0 + DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register + 0x0 + + + B_0x1 + DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register + 0x1 + + + + + TSEL1 + DAC channel1 trigger selection +These bits select the external event used to trigger DAC channel1 +... +Refer to the trigger selection tables in Section114.4.2: DAC pins and internal signals for details on trigger configuration and mapping. +Note: Only used if bit TEN11=11 (DAC channel1 trigger enabled). + 2 + 4 + read-write + + + B_0x0 + SWTRIG1 + 0x0 + + + B_0x1 + dac_ch1_trg1 + 0x1 + + + B_0x2 + dac_ch1_trg2 + 0x2 + + + B_0xF + dac_ch1_trg15 + 0xF + + + + + WAVE1 + DAC channel1 noise/triangle wave generation enable +These bits are set and cleared by software. +1x: Triangle wave generation enabled +Only used if bit TEN11=11 (DAC channel1 trigger enabled). + 6 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP1 + DAC channel1 mask/amplitude selector + 8 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN1 + DAC channel1 DMA enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + DAC channel1 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel1 DMA mode enabled + 0x1 + + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + DAC channel1 DMA Underrun Interrupt disabled + 0x0 + + + B_0x1 + DAC channel1 DMA Underrun Interrupt enabled + 0x1 + + + + + CEN1 + DAC channel1 calibration enable +This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN11=10 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + read-write + + + B_0x0 + DAC channel1 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel1 in calibration mode + 0x1 + + + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWTRIG1 + DAC channel1 software trigger +This bit is set by software to trigger the DAC in software trigger mode. +Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data +These bits are written by software. They specify 12-bit data for DAC channel1. + 0 + 12 + read-write + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data +These bits are written by software. +They specify 12-bit data for DAC channel1. + 4 + 12 + read-write + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data +These bits are written by software. They specify 8-bit data for DAC channel1. + 0 + 8 + read-write + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DOR + DAC channel1 data output +These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + read-only + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAUDR1 + DAC channel1 DMA underrun flag +This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel1 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) + 0x1 + + + + + CAL_FLAG1 + DAC channel1 calibration offset status +This bit is set and cleared by hardware + 14 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST1 + DAC channel1 busy writing sample time flag +This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization). + 15 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written + 0x1 + + + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + OTRIM1 + DAC channel1 offset trimming value + 0 + 5 + read-write + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MODE1 + DAC channel1 mode +These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN11=10 and bit CEN11=10 in the DAC_CR register). If EN11=11 or CEN11=11 the write operation is ignored. +They can be set and cleared by software to select the DAC channel1 mode: +DAC channel1 in Normal mode +DAC channel1 in sample & hold mode +Note: This register can be modified only when EN11=10. + 0 + 3 + read-write + + + B_0x0 + DAC channel1 is connected to external pin with Buffer enabled + 0x0 + + + B_0x1 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled + 0x1 + + + B_0x2 + DAC channel1 is connected to external pin with Buffer disabled + 0x2 + + + B_0x3 + DAC channel1 is connected to on chip peripherals with Buffer disabled + 0x3 + + + B_0x4 + DAC channel1 is connected to external pin with Buffer enabled + 0x4 + + + B_0x5 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled + 0x5 + + + B_0x6 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled + 0x6 + + + B_0x7 + DAC channel1 is connected to on chip peripherals with Buffer disabled + 0x7 + + + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC channel1 sample and hold sample time register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE1 + DAC channel1 sample time (only valid in Sample and hold mode) +These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST11=11, the write operation is ignored. + 0 + 10 + read-write + + + + + DAC_SHHR + DAC_SHHR + DAC sample and hold time register + 0x48 + 0x20 + 0x00010001 + 0xFFFFFFFF + + + THOLD1 + DAC channel1 hold time (only valid in Sample and hold mode) +Hold time1=1(THOLD[9:0]) x LSI clock period +Note: This register can be modified only when EN11=10. + 0 + 10 + read-write + + + + + DAC_SHRR + DAC_SHRR + DAC sample and hold refresh time register + 0x4C + 0x20 + 0x00010001 + 0xFFFFFFFF + + + TREFRESH1 + DAC channel1 refresh time (only valid in Sample and hold mode) +Refresh time1=1(TREFRESH[7:0]) x LSI clock period +Note: This register can be modified only when EN11=10. + 0 + 8 + read-write + + + + + + + DBGMCU + DBGMCU register block + DBGMCU + 0x40015800 + + 0x0 + 0x1000 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + DBGMCU device ID code register + 0x00 + 0x20 + 0x00006000 + 0x0000F000 + + + DEV_ID + Device identifier +This field indicates the device ID. + 0 + 12 + read-only + + + B_0x459 + STM32U031xx + 0x459 + + + B_0x489 + STM32U073/083xx + 0x489 + + + + + REV_ID + Revision identifier +This field indicates the revision of the device. + 16 + 16 + read-only + + + B_0x1000 + Revision A for STM32U031/73/83xx + 0x1000 + + + + + + + DBGMCU_CR + DBGMCU_CR + DBGMCU configuration register + 0x00000004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_STOP + Debug Stop mode +Debug options in Stop mode. + 1 + 1 + read-write + + + B_0x0 + All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. + 0x0 + + + B_0x1 + FCLK and HCLK running, derived from the internal RC oscillator remaining active. If SysTick is enabled, it may generate periodic interrupt and wake up events.Upon Stop mode exit, the software must re-establish the desired clock configuration. + 0x1 + + + + + DBG_STANDBY + Debug Standby and Shutdown modes +Debug options in Standby or Shutdown mode. + 2 + 1 + read-write + + + B_0x0 + Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby) + 0x0 + + + B_0x1 + Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset. + 0x1 + + + + + + + DBGMCU_APB1FZR + DBGMCU_APB1FZR + DBGMCU APB1 freeze register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM2_STOP + TIM2 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. TIM2 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM2 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM3_STOP + TIM3 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. TIM3 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM3 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM4_STOP + TIM4 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. TIM4 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM34 is frozen while CPU is in debug mode + 0x1 + + + + + DBG_TIM6_STOP + TIM6 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. TIM6 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM6 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM7_STOP + TIM7 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. TIM7 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM7 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_RTC_STOP + RTC stop in debug + 10 + 1 + read-write + + + B_0x0 + normal operation. RTC counter continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. RTC counter is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_WWDG_STOP + WWDG stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. WWDG continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. WWDG is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_IWDG_STOP + IWDG stop in debug + 12 + 1 + read-write + + + B_0x0 + normal operation. IWDG continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. IWDG is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_I2C3_STOP + I2C3 SMBUS timeout stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. I2C3 SMBUS timeout continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C3 SMBUS timeout is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM2_STOP + LPTIM2 stop in debug + 30 + 1 + read-write + + + B_0x0 + normal operation. LPTIM2 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM2 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM1_STOP + LPTIM1 stop in debug + 31 + 1 + read-write + + + B_0x0 + normal operation. LPTIM1 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM1 is frozen while CPU is in debug mode. + 0x1 + + + + + + + DBGMCU_APB2FZR + DBGMCU_APB2FZR + DBG APB2 freeze register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM1_STOP + TIM1 stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. TIM1 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM1 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM14_STOP + TIM14 stop in debug + 15 + 1 + read-write + + + B_0x0 + normal operation. TIM14 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM14 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM15_STOP + TIM15 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. TIM15 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM15 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM16_STOP + TIM16 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. TIM16 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM16 is frozen while CPU is in debug mode. + 0x1 + + + + + + + DBGMCU_SR + DBGMCU_SR + DBGMCU status register + 0xFC + 0x20 + 0x00010003 + 0xFFFFFFFF + + + AP1_PRESENT + Identifies whether access port AP1 is present in device + 0 + 1 + read-only + + + B_0x1 + AP1 present + 0x1 + + + + + AP0_PRESENT + Identifies whether access port AP0 is present in device + 1 + 1 + read-only + + + B_0x1 + AP0 present + 0x1 + + + + + AP1_ENABLED + Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + 16 + 1 + read-only + + + B_0x0 + AP1 locked + 0x0 + + + B_0x1 + AP1 enabled + 0x1 + + + + + AP0_ENABLED + Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + 17 + 1 + read-only + + + B_0x0 + AP0 locked + 0x0 + + + B_0x1 + AP0 enabled + 0x1 + + + + + + + DBGMCU_DBG_AUTH_HOST + DBGMCU_DBG_AUTH_HOST + DBGMCU debug authentication mailbox host register + 0x100 + 0x20 + 0x00000000 + 0x00000000 + + + MESSAGE + Debug host to device mailbox message. +During debug authentication the debug host communicates with the device via this register. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_DEVICE + DBGMCU_DBG_AUTH_DEVICE + DBGMCU debug authentication mailbox device register + 0x104 + 0x20 + 0x00000000 + 0x00000000 + + + MESSAGE + Device to debug host mailbox message. +During debug authentication the device communicates with the debug host via this register. + 0 + 32 + read-only + + + + + DBGMCU_PIDR4 + DBGMCU_PIDR4 + DBGMCU CoreSight peripheral identity register 4 + 0xFD0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JEP106CON + JEP106 continuation code + 0 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + SIZE + register file size + 4 + 4 + read-only + + + B_0x0 + The register file occupies a single 4-Kbyte region. + 0x0 + + + + + + + DBGMCU_PIDR0 + DBGMCU_PIDR0 + DBGMCU CoreSight peripheral identity register 0 + 0xFE0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [7:0] + 0 + 8 + read-only + + + B_0x00 + DBGMCU part number + 0x00 + + + + + + + DBGMCU_PIDR1 + DBGMCU_PIDR1 + DBGMCU CoreSight peripheral identity register 1 + 0xFE4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [11:8] + 0 + 4 + read-only + + + B_0x0 + DBGMCU part number + 0x0 + + + + + JEP106ID + JEP106 identity code bits [3:0] + 4 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + + + DBGMCU_PIDR2 + DBGMCU_PIDR2 + DBGMCU CoreSight peripheral identity register 2 + 0xFE8 + 0x20 + 0x0000000A + 0xFFFFFFFF + + + JEP106ID + JEP106 identity code bits [6:4] + 0 + 3 + read-only + + + B_0x2 + STMicroelectronics JEDEC code + 0x2 + + + + + JEDEC + JEDEC assigned value + 3 + 1 + read-only + + + B_0x1 + designer identification specified by JEDEC + 0x1 + + + + + REVISION + component revision number + 4 + 4 + read-only + + + B_0x0 + r0p0 + 0x0 + + + + + + + DBGMCU_PIDR3 + DBGMCU_PIDR3 + DBGMCU CoreSight peripheral identity register 3 + 0xFEC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified + 0 + 4 + read-only + + + B_0x0 + no customer modifications + 0x0 + + + + + REVAND + metal fix version + 4 + 4 + read-only + + + B_0x0 + no metal fix + 0x0 + + + + + + + DBGMCU_CIDR0 + DBGMCU_CIDR0 + DBGMCU CoreSight component identity register 0 + 0xFF0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PREAMBLE + component identification bits [7:0] + 0 + 8 + read-only + + + B_0x0D + common identification value + 0x0D + + + + + + + DBGMCU_CIDR1 + DBGMCU_CIDR1 + DBGMCU CoreSight component identity register 1 + 0xFF4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [11:8] + 0 + 4 + read-only + + + B_0x0 + common identification value + 0x0 + + + + + CLASS + component identification bits [15:12] - component class + 4 + 4 + read-only + + + B_0xF + Non-CoreSight component + 0xF + + + + + + + DBGMCU_CIDR2 + DBGMCU_CIDR2 + DBGMCU CoreSight component identity register 2 + 0xFF8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [23:16] + 0 + 8 + read-only + + + B_0x05 + common identification value + 0x05 + + + + + + + DBGMCU_CIDR3 + DBGMCU_CIDR3 + DBGMCU CoreSight component identity register 3 + 0xFFC + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [31:24] + 0 + 8 + read-only + + + B_0xB1 + common identification value + 0xB1 + + + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x40020800 + + 0x0 + 0x148 + registers + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C5CR + DMAMUX_C5CR + DMAMUX request line multiplexer channel 5 configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C6CR + DMAMUX_C6CR + DMAMUX request line multiplexer channel 6 configuration register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C7CR + DMAMUX_C7CR + DMAMUX request line multiplexer channel 7 configuration register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C8CR + DMAMUX_C8CR + DMAMUX request line multiplexer channel 8 configuration register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C9CR + DMAMUX_C9CR + DMAMUX request line multiplexer channel 9 configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C10CR + DMAMUX_C10CR + DMAMUX request line multiplexer channel 10 configuration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C11CR + DMAMUX_C11CR + DMAMUX request line multiplexer channel 11 configuration register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SOF0 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 0 + 1 + read-only + + + SOF1 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 1 + 1 + read-only + + + SOF2 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 2 + 1 + read-only + + + SOF3 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 3 + 1 + read-only + + + SOF4 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 4 + 1 + read-only + + + SOF5 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 5 + 1 + read-only + + + SOF6 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 6 + 1 + read-only + + + SOF7 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 7 + 1 + read-only + + + SOF8 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 8 + 1 + read-only + + + SOF9 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 9 + 1 + read-only + + + SOF10 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 10 + 1 + read-only + + + SOF11 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 11 + 1 + read-only + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSOF0 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 0 + 1 + write-only + + + CSOF1 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 1 + 1 + write-only + + + CSOF2 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 2 + 1 + write-only + + + CSOF3 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 3 + 1 + write-only + + + CSOF4 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 4 + 1 + write-only + + + CSOF5 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 5 + 1 + write-only + + + CSOF6 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 6 + 1 + write-only + + + CSOF7 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 7 + 1 + write-only + + + CSOF8 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 8 + 1 + write-only + + + CSOF9 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 9 + 1 + write-only + + + CSOF10 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 10 + 1 + write-only + + + CSOF11 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 11 + 1 + write-only + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OF0 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 0 + 1 + read-only + + + OF1 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 1 + 1 + read-only + + + OF2 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 2 + 1 + read-only + + + OF3 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 3 + 1 + read-only + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COF0 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 0 + 1 + write-only + + + COF1 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 1 + 1 + write-only + + + COF2 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 2 + 1 + write-only + + + COF3 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 3 + 1 + write-only + + + + + + + DMA1 + DMA register bank + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CHannel1 + DMA1 channel 1 interrupt + 9 + + + DMA1_Channel2_3 + DMA1 channel 2 and 3 interrupts + 10 + + + DMA1_Channel4_5_6_7 + DMA1 channel 4, 5, 6, 7, DMAMUX, DMA2 channel 1, 2, 3, 4, 5 interrupts + 11 + + + + DMA_ISR + DMA_ISR + DMA interrupt status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GIF1 + Global interrupt flag for channel 1 + 0 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF1 + Transfer complete (TC) flag for channel 1 + 1 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF1 + Half transfer (HT) flag for channel 1 + 2 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF1 + Transfer error (TE) flag for channel 1 + 3 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF2 + Global interrupt flag for channel 2 + 4 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF2 + Transfer complete (TC) flag for channel 2 + 5 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF2 + Half transfer (HT) flag for channel 2 + 6 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF2 + Transfer error (TE) flag for channel 2 + 7 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF3 + Global interrupt flag for channel 3 + 8 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF3 + Transfer complete (TC) flag for channel 3 + 9 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF3 + Half transfer (HT) flag for channel 3 + 10 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF3 + Transfer error (TE) flag for channel 3 + 11 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF4 + global interrupt flag for channel 4 + 12 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF4 + Transfer complete (TC) flag for channel 4 + 13 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF4 + Half transfer (HT) flag for channel 4 + 14 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF4 + Transfer error (TE) flag for channel 4 + 15 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF5 + global interrupt flag for channel 5 + 16 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF5 + Transfer complete (TC) flag for channel 5 + 17 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF5 + Half transfer (HT) flag for channel 5 + 18 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF5 + Transfer error (TE) flag for channel 5 + 19 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF6 + Global interrupt flag for channel 6 + 20 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF6 + Transfer complete (TC) flag for channel 6 + 21 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF6 + Half transfer (HT) flag for channel 6 + 22 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF6 + Transfer error (TE) flag for channel 6 + 23 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF7 + Global interrupt flag for channel 7 + 24 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF7 + Transfer complete (TC) flag for channel 7 + 25 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF7 + Half transfer (HT) flag for channel 7 + 26 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF7 + Transfer error (TE) flag for channel 7 + 27 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + + + DMA_IFCR + DMA_IFCR + DMA interrupt flag clear register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CGIF1 + Global interrupt flag clear for channel 1 + 0 + 1 + write-only + + + CTCIF1 + Transfer complete flag clear for channel 1 + 1 + 1 + write-only + + + CHTIF1 + Half transfer flag clear for channel 1 + 2 + 1 + write-only + + + CTEIF1 + Transfer error flag clear for channel 1 + 3 + 1 + write-only + + + CGIF2 + Global interrupt flag clear for channel 2 + 4 + 1 + write-only + + + CTCIF2 + Transfer complete flag clear for channel 2 + 5 + 1 + write-only + + + CHTIF2 + Half transfer flag clear for channel 2 + 6 + 1 + write-only + + + CTEIF2 + Transfer error flag clear for channel 2 + 7 + 1 + write-only + + + CGIF3 + Global interrupt flag clear for channel 3 + 8 + 1 + write-only + + + CTCIF3 + Transfer complete flag clear for channel 3 + 9 + 1 + write-only + + + CHTIF3 + Half transfer flag clear for channel 3 + 10 + 1 + write-only + + + CTEIF3 + Transfer error flag clear for channel 3 + 11 + 1 + write-only + + + CGIF4 + Global interrupt flag clear for channel 4 + 12 + 1 + write-only + + + CTCIF4 + Transfer complete flag clear for channel 4 + 13 + 1 + write-only + + + CHTIF4 + Half transfer flag clear for channel 4 + 14 + 1 + write-only + + + CTEIF4 + Transfer error flag clear for channel 4 + 15 + 1 + write-only + + + CGIF5 + Global interrupt flag clear for channel 5 + 16 + 1 + write-only + + + CTCIF5 + Transfer complete flag clear for channel 5 + 17 + 1 + write-only + + + CHTIF5 + Half transfer flag clear for channel 5 + 18 + 1 + write-only + + + CTEIF5 + Transfer error flag clear for channel 5 + 19 + 1 + write-only + + + CGIF6 + Global interrupt flag clear for channel 6 + 20 + 1 + write-only + + + CTCIF6 + Transfer complete flag clear for channel 6 + 21 + 1 + write-only + + + CHTIF6 + Half transfer flag clear for channel 6 + 22 + 1 + write-only + + + CTEIF6 + Transfer error flag clear for channel 6 + 23 + 1 + write-only + + + CGIF7 + Global interrupt flag clear for channel 7 + 24 + 1 + write-only + + + CTCIF7 + Transfer complete flag clear for channel 7 + 25 + 1 + write-only + + + CHTIF7 + Half transfer flag clear for channel 7 + 26 + 1 + write-only + + + CTEIF7 + Transfer error flag clear for channel 7 + 27 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA channel 1 number of data to transfer register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA channel 1 peripheral address register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA channel 1 memory address register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA channel 2 number of data to transfer register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA channel 2 peripheral address register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA channel 2 memory address register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA channel 3 peripheral address register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA channel 3 memory address register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA channel 4 configuration register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA channel 4 peripheral address register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA channel 4 memory address register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA channel 5 configuration register + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA channel 5 peripheral address register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA channel 5 memory address register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA channel 6 configuration register + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA channel 6 peripheral address register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA channel 6 memory address register + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA channel 7 configuration register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA channel 7 peripheral address register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA channel 7 memory address register + 0x8C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + + + DMA2 + 0x40020400 + + + EXTI + EXTI register block + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) + 1 + + + EXTI0_1 + EXTI lines 0 and 1 interrupt + 5 + + + EXTI2_3 + EXTI lines 2 and 3 interrupt + 6 + + + EXTI4_15 + EXTI lines 4 to 15 interrupt + 7 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT16 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT17 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT18 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT19 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT20 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT21 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register 1 + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT16 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT17 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT18 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT19 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT20 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT21 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register 1 + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI1 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI2 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI3 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI4 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI5 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI6 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI7 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI8 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI9 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI10 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI11 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI12 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI13 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI14 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI15 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI16 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI17 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI18 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI19 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI20 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI21 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register 1 + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF16 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF17 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF18 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF19 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF20 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF21 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register 1 + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF16 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF17 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF18 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF19 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF20 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF21 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register 1 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI0 GPIO port selection +These bits are written by software to select the source input for EXTI0 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[0] pin + 0x00 + + + B_0x01 + PB[0] pin + 0x01 + + + B_0x02 + PC[0] pin + 0x02 + + + B_0x03 + PD[0] pin + 0x03 + + + B_0x05 + PF[0] pin + 0x05 + + + + + EXTI1 + EXTI1 GPIO port selection +These bits are written by software to select the source input for EXTI1 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[1] pin + 0x00 + + + B_0x01 + PB[1] pin + 0x01 + + + B_0x02 + PC[1] pin + 0x02 + + + B_0x03 + PD[1] pin + 0x03 + + + B_0x05 + PF[1] pin + 0x05 + + + + + EXTI2 + EXTI2 GPIO port selection +These bits are written by software to select the source input for EXTI2 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[2] pin + 0x00 + + + B_0x01 + PB[2] pin + 0x01 + + + B_0x02 + PC[2] pin + 0x02 + + + B_0x03 + PD[2] pin + 0x03 + + + B_0x05 + PF[2] pin + 0x05 + + + + + EXTI3 + EXTI3 GPIO port selection +These bits are written by software to select the source input for EXTI3 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[3] pin + 0x00 + + + B_0x01 + PB[3] pin + 0x01 + + + B_0x02 + PC[3] pin + 0x02 + + + B_0x03 + PD[3] pin + 0x03 + + + B_0x05 + PF[3] pin + 0x05 + + + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register 2 + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI4 GPIO port selection +These bits are written by software to select the source input for EXTI4 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[4] pin + 0x00 + + + B_0x01 + PB[4] pin + 0x01 + + + B_0x02 + PC[4] pin + 0x02 + + + B_0x03 + PD[4] pin + 0x03 + + + B_0x05 + PF[4] pin + 0x05 + + + + + EXTI5 + EXTI5 GPIO port selection +These bits are written by software to select the source input for EXTI5 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[5] pin + 0x00 + + + B_0x01 + PB[5] pin + 0x01 + + + B_0x02 + PC[5] pin + 0x02 + + + B_0x03 + PD[5] pin + 0x03 + + + B_0x05 + PF[5] pin + 0x05 + + + + + EXTI6 + EXTI6 GPIO port selection +These bits are written by software to select the source input for EXTI6 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[6] pin + 0x00 + + + B_0x01 + PB[6] pin + 0x01 + + + B_0x02 + PC[6] pin + 0x02 + + + B_0x03 + PD[6] pin + 0x03 + + + B_0x05 + PF[6] pin + 0x05 + + + + + EXTI7 + EXTI7 GPIO port selection +These bits are written by software to select the source input for EXTI7 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[7] pin + 0x00 + + + B_0x01 + PB[7] pin + 0x01 + + + B_0x02 + PC[7] pin + 0x02 + + + B_0x03 + PD[7] pin + 0x03 + + + B_0x05 + PF[7] pin + 0x05 + + + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register 3 + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTI8 GPIO port selection +These bits are written by software to select the source input for EXTI8 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[8] pin + 0x00 + + + B_0x01 + PB[8] pin + 0x01 + + + B_0x02 + PC[8] pin + 0x02 + + + B_0x03 + PD[8] pin + 0x03 + + + B_0x05 + PF[8] pin + 0x05 + + + + + EXTI9 + EXTI9 GPIO port selection +These bits are written by software to select the source input for EXTI9 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[9] pin + 0x00 + + + B_0x01 + PB[9] pin + 0x01 + + + B_0x02 + PC[9] pin + 0x02 + + + B_0x03 + PD[9] pin + 0x03 + + + B_0x05 + PF[9] pin + 0x05 + + + + + EXTI10 + EXTI10 GPIO port selection +These bits are written by software to select the source input for EXTI10 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[10] pin + 0x00 + + + B_0x01 + PB[10] pin + 0x01 + + + B_0x02 + PC[10] pin + 0x02 + + + B_0x03 + PD[10] pin + 0x03 + + + B_0x05 + PF[10] pin + 0x05 + + + + + EXTI11 + EXTI11 GPIO port selection +These bits are written by software to select the source input for EXTI11 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[11] pin + 0x00 + + + B_0x01 + PB[11] pin + 0x01 + + + B_0x02 + PC[11] pin + 0x02 + + + B_0x03 + PD[11] pin + 0x03 + + + B_0x05 + PF[11] pin + 0x05 + + + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register 4 + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTI12 GPIO port selection +These bits are written by software to select the source input for EXTI12 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[12] pin + 0x00 + + + B_0x01 + PB[12] pin + 0x01 + + + B_0x02 + PC[12] pin + 0x02 + + + B_0x03 + PD[12] pin + 0x03 + + + B_0x05 + PF[12] pin + 0x05 + + + + + EXTI13 + EXTI13 GPIO port selection +These bits are written by software to select the source input for EXTI13 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[13] pin + 0x00 + + + B_0x01 + PB[13] pin + 0x01 + + + B_0x02 + PC[13] pin + 0x02 + + + B_0x03 + PD[13] pin + 0x03 + + + B_0x05 + PF[13] pin + 0x05 + + + + + EXTI14 + EXTI14 GPIO port selection +These bits are written by software to select the source input for EXTI14 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[14] pin + 0x00 + + + B_0x01 + PB[14] pin + 0x01 + + + B_0x02 + PC[14] pin + 0x02 + + + B_0x03 + PD[14] pin + 0x03 + + + B_0x05 + PF[14] pin + 0x05 + + + + + EXTI15 + EXTI15 GPIO port selection +These bits are written by software to select the source input for EXTI15 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[15] pin + 0x00 + + + B_0x01 + PB[15] pin + 0x01 + + + B_0x02 + PC[15] pin + 0x02 + + + B_0x03 + PD[15] pin + 0x03 + + + B_0x05 + PF[15] pin + 0x05 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wake-up with interrupt mask register + 0x080 + 0x20 + 0xFFF80000 + 0xFFFFFFFF + + + IM0 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM1 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM2 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM3 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM4 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM5 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM6 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM7 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM8 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM9 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM10 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM11 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM12 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM13 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM14 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM15 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM16 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM17 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM18 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM19 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM20 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM21 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM22 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 22 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM23 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 23 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM24 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 24 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM25 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 25 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM26 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 26 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM27 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 27 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM28 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 28 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM29 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 29 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM30 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 30 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM31 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 31 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wake-up with event mask register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM1 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM2 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM3 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM4 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM5 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM6 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM7 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM8 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM9 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM10 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM11 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM12 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM13 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM14 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM15 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM16 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM17 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM18 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM19 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM20 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM21 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM22 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 22 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM23 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 23 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM24 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 24 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM25 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 25 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM26 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 26 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM27 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 27 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM28 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 28 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM29 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 29 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM30 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 30 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM31 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 31 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + EXTI_IMR2 + EXTI_IMR2 + EXTI CPU wake-up with interrupt mask register + 0x090 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + IM32 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM33 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM34 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM35 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM36 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM37 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wake-up with event mask register + 0x094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM32 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM33 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM34 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM35 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM36 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM37 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + + + FLASH + Mamba FLASH register block + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global interrupt + 3 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x000 + 0x20 + 0x00040600 + 0xFFFFFFFF + + + LATENCY + Flash memory access latency +The value in this bitfield represents the number of CPU wait states when accessing the flash memory. +Other: Reserved +A new write into the bitfield becomes effective when it returns the same value upon read. + 0 + 3 + read-write + + + B_0x0 + Zero wait states + 0x0 + + + B_0x1 + One wait state + 0x1 + + + + + PRFTEN + CPU Prefetch enable + 8 + 1 + read-write + + + B_0x0 + CPU Prefetch disabled + 0x0 + + + B_0x1 + CPU Prefetch enabled + 0x1 + + + + + ICEN + CPU Instruction cache enable + 9 + 1 + read-write + + + B_0x0 + CPU Instruction cache is disabled + 0x0 + + + B_0x1 + CPU Instruction cache is enabled + 0x1 + + + + + ICRST + CPU Instruction cache reset +This bit can be written only when the instruction cache is disabled. + 11 + 1 + read-write + + + B_0x0 + CPU Instruction cache is not reset + 0x0 + + + B_0x1 + CPU Instruction cache is reset + 0x1 + + + + + EMPTY + Main flash memory area empty +This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. +The bit can be set and reset by software. + 16 + 1 + read-write + + + B_0x0 + Main flash memory area programmed + 0x0 + + + B_0x1 + Main flash memory area empty + 0x1 + + + + + DBG_SWEN + Debug access software enable +Software may use this bit to enable/disable the debugger read access. + 18 + 1 + read-write + + + B_0x0 + Debugger disabled + 0x0 + + + B_0x1 + Debugger enabled + 0x1 + + + + + + + FLASH_KEYR + FLASH_KEYR + FLASH key register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + FLASH key +The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: +KEY1: 0x4567 0123 +KEY2: 0xCDEF 89AB + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + Option byte key +The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: +KEY1: 0x0819 2A3B +KEY2: 0x4C5D 6E7F + 0 + 32 + write-only + + + + + FLASH_SR + FLASH_SR + FLASH status register + 0x010 + 0x20 + 0x00000000 + 0xFFF0FFFF + + + EOP + End of operation +Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. +This bit is set only if the end of operation interrupts are enabled (EOPIE=1). +Cleared by writing 1. + 0 + 1 + read-write + + + OPERR + Operation error +Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. +This bit is set only if error interrupts are enabled (ERRIE=1). +Cleared by writing 1. + 1 + 1 + read-write + + + PROGERR + Programming error +Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. +Cleared by writing 1. + 3 + 1 + read-write + + + WRPERR + Write protection error +Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. +Cleared by writing 1. + 4 + 1 + read-write + + + PGAERR + Programming alignment error +Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. +Cleared by writing 1. + 5 + 1 + read-write + + + SIZERR + Size error +Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). +Cleared by writing 1. + 6 + 1 + read-write + + + PGSERR + Programming sequence error +Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. +Cleared by writing 1. + 7 + 1 + read-write + + + MISSERR + Fast programming data miss error +In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. +Cleared by writing 1. + 8 + 1 + read-write + + + FASTERR + Fast programming error +Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. +Cleared by writing 1. + 9 + 1 + read-write + + + RDERR + PCROP read error +Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. +Cleared by writing 1. + 14 + 1 + read-write + + + OPTVERR + Option and Engineering bits loading validity error + 15 + 1 + read-write + + + BSY1 + Busy +This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. + 16 + 1 + read-only + + + CFGBSY + Programming or erase configuration busy. +This flag is set and cleared by hardware. It is set when the first word is sent for program or when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared when the flash memory program or erase operation completes or ends with an error. +When set, launching any other operation through the FLASH control register (FLASH_CR) is impossible, and must be postponed (a programming or erase operation is ongoing). +When cleared, the program and erase settings in the FLASH control register (FLASH_CR) can be modified. + 18 + 1 + read-only + + + + + FLASH_CR + FLASH_CR + FLASH control register + 0x014 + 0x20 + 0xC0000000 + 0xFFFFFFFF + + + PG + Flash memory programming enable + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PER + Page erase enable + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MER1 + Mass erase +When set, this bit triggers the mass erase, that is, all user pages. + 2 + 1 + read-write + + + PNB + Page number selection +These bits select the page to erase: +... +Note: Values corresponding to addresses outside the main memory are not allowed. + 3 + 7 + read-write + + + B_0x0 + page 0 + 0x0 + + + B_0x1 + page 1 + 0x1 + + + B_0xF + page 15 + 0xF + + + + + STRT + Start erase operation +This bit triggers an erase operation when set. +This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. + 16 + 1 + read-write + + + OPTSTRT + Start of modification of option bytes +This bit triggers an options operation when set. +This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. + 17 + 1 + read-write + + + FSTPG + Fast programming enable + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + EOPIE + End-of-operation interrupt enable +This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ERRIE + Error interrupt enable +This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RDERRIE + PCROP read error interrupt enable +This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OBL_LAUNCH + Option byte load launch +When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. +The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. + 27 + 1 + read-write + + + SEC_PROT + Securable memory area protection enable +This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. +This bit is possible to set only by software and to clear only through a system reset. + 28 + 1 + read-write + + + B_0x0 + Disable (securable area accessible) + 0x0 + + + B_0x1 + Enable (securable area not accessible) + 0x1 + + + + + OPTLOCK + Options Lock +This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. +In case of an unsuccessful unlock operation, this bit remains set until the next reset. + 30 + 1 + read-write + + + LOCK + FLASH_CR Lock +This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. +In case of an unsuccessful unlock operation, this bit remains set until the next system reset. + 31 + 1 + read-write + + + + + FLASH_ECCR + FLASH_ECCR + FLASH ECC register + 0x018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC fail double-word address offset + In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory. + 0 + 14 + read-only + + + SYSF_ECC + System Flash memory ECC fail +This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. + 20 + 1 + read-only + + + ECCCIE + ECC correction interrupt enable + 24 + 1 + read-write + + + B_0x0 + ECCC interrupt disabled + 0x0 + + + B_0x1 + ECCC interrupt enabled + 0x1 + + + + + ECCC + ECC correction +Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. +Cleared by writing 1. + 30 + 1 + read-write + + + ECCD + ECC detection +Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. +Cleared by writing 1. + 31 + 1 + read-write + + + + + FLASH_OPTR + FLASH_OPTR + FLASH option register + 0x020 + 0x20 + 0x00000000 + 0x00000000 + + + RDP + Read protection level +Other: Level 1, memories read protection active + 0 + 8 + read-write + + + B_0xAA + Level 0, read protection not active + 0xAA + + + B_0xCC + Level 2, chip read protection active + 0xCC + + + + + BORR_LEV + BOR reset level + 8 + 3 + read-write + + + B_0x0 + BOR rising level 1 with threshold around 2.1 V + 0x0 + + + B_0x1 + BOR rising level 2 with threshold around 2.3 V + 0x1 + + + B_0x2 + BOR rising level 3 with threshold around 2.6 V + 0x2 + + + B_0x3 + BOR rising level 4 with threshold around 2.9 V + 0x3 + + + + + NRST_STOP + Reset generated when entering Stop mode + 13 + 1 + read-write + + + B_0x0 + Reset generated when entering the Stop mode + 0x0 + + + B_0x1 + No reset generated when entering the Stop mode + 0x1 + + + + + NRST_STDBY + Reset generated when entering Standby mode + 14 + 1 + read-write + + + B_0x0 + Reset generated when entering the Standby mode + 0x0 + + + B_0x1 + No reset generate when entering the Standby mode + 0x1 + + + + + NRST_SHDW + Reset generated when entering Shutdown mode + 15 + 1 + read-write + + + B_0x0 + Reset generated when entering the Shutdown mode + 0x0 + + + B_0x1 + No reset generated when entering the Shutdown mode + 0x1 + + + + + IWDG_SW + Independent watchdog selection + 16 + 1 + read-write + + + B_0x0 + Hardware independent watchdog + 0x0 + + + B_0x1 + Software independent watchdog + 0x1 + + + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Stop mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Stop mode + 0x1 + + + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Standby mode + 0x1 + + + + + WWDG_SW + Window watchdog selection + 19 + 1 + read-write + + + B_0x0 + Hardware window watchdog + 0x0 + + + B_0x1 + Software window watchdog + 0x1 + + + + + BDRST + Backup domain reset + 21 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + RAM_PARITY_CHECK + SRAM parity check control enable/disable + 22 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + BKPSRAM_HW_ERASE_DISABLE + Backup SRAM erase prevention + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + NBOOT_SEL + BOOT0 signal source selection +This option bit defines the source of the BOOT0 signal. + 24 + 1 + read-write + + + B_0x0 + BOOT0 pin (legacy mode) + 0x0 + + + B_0x1 + NBOOT0 option bit + 0x1 + + + + + NBOOT1 + Boot configuration +Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration. + 25 + 1 + read-write + + + NBOOT0 + NBOOT0 option bit + 26 + 1 + read-write + + + B_0x0 + NBOOT01=10 + 0x0 + + + B_0x1 + NBOOT01=11 + 0x1 + + + + + NRST_MODE + NRST pin configuration + 27 + 2 + read-write + + + B_0x1 + Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. + 0x1 + + + B_0x2 + Standard GPIO: only internal RESET is possible + 0x2 + + + B_0x3 + Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode + 0x3 + + + + + IRHEN + Internal reset holder enable bit + 29 + 1 + read-write + + + B_0x0 + Internal resets are propagated as simple pulse on NRST pin + 0x0 + + + B_0x1 + Internal resets drives NRST pin low until it is seen as low level + 0x1 + + + + + + + FLASH_WRP1AR + FLASH_WRP1AR + FLASH WRP area A address register + 0x02C + 0x20 + 0x00000000 + 0xFFF0FFF0 + + + WRP1A_STRT + WRP area A start offset +This bitfield contains the offset of the first page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 7 + read-write + + + WRP1A_END + WRP area A end offset +This bitfield contains the offset of the last page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 7 + read-write + + + + + FLASH_WRP1BR + FLASH_WRP1BR + FLASH WRP area B address register + 0x030 + 0x20 + 0x00000000 + 0xFFF0FFF0 + + + WRP1B_STRT + WRP area B start offset +This bitfield contains the offset of the first page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 7 + read-write + + + WRP1B_END + WRP area B end offset +This bitfield contains the offset of the last page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 7 + read-write + + + + + FLASH_SECR + FLASH_SECR + FLASH security register + 0x080 + 0x20 + 0x0 + 0xFFFEFFE0 + + + HDP1_PEND + Last page of the first hide protection area + 0 + 7 + read-write + + + BOOT_LOCK + used to force boot from user area +If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). + 16 + 1 + read-write + + + B_0x0 + Boot based on the pad/option bit configuration + 0x0 + + + B_0x1 + Boot forced from main flash memory + 0x1 + + + + + HDP1EN + Hide protection area enable + 24 + 8 + read-write + + + + + + + GPIOA + GPIOA address block description + GPIO + 0x50000000 + + 0x0 + 0x2C + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOB + GPIOB address block description + GPIO + 0x50000400 + + 0x0 + 0x2C + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOB_LCKR + GPIOB_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOC + GPIOC address block description + GPIO + 0x50000800 + + 0x0 + 0x2C + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOC_LCKR + GPIOC_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOD + GPIOD address block description + GPIO + 0x50000C00 + + 0x0 + 0x2C + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOD_LCKR + GPIOD_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOE + GPIOE address block description + GPIO + 0x50001000 + + 0x0 + 0x2C + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOE_LCKR + GPIOE_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOF + GPIOF address block description + GPIO + 0x50001400 + + 0x0 + 0x2C + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOF_LCKR + GPIOF_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + IWDG + IWDG address block description + IWDG + 0x40003000 + + 0x0 + 0x18 + registers + + + + IWDG_KR + IWDG_KR + IWDG key register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Key value (write only, read 0x0000) +These bits can be used for several functions, depending upon the value written by the application: +- 0xAAAA: reloads the RL[11:0] value into the IWDCNT down-counter (watchdog refresh), and write-protects registers. This value must be written by software at regular intervals, otherwise the watchdog generates a reset when the counter reaches 0. +- 0x5555: enables write-accesses to the registers. +- 0xCCCC: enables the watchdog (except if the hardware watchdog option is selected) and write-protects registers. +- values different from 0x5555: write-protects registers. +Note that only IWDG_PR, IWDG_RLR, IWDG_EWCR and IWDG_WINR registers have a write-protection mechanism. + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG prescaler register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PR + Prescaler divider +These bits are write access protected, see Section126.4.6. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset to be able to change the prescaler divider. +Others: divider / 1024 +Note: Reading this register returns the prescaler value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 4 + read-write + + + B_0x0 + divider / 4 + 0x0 + + + B_0x1 + divider / 8 + 0x1 + + + B_0x2 + divider / 16 + 0x2 + + + B_0x3 + divider / 32 + 0x3 + + + B_0x4 + divider / 64 + 0x4 + + + B_0x5 + divider / 128 + 0x5 + + + B_0x6 + divider / 256 + 0x6 + + + B_0x7 + divider / 512 + 0x7 + + + + + + + IWDG_RLR + IWDG_RLR + IWDG reload register + 0x08 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + RL + Watchdog counter reload value +These bits are write access protected, see Section126.4.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. +The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG status register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVU + Watchdog prescaler value update +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the V<sub>DD</sub> voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). +The prescaler value can be updated only when PVU bit is reset. + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). +The reload value can be updated only when RVU bit is reset. + 1 + 1 + read-only + + + WVU + Watchdog counter window value update +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). +The window value can be updated only when WVU bit is reset. +This bit is generated only if generic window = 1. + 2 + 1 + read-only + + + EWU + Watchdog interrupt comparator value update +This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the V<sub>DD</sub> voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). +The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. + 3 + 1 + read-only + + + ONF + Watchdog enable status bit +Set to 1 by hardware as soon as the IWDG is started. In software mode, it remains to '1' until the IWDG is reset. In hardware mode, this bit is always set to '1'. + 8 + 1 + read-only + + + B_0x0 + The IWDG is not activated + 0x0 + + + B_0x1 + The IWDG is activated and needs to be refreshed regularly by the application + 0x1 + + + + + EWIF + Watchdog early interrupt flag +This bit is set to 1 by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to 1. + 14 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG window register + 0x10 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + WIN + Watchdog counter window value +These bits are write access protected, see Section126.4.6.They contain the high limit of the window value to be compared with the downcounter. +To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0]1+11 and greater than 1. +The WVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_EWCR + IWDG_EWCR + IWDG early wake-up interrupt register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EWIT + Watchdog counter window value +These bits are write access protected (see Section126.4.6). They are written by software to define at which position of the IWDCNT down-counter the early wake-up interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0]1-11. +EWIT[11:0] must be bigger than 1. +An interrupt is generated only if EWIE = 1. +The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the Early wake-up comparator value and the Interrupt enable bit from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + EWIC + Watchdog early interrupt acknowledge +The software must write a 1 into this bit in order to acknowledge the early wake-up interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. + 14 + 1 + write-only + + + EWIE + Watchdog early interrupt enable +Set and reset by software. +The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the value of this bit. + 15 + 1 + read-write + + + B_0x0 + The early interrupt interface is disabled. + 0x0 + + + B_0x1 + The early interrupt interface is enabled. + 0x1 + + + + + + + + + I2C1 + I2C address block description + I2C + 0x40005400 + + 0x0 + 0x2C + registers + + + I2C1 + I2C1 global interrupt (combined with EXTI line 23) + 23 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer complete (TC) +Note: Transfer complete reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer complete interrupt disabled + 0x0 + + + B_0x1 + Transfer complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration loss (ARLO) +Note: Bus error detection (BERR) +Note: Overrun/Underrun (OVR) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + 18 + 1 + read-write + + + B_0x0 + Wake-up from Stop mode disable. + 0x0 + + + B_0x1 + Wake-up from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + FMP + Fast-mode Plus 20 mA drive enable + 24 + 1 + read-write + + + B_0x0 + 20 mA I/O drive disabled + 0x0 + + + B_0x1 + 20 mA I/O drive enabled + 0x1 + + + + + ADDRACLR + Address match flag (ADDR) automatic clear + 30 + 1 + read-write + + + B_0x0 + ADDR flag is set by hardware, cleared by software by setting ADDRCF bit. + 0x0 + + + B_0x1 + ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral. + 0x1 + + + + + STOPFACLR + STOP detection flag (STOPF) automatic clear + 31 + 1 + read-write + + + B_0x0 + STOPF flag is set by hardware, cleared by software by setting STOPCF bit. + 0x0 + + + B_0x1 + STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral. + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] must be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer + 0x0 + + + B_0x1 + Master requests a read transfer + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit address in write direction + Restart + first seven bits of the 10-bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the first seven bits of the 10-bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer. +Otherwise, setting this bit generates a START condition once the bus is free. +Note: Writing 0 to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In master mode: +Note: Writing 0 to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation + 0x0 + + + B_0x1 + Stop generation after current byte transfer + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing 0 to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN = 0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN = 0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN = 0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN = 0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and dont care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and dont care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL + 1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH + 1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL + 1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings) and for SCL high and low level counters (refer to I2C master initialization). +t<sub>PRESC </sub>= (PRESC + 1) x t<sub>I2CCLK</sub> + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE = 0 +t<sub>TIMEOUT</sub>= (TIMEOUTA + 1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE = 1 +t<sub>IDLE</sub>= (TIMEOUTA + 1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN = 0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN = 0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE = 0) or high for more than t<sub>IDLE </sub>(TIDLE = 1), a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT </sub>= (TIMEOUTB + TIDLE = 01) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN = 0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + I2C2 + 0x40005800 + + I2C2_I2C3 + I2C2/3 global interrupt + 24 + + + + I2C3 + 0x40008800 + + + LPTIM1 + LPTIM1 address block description + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + LPTIM1_ISR_OUTPUT + LPTIM1_ISR_OUTPUT + LPTIM1 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM1_ISR_INPUT + LPTIM1_ISR_INPUT + LPTIM1 interrupt and status register [alternate] + LPTIM1_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM1_ICR_OUTPUT + LPTIM1_ICR_OUTPUT + LPTIM1 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM1_ICR_INPUT + LPTIM1_ICR_INPUT + LPTIM1 interrupt clear register [alternate] + LPTIM1_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM1_DIER_OUTPUT + LPTIM1_DIER_OUTPUT + LPTIM1 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM1_DIER_INPUT + LPTIM1_DIER_INPUT + LPTIM1 interrupt enable register [alternate] + LPTIM1_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM1_CFGR + LPTIM1_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM1_ext_trig0 + 0x0 + + + B_0x1 + LPTIM1_ext_trig1 + 0x1 + + + B_0x2 + LPTIM1_ext_trig2 + 0x2 + + + B_0x3 + LPTIM1_ext_trig3 + 0x3 + + + B_0x4 + LPTIM1_ext_trig4 + 0x4 + + + B_0x5 + LPTIM1_ext_trig5 + 0x5 + + + B_0x6 + LPTIM1_ext_trig6 + 0x6 + + + B_0x7 + LPTIM1_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM1_ARR, LPTIM1_RCR and the LPTIM1_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM1_CR + LPTIM1_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM1_ARR and LPTIM1_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM1_ARR and LPTIM1_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM1_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM1_CNT register asynchronously resets LPTIM1_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM1_CCR1 + LPTIM1_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM1_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_ARR + LPTIM1_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM1_CNT + LPTIM1_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM1_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM1_CFGR2 + LPTIM1_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM1_in1_mux0 + 0x0 + + + B_0x1 + LPTIM1_in1_mux1 + 0x1 + + + B_0x2 + LPTIM1_in1_mux2 + 0x2 + + + B_0x3 + LPTIM1_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM1_in2_mux0 + 0x0 + + + B_0x1 + LPTIM1_in2_mux1 + 0x1 + + + B_0x2 + LPTIM1_in2_mux2 + 0x2 + + + B_0x3 + LPTIM1_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM1_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM1_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM1_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM1_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM1_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM1_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM1_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM1_ic2_mux3 + 0x3 + + + + + + + LPTIM1_RCR + LPTIM1_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM1_CCMR1 + LPTIM1_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM1_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM1_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM1_CCMR2 + LPTIM1_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM1_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM1_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM1_CCR2 + LPTIM1_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM1_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_CCR3 + LPTIM1_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM1_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_CCR4 + LPTIM1_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM1_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPTIM2 + LPTIM2 address block description + LPTIM + 0x40009400 + + 0x0 + 0x400 + registers + + + + LPTIM2_ISR_OUTPUT + LPTIM2_ISR_OUTPUT + LPTIM2 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM2_ISR_INPUT + LPTIM2_ISR_INPUT + LPTIM2 interrupt and status register [alternate] + LPTIM2_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM2_ICR_OUTPUT + LPTIM2_ICR_OUTPUT + LPTIM2 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM2_ICR_INPUT + LPTIM2_ICR_INPUT + LPTIM2 interrupt clear register [alternate] + LPTIM2_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM2_DIER_OUTPUT + LPTIM2_DIER_OUTPUT + LPTIM2 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM2_DIER_INPUT + LPTIM2_DIER_INPUT + LPTIM2 interrupt enable register [alternate] + LPTIM2_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM2_CFGR + LPTIM2_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM2_ext_trig0 + 0x0 + + + B_0x1 + LPTIM2_ext_trig1 + 0x1 + + + B_0x2 + LPTIM2_ext_trig2 + 0x2 + + + B_0x3 + LPTIM2_ext_trig3 + 0x3 + + + B_0x4 + LPTIM2_ext_trig4 + 0x4 + + + B_0x5 + LPTIM2_ext_trig5 + 0x5 + + + B_0x6 + LPTIM2_ext_trig6 + 0x6 + + + B_0x7 + LPTIM2_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM2_ARR, LPTIM2_RCR and the LPTIM2_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM2_CR + LPTIM2_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM2_ARR and LPTIM2_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM2_ARR and LPTIM2_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM2_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM2_CNT register asynchronously resets LPTIM2_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM2_CCR1 + LPTIM2_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM2_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_ARR + LPTIM2_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM2_CNT + LPTIM2_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM2_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM2_CFGR2 + LPTIM2_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM2_in1_mux0 + 0x0 + + + B_0x1 + LPTIM2_in1_mux1 + 0x1 + + + B_0x2 + LPTIM2_in1_mux2 + 0x2 + + + B_0x3 + LPTIM2_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM2_in2_mux0 + 0x0 + + + B_0x1 + LPTIM2_in2_mux1 + 0x1 + + + B_0x2 + LPTIM2_in2_mux2 + 0x2 + + + B_0x3 + LPTIM2_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM2_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM2_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM2_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM2_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM2_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM2_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM2_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM2_ic2_mux3 + 0x3 + + + + + + + LPTIM2_RCR + LPTIM2_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM2_CCMR1 + LPTIM2_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM2_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM2_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM2_CCMR2 + LPTIM2_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM2_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM2_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM2_CCR2 + LPTIM2_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM2_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_CCR3 + LPTIM2_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM2_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_CCR4 + LPTIM2_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM2_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPUART1 + LPUART address block description + LPUART + 0x40008000 + + 0x0 + 0x30 + registers + + + + LPUART_CR1 + LPUART_CR1 + LPUART control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable +When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode +When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. +When this bit is set, the LPUART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the LPUART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the LPUART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the LPUART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). +This bit can only be written when the LPUART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section132.4.14: RS232 Hardware flow control and RS485 Driver Enable. +If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section131.5.21: RS232 Hardware flow control and RS485 Driver Enable. +This bitfield can only be written when the LPUART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the LPUART is disabled (UE=0). +Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_CR1_ALTERNATE + LPUART_CR1_ALTERNATE + LPUART control register 1 + LPUART_CR1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable +When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode +When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. +When this bit is set, the LPUART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the LPUART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the LPUART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the LPUART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). +This bit can only be written when the LPUART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section132.4.14: RS232 Hardware flow control and RS485 Driver Enable. +If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section131.5.21: RS232 Hardware flow control and RS485 Driver Enable. +This bitfield can only be written when the LPUART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the LPUART is disabled (UE=0). +Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + LPUART_CR2 + LPUART_CR2 + LPUART control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the LPUART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + STOP + STOP bits +These bits are used for programming the stop bits. +This bitfield can only be written when the LPUART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the LPUART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ADD + Address of the LPUART node +These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). + 24 + 8 + read-write + + + + + LPUART_CR3 + LPUART_CR3 + LPUART control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the LPUART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the LPUART is disabled (UE=0). + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the LPUART is disabled (UE=0) + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. +This bit can only be written when the LPUART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data. + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the LPUART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the LPUART is disabled (UE=0). + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the LPUART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). +This bitfield can only be written when the LPUART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). +This bitfield can only be written when the LPUART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved. + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + Receive FIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + Receive FIFO becomes full. + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved. + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + TXFIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + TXFIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + TXFIFO becomes empty. + 0x5 + + + + + + + LPUART_BRR + LPUART_BRR + LPUART baud rate register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BRR + LPUART baud rate division (LPUARTDIV) + 0 + 20 + read-write + + + + + LPUART_RQR + LPUART_RQR + LPUART request register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software must wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit clears the RXNE flag. +This enables discarding the received data without reading it, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + LPUART_ISR + LPUART_ISR + LPUART interrupt and status register + 0x1C + 0x20 + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. +An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. +Note: This error is associated with the character in the LPUART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the LPUART_CR3 register. +Note: This error is associated with the character in the LPUART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag +This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: This error is associated with the character in the LPUART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. +An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. +Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. +The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the LPUART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: +When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXFE is set. +When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. +When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. +When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. +An interrupt is generated if TCIE=1 in the LPUART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the LPUART_ICR register or by writing to the LPUART_TDR register. + 6 + 1 + read-only + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. +The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF must be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). +An interrupt is generated if the TXFNFIE bit =1 in the LPUART_CR1 register. +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. +An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. +An interrupt is generated if CMIE=1in the LPUART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. +It can be used to verify that the LPUART is ready for reception before entering low-power mode. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 22 + 1 + read-only + + + TXFE + TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the LPUART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO is not empty. + 0x0 + + + B_0x1 + TXFIFO is empty. + 0x1 + + + + + RXFF + RXFIFO Full +This bit is set by hardware when the number of received data corresponds to RXFIFO1size1+11 (RXFIFO full + 1 data in the LPUART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the LPUART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO is not Full. + 0x0 + + + B_0x1 + RXFIFO is Full. + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the LPUART_CR3 register. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the LPUART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + LPUART_ISR_ALTERNATE + LPUART_ISR_ALTERNATE + LPUART interrupt and status register + LPUART_ISR + 0x1C + 0x20 + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. +An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the LPUART_CR3 register. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag +This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE/RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the LPUART_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled). It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. +An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. +Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the LPUART_RDR shift register has been transferred to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag is set when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the LPUART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the LPUART_TDR register has been transferred into the shift register. It is cleared by a write to the LPUART_TDR register. +An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register. +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. +An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. +An interrupt is generated if CMIE=1in the LPUART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. +It can be used to verify that the LPUART is ready for reception before entering low-power mode. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 22 + 1 + read-only + + + + + LPUART_ICR + LPUART_ICR + LPUART interrupt flag clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the LPUART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the LPUART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the LPUART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. + 4 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the LPUART_ISR register. + 6 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. + 9 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + write-only + + + + + LPUART_RDR + LPUART_RDR + LPUART receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure1254). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + LPUART_TDR + LPUART_TDR + LPUART transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure1254). +When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + LPUART_PRESC + LPUART_PRESC + LPUART prescaler register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The LPUART input clock can be divided by a prescaler: +Remaining combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + LPUART2 + 0x40008400 + + + OPAMP + OPAMP address block description + OPAMP + 0x40007800 + + 0x0 + 0xC + registers + + + + OPAMP_CSR + OPAMP_CSR + OPAMP control/status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPAEN + Operational amplifier Enable + 0 + 1 + read-write + + + B_0x0 + operational amplifier disabled + 0x0 + + + B_0x1 + operational amplifier enabled + 0x1 + + + + + OPALPM + Operational amplifier Low Power Mode +The operational amplifier must be disable to change this configuration. + 1 + 1 + read-write + + + B_0x0 + operational amplifier in normal mode + 0x0 + + + B_0x1 + operational amplifier in low-power mode + 0x1 + + + + + OPAMODE + Operational amplifier PGA mode + 2 + 2 + read-write + + + B_0x0 + internal PGA disable + 0x0 + + + B_0x1 + internal PGA disable + 0x1 + + + B_0x2 + internal PGA enable, gain programmed in PGA_GAIN + 0x2 + + + B_0x3 + internal follower + 0x3 + + + + + PGA_GAIN + Operational amplifier Programmable amplifier gain value + 4 + 2 + read-write + + + B_0x0 + internal PGA Gain 2 + 0x0 + + + B_0x1 + internal PGA Gain 4 + 0x1 + + + B_0x2 + internal PGA Gain 8 + 0x2 + + + B_0x3 + internal PGA Gain 16 + 0x3 + + + + + VM_SEL + Inverting input selection +These bits are used only when OPAMODE = 00, 01 or 10. +1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) + 8 + 2 + read-write + + + B_0x0 + GPIO connected to VINM (valid also in PGA mode for filtering) + 0x0 + + + + + VP_SEL + Non inverted input selection + 10 + 1 + read-write + + + B_0x0 + GPIO connected to VINP + 0x0 + + + B_0x1 + DAC connected to VINP + 0x1 + + + + + CALON + Calibration mode enabled + 12 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Calibration mode (all switches opened by HW) + 0x1 + + + + + CALSEL + Calibration selection + 13 + 1 + read-write + + + B_0x0 + NMOS calibration (200mV applied on OPAMP inputs) + 0x0 + + + B_0x1 + PMOS calibration (VDDA-200mV applied on OPAMP inputs) + 0x1 + + + + + USERTRIM + allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values +This bit is active for both mode normal and low-power. + 14 + 1 + read-write + + + B_0x0 + factory trim code used + 0x0 + + + B_0x1 + user trim code used + 0x1 + + + + + CALOUT + Operational amplifier calibration output +During calibration mode offset is trimmed when this signal toggle. + 15 + 1 + read-only + + + OPA_RANGE + Operational amplifier power supply range for stability +All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. + 31 + 1 + read-write + + + B_0x0 + Low range (VDDA < 2.4V) + 0x0 + + + B_0x1 + High range (VDDA > 2.4V) + 0x1 + + + + + + + OPAMP_OTR + OPAMP_OTR + OPAMP offset trimming register in normal mode + 0x04 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + read-write + + + + + OPAMP_LPOTR + OPAMP_LPOTR + OPAMP offset trimming register in low-power mode + 0x08 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMLPOFFSETN + Low-power mode trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMLPOFFSETP + Low-power mode trim for PMOS differential pairs + 8 + 5 + read-write + + + + + + + PWR + PWR register block + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Power control register 1 + 0x00 + 0x20 + 0x00000208 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when CPU enters the deepsleep mode. +1xx: Shutdown mode +Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. +Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x2 + Stop 2 mode + 0x2 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + Flash memory powered down during Stop mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. + 3 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_LPRUN + Flash memory powered down during Low-power run mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + 4 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_LPSLP + Flash memory powered down during Low-power sleep mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + 5 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + DBP + Disable backup domain write protection +In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. + 8 + 1 + read-write + + + B_0x0 + Access to RTC and Backup registers disabled + 0x0 + + + B_0x1 + Access to RTC and Backup registers enabled + 0x1 + + + + + VOS + Voltage scaling range selection + 9 + 2 + read-write + + + B_0x0 + Cannot be written (forbidden by hardware) + 0x0 + + + B_0x1 + Range 1 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Cannot be written (forbidden by hardware) + 0x3 + + + + + LPR + Low-power run +When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). +Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. + 14 + 1 + read-write + + + + + PWR_CR2 + PWR_CR2 + Power control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDE + Programmable voltage detector enable +Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. +Note: This bit is reset only by a system reset. + 0 + 1 + read-write + + + B_0x0 + Programmable voltage detector disable. + 0x0 + + + B_0x1 + Programmable voltage detector enable. + 0x1 + + + + + PLS + Programmable voltage detector level selection. +These bits select the voltage threshold detected by the programmable voltage detector: +Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. +Note: These bits are reset only by a system reset. + 1 + 3 + read-write + + + B_0x0 + V<sub>PVD0</sub> around 2.01V + 0x0 + + + B_0x1 + V<sub>PVD1</sub> around 2.21V + 0x1 + + + B_0x2 + V<sub>PVD2</sub> around 2.41V + 0x2 + + + B_0x3 + V<sub>PVD3</sub> around 2.51V + 0x3 + + + B_0x4 + V<sub>PVD4</sub> around 2.61V + 0x4 + + + B_0x5 + V<sub>PVD5</sub> around 2.81V + 0x5 + + + B_0x6 + V<sub>PVD6</sub> around 2.91V + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to VREFINT) + 0x7 + + + + + PVME1 + Peripheral voltage monitoring 1 enable: V<sub>DDUSB</sub> vs. 1.21V + 4 + 1 + read-write + + + B_0x0 + PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V threshold) disable. + 0x0 + + + B_0x1 + PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V threshold) enable. + 0x1 + + + + + PVME3 + Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. 1.621V + 5 + 1 + read-write + + + B_0x0 + PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V threshold) disable. + 0x0 + + + B_0x1 + PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V threshold) enable. + 0x1 + + + + + PVME4 + Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. 1.861V + 6 + 1 + read-write + + + B_0x0 + PVM4 (V<sub>DDA</sub> monitoring vs. 1.861V threshold) disable. + 0x0 + + + B_0x1 + PVM4 (V<sub>DDA</sub> monitoring vs. 1.86 V threshold) enable. + 0x1 + + + + + USV + V<sub>DDUSB</sub> USB supply valid +This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. +Setting this bit is mandatory to use the USB FS peripheral. If V<sub>DDUSB</sub> is not always +present in the application, the PVM can be used to determine whether this supply is ready or +not. + 10 + 1 + read-write + + + B_0x0 + V<sub>DDUSB</sub> is not present. Logical and electrical isolation is applied to ignore this supply. + 0x0 + + + B_0x1 + V<sub>DDUSB</sub> is valid. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + Power control register 3 + 0x08 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable Wake-up pin WKUP1 +When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. + 0 + 1 + read-write + + + EWUP2 + Enable Wake-up pin WKUP2 +When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. + 1 + 1 + read-write + + + EWUP3 + Enable Wake-up pin WKUP3 +When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. + 2 + 1 + read-write + + + EWUP4 + Enable Wake-up pin WKUP4 +When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + 3 + 1 + read-write + + + EWUP5 + Enable Wake-up pin WKUP5 +When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. + 4 + 1 + read-write + + + EWUP7 + Enable Wake-up pin WKUP7. +When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register. + 6 + 1 + read-write + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + read-write + + + B_0x0 + SRAM2 is powered off in Standby mode (SRAM2 content is lost). + 0x0 + + + B_0x1 + SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). + 0x1 + + + + + ENULP + Enable ULP sampling +When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. + 9 + 1 + read-write + + + APC + Apply pull-up and pull-down configuration +When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx +and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode. + 10 + 1 + read-write + + + EIWUL + Enable internal wake-up line + 15 + 1 + read-write + + + B_0x0 + Internal wake-up line disable. + 0x0 + + + B_0x1 + Internal wake-up line enable. + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + Power control register 4 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WP1 + Wake-up pin WKUP1 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP2 + Wake-up pin WKUP2 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP3 + Wake-up pin WKUP3 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP4 + Wake-up pin WKUP4 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP5 + Wake-up pin WKUP5 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP7 + Wake-up pin WKUP7 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP7 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + VBE + V<sub>BAT</sub> battery charging enable + 8 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> battery charging disable + 0x0 + + + B_0x1 + V<sub>BAT</sub> battery charging enable + 0x1 + + + + + VBRS + V<sub>BAT</sub> battery charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge V<sub>BAT</sub> through a 5 kOhms resistor + 0x0 + + + B_0x1 + Charge V<sub>BAT</sub> through a 1.5 kOhms resistor + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + Power status register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wake-up flag 1 +This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. + 0 + 1 + read-only + + + WUF2 + Wake-up flag 2 +This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. + 1 + 1 + read-only + + + WUF3 + Wake-up flag 3 +This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. + 2 + 1 + read-only + + + WUF4 + Wake-up flag 4 +This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. + 3 + 1 + read-only + + + WUF5 + Wake-up flag 5 +This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. + 4 + 1 + read-only + + + WUF7 + Wake-up flag 7 +This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register. + 6 + 1 + read-only + + + SBF + Standby flag +This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 8 + 1 + read-only + + + B_0x0 + The device did not enter the Standby mode + 0x0 + + + B_0x1 + The device entered the Standby mode + 0x1 + + + + + STOPF + Stop Flags +These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 9 + 3 + read-only + + + B_0x0 + The device did not enter any Stop mode. + 0x0 + + + B_0x4 + The device entered in Stop 0 mode. + 0x4 + + + B_0x5 + The device entered in Stop 1 mode. + 0x5 + + + B_0x6 + The device entered in Stop 2 mode. + 0x6 + + + + + WUFI + Wake-up flag internal +This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared. + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + Power status register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FLASH_RDY + Flash ready flag +This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. +Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory. + 7 + 1 + read-only + + + B_0x0 + Flash memory in power down + 0x0 + + + B_0x1 + Flash memory ready to be accessed + 0x1 + + + + + REGLPS + Low-power regulator started +This bit provides the information whether the low-power regulator is ready after a power-on +reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased. + 8 + 1 + read-only + + + B_0x0 + The low-power regulator is not ready + 0x0 + + + B_0x1 + The low-power regulator is ready + 0x1 + + + + + REGLPF + Low-power regulator flag +This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits +from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. +This bit is cleared by hardware when the regulator is ready. + 9 + 1 + read-only + + + B_0x0 + The regulator is ready in main mode (MR) + 0x0 + + + B_0x1 + The regulator is in low-power mode (LPR) + 0x1 + + + + + VOSF + Voltage scaling flag +A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. + 10 + 1 + read-only + + + B_0x0 + The regulator is ready in the selected voltage range + 0x0 + + + B_0x1 + The regulator output voltage is changing to the required voltage level + 0x1 + + + + + PVDO + Programmable voltage detector output + 11 + 1 + read-only + + + B_0x0 + V<sub>DD</sub> is above the selected PVD threshold + 0x0 + + + B_0x1 + V<sub>DD</sub> is below the selected PVD threshold + 0x1 + + + + + PVMO1 + Peripheral voltage monitoring output: V<sub>DDUSB</sub> vs. 1.2 V +Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time. + 12 + 1 + read-only + + + B_0x0 + V<sub>DDUSB</sub> voltage is above PVM1 threshold (around 1.21V). + 0x0 + + + B_0x1 + V<sub>DDUSB</sub> voltage is below PVM1 threshold (around 1.21V). + 0x1 + + + + + PVMO3 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.621V +Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time. + 14 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM3 threshold (around 1.621V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM3 threshold (around 1.621V). + 0x1 + + + + + PVMO4 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 2.21V +Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time. + 15 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM4 threshold (around 2.21V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM4 threshold (around 2.21V). + 0x1 + + + + + + + PWR_SCR + PWR_SCR + Power status clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wake-up flag 1 +Setting this bit clears the WUF1 flag in the PWR_SR1 register. + 0 + 1 + write-only + + + CWUF2 + Clear wake-up flag 2 +Setting this bit clears the WUF2 flag in the PWR_SR1 register. + 1 + 1 + write-only + + + CWUF3 + Clear wake-up flag 3 +Setting this bit clears the WUF3 flag in the PWR_SR1 register. + 2 + 1 + write-only + + + CWUF4 + Clear wake-up flag 4 +Setting this bit clears the WUF4 flag in the PWR_SR1 register. + 3 + 1 + write-only + + + CWUF5 + Clear wake-up flag 5 +Setting this bit clears the WUF5 flag in the PWR_SR1 register. + 4 + 1 + write-only + + + CWUF7 + Clear wake-up flag 7 +Setting this bit clears the WUF7 flag in the PWR_SR1 register. + 6 + 1 + write-only + + + CSBF + Clear standby flag +Setting this bit clears the SBF flag in the PWR_SR1 register. + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU7 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + PU14 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 14 + 1 + read-write + + + PU15 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PU1 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PU2 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PU3 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PU4 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PU5 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PU6 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PU7 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PU8 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PU9 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PU10 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PU11 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PU12 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PU13 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PU14 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PU15 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU7 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + PU14 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 14 + 1 + read-write + + + PU15 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU8 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD8 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU3 + Port E pull-up bit 3 +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU7 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD3 + Port E pull-down bit 3 +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD7 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + + + + + RCC + RCC address block description + RCC + 0x40021000 + + 0x0 + 0x9C + registers + + + RCC_CRS + RCC and CRS global interrupt + 4 + + + + RCC_CR + RCC_CR + Clock control register + 0x00 + 0x20 + 0x00000083 + 0xFFFFFFFF + + + MSION + MSI clock enable +This bit is set and cleared by software. +Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. +Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. +Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator +Set by hardware when used directly or indirectly as system clock. + 0 + 1 + read-write + + + B_0x0 + MSI oscillator OFF + 0x0 + + + B_0x1 + MSI oscillator ON + 0x1 + + + + + MSIRDY + MSI clock ready flag +This bit is set by hardware to indicate that the MSI oscillator is stable. +Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. + 1 + 1 + read-only + + + B_0x0 + MSI oscillator not ready + 0x0 + + + B_0x1 + MSI oscillator ready + 0x1 + + + + + MSIPLLEN + MSI clock PLL enable +Set and cleared by software to enable/ disable the PLL part of the MSI clock source. +MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. +This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). + 2 + 1 + read-write + + + B_0x0 + MSI PLL OFF + 0x0 + + + B_0x1 + MSI PLL ON + 0x1 + + + + + MSIRGSEL + MSI clock range selection +Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. +After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. + 3 + 1 + read-write + + + B_0x0 + MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + 0x0 + + + B_0x1 + MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + 0x1 + + + + + MSIRANGE + MSI clock ranges +These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: +others: not allowed (hardware write protection) +Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0) + 4 + 4 + read-write + + + B_0x0 + range 0 around 1001kHz + 0x0 + + + B_0x1 + range 1 around 2001kHz + 0x1 + + + B_0x2 + range 2 around 4001kHz + 0x2 + + + B_0x3 + range 3 around 8001kHz + 0x3 + + + B_0x4 + range 4 around 1M1Hz + 0x4 + + + B_0x5 + range 5 around 21MHz + 0x5 + + + B_0x6 + range 6 around 41MHz (reset value) + 0x6 + + + B_0x7 + range 7 around 81MHz + 0x7 + + + B_0x8 + range 8 around 161MHz + 0x8 + + + B_0x9 + range 9 around 241MHz + 0x9 + + + B_0xA + range 10 around 321MHz + 0xA + + + B_0xB + range 11 around 481MHz + 0xB + + + + + HSION + HSI16 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. +Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator OFF + 0x0 + + + B_0x1 + HSI16 oscillator ON + 0x1 + + + + + HSIKERON + HSI16 always enable for peripheral kernels. +Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator. + 0x0 + + + B_0x1 + HSI16 oscillator is forced ON even in Stop mode. + 0x1 + + + + + HSIRDY + HSI16 clock ready flag +Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. +Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSIASFS + HSI16 automatic start from Stop +Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI16 is parallel of the system wake-up. + 11 + 1 + read-only + + + B_0x0 + HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wake-up clock. + 0x0 + + + B_0x1 + HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wake-up clock. + 0x1 + + + + + HSEON + HSE clock enable +Set and cleared by software. +Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable. +Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable +Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + 19 + 1 + read-write + + + B_0x0 + Clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + PLLON + PLL enable +Set and cleared by software to enable the PLL. +Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + 24 + 1 + read-write + + + B_0x0 + PLL OFF + 0x0 + + + B_0x1 + PLL ON + 0x1 + + + + + PLLRDY + PLL clock ready flag +Set by hardware to indicate that the PLL is locked. + 25 + 1 + read-only + + + B_0x0 + PLL unlocked + 0x0 + + + B_0x1 + PLL locked + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + Internal clock sources calibration register + 0x04 + 0x20 + 0x40004000 + 0xFF00FF00 + + + MSICAL + MSI clock calibration +These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. + 0 + 8 + read-only + + + MSITRIM + MSI clock trimming +These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. + 8 + 8 + read-write + + + HSICAL + HSI16 clock calibration +These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + 16 + 8 + read-only + + + HSITRIM + HSI16 clock trimming +These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. +The default value is 64 when added to the HSICAL value, trim the HSI16 to 161MHz 1 11%. + 24 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + Clock configuration register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SW + System clock switch +This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: +Others: Reserved +The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + 0 + 3 + read-write + + + B_0x0 + MSI + 0x0 + + + B_0x1 + HSI16 + 0x1 + + + B_0x2 + HSE + 0x2 + + + B_0x3 + PLLRCLK + 0x3 + + + B_0x4 + LSI + 0x4 + + + B_0x5 + LSE + 0x5 + + + + + SWS + System clock switch status +This bitfield is controlled by hardware to indicate the clock source used as system clock: +Others: Reserved + 3 + 3 + read-only + + + B_0x0 + MSI + 0x0 + + + B_0x1 + HSI16 + 0x1 + + + B_0x2 + HSE + 0x2 + + + B_0x3 + PLLRCLK + 0x3 + + + B_0x4 + LSI + 0x4 + + + B_0x5 + LSE + 0x5 + + + + + HPRE + AHB prescaler +This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: +0xxx: 1 +Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. + 8 + 4 + read-write + + + B_0x8 + 2 + 0x8 + + + B_0x9 + 4 + 0x9 + + + B_0xA + 8 + 0xA + + + B_0xB + 16 + 0xB + + + B_0xC + 64 + 0xC + + + B_0xD + 128 + 0xD + + + B_0xE + 256 + 0xE + + + B_0xF + 512 + 0xF + + + + + PPRE + APB prescaler +This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: +0xx: 1 + 12 + 3 + read-write + + + B_0x4 + 2 + 0x4 + + + B_0x5 + 4 + 0x5 + + + B_0x6 + 8 + 0x6 + + + B_0x7 + 16 + 0x7 + + + + + STOPWUCK + Wake-up from Stop and CSS backup clock selection +Set and cleared by software to select the system clock used when exiting Stop mode. +The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10). + 15 + 1 + read-write + + + B_0x0 + MSI oscillator selected as wake-up from stop clock and CSS backup clock. + 0x0 + + + B_0x1 + HSI16 oscillator selected as wake-up from stop clock and CSS backup clock + 0x1 + + + + + MCO2SEL + Microcontroller clock output 2 clock selector +This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. + 16 + 4 + read-write + + + B_0x0 + no clock, MCO2 output disabled + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + MSI + 0x2 + + + B_0x3 + HSI16 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x5 + PLLRCLK + 0x5 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSI48 + 0x8 + + + B_0x9 + RTCCLK + 0x9 + + + B_0xA + RTC WAKEUP + 0xA + + + + + MCO2PRE + Microcontroller clock output 2 prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: +... +Others: reserved +It is highly recommended to set this field before the MCO2 output is enabled. + 20 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + MCOSEL + Microcontroller clock output clock selector +This bitfield is controlled by software. It sets the clock selector for MCO output as follows: +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + 24 + 4 + read-write + + + B_0x0 + no clock, MCO output disabled + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + MSI + 0x2 + + + B_0x3 + HSI16 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x5 + PLLRCLK + 0x5 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSI48 + 0x8 + + + B_0x9 + RTCCLK + 0x9 + + + B_0xA + RTC WAKEUP + 0xA + + + + + MCOPRE + Microcontroller clock output prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: +... +Others: reserved +It is highly recommended to set this field before the MCO output is enabled. + 28 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + + + RCC_PLLCFGR + RCC_PLLCFGR + PLL configuration register + 0x0C + 0x20 + 0x00001000 + 0xFFFFFFFF + + + PLLSRC + PLL input clock source +This bit is controlled by software to select PLL clock source, as follows: +The bitfield can be written only when the PLL is disabled. +When the PLL is not used, selecting 00 allows saving power. + 0 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + MSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + HSE + 0x3 + + + + + PLLM + Division factor M of the PLL input clock divider +This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: +The bitfield can be written only when the PLL is disabled. +Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz. + 4 + 3 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + PLLN + PLL frequency multiplication factor N +This bit is controlled by software to set the division factor of the f<sub>VCO</sub> feedback divider (that determines the PLL multiplication ratio) as follows: +... +... +The bitfield can be written only when the PLL is disabled. +Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz. + 8 + 7 + read-write + + + B_0x0 + Invalid + 0x0 + + + B_0x4 + 4 + 0x4 + + + B_0x5 + 5 + 0x5 + + + B_0x7E + 126 + 0x7E + + + B_0x7F + 127 + 0x7F + + + + + PLLPEN + PLLPCLK clock output enable +This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: +Disabling the PLLPCLK clock output, when not used, allows saving power. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLP + PLL VCO division factor P for PLLPCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: +... +The bitfield can be written only when the PLL is disabled. +Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + 17 + 5 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x1F + 32 + 0x1F + + + + + PLLQEN + PLLQCLK clock output enable +This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: +Disabling the PLLQCLK clock output, when not used, allows saving power. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLQ + PLL VCO division factor Q for PLLQCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: +The bitfield can be written only when the PLL is disabled. +Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + 25 + 3 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + PLLREN + PLLRCLK clock output enable +This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: +This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. +Disabling the PLLRCLK clock output, when not used, allows saving power. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLR + PLL VCO division factor R for PLLRCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: +The bitfield can be written only when the PLL is disabled. +The PLLRCLK clock can be selected as system clock. +Caution: The software must set this bitfield so as not to exceed 122MHz on this clock. + 29 + 3 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + + + RCC_CIER + RCC_CIER + Clock interrupt enable register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MSIRDYIE + MSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. + 2 + 1 + read-write + + + B_0x0 + MSI ready interrupt disabled + 0x0 + + + B_0x1 + MSI ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization: + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLRDYIE + PLL ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by PLL lock: + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSIE + LSE clock security system interrupt enable +Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. + 9 + 1 + read-write + + + B_0x0 + Clock security interrupt caused by LSE clock failure disabled + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + 10 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + Clock interrupt flag register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. +Cleared by software setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. +Cleared by software setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + MSIRDYF + MSI ready interrupt flag +Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. +Cleared by software setting the MSIRDYC bit. + 2 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the MSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the MSI oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag +Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +Set by hardware when the HSE clock becomes stable and HSERDYIE is set. +Cleared by software setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + PLLRDYF + PLL ready interrupt flag +Set by hardware when the PLL locks and PLLRDYIE is set. +Cleared by software setting the PLLRDYC bit. + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL lock + 0x1 + + + + + CSSF + HSE clock security system interrupt flag +Set by hardware when a failure is detected in the HSE oscillator. +Cleared by software setting the CSSC bit. + 8 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + LSECSSF + LSE clock security system interrupt flag +Set by hardware when a failure is detected in the LSE oscillator. +Cleared by software by setting the LSECSSC bit. + 9 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by LSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag +Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). +Cleared by software setting the HSI48RDYC bit. + 10 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + Clock interrupt clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +This bit is set by software to clear the LSIRDYF flag. + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSIRDYF flag + 0x1 + + + + + LSERDYC + LSE ready interrupt clear +This bit is set by software to clear the LSERDYF flag. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSERDYF flag + 0x1 + + + + + MSIRDYC + MSI ready interrupt clear +This bit is set by software to clear the MSIRDYF flag. + 2 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + MSIRDYF cleared + 0x1 + + + + + HSIRDYC + HSI16 ready interrupt clear +This bit is set software to clear the HSIRDYF flag. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear +This bit is set by software to clear the HSERDYF flag. + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + PLLRDYC + PLL ready interrupt clear +This bit is set by software to clear the PLLRDYF flag. + 5 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear PLLRDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear +This bit is set by software to clear the HSECSSF flag. + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear +This bit is set by software to clear the LSECSSF flag. + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + HSI48RDYC + HSI48 oscillator ready interrupt clear +This bit is set by software to clear the HSI48RDYF flag. + 10 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSI48RDYC flag + 0x1 + + + + + + + RCC_AHBRSTR + RCC_AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 and DMAMUX reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 and DMAMUX + 0x1 + + + + + DMA2RST + DMA2 and DMAMUX reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA2 and DMAMUX + 0x1 + + + + + FLASHRST + Flash memory interface reset +Set and cleared by software. +This bit can only be set when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset flash memory interface + 0x1 + + + + + CRCRST + CRC reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + RNGRST + Random number generator reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset RNG + 0x1 + + + + + TSCRST + Touch sensing controller reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TSC + 0x1 + + + + + + + RCC_IOPRSTR + RCC_IOPRSTR + I/O port reset register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + I/O port A reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port A + 0x1 + + + + + GPIOBRST + I/O port B reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port B + 0x1 + + + + + GPIOCRST + I/O port C reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port C + 0x1 + + + + + GPIODRST + I/O port D reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port D + 0x1 + + + + + GPIOERST + I/O port E reset +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port E + 0x1 + + + + + GPIOFRST + I/O port F reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port F + 0x1 + + + + + + + RCC_APBRSTR1 + RCC_APBRSTR1 + APB peripheral reset register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM6RST + TIM6 timer reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM6 + 0x1 + + + + + TIM7RST + TIM7 timer reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + LPUART2RST + LPUART2 reset +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART2 + 0x1 + + + + + LCDRST + LCD reset<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LCD + 0x1 + + + + + USBRST + USB reset<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB + 0x1 + + + + + SPI2RST + SPI2 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + USART2RST + USART2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + USART3RST + USART3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART3 + 0x1 + + + + + USART4RST + USART4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART4 + 0x1 + + + + + LPUART1RST + LPUART1 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART1 + 0x1 + + + + + I2C1RST + I2C1 reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + I2C3RST + I2C3 reset +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C3 + 0x1 + + + + + OPAMPRST + OPAMP reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OPAMP + 0x1 + + + + + PWRRST + Power interface reset +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + DAC1RST + DAC1 interface reset +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC1 interface + 0x1 + + + + + LPTIM2RST + Low Power Timer 2 reset +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM2 + 0x1 + + + + + LPTIM1RST + Low Power Timer 1 reset +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM1 + 0x1 + + + + + + + RCC_APBRSTR2 + RCC_APBRSTR2 + APB peripheral reset register 2 + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG, COMP and VREFBUF reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + COMP + VREFBUF + 0x1 + + + + + TIM1RST + TIM1 timer reset +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + USART1RST + USART1 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + TIM15RST + TIM15 timer reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM15 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + ADCRST + ADC reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC + 0x1 + + + + + + + RCC_AHBENR + RCC_AHBENR + AHB peripheral clock enable register + 0x48 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMA2EN + DMA2 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHEN + Flash memory interface clock enable +Set and cleared by software. +This bit can only be cleared when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCEN + CRC clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RNGEN + Random number generator clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TSCEN + Touch sensing controller clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + TSC clock disable + 0x0 + + + B_0x1 + TSC clock enable + 0x1 + + + + + + + RCC_IOPENR + RCC_IOPENR + I/O port clock enable register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + I/O port A clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBEN + I/O port B clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCEN + I/O port C clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODEN + I/O port D clock enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOEEN + I/O port E clock enable<sup>(1)</sup> +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFEN + I/O port F clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_DBGCFGR + RCC_DBGCFGR + Debug configuration register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBGEN + Debug support clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DBGRST + Debug support reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DBG + 0x1 + + + + + + + RCC_APBENR1 + RCC_APBENR1 + APB peripheral clock enable register 1 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3EN + TIM3 timer clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM6EN + TIM6 timer clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM7EN + TIM7 timer clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART2EN + LPUART2 clock enable +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LCDEN + LCD clock enable<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBEN + RTC APB clock enable +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGEN + WWDG clock enable +Set by software to enable the window watchdog clock. Cleared by hardware system reset +This bit can also be set by hardware if the WWDG_SW option bit is 0. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBEN + USB clock enable<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2EN + SPI2 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2EN + USART2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART3EN + USART3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART4EN + USART4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART1EN + LPUART1 clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2EN + I2C2 clock enable +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3EN + I2C3 clock enable +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OPAMPEN + OPAMP clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWREN + Power interface clock enable +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DAC1EN + DAC1 interface clock enable +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM2EN + LPTIM2 clock enable +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM1EN + LPTIM1 clock enable +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBENR2 + RCC_APBENR2 + APB peripheral clock enable register 2 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1EN + TIM1 timer clock enable +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1EN + SPI1 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1EN + USART1 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM15EN + TIM15 timer clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16EN + TIM16 timer clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCEN + ADC clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_AHBSMENR + RCC_AHBSMENR + AHB peripheral clock enable in Sleep/Stop mode register + 0x68 + 0x20 + 0x01051303 + 0xFFFFFFFF + + + DMA1SMEN + DMA1 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMA2SMEN + DMA2 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHSMEN + Flash memory interface clock enable during Sleep mode +Set and cleared by software. +This bit can be activated only when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SRAMSMEN + SRAM clock enable during Sleep mode +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCSMEN + CRC clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RNGSMEN + RNG clock enable during Sleep and Stop mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TSCSMEN + TSC clock enable during Sleep and Stop mode +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_IOPSMENR + RCC_IOPSMENR + I/O port in Sleep mode clock enable register + 0x6C + 0x20 + 0x0000003F + 0xFFFFFFFF + + + GPIOASMEN + I/O port A clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBSMEN + I/O port B clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCSMEN + I/O port C clock enable during Sleep mode +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODSMEN + I/O port D clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOESMEN + I/O port E clock enable during Sleep mode +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFSMEN + I/O port F clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR1 + RCC_APBSMENR1 + APB peripheral clock enable in Sleep/Stop mode register 1 + 0x78 + 0x20 + 0xFF7E4C33 + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3SMEN + TIM3 timer clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM6SMEN + TIM6 timer clock enable during Sleep mode +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM7SMEN + TIM7 timer clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART2SMEN + LPUART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LCDSMEN + LCD clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep mode +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGSMEN + WWDG clock enable during Sleep and Stop modes +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBSMEN + USB clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2SMEN + SPI2 clock enable during Sleep mode +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2SMEN + USART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART3SMEN + USART3 clock enable during Sleep mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART4SMEN + USART4 clock enable during Sleep mode +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART1SMEN + LPUART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1SMEN + I2C1 clock enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2SMEN + I2C2 clock enable during Sleep mode +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3SMEN + I2C3 clock enable during Sleep mode +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OPAMPSMEN + OPAMP clock enable during Sleep and Stop modes +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWRSMEN + Power interface clock enable during Sleep mode +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DAC1SMEN + DAC1 interface clock enable during Sleep and Stop modes +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM2SMEN + Low Power Timer 2 clock enable during Sleep and Stop modes +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM1SMEN + Low Power Timer 1 clock enable during Sleep and Stop modes +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR2 + RCC_APBSMENR2 + APB peripheral clock enable in Sleep/Stop mode register 2 + 0x80 + 0x20 + 0x0017D801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1SMEN + TIM1 timer clock enable during Sleep mode +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1SMEN + SPI1 clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1SMEN + USART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM15SMEN + TIM15 timer clock enable during Sleep mode +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16SMEN + TIM16 timer clock enable during Sleep mode +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCSMEN + ADC clock enable during Sleep mode +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_CCIPR + RCC_CCIPR + Peripherals independent clock configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection +This bitfield is controlled by software to select USART1 clock source as follows: + 0 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + USART2SEL + USART2 clock source selection +This bitfield is controlled by software to select USART2 clock source as follows: + 2 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART2SEL + LPUART2 clock source selection +This bitfield is controlled by software to select LPUART2 clock source as follows: + 8 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART1SEL + LPUART1 clock source selection +This bitfield is controlled by software to select LPUART1 clock source as follows: + 10 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + I2C1SEL + I2C1 clock source selection +This bitfield is controlled by software to select I2C1 clock source as follows: + 12 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + I2C3SEL + I2C3 clock source selection +This bitfield is controlled by software to select I2C3 clock source as follows: + 16 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + LPTIM1SEL + LPTIM1 clock source selection +This bitfield is controlled by software to select LPTIM1 clock source as follows: + 18 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPTIM2SEL + LPTIM2 clock source selection +This bitfield is controlled by software to select LPTIM2 clock source as follows: + 20 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + TIM1SEL + TIM1 clock source selection +This bit is set and cleared by software. It selects TIM1 clock source as follows: + 24 + 1 + read-write + + + B_0x0 + TIMPCLK + 0x0 + + + B_0x1 + PLLQCLK + 0x1 + + + + + TIM15SEL + TIM15 clock source selection +This bit is set and cleared by software. It selects TIM15 clock source as follows: + 25 + 1 + read-write + + + B_0x0 + TIMPCLK + 0x0 + + + B_0x1 + PLLQCLK + 0x1 + + + + + CLK48SEL + 481MHz clock source selection +This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG: + 26 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + MSI + 0x1 + + + B_0x2 + PLLQCLK + 0x2 + + + B_0x3 + HSI48<sup>(1)</sup> + 0x3 + + + + + ADCSEL + ADCs clock source selection +This bitfield is controlled by software to select the clock source for ADC: + 28 + 2 + read-write + + + B_0x0 + System clock + 0x0 + + + B_0x1 + PLLPCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + + + RCC_BDCR + RCC_BDCR + RTC domain control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +Set and cleared by software to enable LSE oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): +After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and cleared by software to bypass the LSE oscillator (in debug mode). +This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0). + 2 + 1 + read-write + + + B_0x0 + Not bypassed + 0x0 + + + B_0x1 + Bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +Set by software to select the LSE oscillator drive capability as follows: +Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. + 3 + 2 + read-write + + + B_0x0 + low driving capability + 0x0 + + + B_0x1 + medium-low driving capability + 0x1 + + + B_0x2 + medium-high driving capability + 0x2 + + + B_0x3 + high driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable +Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: +LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD +=1). In that case the software must disable the LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection +Set by hardware to indicate when a failure is detected by the clock security system +on the external 321kHz oscillator (LSE): + 6 + 1 + read-only + + + B_0x0 + No failure detected + 0x0 + + + B_0x1 + Failure detected + 0x1 + + + + + LSESYSEN + LSE clock enable for system usage +This bit must be set by software to enable the LSE clock for a system usage. + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled, LSE distributed to peripherals including LSCO/MCO/SYSCLK. + 0x1 + + + + + RTCSEL + RTC clock source selection +Set by software to select the clock source for the RTC as follows: +Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00. + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE + 0x1 + + + B_0x2 + LSI + 0x2 + + + B_0x3 + HSE divided by 32 + 0x3 + + + + + LSESYSRDY + LSE clock ready for system usage +This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. +Cleared by hardware to indicate that the LSE clock is not ready to be used by the system. + 11 + 1 + read-only + + + B_0x0 + LSE clock not ready for system + 0x0 + + + B_0x1 + LSE clock ready for system + 0x1 + + + + + RTCEN + RTC clock enable +Set and cleared by software. The bit enables clock to RTC and TAMP. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + BDRST + RTC domain software reset +Set and cleared by software to reset the RTC domain: + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSCOSEL + Low-speed clock output selection +Set and cleared by software to select the low-speed output clock: + 25 + 1 + read-write + + + B_0x0 + LSI + 0x0 + + + B_0x1 + LSE + 0x1 + + + + + + + RCC_CSR + RCC_CSR + Control/status register + 0x94 + 0x20 + 0x00000000 + 0x00FFFFFF + + + LSION + LSI oscillator enable +Set and cleared by software to enable/disable the LSI oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): +After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSIPREDIV + Internal low-speed oscillator pre-divided by 128 +Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit. + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator is not divided + 0x0 + + + B_0x1 + LSI RC oscillator is divided by 128 + 0x1 + + + + + MSISRANGE + MSI range after Standby mode +Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. +Others: Reserved +Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency. + 8 + 4 + read-write + + + B_0x4 + Range 7 around 81MHz + 0x4 + + + + + RMVF + Remove reset flags +Set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag +Set by hardware when a reset from the Option byte loading occurs. +Cleared by setting the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from Option byte loading occurred + 0x0 + + + B_0x1 + Reset from Option byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag +Set by hardware when a reset from the NRST pin occurs. +Cleared by setting the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + PWRRSTF + BOR or POR/PDR flag +Set by hardware when a BOR or POR/PDR occurs. +Cleared by setting the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR or POR occurred + 0x0 + + + B_0x1 + BOR or POR occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Set by hardware when a software reset occurs. +Cleared by setting the RMVF bit. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag +Set by hardware when an independent watchdog reset domain occurs. +Cleared by setting the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +Set by hardware when a window watchdog reset occurs. +Cleared by setting the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. +Cleared by setting the RMVF bit. +This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared. + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x98 + 0x20 + 0x00008800 + 0x0000FFFF + + + HSI48ON + HSI48 RC oscillator enable<sup>(1)</sup> + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag<sup>(1)</sup> +The flag is set when the HSI48 clock is ready for use. + 1 + 1 + read-only + + + HSI48CAL + HSI48 clock calibration +These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + 7 + 9 + read-only + + + + + + + RNG + RNG address block description + RNG + 0x40025000 + + 0x0 + 0x14 + registers + + + + RNG_CR + RNG_CR + RNG control register + 0x000 + 0x20 + 0x00800D00 + 0xFFFFFFFF + + + RNGEN + True random number generator enable + 2 + 1 + read-write + + + B_0x0 + True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. + 0x0 + + + B_0x1 + True random number generator is enabled. + 0x1 + + + + + IE + Interrupt enable + 3 + 1 + read-write + + + B_0x0 + RNG interrupt is disabled + 0x0 + + + B_0x1 + RNG interrupt is enabled. An interrupt is pending as soon as DRDY1=11, SEIS1=11 or CEIS1=11 in the RNG_SR register. + 0x1 + + + + + CED + Clock error detection +The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED, the RNG must be disabled. +Writing this bit is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 5 + 1 + read-write + + + B_0x0 + Clock error detection enabled + 0x0 + + + B_0x1 + Clock error detection is disabled + 0x1 + + + + + ARDIS + Auto reset disable +When auto-reset is enabled the application still need to clear the SEIS bit after a noise source error. +Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 7 + 1 + read-write + + + B_0x0 + When a noise source error occurs RNG performs an automatic reset to clear the SECS bit. + 0x0 + + + B_0x1 + When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation. + 0x1 + + + + + RNG_CONFIG3 + RNG configuration 3 +Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. +If the NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG. + 8 + 4 + read-write + + + NISTC + NIST custom +two conditioning loops are performed and 256 bits of noise source are used. +Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 12 + 1 + read-write + + + B_0x0 + Hardware default values for NIST compliant RNG. In this configuration per 128-bit output + 0x0 + + + B_0x1 + Custom values for NIST compliant RNG. See Section120.6: RNG entropy source validation for proposed configuration. + 0x1 + + + + + RNG_CONFIG2 + RNG configuration 2 +Reserved to the RNG configuration (bitfield 2). Bit 13 can be set when RNG power consumption is critical. See Section120.3.8: RNG low-power use. Refer to the RNG_CONFIG1 bitfield for details. + 13 + 3 + read-write + + + CLKDIV + Clock divider factor +This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN1=10). +... +Writing these bits is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 16 + 4 + read-write + + + B_0x0 + internal RNG clock after divider is similar to incoming RNG clock. + 0x0 + + + B_0x1 + two RNG clock cycles per internal RNG clock. + 0x1 + + + B_0x2 + 2<sup>2</sup> (= 4) RNG clock cycles per internal RNG clock. + 0x2 + + + B_0xF + 2<sup>15</sup> RNG clock cycles per internal clock (for example. an incoming 481MHz RNG clock becomes a 1.51kHz internal RNG clock) + 0xF + + + + + RNG_CONFIG1 + RNG configuration 1 +Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section120.6: RNG entropy source validation. +Writing any bit of RNG_CONFIG1 is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 20 + 6 + read-write + + + CONDRST + Conditioning soft reset +Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_HTCR are not changed by CONDRST. +This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. +When CONDRST is set to 0 by the software, its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles. + 30 + 1 + read-write + + + CONFIGLOCK + RNG Config lock +This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset. + 31 + 1 + read-write + + + B_0x0 + Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. + 0x0 + + + B_0x1 + Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG status register + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DRDY + Data ready +Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. +Note: The DRDY bit can rise when the peripheral is disabled (RNGEN1=10 in the RNG_CR register). +If IE=1 in the RNG_CR register, an interrupt is generated when DRDY1=11. + 0 + 1 + read-only + + + B_0x0 + The RNG_DR register is not yet valid, no random data is available. + 0x0 + + + B_0x1 + The RNG_DR register contains valid random data. + 0x1 + + + + + CECS + Clock error current status +Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. + 1 + 1 + read-only + + + B_0x0 + The RNG clock is correct (f<sub>RNGCLK</sub>> f<sub>HCLK</sub>/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. + 0x0 + + + B_0x1 + The RNG clock is too slow (f<sub>RNGCLK</sub>< f<sub>HCLK</sub>/32). + 0x1 + + + + + SECS + Seed error current status +Runtime repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) +Startup or continuous adaptive proportion test on noise source failed. +Startup post-processing/conditioning sanity check failed. + 2 + 1 + read-only + + + B_0x0 + No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. + 0x0 + + + B_0x1 + At least one of the following faulty sequences has been detected: + 0x1 + + + + + CEIS + Clock error interrupt status +This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 5 + 1 + read-write + + + B_0x0 + The RNG clock is correct (f<sub>RNGCLK</sub>> f<sub>HCLK</sub>/32) + 0x0 + + + B_0x1 + The RNG clock before the internal divider is detected too slow (f<sub>RNGCLK</sub>< f<sub>HCLK</sub>/32) + 0x1 + + + + + SEIS + Seed error interrupt status +This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 6 + 1 + read-write + + + B_0x0 + No faulty sequence detected + 0x0 + + + B_0x1 + At least one faulty sequence is detected. See SECS bit description for details. + 0x1 + + + + + + + RNG_DR + RNG_DR + RNG data register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNDATA + Random data +32-bit random data, which are valid when DRDY1=11. When DRDY1=10, the RNDATA value is1zero. +When DRDY is set, it is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). + 0 + 32 + read-only + + + + + RNG_HTCR + RNG_HTCR + RNG health test control register + 0x010 + 0x20 + 0x000072AC + 0xFFFFFFFF + + + HTCFG + health test configuration +This configuration is used by RNG to configure the health tests. See Section120.6: RNG entropy source validation for the recommended value. +Note: The RNG behavior, including the read to this register, is not guaranteed if a different value from the recommended value is written. + 0 + 32 + read-write + + + + + + + RTC + RTC register block + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP + RTC and TAMP interrupts(combined EXTI lines 19 and 21) + 2 + + + + RTC_TR + RTC_TR + RTC time register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_DR + RTC_DR + RTC date register + 0x04 + 0x20 + 0x00002101 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-write + + + DT + Date tens in BCD format + 4 + 2 + read-write + + + MU + Month units in BCD format + 8 + 4 + read-write + + + MT + Month tens in BCD format + 12 + 1 + read-write + + + WDU + Week day units +... + 13 + 3 + read-write + + + B_0x0 + forbidden + 0x0 + + + B_0x1 + Monday + 0x1 + + + B_0x7 + Sunday + 0x7 + + + + + YU + Year units in BCD format + 16 + 4 + read-write + + + YT + Year tens in BCD format + 20 + 4 + read-write + + + + + RTC_SSR + RTC_SSR + RTC subsecond register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous binary counter +SS[31:16]: Synchronous binary counter MSB values +When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): +SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter. +When BCD mode is selected (BIN=00): +SS[31:16] are forced by hardware to 0x0000. +SS[15:0]: Subsecond value/synchronous binary counter LSB values +When Binary mode is selected (BIN = 01 or 10 or 11): +SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter. +When BCD mode is selected (BIN=00): +SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: +Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) +SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. + 0 + 32 + read-only + + + + + RTC_ICSR + RTC_ICSR + RTC initialization control and status register + 0x0C + 0x20 + 0x00000007 + 0xFFFFFFFF + + + WUTWF + Wake-up timer write flag +This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. + 2 + 1 + read-only + + + B_0x0 + Wake-up timer configuration update not allowed except in initialization mode + 0x0 + + + B_0x1 + Wake-up timer configuration update allowed + 0x1 + + + + + SHPF + Shift operation pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-only + + + B_0x0 + No shift operation is pending + 0x0 + + + B_0x1 + A shift operation is pending + 0x1 + + + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). + 4 + 1 + read-only + + + B_0x0 + Calendar has not been initialized + 0x0 + + + B_0x1 + Calendar has been initialized + 0x1 + + + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. + 5 + 1 + read-write + + + B_0x0 + Calendar shadow registers not yet synchronized + 0x0 + + + B_0x1 + Calendar shadow registers synchronized + 0x1 + + + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. + 6 + 1 + read-only + + + B_0x0 + Calendar registers update is not allowed + 0x0 + + + B_0x1 + Calendar registers update is allowed + 0x1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + + B_0x0 + Free running mode + 0x0 + + + B_0x1 + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. Counters are stopped and start counting from the new value when INIT is reset. + 0x1 + + + + + BIN + Binary mode + 8 + 2 + read-write + + + B_0x0 + Free running BCD calendar mode (Binary mode disabled). + 0x0 + + + B_0x1 + Free running Binary mode (BCD mode disabled) + 0x1 + + + B_0x2 + Free running BCD calendar and Binary modes + 0x2 + + + B_0x3 + Free running BCD calendar and Binary modes + 0x3 + + + + + BCDU + BCD update (BIN = 10 or 11) +In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits. + 10 + 3 + read-write + + + B_0x0 + 1s calendar increment is generated each time SS[7:0] = 0 + 0x0 + + + B_0x1 + 1s calendar increment is generated each time SS[8:0] = 0 + 0x1 + + + B_0x2 + 1s calendar increment is generated each time SS[9:0] = 0 + 0x2 + + + B_0x3 + 1s calendar increment is generated each time SS[10:0] = 0 + 0x3 + + + B_0x4 + 1s calendar increment is generated each time SS[11:0] = 0 + 0x4 + + + B_0x5 + 1s calendar increment is generated each time SS[12:0] = 0 + 0x5 + + + B_0x6 + 1s calendar increment is generated each time SS[13:0] = 0 + 0x6 + + + B_0x7 + 1s calendar increment is generated each time SS[14:0] = 0 + 0x7 + + + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + RTC prescaler register + 0x10 + 0x20 + 0x007F00FF + 0xFFFFFFFF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC wake-up timer register + 0x14 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + WUT + Wake-up auto-reload value bits +When the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]1+11) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. +When WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs between WUT and (WUT + 2) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + WUTOCLR + Wake-up auto-reload output clear value +When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto-reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0]. +When WUTOCLR[15:0] = 0x0000, WUTF is set by hardware when the WUT down-counter +reaches 0 and is cleared by software. + 16 + 16 + read-write + + + + + RTC_CR + RTC_CR + RTC control register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUCKSEL + ck_wut wake-up clock selection +10x: ck_spre (usually 11Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. +11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 2<sup>16</sup> is added to the WUT counter value. + 0 + 3 + read-write + + + B_0x0 + RTC/16 clock is selected + 0x0 + + + B_0x1 + RTC/8 clock is selected + 0x1 + + + B_0x2 + RTC/4 clock is selected + 0x2 + + + B_0x3 + RTC/2 clock is selected + 0x3 + + + + + TSEDGE + Timestamp event active edge +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + B_0x0 + RTC_TS input rising edge generates a timestamp event + 0x0 + + + B_0x1 + RTC_TS input falling edge generates a timestamp event + 0x1 + + + + + REFCKON + RTC_REFIN reference clock detection enable (50 or 601Hz) +Note: BIN must be 0x00 and PREDIV_S must be 0x00FF. + 4 + 1 + read-write + + + B_0x0 + RTC_REFIN detection disabled + 0x0 + + + B_0x1 + RTC_REFIN detection enabled + 0x1 + + + + + BYPSHAD + Bypass the shadow registers +Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. + 5 + 1 + read-write + + + B_0x0 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. + 0x0 + + + B_0x1 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 0x1 + + + + + FMT + Hour format + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + SSRUIE + SSR underflow interrupt enable + 7 + 1 + read-write + + + B_0x0 + SSR underflow interrupt disabled + 0x0 + + + B_0x1 + SSR underflow interrupt enabled + 0x1 + + + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + B_0x0 + Alarm A disabled + 0x0 + + + B_0x1 + Alarm A enabled + 0x1 + + + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + B_0x0 + Alarm B disabled + 0x0 + + + B_0x1 + Alarm B enabled + 0x1 + + + + + WUTE + Wake-up timer enable +Note: When the wake-up timer is disabled, wait for WUTWF = 1 before enabling it again. + 10 + 1 + read-write + + + B_0x0 + Wake-up timer disabled + 0x0 + + + B_0x1 + Wake-up timer enabled + 0x1 + + + + + TSE + timestamp enable + 11 + 1 + read-write + + + B_0x0 + timestamp disable + 0x0 + + + B_0x1 + timestamp enable + 0x1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + B_0x0 + Alarm A interrupt disabled + 0x0 + + + B_0x1 + Alarm A interrupt enabled + 0x1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + B_0x0 + Alarm B interrupt disable + 0x0 + + + B_0x1 + Alarm B interrupt enable + 0x1 + + + + + WUTIE + Wake-up timer interrupt enable + 14 + 1 + read-write + + + B_0x0 + Wake-up timer interrupt disabled + 0x0 + + + B_0x1 + Wake-up timer interrupt enabled + 0x1 + + + + + TSIE + Timestamp interrupt enable + 15 + 1 + read-write + + + B_0x0 + Timestamp interrupt disable + 0x0 + + + B_0x1 + Timestamp interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. + 16 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Adds 1 hour to the current time. This can be used for summer time change + 0x1 + + + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. + 17 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Subtracts 1 hour to the current time. This can be used for winter time change. + 0x1 + + + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE = 1, this bit selects which signal is output on CALIB. +These frequencies are valid for RTCCLK at 32.7681kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section128.3.16: Calibration clock output. + 19 + 1 + read-write + + + B_0x0 + Calibration output is 5121Hz + 0x0 + + + B_0x1 + Calibration output is 11Hz + 0x1 + + + + + POL + Output polarity +This bit is used to configure the polarity of TAMPALRM output. + 20 + 1 + read-write + + + B_0x0 + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x0 + + + B_0x1 + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x1 + + + + + OSEL + Output selection +These bits are used to select the flag to be routed to TAMPALRM output. + 21 + 2 + read-write + + + B_0x0 + Output disabled + 0x0 + + + B_0x1 + Alarm A output enabled + 0x1 + + + B_0x2 + Alarm B output enabled + 0x2 + + + B_0x3 + Wake-up output enabled + 0x3 + + + + + COE + Calibration output enable +This bit enables the CALIB output + 23 + 1 + read-write + + + B_0x0 + Calibration output disabled + 0x0 + + + B_0x1 + Calibration output enabled + 0x1 + + + + + ITSE + timestamp on internal event enable + 24 + 1 + read-write + + + B_0x0 + internal event timestamp disabled + 0x0 + + + B_0x1 + internal event timestamp enabled + 0x1 + + + + + TAMPTS + Activate timestamp on tamper detection event +TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. +Note: TAMPTS must be cleared before entering RTC initialization mode. + 25 + 1 + read-write + + + B_0x0 + Tamper detection event does not cause a RTC timestamp to be saved + 0x0 + + + B_0x1 + Save RTC timestamp on tamper detection event + 0x1 + + + + + TAMPOE + Tamper detection output enable on TAMPALRM + 26 + 1 + read-write + + + B_0x0 + The tamper flag is not routed on TAMPALRM + 0x0 + + + B_0x1 + The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. + 0x1 + + + + + ALRAFCLR + Alarm A flag automatic clear + 27 + 1 + read-write + + + B_0x0 + Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm A event generates a trigger event. ALRAF is automatically cleared by hardware after 1 ck_apre cycle. + 0x1 + + + + + ALRBFCLR + Alarm B flag automatic clear + 28 + 1 + read-write + + + B_0x0 + Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm B event generates a trigger event. ALRBF is automatically cleared by hardware after 1 ck_apre cycle. + 0x1 + + + + + TAMPALRM_PU + TAMPALRM pull-up enable + 29 + 1 + read-write + + + B_0x0 + No pull-up is applied on TAMPALRM output + 0x0 + + + B_0x1 + A pull-up is applied on TAMPALRM output + 0x1 + + + + + TAMPALRM_TYPE + TAMPALRM output type + 30 + 1 + read-write + + + B_0x0 + TAMPALRM is push-pull output + 0x0 + + + B_0x1 + TAMPALRM is open-drain output + 0x1 + + + + + OUT2EN + RTC_OUT2 output enable + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00. +Refer to RTC register write protection for a description of how to unlock RTC register write protection. + 0 + 8 + write-only + + + + + RTC_CALR + RTC_CALR + RTC calibration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 2<sup>20</sup> RTCCLK pulses (321seconds if the input frequency is 327681Hz). This decreases the frequency of the calendar with a resolution of 0.95371ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section128.3.14: RTC smooth digital calibration on page1733. + 0 + 9 + read-write + + + LPCAL + RTC low-power mode + 12 + 1 + read-write + + + B_0x0 + Calibration window is 2<sup>20</sup> RTCCLK, which is a high-consumption mode. This mode must be set only when less than 32s calibration window is required. + 0x0 + + + B_0x1 + Calibration window is 2<sup>20</sup> ck_apre, which is the required configuration for ultra-low consumption mode. + 0x1 + + + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. +Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section128.3.14: RTC smooth digital calibration. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1, the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section128.3.14: RTC smooth digital calibration. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.51ppm. + 15 + 1 + read-write + + + B_0x0 + No RTCCLK pulses are added. + 0x0 + + + B_0x1 + One RTCCLK pulse is effectively inserted every 2<sup>11</sup> pulses (frequency increased by 488.51ppm). + 0x1 + + + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC shift control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / (PREDIV_S + 1) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: +Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). +In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0. +Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. + 0 + 15 + write-only + + + ADD1S + Add one second +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Add one second to the clock/calendar + 0x1 + + + + + + + RTC_TSTR + RTC_TSTR + RTC timestamp time register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-only + + + ST + Second tens in BCD format. + 4 + 3 + read-only + + + MNU + Minute units in BCD format. + 8 + 4 + read-only + + + MNT + Minute tens in BCD format. + 12 + 3 + read-only + + + HU + Hour units in BCD format. + 16 + 4 + read-only + + + HT + Hour tens in BCD format. + 20 + 2 + read-only + + + PM + AM/PM notation + 22 + 1 + read-only + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_TSDR + RTC_TSDR + RTC timestamp date register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-only + + + DT + Date tens in BCD format + 4 + 2 + read-only + + + MU + Month units in BCD format + 8 + 4 + read-only + + + MT + Month tens in BCD format + 12 + 1 + read-only + + + WDU + Week day units + 13 + 3 + read-only + + + + + RTC_TSSSR + RTC_TSSSR + RTC timestamp subsecond register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subsecond value/synchronous binary counter values +SS[31:0] is the value of the synchronous prescaler counter when the timestamp event occurred. + 0 + 32 + read-only + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC alarm A register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm A set if the seconds match + 0x0 + + + B_0x1 + Seconds dont care in alarm A comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm A set if the minutes match + 0x0 + + + B_0x1 + Minutes dont care in alarm A comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm A hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm A set if the hours match + 0x0 + + + B_0x1 + Hours dont care in alarm A comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is dont care. + 0x1 + + + + + MSK4 + Alarm A date mask + 31 + 1 + read-write + + + B_0x0 + Alarm A set if the date/day match + 0x0 + + + B_0x1 + Date/day dont care in alarm A comparison + 0x1 + + + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC alarm A subsecond register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. +This field is the mirror of SS[14:0] in the RTC_ALRABINR, and so can also be read or written through RTC_ALRABINR. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +From 32 to 63: All 32 SS bits are compared and must match to activate alarm. +Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[31:1] are dont care in Alarm A comparison. Only SS[0] is compared. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) +Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRABINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRABINR.SS[31:0]. + 0x1 + + + + + + + RTC_ALRMBR + RTC_ALRMBR + RTC alarm B register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MSK1 + Alarm B seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm B set if the seconds match + 0x0 + + + B_0x1 + Seconds dont care in alarm B comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm B minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm B set if the minutes match + 0x0 + + + B_0x1 + Minutes dont care in alarm B comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm B hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm B set if the hours match + 0x0 + + + B_0x1 + Hours dont care in alarm B comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is dont care. + 0x1 + + + + + MSK4 + Alarm B date mask + 31 + 1 + read-write + + + B_0x0 + Alarm B set if the date and day match + 0x0 + + + B_0x1 + Date and day dont care in alarm B comparison + 0x1 + + + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + RTC alarm B subsecond register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. +This field is the mirror of SS[14:0] in the RTC_ALRBBINR, and so can also be read or written through RTC_ALRBBINR. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +From 32 to 63: All 32 SS bits are compared and must match to activate alarm. +Note: In BCD mode (BIN=00)The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[31:1] are dont care in Alarm B comparison. Only SS[0] is compared. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) +Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRBBINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRBBINR.SS[31:0]. + 0x1 + + + + + + + RTC_SR + RTC_SR + RTC status register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). + 0 + 1 + read-only + + + ALRBF + Alarm B flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR). + 1 + 1 + read-only + + + WUTF + Wake-up timer flag +This flag is set by hardware when the wake-up auto-reload counter reaches 0. +If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wake-up auto-reload counter reaches WUTOCLR value. +If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 2 + 1 + read-only + + + TSF + Timestamp flag +This flag is set by hardware when a timestamp event occurs. +If ITSF flag is set, TSF must be cleared together with ITSF. +Note: TSF is not set if TAMPTS1=11 and the tamper flag is read during the 3 ck_apre cycles following tamper event. Refer to Timestamp on tamper event for more details. + 3 + 1 + read-only + + + TSOVF + Timestamp overflow flag +This flag is set by hardware when a timestamp event occurs while TSF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + ITSF + Internal timestamp flag +This flag is set by hardware when a timestamp on the internal event occurs. + 5 + 1 + read-only + + + SSRUF + SSR underflow flag +This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1. + 6 + 1 + read-only + + + + + RTC_MISR + RTC_MISR + RTC masked interrupt status register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A masked flag +This flag is set by hardware when the alarm A interrupt occurs. + 0 + 1 + read-only + + + ALRBMF + Alarm B masked flag +This flag is set by hardware when the alarm B interrupt occurs. + 1 + 1 + read-only + + + WUTMF + Wake-up timer masked flag +This flag is set by hardware when the wake-up timer interrupt occurs. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 2 + 1 + read-only + + + TSMF + Timestamp masked flag +This flag is set by hardware when a timestamp interrupt occurs. +If ITSF flag is set, TSF must be cleared together with ITSF. + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow masked flag +This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + ITSMF + Internal timestamp masked flag +This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. + 5 + 1 + read-only + + + SSRUMF + SSR underflow masked flag +This flag is set by hardware when the SSR underflow interrupt occurs. + 6 + 1 + read-only + + + + + RTC_SCR + RTC_SCR + RTC status clear register + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALRAF + Clear alarm A flag +Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. + 0 + 1 + write-only + + + CALRBF + Clear alarm B flag +Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. + 1 + 1 + write-only + + + CWUTF + Clear wake-up timer flag +Writing 1 in this bit clears the WUTF bit in the RTC_SR register. + 2 + 1 + write-only + + + CTSF + Clear timestamp flag +Writing 1 in this bit clears the TSF bit in the RTC_SR register. +If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. + 3 + 1 + write-only + + + CTSOVF + Clear timestamp overflow flag +Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + write-only + + + CITSF + Clear internal timestamp flag +Writing 1 in this bit clears the ITSF bit in the RTC_SR register. + 5 + 1 + write-only + + + CSSRUF + Clear SSR underflow flag +Writing 1 in this bit clears the SSRUF in the RTC_SR register. + 6 + 1 + write-only + + + + + RTC_ALRABINR + RTC_ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode +This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. +SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR. + 0 + 32 + read-write + + + + + RTC_ALRBBINR + RTC_ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode +This value is compared with the contents of the synchronous counter to determine if Alarm Bis to be activated. Only bits 0 up MASKSS-1 are compared. +SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMBSSRR, and so can also be read or written through RTC_ALRMBSSR. + 0 + 32 + read-write + + + + + + + SPI1 + SPI address block description + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 25 + + + + SPI_CR1 + SPI_CR1 + SPI control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page1954. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPI_DR register. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPI_CR2 + SPI_CR2 + SPI control register 2 + 0x04 + 16 + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). +Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). +Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPI_SR + SPI_SR + SPI status register + 0x08 + 16 + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPI_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPI_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section1: Mode fault (MODF) on page1964 for the software sequence. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section133.4.10: SPI status flags and Procedure for disabling the SPI on page1954. + 7 + 1 + read-only + + + B_0x0 + SPI not busy + 0x0 + + + B_0x1 + SPI is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode. Refer to Section133.4.11: SPI error flags. +This flag is set by hardware and reset when SPI_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPI_DR + SPI_DR + SPI data register + 0x0C + 16 + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section133.4.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_CRCPR + SPI_CRCPR + SPI CRC polynomial register + 0x10 + 16 + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_RXCRCR + SPI_RXCRCR + SPI Rx CRC register + 0x14 + 16 + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_TXCRCR + SPI_TXCRCR + SPI Tx CRC register + 0x18 + 16 + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + SYSCFG + SYSCFG register block + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + SYSCFG configuration register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + MEM_MODE + Memory mapping selection bits +These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. +X0: Main flash memory mapped at 0x000010000 + 0 + 2 + read-write + + + B_0x1 + System flash memory mapped at 0x000010000 + 0x1 + + + B_0x3 + Embedded SRAM mapped at 0x000010000 + 0x3 + + + + + PA11_RMP + PA11 pin remapping +This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. + 3 + 1 + read-write + + + B_0x0 + No remap (PA11) + 0x0 + + + B_0x1 + Remap (PA9) + 0x1 + + + + + PA12_RMP + PA12 pin remapping +This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. + 4 + 1 + read-write + + + B_0x0 + No remap (PA12) + 0x0 + + + B_0x1 + Remap (PA10) + 0x1 + + + + + IR_POL + IR output polarity selection + 5 + 1 + read-write + + + B_0x0 + Output of IRTIM (IR_OUT) is not inverted + 0x0 + + + B_0x1 + Output of IRTIM (IR_OUT) is inverted + 0x1 + + + + + IR_MOD + IR Modulation Envelope signal selection +This bitfield selects the signal for IR modulation envelope: + 6 + 2 + read-write + + + B_0x0 + TIM16 + 0x0 + + + B_0x1 + USART1 + 0x1 + + + B_0x2 + USART2 + 0x2 + + + + + BOOSTEN + I/O analog switch voltage booster enable +This bit selects the way of supplying I/O analog switches: +When using the analog inputs , setting to 0 is recommended for high V<sub>DD</sub>, setting to 1 for low V<sub>DD</sub> (less than 2.4 V). + 8 + 1 + read-write + + + B_0x0 + V<sub>DD</sub> + 0x0 + + + B_0x1 + Dedicated voltage booster (supplied by V<sub>DD</sub>) + 0x1 + + + + + I2C_PB6_FMP + Fast Mode Plus (FM+) enable for PB6 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB6 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB7_FMP + Fast Mode Plus (FM+) enable for PB7 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB7 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB8_FMP + Fast Mode Plus (FM+) enable for PB8 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB8 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB9_FMP + Fast Mode Plus (FM+) enable for PB9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB9 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA9_FMP + Fast Mode Plus (FM+) enable for PA9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA9 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA10_FMP + Fast Mode Plus (FM+) enable for PA10 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA10 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3_FMP + Fast Mode Plus (FM+) enable for I2C3 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + SYSCFG configuration register 2 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCL + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP bit enable bit +This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input. + 0 + 1 + read-write + + + B_0x0 + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP output disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP output connected to TIM1/15/16 Break input + 0x1 + + + + + SPL + SRAM1 parity lock bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input. + 1 + 1 + read-write + + + B_0x0 + SRAM1 parity error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + SRAM1 parity error connected to TIM1/15/16 Break input + 0x1 + + + + + PVDL + PVD lock enable bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. + 2 + 1 + read-write + + + B_0x0 + PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be programmed by the application. + 0x0 + + + B_0x1 + PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read only. + 0x1 + + + + + ECCL + ECC error lock bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input. + 3 + 1 + read-write + + + B_0x0 + ECC error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + ECC error connected to TIM1/15/16 Break input + 0x1 + + + + + BKPL + Backup SRAM2 parity lock +This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input. + 4 + 1 + read-write + + + B_0x0 + SRAM2 parity error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + SRAM2 parity error connected to TIM1/15/16 Break input + 0x1 + + + + + BKPF + Backup SRAM2 parity error flag +This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1. + 7 + 1 + read-write + + + B_0x0 + No SRAM2 parity error detected + 0x0 + + + B_0x1 + SRAM2 parity error detected + 0x1 + + + + + SPF + SRAM1 parity error flag +This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1. + 8 + 1 + read-write + + + B_0x0 + No SRAM1 parity error detected + 0x0 + + + B_0x1 + SRAM1 parity error detected + 0x1 + + + + + + + SYSCFG_SCSR + SYSCFG_SCSR + SYSCFG SRAM2 control and status register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRAM2ER + SRAM2 erase +Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. +Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. + 0 + 1 + read-write + + + SRAM2BSY + SRAM2 busy by erase operation + 1 + 1 + read-only + + + B_0x0 + No SRAM2 erase operation is ongoing + 0x0 + + + B_0x1 + SRAM2 erase operation is ongoing + 0x1 + + + + + + + SYSCFG_SKR + SYSCFG_SKR + SYSCFG SRAM2 key register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + SRAM2 write protection key for software erase +The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: +Write 0xCA into KEY[7:0] +Write 0x53 into KEY[7:0] +Writing a wrong key reactivates the write protection. + 0 + 8 + write-only + + + + + SYSCFG_TSCCR + SYSCFG_TSCCR + SYSCFG TSC comparator register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G2_IO1 + Comparator mode for group 2 on I/O 1 + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PB4 to COMP2 + 0x1 + + + + + G2_IO3 + Comparator mode for group 2 on I/O 3 + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PB6 to COMP2 + 0x1 + + + + + G4_IO3 + Comparator mode for group 4 on I/O 3 + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PC6 to COMP2 + 0x1 + + + + + G6_IO1 + Comparator mode for group 6 on I/O 1 + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PD10 to COMP1 + 0x1 + + + + + G7_IO1 + Comparator mode for group 7 on I/O 1 + 4 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PA9 to COMP1 + 0x1 + + + + + TSC_IOCTRL + I/O control in comparator mode +The I/O control in comparator mode can be overwritten by hardware. + 5 + 1 + read-write + + + B_0x0 + I/O configured through the corresponding control register + 0x0 + + + B_0x1 + I/O configured as analog when TSC AF is activated + 0x1 + + + + + + + SYSCFG_ITLINE0 + SYSCFG_ITLINE0 + SYSCFG interrupt line 0 status register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WWDG + Window watchdog interrupt pending flag + 0 + 1 + read-only + + + + + SYSCFG_ITLINE1 + SYSCFG_ITLINE1 + SYSCFG interrupt line 1 status register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDOUT + PVD supply monitoring interrupt request pending (EXTI line 16). + 0 + 1 + read-only + + + PVMOUT1 + V<sub>DDUSB</sub> supply monitoring interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + PVMOUT3 + ADC supply monitoring interrupt request pending (EXTI line 20) + 2 + 1 + read-only + + + PVMOUT4 + DAC supply monitoring interrupt request pending (EXTI line 21) + 3 + 1 + read-only + + + + + SYSCFG_ITLINE2 + SYSCFG_ITLINE2 + SYSCFG interrupt line 2 status register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP + Tamper interrupt request pending (EXTI line 21) + 0 + 1 + read-only + + + RTC + RTC interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE3 + SYSCFG_ITLINE3 + SYSCFG interrupt line 3 status register + 0x8C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FLASH_ITF + Flash interface interrupt request pending + 0 + 1 + read-only + + + FLASH_ECC + Flash interface ECC interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE4 + SYSCFG_ITLINE4 + SYSCFG interrupt line 4 status register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RCC + Reset and clock control interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE5 + SYSCFG_ITLINE5 + SYSCFG interrupt line 5 status register + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI line 0 interrupt request pending + 0 + 1 + read-only + + + EXTI1 + EXTI line 1 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE6 + SYSCFG_ITLINE6 + SYSCFG interrupt line 6 status register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI2 + EXTI line 2 interrupt request pending + 0 + 1 + read-only + + + EXTI3 + EXTI line 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE7 + SYSCFG_ITLINE7 + SYSCFG interrupt line 7 status register + 0x9C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI line 4 interrupt request pending + 0 + 1 + read-only + + + EXTI5 + EXTI line 5 interrupt request pending + 1 + 1 + read-only + + + EXTI6 + EXTI line 6 interrupt request pending + 2 + 1 + read-only + + + EXTI7 + EXTI line 7 interrupt request pending + 3 + 1 + read-only + + + EXTI8 + EXTI line 8 interrupt request pending + 4 + 1 + read-only + + + EXTI9 + EXTI line 9 interrupt request pending + 5 + 1 + read-only + + + EXTI10 + EXTI line 10 interrupt request pending + 6 + 1 + read-only + + + EXTI11 + EXTI line 11 interrupt request pending + 7 + 1 + read-only + + + EXTI12 + EXTI line 12 interrupt request pending + 8 + 1 + read-only + + + EXTI13 + EXTI line 13 interrupt request pending + 9 + 1 + read-only + + + EXTI14 + EXTI line 14 interrupt request pending + 10 + 1 + read-only + + + EXTI15 + EXTI line 15 interrupt request pending + 11 + 1 + read-only + + + + + SYSCFG_ITLINE8 + SYSCFG_ITLINE8 + SYSCFG interrupt line 8 status register + 0xA0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USB + USB interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE9 + SYSCFG_ITLINE9 + SYSCFG interrupt line 9 status register + 0xA4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH1 + DMA1 channel 1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE10 + SYSCFG_ITLINE10 + SYSCFG interrupt line 10 status register + 0xA8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH2 + DMA1 channel 2 interrupt request pending + 0 + 1 + read-only + + + DMA1_CH3 + DMA1 channel 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE11 + SYSCFG_ITLINE11 + SYSCFG interrupt line 11 status register + 0xAC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAMUX + DMAMUX interrupt request pending + 0 + 1 + read-only + + + DMA1_CH4 + DMA1 channel 4 interrupt request pending + 1 + 1 + read-only + + + DMA1_CH5 + DMA1 channel 5 interrupt request pending + 2 + 1 + read-only + + + DMA1_CH6 + DMA1 channel 6 interrupt request pending + 3 + 1 + read-only + + + DMA1_CH7 + DMA1 channel 7 interrupt request pending + 4 + 1 + read-only + + + DMA2_CH1 + DMA2 channel 1 interrupt request pending + 5 + 1 + read-only + + + DMA2_CH2 + DMA2 channel 2 interrupt request pending + 6 + 1 + read-only + + + DMA2_CH3 + DMA2 channel 3 interrupt request pending + 7 + 1 + read-only + + + DMA2_CH4 + DMA2 channel 4 interrupt request pending + 8 + 1 + read-only + + + DMA2_CH5 + DMA2 channel 5 interrupt request pending + 9 + 1 + read-only + + + + + SYSCFG_ITLINE12 + SYSCFG_ITLINE12 + SYSCFG interrupt line 12 status register + 0xB0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC interrupt request pending + 0 + 1 + read-only + + + COMP1 + Comparator 1 interrupt request pending (EXTI line 17) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE13 + SYSCFG_ITLINE13 + SYSCFG interrupt line 13 status register + 0xB4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1_CCU + Timer 1 commutation interrupt request pending + 0 + 1 + read-only + + + TIM1_TRG + Timer 1 trigger interrupt request pending + 1 + 1 + read-only + + + TIM1_UPD + Timer 1 update interrupt request pending + 2 + 1 + read-only + + + TIM1_BRK + Timer 1 break interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE14 + SYSCFG_ITLINE14 + SYSCFG interrupt line 14 status register + 0xB8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1_CC1 + Timer 1 capture compare 1 interrupt request pending + 0 + 1 + read-only + + + TIM1_CC2 + Timer 1 capture compare 2 interrupt request pending + 1 + 1 + read-only + + + TIM1_CC3 + Timer 1 capture compare 3 interrupt request pending + 2 + 1 + read-only + + + TIM1_CC4 + Timer 1 capture compare 4 interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE15 + SYSCFG_ITLINE15 + SYSCFG interrupt line 15 status register + 0xBC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2 + Timer 2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE16 + SYSCFG_ITLINE16 + SYSCFG interrupt line 16 status register + 0xC0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM3 + Timer 3 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE17 + SYSCFG_ITLINE17 + SYSCFG interrupt line 17 status register + 0xC4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM6 + Timer 6 interrupt request pending + 0 + 1 + read-only + + + DAC + DAC underrun interrupt request pending + 1 + 1 + read-only + + + LPTIM1 + Low-power timer 1 interrupt request pending (EXTI line 29) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE18 + SYSCFG_ITLINE18 + SYSCFG interrupt line 18 status register + 0xC8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM7 + Timer 7 interrupt request pending + 0 + 1 + read-only + + + LPTIM2 + Low-power timer 2 interrupt request pending (EXTI line 30) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE19 + SYSCFG_ITLINE19 + SYSCFG interrupt line 19 status register + 0xCC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM15 + Timer 15 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE20 + SYSCFG_ITLINE20 + SYSCFG interrupt line 20 status register + 0xD0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM16 + Timer 16 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE21 + SYSCFG_ITLINE21 + SYSCFG interrupt line 21 status register + 0xD4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSC_MCE + TSC max count error interrupt request pending + 0 + 1 + read-only + + + TSC_EOA + TSC end of acquisition interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE22 + SYSCFG_ITLINE22 + SYSCFG interrupt line 22 status register + 0xD8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCD + LCD interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE23 + SYSCFG_ITLINE23 + SYSCFG interrupt line 23 status register + 0xDC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C1 + I2C1 interrupt request pending (EXTI line 33) + 0 + 1 + read-only + + + + + SYSCFG_ITLINE24 + SYSCFG_ITLINE24 + SYSCFG interrupt line 24 status register + 0xE0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C2 + I2C2 interrupt request pending + 0 + 1 + read-only + + + I2C3 + I2C3 interrupt request pending (EXTI line 23) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE25 + SYSCFG_ITLINE25 + SYSCFG interrupt line 25 status register + 0xE4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI1 + SPI1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE26 + SYSCFG_ITLINE26 + SYSCFG interrupt line 26 status register + 0xE8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI2 + SPI2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE27 + SYSCFG_ITLINE27 + SYSCFG interrupt line 27 status register + 0xEC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1 + USART1 interrupt request pending, combined with EXTI line 25 + 0 + 1 + read-only + + + + + SYSCFG_ITLINE28 + SYSCFG_ITLINE28 + SYSCFG interrupt line 28 status register + 0xF0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART2 + USART2 interrupt request pending (EXTI line 35) + 0 + 1 + read-only + + + LPUART2 + LPUART2 interrupt request pending (EXTI line 31) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE29 + SYSCFG_ITLINE29 + SYSCFG interrupt line 29 status register + 0xF4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART3 + USART3 interrupt request pending + 0 + 1 + read-only + + + LPUART1 + LPUART1 interrupt request pending (EXTI line 30) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE30 + SYSCFG_ITLINE30 + SYSCFG interrupt line 30 status register + 0xF8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART4 + USART4 interrupt request pending + 0 + 1 + read-only + + + LPUART3 + LPUART3 interrupt request pending (EXTI line 32) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE31 + SYSCFG_ITLINE31 + SYSCFG interrupt line 31 status register + 0xFC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNG + RNG interrupt request pending + 0 + 1 + read-only + + + + + + + TAMP + TAMP register block + TAMP + 0x4000B000 + + 0x0 + 0x400 + registers + + + + TAMP_CR1 + TAMP_CR1 + TAMP control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1E + Tamper detection on TAMP_IN1 enable + 0 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN1 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN1 is enabled. + 0x1 + + + + + TAMP2E + Tamper detection on TAMP_IN2 enable<sup>(1)</sup> + 1 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN2 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN2 is enabled. + 0x1 + + + + + TAMP3E + Tamper detection on TAMP_IN3 enable<sup>(1)</sup> + 2 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN3 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN3 is enabled. + 0x1 + + + + + TAMP4E + Tamper detection on TAMP_IN4 enable<sup>(1)</sup> + 3 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN4 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN4 is enabled. + 0x1 + + + + + TAMP5E + Tamper detection on TAMP_IN5 enable<sup>(1)</sup> + 4 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN5 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN5 is enabled. + 0x1 + + + + + ITAMP3E + Internal tamper 3 enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 disabled. + 0x0 + + + B_0x1 + Internal tamper 3 enabled. + 0x1 + + + + + ITAMP4E + Internal tamper 4 enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 disabled. + 0x0 + + + B_0x1 + Internal tamper 4 enabled. + 0x1 + + + + + ITAMP5E + Internal tamper 5 enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 disabled. + 0x0 + + + B_0x1 + Internal tamper 5 enabled. + 0x1 + + + + + ITAMP6E + Internal tamper 6 enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 disabled. + 0x0 + + + B_0x1 + Internal tamper 6 enabled. + 0x1 + + + + + + + TAMP_CR2 + TAMP_CR2 + TAMP control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1POM + Tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Tamper 1 event detection is in potential mode. + 0x1 + + + + + TAMP2POM + Tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 2 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP3POM + Tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 3 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP4POM + Tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 4 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP5POM + Tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 5 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP1MSK + Tamper 1 mask +The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + 16 + 1 + read-write + + + B_0x0 + Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + TAMP2MSK + Tamper 2 mask +The tamper 2 interrupt must not be enabled when TAMP2MSK is set. + 17 + 1 + read-write + + + B_0x0 + Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + TAMP3MSK + Tamper 3 mask +The tamper 3 interrupt must not be enabled when TAMP3MSK is set. + 18 + 1 + read-write + + + B_0x0 + Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + BKBLOCK + Backup registers and device secrets<sup>(1)</sup> access blocked + 22 + 1 + read-write + + + B_0x0 + backup registers and device secrets<sup>(1)</sup> can be accessed if no tamper flag is set + 0x0 + + + B_0x1 + backup registers and device secrets<sup>(1)</sup> cannot be accessed + 0x1 + + + + + BKERASE + Backup registers and device secrets<sup>(1)</sup> erase +Writing 1 to this bit reset the backup registers and device secrets<sup>(1)</sup>. Writing 0 has no effect. This bit is always read as 0. + 23 + 1 + write-only + + + TAMP1TRG + Active level for tamper 1 input +If TAMPFLT1=100 tamper 1 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 1 input falling edge triggers a tamper detection event. + 24 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 1 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 1 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP2TRG + Active level for tamper 2 input +If TAMPFLT = 00 tamper 2 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 2 input falling edge triggers a tamper detection event. + 25 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 2 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 2 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP3TRG + Active level for tamper 3 input +If TAMPFLT1=100 tamper 3 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 3 input falling edge triggers a tamper detection event. + 26 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 3 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 3 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP4TRG + Active level for tamper 4 input (active mode disabled) +If TAMPFLT1=100 tamper 4 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 4 input falling edge triggers a tamper detection event. + 27 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 4 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 4 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP5TRG + Active level for tamper 5 input (active mode disabled) +If TAMPFLT1=100 tamper 5 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 5 input falling edge triggers a tamper detection event. + 28 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 5 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 5 input staying low triggers a tamper detection event + 0x1 + + + + + + + TAMP_CR3 + TAMP_CR3 + TAMP control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ITAMP3POM + Internal tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Internal tamper 3 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 3 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP4POM + Internal tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Internal tamper 4 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 4 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP5POM + Internal tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Internal tamper 5 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 5 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP6POM + Internal tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Internal tamper 6 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Internal tamper 6 event detection is in potential mode. + 0x1 + + + + + + + TAMP_FLTCR + TAMP_FLTCR + TAMP filter control register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMPFREQ + Tamper sampling frequency +Determines the frequency at which each of the TAMP_INx inputs are sampled. + 0 + 3 + read-write + + + B_0x0 + RTCCLK / 32768 (11Hz when RTCCLK = 327681Hz) + 0x0 + + + B_0x1 + RTCCLK / 16384 (21Hz when RTCCLK = 327681Hz) + 0x1 + + + B_0x2 + RTCCLK / 8192 (41Hz when RTCCLK = 327681Hz) + 0x2 + + + B_0x3 + RTCCLK / 4096 (81Hz when RTCCLK = 327681Hz) + 0x3 + + + B_0x4 + RTCCLK / 2048 (161Hz when RTCCLK = 327681Hz) + 0x4 + + + B_0x5 + RTCCLK / 1024 (321Hz when RTCCLK = 327681Hz) + 0x5 + + + B_0x6 + RTCCLK / 512 (641Hz when RTCCLK = 327681Hz) + 0x6 + + + B_0x7 + RTCCLK / 256 (1281Hz when RTCCLK = 327681Hz) + 0x7 + + + + + TAMPFLT + TAMP_INx filter count +These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. + 3 + 2 + read-write + + + B_0x0 + Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). + 0x0 + + + B_0x1 + Tamper event is activated after 2 consecutive samples at the active level. + 0x1 + + + B_0x2 + Tamper event is activated after 4 consecutive samples at the active level. + 0x2 + + + B_0x3 + Tamper event is activated after 8 consecutive samples at the active level. + 0x3 + + + + + TAMPPRCH + TAMP_INx precharge duration +These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. + 5 + 2 + read-write + + + B_0x0 + 1 RTCCLK cycle + 0x0 + + + B_0x1 + 2 RTCCLK cycles + 0x1 + + + B_0x2 + 4 RTCCLK cycles + 0x2 + + + B_0x3 + 8 RTCCLK cycles + 0x3 + + + + + TAMPPUDIS + TAMP_INx pull-up disable +This bit determines if each of the TAMPx pins are precharged before each sample. + 7 + 1 + read-write + + + B_0x0 + Precharge TAMP_INx pins before sampling (enable internal pull-up) + 0x0 + + + B_0x1 + Disable precharge of TAMP_INx pins. + 0x1 + + + + + + + TAMP_IER + TAMP_IER + TAMP interrupt enable register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1IE + Tamper 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 1 interrupt enabled. + 0x1 + + + + + TAMP2IE + Tamper 2 interrupt enable + 1 + 1 + read-write + + + B_0x0 + Tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 2 interrupt enabled. + 0x1 + + + + + TAMP3IE + Tamper 3 interrupt enable + 2 + 1 + read-write + + + B_0x0 + Tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 3 interrupt enabled.. + 0x1 + + + + + TAMP4IE + Tamper 4 interrupt enable + 3 + 1 + read-write + + + B_0x0 + Tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 4 interrupt enabled. + 0x1 + + + + + TAMP5IE + Tamper 5 interrupt enable + 4 + 1 + read-write + + + B_0x0 + Tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP3IE + Internal tamper 3 interrupt enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 3 interrupt enabled. + 0x1 + + + + + ITAMP4IE + Internal tamper 4 interrupt enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 4 interrupt enabled. + 0x1 + + + + + ITAMP5IE + Internal tamper 5 interrupt enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP6IE + Internal tamper 6 interrupt enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 6 interrupt enabled. + 0x1 + + + + + + + TAMP_SR + TAMP_SR + TAMP status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1F + TAMP1 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. + 0 + 1 + read-only + + + TAMP2F + TAMP2 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. + 1 + 1 + read-only + + + TAMP3F + TAMP3 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. + 2 + 1 + read-only + + + TAMP4F + TAMP4 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP4 input. + 3 + 1 + read-only + + + TAMP5F + TAMP5 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP5 input. + 4 + 1 + read-only + + + ITAMP3F + Internal tamper 3 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. + 18 + 1 + read-only + + + ITAMP4F + Internal tamper 4 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. + 19 + 1 + read-only + + + ITAMP5F + Internal tamper 5 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. + 20 + 1 + read-only + + + ITAMP6F + Internal tamper 6 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. + 21 + 1 + read-only + + + + + TAMP_MISR + TAMP_MISR + TAMP masked interrupt status register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 interrupt masked flag +This flag is set by hardware when the tamper 1 interrupt is raised. + 0 + 1 + read-only + + + TAMP2MF + TAMP2 interrupt masked flag +This flag is set by hardware when the tamper 2 interrupt is raised. + 1 + 1 + read-only + + + TAMP3MF + TAMP3 interrupt masked flag +This flag is set by hardware when the tamper 3 interrupt is raised. + 2 + 1 + read-only + + + TAMP4MF + TAMP4 interrupt masked flag +This flag is set by hardware when the tamper 4 interrupt is raised. + 3 + 1 + read-only + + + TAMP5MF + TAMP5 interrupt masked flag +This flag is set by hardware when the tamper 5 interrupt is raised. + 4 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 interrupt masked flag +This flag is set by hardware when the internal tamper 3 interrupt is raised. + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 interrupt masked flag +This flag is set by hardware when the internal tamper 4 interrupt is raised. + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 interrupt masked flag +This flag is set by hardware when the internal tamper 5 interrupt is raised. + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 interrupt masked flag +This flag is set by hardware when the internal tamper 6 interrupt is raised. + 21 + 1 + read-only + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CTAMP1F + Clear TAMP1 detection flag +Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. + 0 + 1 + write-only + + + CTAMP2F + Clear TAMP2 detection flag +Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. + 1 + 1 + write-only + + + CTAMP3F + Clear TAMP3 detection flag +Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. + 2 + 1 + write-only + + + CTAMP4F + Clear TAMP4 detection flag +Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register. + 3 + 1 + write-only + + + CTAMP5F + Clear TAMP5 detection flag +Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register. + 4 + 1 + write-only + + + CITAMP3F + Clear ITAMP3 detection flag +Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. + 18 + 1 + write-only + + + CITAMP4F + Clear ITAMP4 detection flag +Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. + 19 + 1 + write-only + + + CITAMP5F + Clear ITAMP5 detection flag +Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. + 20 + 1 + write-only + + + CITAMP6F + Clear ITAMP6 detection flag +Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. + 21 + 1 + write-only + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + + + TIM1 + TIM1 address block description + TIM + 0x40012C00 + + 0x0 + 0x6C + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 break, update, trigger and commutation interrupts + 13 + + + TIM1_CC + TIM1 Capture Compare interrupt + 14 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (ETR, TIx): +Note: t<sub>DTS</sub> = 1/f<sub>DTS</sub>, t<sub>CK_INT</sub> = 1/f<sub>CK_INT</sub>. + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub>=t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub>=2*t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub>=4*t<sub>CK_INT</sub> + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output Idle state 2 (OC2 output) +Refer to OIS1 bit + 10 + 1 + read-write + + + OIS2N + Output Idle state 2 (OC2N output) +Refer to OIS1N bit + 11 + 1 + read-write + + + OIS3 + Output Idle state 3 (OC3 output) +Refer to OIS1 bit + 12 + 1 + read-write + + + OIS3N + Output Idle state 3 (OC3N output) +Refer to OIS1N bit + 13 + 1 + read-write + + + OIS4 + Output Idle state 4 (OC4 output) +Refer to OIS1 bit + 14 + 1 + read-write + + + OIS5 + Output Idle state 5 (OC5 output) +Refer to OIS1 bit + 16 + 1 + read-write + + + OIS6 + Output Idle state 6 (OC6 output) +Refer to OIS1 bit + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 +These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO2) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO2) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO2) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO2) + 0x7 + + + B_0x8 + Compare - OC5REFC signal is used as trigger output (TRGO2) + 0x8 + + + B_0x9 + Compare - OC6REFC signal is used as trigger output (TRGO2) + 0x9 + + + B_0xA + Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 + 0xA + + + B_0xB + Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 + 0xB + + + B_0xC + Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xC + + + B_0xD + Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xD + + + B_0xE + Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xE + + + B_0xF + Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xF + + + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Codes above 1000: Reserved. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection +This bit is used to select the OCREF clear source. + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[0]: Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See Table1118: TIM1 internal trigger connection on page1561 for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of f<sub>CK_INT</sub> frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to Section122.4.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag +This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + B2IF + Break 2 interrupt flag +This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag +Refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +Refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +Refer to CC1OF description + 12 + 1 + read-write + + + SBIF + System Break interrupt flag +This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. +This flag must be reset to re-start PWM operation. + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag +Refer to CC1IF description (Note: Channel 5 can only be configured as output) + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag +Refer to CC1IF description (Note: Channel 6 can only be configured as output) + 17 + 1 + read-write + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/Compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/Compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware +Note: This bit acts only on channels having a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. + 0x1 + + + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + B2G + Break 2 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. + 0x1 + + + + + + + TIM1_CCMR1_INPUT + TIM1_CCMR1_INPUT + TIM1 capture/compare mode register 1 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC2F + Input capture 2 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR1_OUTPUT + TIM1_CCMR1_OUTPUT + TIM1 capture/compare mode register 1 + TIM1_CCMR1_INPUT + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ocref_clr_int signal + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input) + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output Compare 2 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode +Refer to OC1M[3:0] description. + 12 + 3 + read-write + + + OC2CE + Output Compare 2 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2_INPUT + TIM1_CCMR2_INPUT + TIM1 capture/compare mode register 2 + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +Refer to IC1PSC[1:0] description. + 2 + 2 + read-write + + + IC3F + Input capture 3 filter +Refer to IC1F[3:0] description. + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC4F + Input capture 4 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR2_OUTPUT + TIM1_CCMR2_OUTPUT + TIM1 capture/compare mode register 1 + TIM1_CCMR2_INPUT + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode +Refer to OC1M[3:0] description. + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode +Refer to OC3M[3:0] description. + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table1119 for details. +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (channel configured as output). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/Compare 2 complementary output enable +Refer to CC1NE description + 6 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output polarity +Refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/Compare 3 complementary output enable +Refer to CC1NE description + 10 + 1 + read-write + + + CC3NP + Capture/Compare 3 complementary output polarity +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable +Refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output polarity +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 complementary output polarity +Refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/Compare 5 output enable +Refer to CC1E description + 16 + 1 + read-write + + + CC5P + Capture/Compare 5 output polarity +Refer to CC1P description + 17 + 1 + read-write + + + CC6E + Capture/Compare 6 output enable +Refer to CC1E description + 20 + 1 + read-write + + + CC6P + Capture/Compare 6 output polarity +Refer to CC1P description + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section122.3.1: Time-base unit on page1497 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x30 + 16 + 0x0000 + 0xFFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to: +the number of PWM periods in edge-aligned mode +the number of half PWM period in center-aligned mode. + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x34 + 16 + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x38 + 16 + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. +If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x3C + 16 + 0x0000 + 0xFFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x40 + 16 + 0x0000 + 0xFFFF + + + CCR4 + Capture/Compare value +If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +This bit enables the complete break protection (including all sources connected to bk_acth and BRK sources, as per Figure1152: Break and Break2 circuitry overview). +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. OC and OCN outputs are disabled + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter +This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 20 + 4 + read-write + + + B_0x0 + No filter, BRK2 acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable +Note: The BRK2 must only be used with OSSR = OSSI = 1. +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 24 + 1 + read-write + + + B_0x0 + Break input BRK2 disabled + 0x0 + + + B_0x1 + Break input BRK2 enabled + 0x1 + + + + + BK2P + Break 2 polarity +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 25 + 1 + read-write + + + B_0x0 + Break input BRK2 is active low + 0x0 + + + B_0x1 + Break input BRK2 is active high + 0x1 + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BK2DSRM + Break2 Disarm +Refer to BKDSRM description + 27 + 1 + read-write + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional +Refer to BKBID description + 29 + 1 + read-write + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x48 + 16 + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... +Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. +If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: +(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL +In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA +According to the configuration of the DMA Data Size, several cases may occur: +If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. +If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x11 + 18 transfers + 0x11 + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 32 + read-write + + + + + TIM1_OR1 + TIM1_OR1 + TIM1 option register 1 + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection +This bit selects the ocref_clr input source. +Others: Reserved +Note: COMP3 is available on STM32G0B1xx and STM32G0C1xx salestypes only. + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC5M + OC5M[0]: Output compare 5 mode +Refer to OC1M description. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC6M + OC6M[0]: Output compare 6 mode +Refer to OC1M description. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/Compare 5 value +CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. + 0 + 16 + read-write + + + GC5C1 + Group Channel 5 and Channel 1 +Distortion on Channel 1 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC1REFC5 + 0x0 + + + B_0x1 + OC1REFC is the logical AND of OC1REFC and OC5REF + 0x1 + + + + + GC5C2 + Group Channel 5 and Channel 2 +Distortion on Channel 2 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC2REFC + 0x0 + + + B_0x1 + OC2REFC is the logical AND of OC2REFC and OC5REF + 0x1 + + + + + GC5C3 + Group Channel 5 and Channel 3 +Distortion on Channel 3 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). +Note: it is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC3REFC + 0x0 + + + B_0x1 + OC3REFC is the logical AND of OC3REFC and OC5REF + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x5C + 16 + 0x0000 + 0xFFFF + + + CCR6 + Capture/Compare 6 value +CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. + 0 + 16 + read-write + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x60 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable +This bit enables the COMP1 for the timers BRK input. COMP1 output is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable +This bit enables the COMP2 for the timers BRK input. COMP2 output is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + B_0x2 + COMP2 output + 0x2 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + B_0x6 + COMP3 output (available on STM32G0B1xx and STM32G0C1xx salestypes only) + 0x6 + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 Alternate function register 2 + 0x64 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BK2INE + BRK2 BKIN input enable +This bit enables the BKIN2 alternate function input for the timers BRK2 input. BKIN2 input is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN2 input disabled + 0x0 + + + B_0x1 + BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + BRK2 COMP1 enable +This bit enables the COMP1 for the timers BRK2 input. COMP1 output is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BK2CMP2E + BRK2 COMP2 enable +This bit enables the COMP2 for the timers BRK2 input. COMP2 output is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BK2INP + BRK2 BKIN2 input polarity +This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + BK2CMP1P + BRK2 COMP1 input polarity +This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + BK2CMP2P + BRK2 COMP2 input polarity +This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM1_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM1_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM1_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM1_CH4 input + 0x0 + + + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40000000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 global interrupt + 15 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section23. + 0x1 + + + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1_ALTERNATE1 + TIM2 capture/compare mode register 1 + TIM2_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2_ALTERNATE1 + TIM2 capture/compare mode register 2 + TIM2_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM2_CNT_ALTERNATE1 + TIM2_CNT_ALTERNATE1 + TIM2 counter + TIM2_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM2_OR1 + TIM2_OR1 + TIM2 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection + + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 + 0x1 + + + B_0x2 + COMP2 + 0x2 + + + B_0x3 + LSE + 0x3 + + + B_0x4 + MCO + 0x4 + + + B_0x5 + MCO2 + 0x5 + + + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM2_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM2_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM2_CH3 input + 0x0 + + + + + + + + + TIM3 + TIM3 address block description + TIM3 + 0x40000400 + + 0x0 + 0x6C + registers + + + TIM3 + TIM3 global interrupt + 16 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section23. + 0x1 + + + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_ALTERNATE1 + TIM3_CCMR1_ALTERNATE1 + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_ALTERNATE1 + TIM3_CCMR2_ALTERNATE1 + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM3_CNT_ALTERNATE1 + TIM3_CNT_ALTERNATE1 + TIM3 counter + TIM3_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM3_OR1 + TIM3_OR1 + TIM3 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection + + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + B_0x2 + COMP2 output + 0x2 + + + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM3_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM3_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM3_CH3 input + 0x0 + + + + + + + + + TIM6 + TIM6 address block description + TIM + 0x40001000 + + 0x0 + 0x30 + registers + + + TIM6_DAC_LPTIM1 + TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) + 17 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. +CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x04 + 16 + 0x0000 + 0xFFFF + + + MMS + Master mode selection +These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/Interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 16 + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). + 0x1 + + + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded into the active prescaler register at each update event. +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Prescaler value +ARR is the value to be loaded into the actual auto-reload register. +Refer to Section123.3.1: Time-base unit on page1596 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + + + TIM7 + TIM7 address block description + TIM + 0x40001400 + + 0x0 + 0x30 + registers + + + TIM7_LPTIM2 + TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) + 18 + + + + TIM7_CR1 + TIM7_CR1 + TIM7 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. +CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM7_CR2 + TIM7_CR2 + TIM7 control register 2 + 0x04 + 16 + 0x0000 + 0xFFFF + + + MMS + Master mode selection +These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + + + + + TIM7_DIER + TIM7_DIER + TIM7 DMA/Interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM7_SR + TIM7_SR + TIM7 status register + 0x10 + 16 + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + + + TIM7_EGR + TIM7_EGR + TIM7 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). + 0x1 + + + + + + + TIM7_CNT + TIM7_CNT + TIM7 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM7_PSC + TIM7_PSC + TIM7 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded into the active prescaler register at each update event. +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM7_ARR + TIM7_ARR + TIM7 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Prescaler value +ARR is the value to be loaded into the actual auto-reload register. +Refer to Section123.3.1: Time-base unit on page1596 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + + + TIM15 + TIM15 address block description + TIM15 + 0x40014000 + + 0x0 + 0x6C + registers + + + TIM15_LPTIM3 + TIM15 and LPTIM3 global interrupt (combined with EXTI line 29) + 19 + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt if enabled + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO). + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO). + 0x5 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) + + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) + + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (OC2 output) + + 10 + 1 + read-write + + + B_0x0 + OC2=0 when MOE=0 + 0x0 + + + B_0x1 + OC2=1 when MOE=0 + 0x1 + + + + + + + TIM15_SMCR + TIM15_SMCR + TIM15 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred + 0x0 + + + B_0x1 + Trigger interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag + + 10 + 1 + read-write + + + + + TIM15_EGR + TIM15_EGR + TIM15 event generation register + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation + + 2 + 1 + write-only + + + COMG + Capture/Compare control update generation + + 5 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM15_CCMR1 + TIM15_CCMR1 + TIM15 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM15_CCMR1_ALTERNATE1 + TIM15_CCMR1_ALTERNATE1 + TIM15 capture/compare mode register 1 + TIM15_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + CC2E + Capture/Compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity + + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity + + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value + + 0 + 16 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value + + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value + + 0 + 16 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register 2 + 0x38 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value + + 0 + 16 + read-write + + + + + TIM15_BDTR + TIM15_BDTR + TIM15 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable + + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable + + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity + + 10 + 1 + read-write + + + B_0x0 + COMP1 input is active low + 0x0 + + + B_0x1 + COMP1 input is active high + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity + + 11 + 1 + read-write + + + B_0x0 + COMP2 input is active low + 0x0 + + + B_0x1 + COMP2 input is active high + 0x1 + + + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input + + 0 + 4 + read-write + + + B_0x0 + TIM15_CH1 input + 0x0 + + + B_0x1 + TIM2_IC1 + 0x1 + + + B_0x2 + TIM3_IC1 + 0x2 + + + + + TI2SEL + selects TI2[0] to TI2[15] input + + 8 + 4 + read-write + + + B_0x0 + TIM15_CH2 input + 0x0 + + + B_0x1 + TIM2_IC2 + 0x1 + + + B_0x2 + TIM3_IC2 + 0x2 + + + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40014400 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 global interrupt + 20 + + + + TIM16_CR1 + TIM16_CR1 + TIM16 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM16_CR2 + TIM16_CR2 + TIM16 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) + + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) + + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + + + TIM16_DIER + TIM16_DIER + TIM16 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + + + TIM16_SR + TIM16_SR + TIM16 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM16_EGR + TIM16_EGR + TIM16 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + COMG + Capture/Compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM16_CCMR1 + TIM16_CCMR1 + TIM16 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input. + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N= + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + + + TIM16_CCMR1_ALTERNATE1 + TIM16_CCMR1_ALTERNATE1 + TIM16 capture/compare mode register 1 + TIM16_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM16_CCER + TIM16_CCER + TIM16 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + + + TIM16_CNT + TIM16_CNT + TIM16 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM16_PSC + TIM16_PSC + TIM16 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM16_ARR + TIM16_ARR + TIM16 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value + + 0 + 16 + read-write + + + + + TIM16_RCR + TIM16_RCR + TIM16 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value + + 0 + 8 + read-write + + + + + TIM16_CCR1 + TIM16_CCR1 + TIM16 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value + + 0 + 16 + read-write + + + + + TIM16_BDTR + TIM16_BDTR + TIM16 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM16_DCR + TIM16_DCR + TIM16 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM16_DMAR + TIM16_DMAR + TIM16 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable + + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable + + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity + + 10 + 1 + read-write + + + B_0x0 + COMP1 input is active low + 0x0 + + + B_0x1 + COMP1 input is active high + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity + + 11 + 1 + read-write + + + B_0x0 + COMP2 input is active low + 0x0 + + + B_0x1 + COMP2 input is active high + 0x1 + + + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input + + 0 + 4 + read-write + + + B_0x0 + TIM16_CH1 input + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + LSE + 0x2 + + + B_0x3 + RTC wakeup + 0x3 + + + B_0x4 + MCO2 + 0x4 + + + + + + + + + TSC + TSC address block description + TSC + 0x40024000 + + 0x0 + 0x50 + registers + + + TSC + TSC global interrupt + 21 + + + + TSC_CR + TSC_CR + TSC control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSCE + Touch sensing controller enable +This bit is set and cleared by software to enable/disable the touch sensing controller. +Note: When the touch sensing controller is disabled, TSC registers settings have no effect. + 0 + 1 + read-write + + + B_0x0 + Touch sensing controller disabled + 0x0 + + + B_0x1 + Touch sensing controller enabled + 0x1 + + + + + START + Start a new acquisition +This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. + 1 + 1 + read-write + + + B_0x0 + Acquisition not started + 0x0 + + + B_0x1 + Start a new acquisition + 0x1 + + + + + AM + Acquisition mode +This bit is set and cleared by software to select the acquisition mode. +Note: This bit must not be modified when an acquisition is ongoing. + 2 + 1 + read-write + + + B_0x0 + Normal acquisition mode (acquisition starts as soon as START bit is set) + 0x0 + + + B_0x1 + Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) + 0x1 + + + + + SYNCPOL + Synchronization pin polarity +This bit is set and cleared by software to select the polarity of the synchronization input pin. + 3 + 1 + read-write + + + B_0x0 + Falling edge only + 0x0 + + + B_0x1 + Rising edge and high level + 0x1 + + + + + IODEF + I/O Default mode +This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). +Note: This bit must not be modified when an acquisition is ongoing. + 4 + 1 + read-write + + + B_0x0 + I/Os are forced to output push-pull low + 0x0 + + + B_0x1 + I/Os are in input floating + 0x1 + + + + + MCV + Max count value +These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. +Note: These bits must not be modified when an acquisition is ongoing. + 5 + 3 + read-write + + + B_0x0 + 255 + 0x0 + + + B_0x1 + 511 + 0x1 + + + B_0x2 + 1023 + 0x2 + + + B_0x3 + 2047 + 0x3 + + + B_0x4 + 4095 + 0x4 + + + B_0x5 + 8191 + 0x5 + + + B_0x6 + 16383 + 0x6 + + + + + PGPSC + Pulse generator prescaler +These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. + 12 + 3 + read-write + + + B_0x0 + f<sub>HCLK</sub> + 0x0 + + + B_0x1 + f<sub>HCLK</sub> /2 + 0x1 + + + B_0x2 + f<sub>HCLK</sub> /4 + 0x2 + + + B_0x3 + f<sub>HCLK</sub> /8 + 0x3 + + + B_0x4 + f<sub>HCLK</sub> /16 + 0x4 + + + B_0x5 + f<sub>HCLK</sub> /32 + 0x5 + + + B_0x6 + f<sub>HCLK</sub> /64 + 0x6 + + + B_0x7 + f<sub>HCLK</sub> /128 + 0x7 + + + + + SSPSC + Spread spectrum prescaler +This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). +Note: This bit must not be modified when an acquisition is ongoing. + 15 + 1 + read-write + + + B_0x0 + f<sub>HCLK</sub> + 0x0 + + + B_0x1 + f<sub>HCLK</sub> /2 + 0x1 + + + + + SSE + Spread spectrum enable +This bit is set and cleared by software to enable/disable the spread spectrum feature. +Note: This bit must not be modified when an acquisition is ongoing. + 16 + 1 + read-write + + + B_0x0 + Spread spectrum disabled + 0x0 + + + B_0x1 + Spread spectrum enabled + 0x1 + + + + + SSD + Spread spectrum deviation +These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. +... +Note: These bits must not be modified when an acquisition is ongoing. + 17 + 7 + read-write + + + B_0x0 + 1x t<sub>SSCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>SSCLK</sub> + 0x1 + + + B_0x7F + 128x t<sub>SSCLK</sub> + 0x7F + + + + + CTPL + Charge transfer pulse low +These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from C<sub>X</sub> to C<sub>S</sub>). +... +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. + 24 + 4 + read-write + + + B_0x0 + 1x t<sub>PGCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>PGCLK</sub> + 0x1 + + + B_0xF + 16x t<sub>PGCLK</sub> + 0xF + + + + + CTPH + Charge transfer pulse high +These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of C<sub>X</sub>). +... +Note: These bits must not be modified when an acquisition is ongoing. + 28 + 4 + read-write + + + B_0x0 + 1x t<sub>PGCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>PGCLK</sub> + 0x1 + + + B_0xF + 16x t<sub>PGCLK</sub> + 0xF + + + + + + + TSC_IER + TSC_IER + TSC interrupt enable register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIE + End of acquisition interrupt enable +This bit is set and cleared by software to enable/disable the end of acquisition interrupt. + 0 + 1 + read-write + + + B_0x0 + End of acquisition interrupt disabled + 0x0 + + + B_0x1 + End of acquisition interrupt enabled + 0x1 + + + + + MCEIE + Max count error interrupt enable +This bit is set and cleared by software to enable/disable the max count error interrupt. + 1 + 1 + read-write + + + B_0x0 + Max count error interrupt disabled + 0x0 + + + B_0x1 + Max count error interrupt enabled + 0x1 + + + + + + + TSC_ICR + TSC_ICR + TSC interrupt clear register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIC + End of acquisition interrupt clear +This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding EOAF of the TSC_ISR register + 0x1 + + + + + MCEIC + Max count error interrupt clear +This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding MCEF of the TSC_ISR register + 0x1 + + + + + + + TSC_ISR + TSC_ISR + TSC interrupt status register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAF + End of acquisition flag +This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register. + 0 + 1 + read-only + + + B_0x0 + Acquisition is ongoing or not started + 0x0 + + + B_0x1 + Acquisition is complete + 0x1 + + + + + MCEF + Max count error flag +This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register. + 1 + 1 + read-only + + + B_0x0 + No max count error (MCE) detected + 0x0 + + + B_0x1 + Max count error (MCE) detected + 0x1 + + + + + + + TSC_IOHCR + TSC_IOHCR + TSC I/O hysteresis control register + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 0 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 1 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 2 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 3 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 4 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 5 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 6 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 7 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 8 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 9 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 10 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 11 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 12 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 13 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 14 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 15 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 16 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 17 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 18 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 19 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 20 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 21 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 22 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 23 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 24 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 25 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 26 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 27 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + + + TSC_IOASCR + TSC_IOASCR + TSC I/O analog switch control register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 0 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 1 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 2 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 3 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 4 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 5 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 6 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 7 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 8 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 9 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 10 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 11 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 12 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 13 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 14 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 15 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 16 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 17 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 18 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 19 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 20 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 21 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 22 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 23 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 24 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 25 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 26 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 27 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + + + TSC_IOSCR + TSC_IOSCR + TSC I/O sampling control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 0 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 1 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 2 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 3 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 4 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 5 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 6 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 7 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 8 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 9 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 10 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 11 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 12 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 13 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 14 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 15 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 16 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 17 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 18 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 19 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 20 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 21 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 22 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 23 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 24 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 25 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 26 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 27 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + + + TSC_IOCCR + TSC_IOCCR + TSC I/O channel control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 0 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 1 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 2 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 3 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 4 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 5 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 6 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 7 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 8 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 9 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 10 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 11 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 12 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 13 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 14 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 15 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 16 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 17 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 18 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 19 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 20 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 21 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 22 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 23 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 24 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 25 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 26 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 27 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + + + TSC_IOGCSR + TSC_IOGCSR + TSC I/O group control status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 0 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G2E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 1 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G3E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 2 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G4E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 3 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G5E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 4 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G6E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 5 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G7E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 6 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G1S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 16 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G2S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 17 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G3S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 18 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G4S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 19 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G5S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 20 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G6S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 21 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G7S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 22 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + + + TSC_IOG1CR + TSC_IOG1CR + TSC I/O group 1 counter register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG2CR + TSC_IOG2CR + TSC I/O group 2 counter register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG3CR + TSC_IOG3CR + TSC I/O group 3 counter register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG4CR + TSC_IOG4CR + TSC I/O group 4 counter register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG5CR + TSC_IOG5CR + TSC I/O group 5 counter register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG6CR + TSC_IOG6CR + TSC I/O group 6 counter register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG7CR + TSC_IOG7CR + TSC I/O group 7 counter register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + + + USART1 + USART address block description + USART + 0x40013800 + + 0x0 + 0x30 + registers + + + USART1 + USART1 global interrupt (combined with EXTI line 25) + 27 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + None + 31 + 1 + read-write + + + + + USART_CR1_ALTERNATE + USART_CR1_ALTERNATE + USART control register 1 + USART_CR1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous Slave mode enable +When the SLVEN bit is set, the Synchronous slave mode is enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the USART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +This bit can only be written when the USART is disabled (UE=0). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in Synchronous mode. +The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase +This bit is used to select the phase of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure1233 and Figure1234) +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +This bit enables the user to select the polarity of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable +This bit enables the user to enable the CK pin. +This bit can only be written when the USART is disabled (UE=0). +Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. +In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +Note: UE = 1 + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits +These bits are used for programming the stop bits. +This bitfield can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0.5 stop bit. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1.5 stop bits + 0x3 + + + + + LINEN + LIN mode enable +This bit is set and cleared by software. +The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable +This bit is set and cleared by software. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode +These bits are set and cleared by software. +This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). +Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable +This bit is set and cleared by software. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node +These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1or UDR = 1 in the USART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable +This bit is set and cleared by software. +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable +This bit is used for enabling Smartcard mode. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the USART is disabled (UE=0). +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the USART is disabled (UE=0) +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable +This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data are written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the USART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode) + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count +This bitfield specifies the number of retries for transmission and reception in Smartcard mode. +In Transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). +In Reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). +This bitfield must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. +0x1 to 0x7: number of automatic retransmission attempts (before signaling error) +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in Transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate +BRR[15:4] +BRR[15:4] correspond to USARTDIV[15:4] +BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared. + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value +PSC[7:0] = IrDA Normal and Low-power baud rate +This bitfield is used for programming the prescaler for dividing the USART source clock to achieve the low-power frequency: +The source clock is divided by the value given in the register (8 significant bits): +... +PSC[4:0]: Prescaler value +This bitfield is used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: +... +This bitfield can only be written when the USART is disabled (UE=0). +Note: Bits [7:5] must be kept cleared if Smartcard mode is used. +Note: This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to Section131.4: USART implementation on page1826. + 0 + 8 + read-write + + + B_0x0_SMARTCARD_MODE + Reserved - do not program this value + 0x0 + + + B_0x1_SMARTCARD_MODE + divides the source clock by 2 + 0x1 + + + B_0x2_SMARTCARD_MODE + divides the source clock by 4 + 0x2 + + + B_0x3_SMARTCARD_MODE + divides the source clock by 6 + 0x3 + + + + + GT + Guard time value +This bitfield is used to program the Guard time value in terms of number of baud clock periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value +This bitfield gives the Receiver timeout value in terms of number of bit duration. +In Standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. +Note: This value must only be programmed once per received character. + 0 + 24 + read-write + + + BLEN + Block Length +This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). +This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. +Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request +Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 0 + 1 + write-only + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software must wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This enables to discard the received data without reading them, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section131.5.9: Tolerance of the USART receiver to clock deviation on page1845). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. +RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: +When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXE/TXFE is set. +When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. +When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. +When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. +An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF must be checked prior to writing in TXFIFO (TXFNF and TXFE is set at the same time). +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if EOBIE1=11 in the USART_CR1 register. +It is cleared by software, writing 1 to EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-only + + + TXFE + TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO Full +This bit is set by hardware when the number of received data corresponds to RXFIFO1size1+11 (RXFIFO full + 1 data in the USART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section131.4: USART implementation on page1826. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. +Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section131.5.9: Tolerance of the USART receiver to clock deviation on page1845). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag is set when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). +An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if EOBIE1=11 in the USART_CR1 register. +It is cleared by software, writing 1 to EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section131.4: USART implementation on page1826. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register. + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register. + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 11 + 1 + write-only + + + EOBCF + End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register. +Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826 + 13 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure1227). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure1227). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The USART input clock can be divided by a prescaler factor: +Remaining combinations: Reserved +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + USART2 + 0x40004400 + + USART2_LPUART2 + USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) + 28 + + + + USART3 + 0x40004800 + + USART3_LPUART1 + USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) + 29 + + + + USART4 + 0x40004C00 + + USART4 + USART4 global interrupt (combined with EXTI lines 20 and 34) + 30 + + + + VREFBUF + VREFBUF address block description + VREFBUF + 0x40010030 + + 0x0 + 0x8 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x00 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + ENVR + Voltage reference buffer mode enable +This bit is used to enable the voltage reference buffer mode. + 0 + 1 + read-write + + + B_0x0 + Internal voltage reference mode disable (external voltage reference mode). + 0x0 + + + B_0x1 + Internal voltage reference mode (reference buffer enable or hold mode) enable. + 0x1 + + + + + HIZ + High impedance mode +This bit controls the analog switch to connect or not the V<sub>REF+</sub> pin. +Refer to Table172: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. + 1 + 1 + read-write + + + B_0x0 + V<sub>REF+</sub> pin is internally connected to the voltage reference buffer output. + 0x0 + + + B_0x1 + V<sub>REF+</sub> pin is high impedance. + 0x1 + + + + + VRS + Voltage reference scale +This bit selects the value generated by the voltage reference buffer. + 2 + 1 + read-write + + + B_0x0 + Voltage reference set to V<sub>REF_OUT1</sub> (around 2.0481V). + 0x0 + + + B_0x1 + Voltage reference set to V<sub>REF_OUT2</sub> (around 2.51V). + 0x1 + + + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + B_0x0 + the voltage reference buffer output is not ready. + 0x0 + + + B_0x1 + the voltage reference buffer output reached the requested level. + 0x1 + + + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + TRIM + None + 0 + 6 + read-write + + + + + + + WWDG + WWDG address block description + WWDG + 0x40002C00 + + 0x0 + 0xC + registers + + + WWDG + Window watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + WWDG control register + 0x000 + 0x20 + 0x0000007F + 0xFFFFFFFF + + + T + 7-bit counter (MSB to LSB) +These bits contain the value of the watchdog counter, decremented every +(4096 x 2<sup>WDGTB[2:0]</sup>) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). + 0 + 7 + read-write + + + WDGA + Activation bit +This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset. + 7 + 1 + read-write + + + B_0x0 + Watchdog disabled + 0x0 + + + B_0x1 + Watchdog enabled + 0x1 + + + + + + + WWDG_CFR + WWDG_CFR + WWDG configuration register + 0x004 + 0x20 + 0x0000007F + 0xFFFFFFFF + + + W + 7-bit window value +These bits contain the window value to be compared with the down-counter. + 0 + 7 + read-write + + + EWI + Early wake-up interrupt enable +Set by software and cleared by hardware after a reset. When set, an interrupt occurs whenever the counter reaches the value 0x40. + 9 + 1 + read-write + + + WDGTB + Timer base +The timebase of the prescaler can be modified as follows: + 11 + 3 + read-write + + + B_0x0 + CK counter clock (PCLK div 4096) div 1 + 0x0 + + + B_0x1 + CK counter clock (PCLK div 4096) div 2 + 0x1 + + + B_0x2 + CK counter clock (PCLK div 4096) div 4 + 0x2 + + + B_0x3 + CK counter clock (PCLK div 4096) div 8 + 0x3 + + + B_0x4 + CK counter clock (PCLK div 4096) div 16 + 0x4 + + + B_0x5 + CK counter clock (PCLK div 4096) div 32 + 0x5 + + + B_0x6 + CK counter clock (PCLK div 4096) div 64 + 0x6 + + + B_0x7 + CK counter clock (PCLK div 4096) div 128 + 0x7 + + + + + + + WWDG_SR + WWDG_SR + WWDG status register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EWIF + Early wake-up interrupt flag +This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled. + 0 + 1 + read-write + + + + + + + diff --git a/svd/STM32U0xx/STM32U073.svd b/svd/STM32U0xx/STM32U073.svd new file mode 100644 index 0000000..eae75a0 --- /dev/null +++ b/svd/STM32U0xx/STM32U073.svd @@ -0,0 +1,97238 @@ + + + + STM32U073 + 1.0 + STM32U073 + + CM0+ + r0p1 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x40012400 + + 0x0 + 0x30C + registers + + + ADC_COMP + ADC and COMP interrupts (ADC combined with EXTI lines 17 and 18) + 12 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready +This bit is set by hardware after the ADC has been enabled (ADEN+1) and when the ADC reaches a state where it is ready to accept conversion requests. +It is cleared by software writing 1 to it. + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag +This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1. + 1 + 1 + read-write + + + B_0x0 + Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag +This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. + 2 + 1 + read-write + + + B_0x0 + Channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Channel conversion complete + 0x1 + + + + + EOS + End of sequence flag +This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. + 3 + 1 + read-write + + + B_0x0 + Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Conversion sequence complete + 0x1 + + + + + OVR + ADC overrun +This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + AWD1 + Analog watchdog 1 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. + 7 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. + 8 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. + 9 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + EOCAL + End Of Calibration flag +This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. + 11 + 1 + read-write + + + B_0x0 + Calibration is not complete + 0x0 + + + B_0x1 + Calibration is complete + 0x1 + + + + + CCRDY + Channel Configuration Ready flag +This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. +Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. + 13 + 1 + read-write + + + B_0x0 + Channel configuration update not applied. + 0x0 + + + B_0x1 + Channel configuration update is applied. + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable +This bit is set and cleared by software to enable/disable the ADC Ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled. + 0x0 + + + B_0x1 + ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable +This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. + 0x1 + + + + + EOCIE + End of conversion interrupt enable +This bit is set and cleared by software to enable/disable the end of conversion interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled + 0x0 + + + B_0x1 + EOC interrupt enabled. An interrupt is generated when the EOC bit is set. + 0x1 + + + + + EOSIE + End of conversion sequence interrupt enable +This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. An interrupt is generated when the EOS bit is set. + 0x1 + + + + + OVRIE + Overrun interrupt enable +This bit is set and cleared by software to enable/disable the overrun interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + EOCALIE + End of calibration interrupt enable +This bit is set and cleared by software to enable/disable the end of calibration interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + End of calibration interrupt disabled + 0x0 + + + B_0x1 + End of calibration interrupt enabled + 0x1 + + + + + CCRDYIE + Channel Configuration Ready Interrupt enable +This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Channel configuration ready interrupt disabled + 0x0 + + + B_0x1 + Channel configuration ready interrupt enabled + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADEN + ADC enable command +This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. +It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command + 1 + 1 + read-write + + + B_0x0 + No ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. + 0x1 + + + + + ADSTART + ADC start conversion command + 2 + 1 + read-write + + + B_0x0 + No ADC conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. + 0x1 + + + + + ADSTP + ADC stop conversion command + 4 + 1 + read-write + + + B_0x0 + No ADC stop conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. + 0x1 + + + + + ADVREGEN + ADC Voltage Regulator Enable + 28 + 1 + read-write + + + B_0x0 + ADC voltage regulator disabled + 0x0 + + + B_0x1 + ADC voltage regulator enabled + 0x1 + + + + + ADCAL + ADC calibration +This bit is set by software to start the calibration of the ADC. + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. + 0x1 + + + + + + + ADC_CFGR1 + ADC_CFGR1 + ADC configuration register 1 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable +This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration +This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN1=11. +For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. + 1 + 1 + read-write + + + B_0x0 + DMA one shot mode selected + 0x0 + + + B_0x1 + DMA circular mode selected + 0x1 + + + + + SCANDIR + Scan sequence direction +This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Upward scan (from CHSEL0 to CHSEL) + 0x0 + + + B_0x1 + Backward scan (from CHSEL to CHSEL0) + 0x1 + + + + + RES + Data resolution +These bits are written by software to select the resolution of the conversion. + 3 + 2 + read-write + + + B_0x0 + 12 bits + 0x0 + + + B_0x1 + 10 bits + 0x1 + + + B_0x2 + 8 bits + 0x2 + + + B_0x3 + 6 bits + 0x3 + + + + + ALIGN + Data alignment +This bit is set and cleared by software to select right or left alignment. Refer to Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332 + 5 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + EXTSEL + External trigger selection +These bits select the external event used to trigger the start of conversion (refer to Table160: External triggers for details): + 6 + 3 + read-write + + + B_0x0 + TRG0 + 0x0 + + + B_0x1 + TRG1 + 0x1 + + + B_0x2 + TRG2 + 0x2 + + + B_0x3 + TRG3 + 0x3 + + + B_0x4 + TRG4 + 0x4 + + + B_0x5 + TRG5 + 0x5 + + + B_0x6 + TRG6 + 0x6 + + + B_0x7 + TRG7 + 0x7 + + + + + EXTEN + External trigger enable and polarity selection +These bits are set and cleared by software to select the external trigger polarity and enable the trigger. + 10 + 2 + read-write + + + B_0x0 + Hardware trigger detection disabled (conversions can be started by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + OVRMOD + Overrun management mode +This bit is set and cleared by software and configure the way data overruns are managed. + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / continuous conversion mode +This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + WAIT + Wait conversion mode +This bit is set and cleared by software to enable/disable wait conversion mode.<sup>.</sup> + 14 + 1 + read-write + + + B_0x0 + Wait conversion mode off + 0x0 + + + B_0x1 + Wait conversion mode on + 0x1 + + + + + AUTOFF + Auto-off mode +This bit is set and cleared by software to enable/disable auto-off mode.<sup>.</sup> + 15 + 1 + read-write + + + B_0x0 + Auto-off mode disabled + 0x0 + + + B_0x1 + Auto-off mode enabled + 0x1 + + + + + DISCEN + Discontinuous mode +This bit is set and cleared by software to enable/disable discontinuous mode. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode disabled + 0x0 + + + B_0x1 + Discontinuous mode enabled + 0x1 + + + + + CHSELRMOD + Mode selection of the ADC_CHSELR register +This bit is set and cleared by software to control the ADC_CHSELR feature: +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 21 + 1 + read-write + + + B_0x0 + Each bit of the ADC_CHSELR register enables an input + 0x0 + + + B_0x1 + ADC_CHSELR register is able to sequence up to 8 channels + 0x1 + + + + + AWD1SGL + Enable the watchdog on a single channel or on all channels +This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled + 0x0 + + + B_0x1 + Analog watchdog 1 enabled + 0x1 + + + + + AWD1CH + Analog watchdog channel selection +These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. +..... +Others: Reserved +Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. + 26 + 5 + read-write + + + B_0x0 + ADC analog input Channel 0 monitored by AWD + 0x0 + + + B_0x1 + ADC analog input Channel 1 monitored by AWD + 0x1 + + + B_0x13 + ADC analog input Channel 19 monitored by AWD + 0x13 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVSE + Oversampler Enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 0 + 1 + read-write + + + B_0x0 + Oversampler disabled + 0x0 + + + B_0x1 + Oversampler enabled + 0x1 + + + + + OVSR + Oversampling ratio +This bit filed defines the number of oversampling ratio. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift +This bit is set and cleared by software. +Others: Reserved +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TOVS + Triggered Oversampling +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively after a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a trigger + 0x1 + + + + + LFTRIG + Low frequency trigger mode enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 29 + 1 + read-write + + + B_0x0 + Low Frequency Trigger Mode disabled + 0x0 + + + B_0x1 + Low Frequency Trigger Mode enabled + 0x1 + + + + + CKMODE + ADC clock mode +These bits are set and cleared by software to define how the analog ADC is clocked: +In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. +Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10). + 30 + 2 + read-write + + + B_0x0 + ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) + 0x0 + + + B_0x1 + PCLK/2 (Synchronous clock mode) + 0x1 + + + B_0x2 + PCLK/4 (Synchronous clock mode) + 0x2 + + + + + + + ADC_SMPR + ADC_SMPR + ADC sampling time register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMP1 + Sampling time selection 1 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMP2 + Sampling time selection 2 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMPSEL0 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL1 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL2 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL3 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL4 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL5 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL6 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL7 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL8 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL9 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL10 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL11 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL12 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 20 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL13 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 21 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL14 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL15 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL16 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL17 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL18 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 26 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL19 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 27 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + + + ADC_AWD1TR + ADC_AWD1TR + ADC watchdog threshold register + 0x20 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT1 + Analog watchdog 1 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_AWD2TR + ADC_AWD2TR + ADC watchdog threshold register + 0x24 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT2 + Analog watchdog 2 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_CHSELR + ADC_CHSELR + ADC channel selection register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CHSEL0 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 0 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL1 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 1 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL2 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL3 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 3 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL4 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 4 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL5 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 5 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL6 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 6 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL7 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 7 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL8 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 8 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL9 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 9 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL10 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 10 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL11 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 11 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL12 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 12 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL13 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 13 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL14 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 14 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL15 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 15 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL16 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 16 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL17 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 17 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL18 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 18 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL19 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 19 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + + + ADC_CHSELR_ALTERNATE + ADC_CHSELR_ALTERNATE + ADC channel selection register + ADC_CHSELR + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SQ1 + 1st conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 0 + 4 + read-write + + + SQ2 + 2nd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 4 + 4 + read-write + + + SQ3 + 3rd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 4 + read-write + + + SQ4 + 4th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 4 + read-write + + + SQ5 + 5th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 4 + read-write + + + SQ6 + 6th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 20 + 4 + read-write + + + SQ7 + 7th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 24 + 4 + read-write + + + SQ8 + 8th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +... +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 28 + 4 + read-write + + + B_0x0 + CH0 + 0x0 + + + B_0x1 + CH1 + 0x1 + + + B_0xC + CH12 + 0xC + + + B_0xD + CH13 + 0xD + + + B_0xE + CH14 + 0xE + + + B_0xF + No channel selected (End of sequence) + 0xF + + + + + + + ADC_AWD3TR + ADC_AWD3TR + ADC watchdog threshold register + 0x2C + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT3 + Analog watchdog 3 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_DR + ADC_DR + ADC data register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + Converted data +These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD2CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC Analog Watchdog 3 Configuration register + 0xA4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD3CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factor + 0xB4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALFACT + Calibration factor +These bits are written by hardware or by software. +Once a calibration is complete,1they are updated by hardware with the calibration factors. +Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new conversion is launched. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. +Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + 0 + 7 + read-write + + + + + ADC_CCR + ADC_CCR + ADC common configuration register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESC + ADC prescaler +Set and cleared by software to select the frequency of the clock to the ADC. +Other: Reserved +Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10). + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + V<sub>REFINT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>REFINT</sub>. +Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + V<sub>REFINT</sub> disabled + 0x0 + + + B_0x1 + V<sub>REFINT</sub> enabled + 0x1 + + + + + TSEN + Temperature sensor enable +This bit is set and cleared by software to enable/disable the temperature sensor. +Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Temperature sensor disabled + 0x0 + + + B_0x1 + Temperature sensor enabled + 0x1 + + + + + VBATEN + V<sub>BAT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>BAT</sub> channel. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing) + 24 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> channel disabled + 0x0 + + + B_0x1 + V<sub>BAT</sub> channel enabled + 0x1 + + + + + + + + + COMP1 + COMP address block description + COMP + 0x40010200 + + 0x0 + 0x8 + registers + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Comparator 1 enable bit +This bit is controlled by software (if not locked). It enables the comparator 1: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + INMSEL + Comparator 1 signal selector for inverting input INM +This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 1: +Refer to Table176: COMP1 inverting input assignment. + 4 + 4 + read-write + + + INPSEL + Comparator 1 signal selector for noninverting input +This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 1 (also see the WINMODE bit): +Refer to Table175: COMP1 noninverting input assignment. + 8 + 3 + read-write + + + WINMODE + Comparator 1 noninverting input selector for window mode +This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 1: + 11 + 1 + read-write + + + B_0x0 + Signal selected with INPSEL[2:0] bitfield of this register + 0x0 + + + B_0x1 + COMP_INP signal of the comparator 2 (required for window mode, see Figure164) + 0x1 + + + + + WINOUT + Comparator 1 output selector +This bit is controlled by software (if not locked). It selects the comparator 1 output: + 14 + 1 + read-write + + + B_0x0 + COMP_VALUE + 0x0 + + + B_0x1 + COMP_VALUE XOR COMP_VALUE (required for window mode, see Figure164) + 0x1 + + + + + POLARITY + Comparator 1 polarity selector +This bit is controlled by software (if not locked). It selects the comparator 1 output polarity: + 15 + 1 + read-write + + + B_0x0 + Non-inverted + 0x0 + + + B_0x1 + Inverted + 0x1 + + + + + HYST + Comparator 1 hysteresis selector +This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1: + 16 + 2 + read-write + + + B_0x0 + No hysteresis + 0x0 + + + B_0x1 + Low hysteresis + 0x1 + + + B_0x2 + Medium hysteresis + 0x2 + + + B_0x3 + High hysteresis + 0x3 + + + + + PWRMODE + Comparator 1 power mode selector +This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1: + 18 + 2 + read-write + + + B_0x0 + High speed/high power + 0x0 + + + B_0x1 + Medium speed/medium power + 0x1 + + + B_0x2 + Medium speed/medium power + 0x2 + + + B_0x3 + Low speed/low power + 0x3 + + + + + BLANKSEL + Comparator 1 blanking source selector +This bitfield is controlled by software (if not locked). It selects the blanking source: +Others: Reserved, must not be used + 20 + 5 + read-write + + + B_0x0 + No blanking + 0x0 + + + B_0x1 + TIM1 OC4 enabled as blanking source + 0x1 + + + B_0x2 + TIM1 OC5 enabled as blanking source + 0x2 + + + B_0x4 + TIM2 OC3 enabled as blanking source + 0x4 + + + B_0x8 + TIM3 OC3 enabled as blanking source + 0x8 + + + B_0x10 + TIM15 OC2 enabled as blanking source + 0x10 + + + + + VALUE + Comparator 1 output status +This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in Figure163. + 30 + 1 + read-only + + + LOCK + COMP_CSR register lock +This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. + 31 + 1 + read-write + + + B_0x0 + Not locked + 0x0 + + + B_0x1 + Locked + 0x1 + + + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Comparator 2 enable bit +This bit is controlled by software (if not locked). It enables the comparator 2: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + INMSEL + Comparator 2 signal selector for inverting input INM +This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 2: +Refer to Table178: COMP2 inverting input assignment. + 4 + 4 + read-write + + + INPSEL + Comparator 2 signal selector for noninverting input +This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 2 (also see the WINMODE bit): +Refer to Table177: COMP2 noninverting input assignment. + 8 + 2 + read-write + + + WINMODE + Comparator 2 noninverting input selector for window mode +This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 2: + 11 + 1 + read-write + + + B_0x0 + Signal selected with INPSEL[1:0] bitfield of this register + 0x0 + + + B_0x1 + COMP_INP signal of the comparator 1 (required for window mode, see Figure164) + 0x1 + + + + + WINOUT + Comparator 2 output selector +This bit is controlled by software (if not locked). It selects the comparator 2 output: + 14 + 1 + read-write + + + B_0x0 + COMP_VALUE + 0x0 + + + B_0x1 + COMP_VALUE XOR COMP_VALUE (required for window mode, see Figure164) + 0x1 + + + + + POLARITY + Comparator 2 polarity selector +This bit is controlled by software (if not locked). It selects the comparator 2 output polarity: + 15 + 1 + read-write + + + B_0x0 + Non-inverted + 0x0 + + + B_0x1 + Inverted + 0x1 + + + + + HYST + Comparator 2 hysteresis selector +This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2: + 16 + 2 + read-write + + + B_0x0 + No hysteresis + 0x0 + + + B_0x1 + Low hysteresis + 0x1 + + + B_0x2 + Medium hysteresis + 0x2 + + + B_0x3 + High hysteresis + 0x3 + + + + + PWRMODE + Comparator 2 power mode selector +This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2: + 18 + 2 + read-write + + + B_0x0 + High speed/high power + 0x0 + + + B_0x1 + Medium speed/medium power + 0x1 + + + B_0x2 + Medium speed/medium power + 0x2 + + + B_0x3 + Low speed/low power + 0x3 + + + + + BLANKSEL + Comparator 2 blanking source selector +This bitfield is controlled by software (if not locked). It selects the blanking source: +Others: Reserved, must not be used + 20 + 5 + read-write + + + B_0x0 + No blanking + 0x0 + + + B_0x1 + TIM1 OC4 enabled as blanking source + 0x1 + + + B_0x2 + TIM1 OC5 enabled as blanking source + 0x2 + + + B_0x4 + TIM2 OC3 enabled as blanking source + 0x4 + + + B_0x8 + TIM3 OC3 enabled as blanking source + 0x8 + + + B_0x10 + TIM15 OC2 enabled as blanking source + 0x10 + + + + + VALUE + Comparator 2 output status +This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in Figure163. + 30 + 1 + read-only + + + LOCK + COMP_CSR register lock +This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. + 31 + 1 + read-write + + + B_0x0 + Not locked + 0x0 + + + B_0x1 + Locked + 0x1 + + + + + + + + + CRC + CRC address block description + CRC + 0x40023000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected (RTYPE_IN1=10 or 1) + 0x0 + + + B_0x1 + Bit reversal done by byte (RTYPE_IN1=10) or half-word reversal done by word (RTYPE_IN1=11) + 0x1 + + + B_0x2 + Bit reversal done by half-word (RTYPE_IN1=10) or byte reversal done by word (RTYPE_IN1=11) + 0x2 + + + B_0x3 + Bit reversal done by word (RTYPE_IN1=10) or bit order is not affected (RTYPE_IN1=11) + 0x3 + + + + + REV_OUT + Reverse output data +This bitfield controls the reversal of the bit order of the output data. + 7 + 2 + read-write + + + B_0x0 + Bit order not affected (RTYPE_OUT1=10 or 1) + 0x0 + + + B_0x1 + Bit-reversed output format (RTYPE_OUT1=10) or half-word reversal done by word (RTYPE_OUT1=11) + 0x1 + + + B_0x2 + Bit order not affected (RTYPE_OUT1=10) or byte reversal done by word (RTYPE_OUT1=11) + 0x2 + + + B_0x3 + Bit order not affected (RTYPE_OUT1=10 or 1) + 0x3 + + + + + RTYPE_IN + Reverse type input +This bit controls the reversal granularity of the input data. + 9 + 1 + read-write + + + B_0x0 + Bit level input + 0x0 + + + B_0x1 + Byte or half-word level input + 0x1 + + + + + RTYPE_OUT + Reverse type output +This bit controls the reversal granularity of the output data. + 10 + 1 + read-write + + + B_0x0 + Bit level output + 0x0 + + + B_0x1 + Byte or half-word level output + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + CRS + CRS address block description + CRS + 0x40006C00 + + 0x0 + 0x10 + registers + + + + CRS_CR + CRS_CR + CRS control register + 0x00 + 0x20 + 0x00004000 + 0xFFFFFFFF + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + B_0x0 + SYNC event OK (SYNCOKF) interrupt disabled + 0x0 + + + B_0x1 + SYNC event OK (SYNCOKF) interrupt enabled + 0x1 + + + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + B_0x0 + SYNC warning (SYNCWARNF) interrupt disabled + 0x0 + + + B_0x1 + SYNC warning (SYNCWARNF) interrupt enabled + 0x1 + + + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + B_0x0 + Synchronization or trimming error (ERRF) interrupt disabled + 0x0 + + + B_0x1 + Synchronization or trimming error (ERRF) interrupt enabled + 0x1 + + + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + B_0x0 + Expected SYNC (ESYNCF) interrupt disabled + 0x0 + + + B_0x1 + Expected SYNC (ESYNCF) interrupt enabled + 0x1 + + + + + CEN + Frequency error counter enable +This bit enables the oscillator clock for the frequency error counter. +When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + B_0x0 + Frequency error counter disabled + 0x0 + + + B_0x1 + Frequency error counter enabled + 0x1 + + + + + AUTOTRIMEN + Automatic trimming enable +This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section15.4.4 for more details. + 6 + 1 + read-write + + + B_0x0 + Automatic trimming disabled, TRIM bits can be adjusted by the user. + 0x0 + + + B_0x1 + Automatic trimming enabled, TRIM bits are read-only and under hardware control. + 0x1 + + + + + SWSYNC + Generate software SYNC event +This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + A software SYNC event is generated. + 0x1 + + + + + TRIM + HSI48 oscillator smooth trimming +The default value of the HSI48 oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval. + 8 + 7 + read-write + + + + + CRS_CFGR + CRS_CFGR + CRS configuration register + 0x04 + 0x20 + 0x2022BB7F + 0xFFFFFFFF + + + RELOAD + Counter reload value +RELOAD is the value to be loaded in the frequency error counter with each SYNC event. +Refer to Section15.4.3 for more details about counter behavior. + 0 + 16 + read-write + + + FELIM + Frequency error limit +FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section15.4.4 for more details about FECAP evaluation. + 16 + 8 + read-write + + + SYNCDIV + SYNC divider +These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + read-write + + + B_0x0 + SYNC not divided (default) + 0x0 + + + B_0x1 + SYNC divided by 2 + 0x1 + + + B_0x2 + SYNC divided by 4 + 0x2 + + + B_0x3 + SYNC divided by 8 + 0x3 + + + B_0x4 + SYNC divided by 16 + 0x4 + + + B_0x5 + SYNC divided by 32 + 0x5 + + + B_0x6 + SYNC divided by 64 + 0x6 + + + B_0x7 + SYNC divided by 128 + 0x7 + + + + + SYNCSRC + SYNC signal source selection +These bits are set and cleared by software to select the SYNC signal source (see Table122): +Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF is not generated by the host. No SYNC signal is therefore provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs must be used as SYNC signal. + 28 + 2 + read-write + + + B_0x0 + crs_sync_in_1 selected as SYNC signal source + 0x0 + + + B_0x1 + crs_sync_in_2 selected as SYNC signal source + 0x1 + + + B_0x2 + crs_sync_in_3 selected as SYNC signal source + 0x2 + + + B_0x3 + crs_sync_in_4 selected as SYNC signal source + 0x3 + + + + + SYNCPOL + SYNC polarity selection +This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + read-write + + + B_0x0 + SYNC active on rising edge (default) + 0x0 + + + B_0x1 + SYNC active on falling edge + 0x1 + + + + + + + CRS_ISR + CRS_ISR + CRS interrupt and status register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYNCOKF + SYNC event OK flag +This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + read-only + + + B_0x0 + No SYNC event OK signaled + 0x0 + + + B_0x1 + SYNC event OK signaled + 0x1 + + + + + SYNCWARNF + SYNC warning flag +This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + read-only + + + B_0x0 + No SYNC warning signaled + 0x0 + + + B_0x1 + SYNC warning signaled + 0x1 + + + + + ERRF + Error flag +This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + read-only + + + B_0x0 + No synchronization or trimming error signaled + 0x0 + + + B_0x1 + Synchronization or trimming error signaled + 0x1 + + + + + ESYNCF + Expected SYNC flag +This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + read-only + + + B_0x0 + No expected SYNC signaled + 0x0 + + + B_0x1 + Expected SYNC signaled + 0x1 + + + + + SYNCERR + SYNC error +This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action has to be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + read-only + + + B_0x0 + No SYNC error signaled + 0x0 + + + B_0x1 + SYNC error signaled + 0x1 + + + + + SYNCMISS + SYNC missed +This flag is set by hardware when the frequency error counter reaches value FELIM * 128 and no SYNC is detected, meaning either that a SYNC pulse was missed, or the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, hence some other action must be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC), and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + read-only + + + B_0x0 + No SYNC missed error signaled + 0x0 + + + B_0x1 + SYNC missed error signaled + 0x1 + + + + + TRIMOVF + Trimming overflow or underflow +This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + read-only + + + B_0x0 + No trimming error signaled + 0x0 + + + B_0x1 + Trimming error signaled + 0x1 + + + + + FEDIR + Frequency error direction +FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + read-only + + + B_0x0 + Up-counting direction, the actual frequency is above the target + 0x0 + + + B_0x1 + Down-counting direction, the actual frequency is below the target + 0x1 + + + + + FECAP + Frequency error capture +FECAP is the frequency error counter value latched in the time of the last SYNC event. +Refer to Section15.4.4 for more details about FECAP usage. + 16 + 16 + read-only + + + + + CRS_ICR + CRS_ICR + CRS interrupt flag clear register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYNCOKC + SYNC event OK clear flag +Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + read-write + + + SYNCWARNC + SYNC warning clear flag +Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + read-write + + + ERRC + Error clear flag +Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + read-write + + + ESYNCC + Expected SYNC clear flag +Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + read-write + + + + + + + DAC + DAC address block description + DAC + 0x40007400 + + 0x0 + 0x50 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN1 + DAC channel1 enable +This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + read-write + + + B_0x0 + DAC channel1 disabled + 0x0 + + + B_0x1 + DAC channel1 enabled + 0x1 + + + + + TEN1 + DAC channel1 trigger enable +This bit is set and cleared by software to enable/disable DAC channel1 trigger. +Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle. + 1 + 1 + read-write + + + B_0x0 + DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register + 0x0 + + + B_0x1 + DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register + 0x1 + + + + + TSEL1 + DAC channel1 trigger selection +These bits select the external event used to trigger DAC channel1 +... +Refer to the trigger selection tables in Section114.4.2: DAC pins and internal signals for details on trigger configuration and mapping. +Note: Only used if bit TEN11=11 (DAC channel1 trigger enabled). + 2 + 4 + read-write + + + B_0x0 + SWTRIG1 + 0x0 + + + B_0x1 + dac_ch1_trg1 + 0x1 + + + B_0x2 + dac_ch1_trg2 + 0x2 + + + B_0xF + dac_ch1_trg15 + 0xF + + + + + WAVE1 + DAC channel1 noise/triangle wave generation enable +These bits are set and cleared by software. +1x: Triangle wave generation enabled +Only used if bit TEN11=11 (DAC channel1 trigger enabled). + 6 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP1 + DAC channel1 mask/amplitude selector + 8 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN1 + DAC channel1 DMA enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + DAC channel1 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel1 DMA mode enabled + 0x1 + + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + DAC channel1 DMA Underrun Interrupt disabled + 0x0 + + + B_0x1 + DAC channel1 DMA Underrun Interrupt enabled + 0x1 + + + + + CEN1 + DAC channel1 calibration enable +This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN11=10 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + read-write + + + B_0x0 + DAC channel1 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel1 in calibration mode + 0x1 + + + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWTRIG1 + DAC channel1 software trigger +This bit is set by software to trigger the DAC in software trigger mode. +Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data +These bits are written by software. They specify 12-bit data for DAC channel1. + 0 + 12 + read-write + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data +These bits are written by software. +They specify 12-bit data for DAC channel1. + 4 + 12 + read-write + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data +These bits are written by software. They specify 8-bit data for DAC channel1. + 0 + 8 + read-write + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DOR + DAC channel1 data output +These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + read-only + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAUDR1 + DAC channel1 DMA underrun flag +This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel1 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) + 0x1 + + + + + CAL_FLAG1 + DAC channel1 calibration offset status +This bit is set and cleared by hardware + 14 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST1 + DAC channel1 busy writing sample time flag +This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization). + 15 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written + 0x1 + + + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + OTRIM1 + DAC channel1 offset trimming value + 0 + 5 + read-write + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MODE1 + DAC channel1 mode +These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN11=10 and bit CEN11=10 in the DAC_CR register). If EN11=11 or CEN11=11 the write operation is ignored. +They can be set and cleared by software to select the DAC channel1 mode: +DAC channel1 in Normal mode +DAC channel1 in sample & hold mode +Note: This register can be modified only when EN11=10. + 0 + 3 + read-write + + + B_0x0 + DAC channel1 is connected to external pin with Buffer enabled + 0x0 + + + B_0x1 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled + 0x1 + + + B_0x2 + DAC channel1 is connected to external pin with Buffer disabled + 0x2 + + + B_0x3 + DAC channel1 is connected to on chip peripherals with Buffer disabled + 0x3 + + + B_0x4 + DAC channel1 is connected to external pin with Buffer enabled + 0x4 + + + B_0x5 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled + 0x5 + + + B_0x6 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled + 0x6 + + + B_0x7 + DAC channel1 is connected to on chip peripherals with Buffer disabled + 0x7 + + + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC channel1 sample and hold sample time register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE1 + DAC channel1 sample time (only valid in Sample and hold mode) +These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST11=11, the write operation is ignored. + 0 + 10 + read-write + + + + + DAC_SHHR + DAC_SHHR + DAC sample and hold time register + 0x48 + 0x20 + 0x00010001 + 0xFFFFFFFF + + + THOLD1 + DAC channel1 hold time (only valid in Sample and hold mode) +Hold time1=1(THOLD[9:0]) x LSI clock period +Note: This register can be modified only when EN11=10. + 0 + 10 + read-write + + + + + DAC_SHRR + DAC_SHRR + DAC sample and hold refresh time register + 0x4C + 0x20 + 0x00010001 + 0xFFFFFFFF + + + TREFRESH1 + DAC channel1 refresh time (only valid in Sample and hold mode) +Refresh time1=1(TREFRESH[7:0]) x LSI clock period +Note: This register can be modified only when EN11=10. + 0 + 8 + read-write + + + + + + + DBGMCU + DBGMCU register block + DBGMCU + 0x40015800 + + 0x0 + 0x1000 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + DBGMCU device ID code register + 0x00 + 0x20 + 0x00006000 + 0x0000F000 + + + DEV_ID + Device identifier +This field indicates the device ID. + 0 + 12 + read-only + + + B_0x459 + STM32U031xx + 0x459 + + + B_0x489 + STM32U073/083xx + 0x489 + + + + + REV_ID + Revision identifier +This field indicates the revision of the device. + 16 + 16 + read-only + + + B_0x1000 + Revision A for STM32U031/73/83xx + 0x1000 + + + + + + + DBGMCU_CR + DBGMCU_CR + DBGMCU configuration register + 0x00000004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_STOP + Debug Stop mode +Debug options in Stop mode. + 1 + 1 + read-write + + + B_0x0 + All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. + 0x0 + + + B_0x1 + FCLK and HCLK running, derived from the internal RC oscillator remaining active. If SysTick is enabled, it may generate periodic interrupt and wake up events.Upon Stop mode exit, the software must re-establish the desired clock configuration. + 0x1 + + + + + DBG_STANDBY + Debug Standby and Shutdown modes +Debug options in Standby or Shutdown mode. + 2 + 1 + read-write + + + B_0x0 + Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby) + 0x0 + + + B_0x1 + Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset. + 0x1 + + + + + + + DBGMCU_APB1FZR + DBGMCU_APB1FZR + DBGMCU APB1 freeze register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM2_STOP + TIM2 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. TIM2 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM2 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM3_STOP + TIM3 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. TIM3 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM3 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM4_STOP + TIM4 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. TIM4 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM34 is frozen while CPU is in debug mode + 0x1 + + + + + DBG_TIM6_STOP + TIM6 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. TIM6 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM6 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM7_STOP + TIM7 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. TIM7 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM7 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_RTC_STOP + RTC stop in debug + 10 + 1 + read-write + + + B_0x0 + normal operation. RTC counter continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. RTC counter is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_WWDG_STOP + WWDG stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. WWDG continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. WWDG is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_IWDG_STOP + IWDG stop in debug + 12 + 1 + read-write + + + B_0x0 + normal operation. IWDG continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. IWDG is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_I2C3_STOP + I2C3 SMBUS timeout stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. I2C3 SMBUS timeout continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C3 SMBUS timeout is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM2_STOP + LPTIM2 stop in debug + 30 + 1 + read-write + + + B_0x0 + normal operation. LPTIM2 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM2 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM1_STOP + LPTIM1 stop in debug + 31 + 1 + read-write + + + B_0x0 + normal operation. LPTIM1 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM1 is frozen while CPU is in debug mode. + 0x1 + + + + + + + DBGMCU_APB2FZR + DBGMCU_APB2FZR + DBG APB2 freeze register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM1_STOP + TIM1 stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. TIM1 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM1 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM14_STOP + TIM14 stop in debug + 15 + 1 + read-write + + + B_0x0 + normal operation. TIM14 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM14 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM15_STOP + TIM15 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. TIM15 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM15 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM16_STOP + TIM16 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. TIM16 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM16 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM3_STOP + LPTIM3 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. LPTIM3 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM3 is frozen while CPU is in debug mode. + 0x1 + + + + + + + DBGMCU_SR + DBGMCU_SR + DBGMCU status register + 0xFC + 0x20 + 0x00010003 + 0xFFFFFFFF + + + AP1_PRESENT + Identifies whether access port AP1 is present in device + 0 + 1 + read-only + + + B_0x1 + AP1 present + 0x1 + + + + + AP0_PRESENT + Identifies whether access port AP0 is present in device + 1 + 1 + read-only + + + B_0x1 + AP0 present + 0x1 + + + + + AP1_ENABLED + Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + 16 + 1 + read-only + + + B_0x0 + AP1 locked + 0x0 + + + B_0x1 + AP1 enabled + 0x1 + + + + + AP0_ENABLED + Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + 17 + 1 + read-only + + + B_0x0 + AP0 locked + 0x0 + + + B_0x1 + AP0 enabled + 0x1 + + + + + + + DBGMCU_DBG_AUTH_HOST + DBGMCU_DBG_AUTH_HOST + DBGMCU debug authentication mailbox host register + 0x100 + 0x20 + 0x00000000 + 0x00000000 + + + MESSAGE + Debug host to device mailbox message. +During debug authentication the debug host communicates with the device via this register. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_DEVICE + DBGMCU_DBG_AUTH_DEVICE + DBGMCU debug authentication mailbox device register + 0x104 + 0x20 + 0x00000000 + 0x00000000 + + + MESSAGE + Device to debug host mailbox message. +During debug authentication the device communicates with the debug host via this register. + 0 + 32 + read-only + + + + + DBGMCU_PIDR4 + DBGMCU_PIDR4 + DBGMCU CoreSight peripheral identity register 4 + 0xFD0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JEP106CON + JEP106 continuation code + 0 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + SIZE + register file size + 4 + 4 + read-only + + + B_0x0 + The register file occupies a single 4-Kbyte region. + 0x0 + + + + + + + DBGMCU_PIDR0 + DBGMCU_PIDR0 + DBGMCU CoreSight peripheral identity register 0 + 0xFE0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [7:0] + 0 + 8 + read-only + + + B_0x00 + DBGMCU part number + 0x00 + + + + + + + DBGMCU_PIDR1 + DBGMCU_PIDR1 + DBGMCU CoreSight peripheral identity register 1 + 0xFE4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [11:8] + 0 + 4 + read-only + + + B_0x0 + DBGMCU part number + 0x0 + + + + + JEP106ID + JEP106 identity code bits [3:0] + 4 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + + + DBGMCU_PIDR2 + DBGMCU_PIDR2 + DBGMCU CoreSight peripheral identity register 2 + 0xFE8 + 0x20 + 0x0000000A + 0xFFFFFFFF + + + JEP106ID + JEP106 identity code bits [6:4] + 0 + 3 + read-only + + + B_0x2 + STMicroelectronics JEDEC code + 0x2 + + + + + JEDEC + JEDEC assigned value + 3 + 1 + read-only + + + B_0x1 + designer identification specified by JEDEC + 0x1 + + + + + REVISION + component revision number + 4 + 4 + read-only + + + B_0x0 + r0p0 + 0x0 + + + + + + + DBGMCU_PIDR3 + DBGMCU_PIDR3 + DBGMCU CoreSight peripheral identity register 3 + 0xFEC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified + 0 + 4 + read-only + + + B_0x0 + no customer modifications + 0x0 + + + + + REVAND + metal fix version + 4 + 4 + read-only + + + B_0x0 + no metal fix + 0x0 + + + + + + + DBGMCU_CIDR0 + DBGMCU_CIDR0 + DBGMCU CoreSight component identity register 0 + 0xFF0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PREAMBLE + component identification bits [7:0] + 0 + 8 + read-only + + + B_0x0D + common identification value + 0x0D + + + + + + + DBGMCU_CIDR1 + DBGMCU_CIDR1 + DBGMCU CoreSight component identity register 1 + 0xFF4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [11:8] + 0 + 4 + read-only + + + B_0x0 + common identification value + 0x0 + + + + + CLASS + component identification bits [15:12] - component class + 4 + 4 + read-only + + + B_0xF + Non-CoreSight component + 0xF + + + + + + + DBGMCU_CIDR2 + DBGMCU_CIDR2 + DBGMCU CoreSight component identity register 2 + 0xFF8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [23:16] + 0 + 8 + read-only + + + B_0x05 + common identification value + 0x05 + + + + + + + DBGMCU_CIDR3 + DBGMCU_CIDR3 + DBGMCU CoreSight component identity register 3 + 0xFFC + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [31:24] + 0 + 8 + read-only + + + B_0xB1 + common identification value + 0xB1 + + + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x40020800 + + 0x0 + 0x148 + registers + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C5CR + DMAMUX_C5CR + DMAMUX request line multiplexer channel 5 configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C6CR + DMAMUX_C6CR + DMAMUX request line multiplexer channel 6 configuration register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C7CR + DMAMUX_C7CR + DMAMUX request line multiplexer channel 7 configuration register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C8CR + DMAMUX_C8CR + DMAMUX request line multiplexer channel 8 configuration register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C9CR + DMAMUX_C9CR + DMAMUX request line multiplexer channel 9 configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C10CR + DMAMUX_C10CR + DMAMUX request line multiplexer channel 10 configuration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C11CR + DMAMUX_C11CR + DMAMUX request line multiplexer channel 11 configuration register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SOF0 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 0 + 1 + read-only + + + SOF1 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 1 + 1 + read-only + + + SOF2 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 2 + 1 + read-only + + + SOF3 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 3 + 1 + read-only + + + SOF4 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 4 + 1 + read-only + + + SOF5 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 5 + 1 + read-only + + + SOF6 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 6 + 1 + read-only + + + SOF7 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 7 + 1 + read-only + + + SOF8 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 8 + 1 + read-only + + + SOF9 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 9 + 1 + read-only + + + SOF10 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 10 + 1 + read-only + + + SOF11 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 11 + 1 + read-only + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSOF0 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 0 + 1 + write-only + + + CSOF1 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 1 + 1 + write-only + + + CSOF2 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 2 + 1 + write-only + + + CSOF3 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 3 + 1 + write-only + + + CSOF4 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 4 + 1 + write-only + + + CSOF5 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 5 + 1 + write-only + + + CSOF6 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 6 + 1 + write-only + + + CSOF7 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 7 + 1 + write-only + + + CSOF8 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 8 + 1 + write-only + + + CSOF9 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 9 + 1 + write-only + + + CSOF10 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 10 + 1 + write-only + + + CSOF11 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 11 + 1 + write-only + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OF0 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 0 + 1 + read-only + + + OF1 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 1 + 1 + read-only + + + OF2 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 2 + 1 + read-only + + + OF3 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 3 + 1 + read-only + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COF0 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 0 + 1 + write-only + + + COF1 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 1 + 1 + write-only + + + COF2 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 2 + 1 + write-only + + + COF3 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 3 + 1 + write-only + + + + + + + DMA1 + DMA register bank + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CHannel1 + DMA1 channel 1 interrupt + 9 + + + DMA1_Channel2_3 + DMA1 channel 2 and 3 interrupts + 10 + + + DMA1_Channel4_5_6_7 + DMA1 channel 4, 5, 6, 7, DMAMUX, DMA2 channel 1, 2, 3, 4, 5 interrupts + 11 + + + + DMA_ISR + DMA_ISR + DMA interrupt status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GIF1 + Global interrupt flag for channel 1 + 0 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF1 + Transfer complete (TC) flag for channel 1 + 1 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF1 + Half transfer (HT) flag for channel 1 + 2 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF1 + Transfer error (TE) flag for channel 1 + 3 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF2 + Global interrupt flag for channel 2 + 4 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF2 + Transfer complete (TC) flag for channel 2 + 5 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF2 + Half transfer (HT) flag for channel 2 + 6 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF2 + Transfer error (TE) flag for channel 2 + 7 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF3 + Global interrupt flag for channel 3 + 8 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF3 + Transfer complete (TC) flag for channel 3 + 9 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF3 + Half transfer (HT) flag for channel 3 + 10 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF3 + Transfer error (TE) flag for channel 3 + 11 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF4 + global interrupt flag for channel 4 + 12 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF4 + Transfer complete (TC) flag for channel 4 + 13 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF4 + Half transfer (HT) flag for channel 4 + 14 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF4 + Transfer error (TE) flag for channel 4 + 15 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF5 + global interrupt flag for channel 5 + 16 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF5 + Transfer complete (TC) flag for channel 5 + 17 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF5 + Half transfer (HT) flag for channel 5 + 18 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF5 + Transfer error (TE) flag for channel 5 + 19 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF6 + Global interrupt flag for channel 6 + 20 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF6 + Transfer complete (TC) flag for channel 6 + 21 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF6 + Half transfer (HT) flag for channel 6 + 22 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF6 + Transfer error (TE) flag for channel 6 + 23 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF7 + Global interrupt flag for channel 7 + 24 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF7 + Transfer complete (TC) flag for channel 7 + 25 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF7 + Half transfer (HT) flag for channel 7 + 26 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF7 + Transfer error (TE) flag for channel 7 + 27 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + + + DMA_IFCR + DMA_IFCR + DMA interrupt flag clear register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CGIF1 + Global interrupt flag clear for channel 1 + 0 + 1 + write-only + + + CTCIF1 + Transfer complete flag clear for channel 1 + 1 + 1 + write-only + + + CHTIF1 + Half transfer flag clear for channel 1 + 2 + 1 + write-only + + + CTEIF1 + Transfer error flag clear for channel 1 + 3 + 1 + write-only + + + CGIF2 + Global interrupt flag clear for channel 2 + 4 + 1 + write-only + + + CTCIF2 + Transfer complete flag clear for channel 2 + 5 + 1 + write-only + + + CHTIF2 + Half transfer flag clear for channel 2 + 6 + 1 + write-only + + + CTEIF2 + Transfer error flag clear for channel 2 + 7 + 1 + write-only + + + CGIF3 + Global interrupt flag clear for channel 3 + 8 + 1 + write-only + + + CTCIF3 + Transfer complete flag clear for channel 3 + 9 + 1 + write-only + + + CHTIF3 + Half transfer flag clear for channel 3 + 10 + 1 + write-only + + + CTEIF3 + Transfer error flag clear for channel 3 + 11 + 1 + write-only + + + CGIF4 + Global interrupt flag clear for channel 4 + 12 + 1 + write-only + + + CTCIF4 + Transfer complete flag clear for channel 4 + 13 + 1 + write-only + + + CHTIF4 + Half transfer flag clear for channel 4 + 14 + 1 + write-only + + + CTEIF4 + Transfer error flag clear for channel 4 + 15 + 1 + write-only + + + CGIF5 + Global interrupt flag clear for channel 5 + 16 + 1 + write-only + + + CTCIF5 + Transfer complete flag clear for channel 5 + 17 + 1 + write-only + + + CHTIF5 + Half transfer flag clear for channel 5 + 18 + 1 + write-only + + + CTEIF5 + Transfer error flag clear for channel 5 + 19 + 1 + write-only + + + CGIF6 + Global interrupt flag clear for channel 6 + 20 + 1 + write-only + + + CTCIF6 + Transfer complete flag clear for channel 6 + 21 + 1 + write-only + + + CHTIF6 + Half transfer flag clear for channel 6 + 22 + 1 + write-only + + + CTEIF6 + Transfer error flag clear for channel 6 + 23 + 1 + write-only + + + CGIF7 + Global interrupt flag clear for channel 7 + 24 + 1 + write-only + + + CTCIF7 + Transfer complete flag clear for channel 7 + 25 + 1 + write-only + + + CHTIF7 + Half transfer flag clear for channel 7 + 26 + 1 + write-only + + + CTEIF7 + Transfer error flag clear for channel 7 + 27 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA channel 1 number of data to transfer register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA channel 1 peripheral address register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA channel 1 memory address register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA channel 2 number of data to transfer register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA channel 2 peripheral address register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA channel 2 memory address register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA channel 3 peripheral address register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA channel 3 memory address register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA channel 4 configuration register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA channel 4 peripheral address register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA channel 4 memory address register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA channel 5 configuration register + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA channel 5 peripheral address register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA channel 5 memory address register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA channel 6 configuration register + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA channel 6 peripheral address register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA channel 6 memory address register + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA channel 7 configuration register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA channel 7 peripheral address register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA channel 7 memory address register + 0x8C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + + + DMA2 + 0x40020400 + + + EXTI + EXTI register block + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) + 1 + + + EXTI0_1 + EXTI lines 0 and 1 interrupt + 5 + + + EXTI2_3 + EXTI lines 2 and 3 interrupt + 6 + + + EXTI4_15 + EXTI lines 4 to 15 interrupt + 7 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT16 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT17 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT18 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT19 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT20 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT21 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register 1 + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT16 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT17 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT18 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT19 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT20 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT21 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register 1 + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI1 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI2 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI3 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI4 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI5 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI6 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI7 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI8 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI9 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI10 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI11 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI12 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI13 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI14 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI15 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI16 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI17 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI18 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI19 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI20 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI21 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register 1 + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF16 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF17 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF18 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF19 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF20 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF21 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register 1 + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF16 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF17 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF18 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF19 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF20 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF21 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register 1 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI0 GPIO port selection +These bits are written by software to select the source input for EXTI0 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[0] pin + 0x00 + + + B_0x01 + PB[0] pin + 0x01 + + + B_0x02 + PC[0] pin + 0x02 + + + B_0x03 + PD[0] pin + 0x03 + + + B_0x05 + PF[0] pin + 0x05 + + + + + EXTI1 + EXTI1 GPIO port selection +These bits are written by software to select the source input for EXTI1 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[1] pin + 0x00 + + + B_0x01 + PB[1] pin + 0x01 + + + B_0x02 + PC[1] pin + 0x02 + + + B_0x03 + PD[1] pin + 0x03 + + + B_0x05 + PF[1] pin + 0x05 + + + + + EXTI2 + EXTI2 GPIO port selection +These bits are written by software to select the source input for EXTI2 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[2] pin + 0x00 + + + B_0x01 + PB[2] pin + 0x01 + + + B_0x02 + PC[2] pin + 0x02 + + + B_0x03 + PD[2] pin + 0x03 + + + B_0x05 + PF[2] pin + 0x05 + + + + + EXTI3 + EXTI3 GPIO port selection +These bits are written by software to select the source input for EXTI3 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[3] pin + 0x00 + + + B_0x01 + PB[3] pin + 0x01 + + + B_0x02 + PC[3] pin + 0x02 + + + B_0x03 + PD[3] pin + 0x03 + + + B_0x05 + PF[3] pin + 0x05 + + + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register 2 + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI4 GPIO port selection +These bits are written by software to select the source input for EXTI4 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[4] pin + 0x00 + + + B_0x01 + PB[4] pin + 0x01 + + + B_0x02 + PC[4] pin + 0x02 + + + B_0x03 + PD[4] pin + 0x03 + + + B_0x05 + PF[4] pin + 0x05 + + + + + EXTI5 + EXTI5 GPIO port selection +These bits are written by software to select the source input for EXTI5 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[5] pin + 0x00 + + + B_0x01 + PB[5] pin + 0x01 + + + B_0x02 + PC[5] pin + 0x02 + + + B_0x03 + PD[5] pin + 0x03 + + + B_0x05 + PF[5] pin + 0x05 + + + + + EXTI6 + EXTI6 GPIO port selection +These bits are written by software to select the source input for EXTI6 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[6] pin + 0x00 + + + B_0x01 + PB[6] pin + 0x01 + + + B_0x02 + PC[6] pin + 0x02 + + + B_0x03 + PD[6] pin + 0x03 + + + B_0x05 + PF[6] pin + 0x05 + + + + + EXTI7 + EXTI7 GPIO port selection +These bits are written by software to select the source input for EXTI7 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[7] pin + 0x00 + + + B_0x01 + PB[7] pin + 0x01 + + + B_0x02 + PC[7] pin + 0x02 + + + B_0x03 + PD[7] pin + 0x03 + + + B_0x05 + PF[7] pin + 0x05 + + + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register 3 + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTI8 GPIO port selection +These bits are written by software to select the source input for EXTI8 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[8] pin + 0x00 + + + B_0x01 + PB[8] pin + 0x01 + + + B_0x02 + PC[8] pin + 0x02 + + + B_0x03 + PD[8] pin + 0x03 + + + B_0x05 + PF[8] pin + 0x05 + + + + + EXTI9 + EXTI9 GPIO port selection +These bits are written by software to select the source input for EXTI9 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[9] pin + 0x00 + + + B_0x01 + PB[9] pin + 0x01 + + + B_0x02 + PC[9] pin + 0x02 + + + B_0x03 + PD[9] pin + 0x03 + + + B_0x05 + PF[9] pin + 0x05 + + + + + EXTI10 + EXTI10 GPIO port selection +These bits are written by software to select the source input for EXTI10 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[10] pin + 0x00 + + + B_0x01 + PB[10] pin + 0x01 + + + B_0x02 + PC[10] pin + 0x02 + + + B_0x03 + PD[10] pin + 0x03 + + + B_0x05 + PF[10] pin + 0x05 + + + + + EXTI11 + EXTI11 GPIO port selection +These bits are written by software to select the source input for EXTI11 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[11] pin + 0x00 + + + B_0x01 + PB[11] pin + 0x01 + + + B_0x02 + PC[11] pin + 0x02 + + + B_0x03 + PD[11] pin + 0x03 + + + B_0x05 + PF[11] pin + 0x05 + + + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register 4 + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTI12 GPIO port selection +These bits are written by software to select the source input for EXTI12 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[12] pin + 0x00 + + + B_0x01 + PB[12] pin + 0x01 + + + B_0x02 + PC[12] pin + 0x02 + + + B_0x03 + PD[12] pin + 0x03 + + + B_0x05 + PF[12] pin + 0x05 + + + + + EXTI13 + EXTI13 GPIO port selection +These bits are written by software to select the source input for EXTI13 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[13] pin + 0x00 + + + B_0x01 + PB[13] pin + 0x01 + + + B_0x02 + PC[13] pin + 0x02 + + + B_0x03 + PD[13] pin + 0x03 + + + B_0x05 + PF[13] pin + 0x05 + + + + + EXTI14 + EXTI14 GPIO port selection +These bits are written by software to select the source input for EXTI14 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[14] pin + 0x00 + + + B_0x01 + PB[14] pin + 0x01 + + + B_0x02 + PC[14] pin + 0x02 + + + B_0x03 + PD[14] pin + 0x03 + + + B_0x05 + PF[14] pin + 0x05 + + + + + EXTI15 + EXTI15 GPIO port selection +These bits are written by software to select the source input for EXTI15 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[15] pin + 0x00 + + + B_0x01 + PB[15] pin + 0x01 + + + B_0x02 + PC[15] pin + 0x02 + + + B_0x03 + PD[15] pin + 0x03 + + + B_0x05 + PF[15] pin + 0x05 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wake-up with interrupt mask register + 0x080 + 0x20 + 0xFFF80000 + 0xFFFFFFFF + + + IM0 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM1 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM2 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM3 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM4 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM5 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM6 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM7 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM8 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM9 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM10 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM11 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM12 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM13 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM14 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM15 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM16 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM17 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM18 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM19 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM20 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM21 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM22 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 22 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM23 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 23 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM24 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 24 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM25 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 25 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM26 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 26 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM27 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 27 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM28 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 28 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM29 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 29 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM30 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 30 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM31 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 31 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wake-up with event mask register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM1 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM2 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM3 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM4 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM5 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM6 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM7 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM8 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM9 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM10 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM11 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM12 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM13 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM14 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM15 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM16 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM17 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM18 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM19 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM20 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM21 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM22 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 22 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM23 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 23 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM24 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 24 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM25 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 25 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM26 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 26 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM27 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 27 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM28 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 28 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM29 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 29 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM30 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 30 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM31 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 31 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + EXTI_IMR2 + EXTI_IMR2 + EXTI CPU wake-up with interrupt mask register + 0x090 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + IM32 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM33 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM34 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM35 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM36 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM37 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wake-up with event mask register + 0x094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM32 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM33 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM34 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM35 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM36 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM37 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + + + FLASH + Mamba FLASH register block + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global interrupt + 3 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x000 + 0x20 + 0x00040600 + 0xFFFFFFFF + + + LATENCY + Flash memory access latency +The value in this bitfield represents the number of CPU wait states when accessing the flash memory. +Other: Reserved +A new write into the bitfield becomes effective when it returns the same value upon read. + 0 + 3 + read-write + + + B_0x0 + Zero wait states + 0x0 + + + B_0x1 + One wait state + 0x1 + + + + + PRFTEN + CPU Prefetch enable + 8 + 1 + read-write + + + B_0x0 + CPU Prefetch disabled + 0x0 + + + B_0x1 + CPU Prefetch enabled + 0x1 + + + + + ICEN + CPU Instruction cache enable + 9 + 1 + read-write + + + B_0x0 + CPU Instruction cache is disabled + 0x0 + + + B_0x1 + CPU Instruction cache is enabled + 0x1 + + + + + ICRST + CPU Instruction cache reset +This bit can be written only when the instruction cache is disabled. + 11 + 1 + read-write + + + B_0x0 + CPU Instruction cache is not reset + 0x0 + + + B_0x1 + CPU Instruction cache is reset + 0x1 + + + + + EMPTY + Main flash memory area empty +This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. +The bit can be set and reset by software. + 16 + 1 + read-write + + + B_0x0 + Main flash memory area programmed + 0x0 + + + B_0x1 + Main flash memory area empty + 0x1 + + + + + DBG_SWEN + Debug access software enable +Software may use this bit to enable/disable the debugger read access. + 18 + 1 + read-write + + + B_0x0 + Debugger disabled + 0x0 + + + B_0x1 + Debugger enabled + 0x1 + + + + + + + FLASH_KEYR + FLASH_KEYR + FLASH key register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + FLASH key +The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: +KEY1: 0x4567 0123 +KEY2: 0xCDEF 89AB + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + Option byte key +The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: +KEY1: 0x0819 2A3B +KEY2: 0x4C5D 6E7F + 0 + 32 + write-only + + + + + FLASH_SR + FLASH_SR + FLASH status register + 0x010 + 0x20 + 0x00000000 + 0xFFF0FFFF + + + EOP + End of operation +Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. +This bit is set only if the end of operation interrupts are enabled (EOPIE=1). +Cleared by writing 1. + 0 + 1 + read-write + + + OPERR + Operation error +Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. +This bit is set only if error interrupts are enabled (ERRIE=1). +Cleared by writing 1. + 1 + 1 + read-write + + + PROGERR + Programming error +Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. +Cleared by writing 1. + 3 + 1 + read-write + + + WRPERR + Write protection error +Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. +Cleared by writing 1. + 4 + 1 + read-write + + + PGAERR + Programming alignment error +Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. +Cleared by writing 1. + 5 + 1 + read-write + + + SIZERR + Size error +Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). +Cleared by writing 1. + 6 + 1 + read-write + + + PGSERR + Programming sequence error +Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. +Cleared by writing 1. + 7 + 1 + read-write + + + MISSERR + Fast programming data miss error +In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. +Cleared by writing 1. + 8 + 1 + read-write + + + FASTERR + Fast programming error +Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. +Cleared by writing 1. + 9 + 1 + read-write + + + RDERR + PCROP read error +Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. +Cleared by writing 1. + 14 + 1 + read-write + + + OPTVERR + Option and Engineering bits loading validity error + 15 + 1 + read-write + + + BSY1 + Busy +This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. + 16 + 1 + read-only + + + CFGBSY + Programming or erase configuration busy. +This flag is set and cleared by hardware. It is set when the first word is sent for program or when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared when the flash memory program or erase operation completes or ends with an error. +When set, launching any other operation through the FLASH control register (FLASH_CR) is impossible, and must be postponed (a programming or erase operation is ongoing). +When cleared, the program and erase settings in the FLASH control register (FLASH_CR) can be modified. + 18 + 1 + read-only + + + + + FLASH_CR + FLASH_CR + FLASH control register + 0x014 + 0x20 + 0xC0000000 + 0xFFFFFFFF + + + PG + Flash memory programming enable + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PER + Page erase enable + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MER1 + Mass erase +When set, this bit triggers the mass erase, that is, all user pages. + 2 + 1 + read-write + + + PNB + Page number selection +These bits select the page to erase: +... +Note: Values corresponding to addresses outside the main memory are not allowed. + 3 + 7 + read-write + + + B_0x0 + page 0 + 0x0 + + + B_0x1 + page 1 + 0x1 + + + B_0xF + page 15 + 0xF + + + + + STRT + Start erase operation +This bit triggers an erase operation when set. +This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. + 16 + 1 + read-write + + + OPTSTRT + Start of modification of option bytes +This bit triggers an options operation when set. +This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. + 17 + 1 + read-write + + + FSTPG + Fast programming enable + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + EOPIE + End-of-operation interrupt enable +This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ERRIE + Error interrupt enable +This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RDERRIE + PCROP read error interrupt enable +This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OBL_LAUNCH + Option byte load launch +When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. +The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. + 27 + 1 + read-write + + + SEC_PROT + Securable memory area protection enable +This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. +This bit is possible to set only by software and to clear only through a system reset. + 28 + 1 + read-write + + + B_0x0 + Disable (securable area accessible) + 0x0 + + + B_0x1 + Enable (securable area not accessible) + 0x1 + + + + + OPTLOCK + Options Lock +This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. +In case of an unsuccessful unlock operation, this bit remains set until the next reset. + 30 + 1 + read-write + + + LOCK + FLASH_CR Lock +This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. +In case of an unsuccessful unlock operation, this bit remains set until the next system reset. + 31 + 1 + read-write + + + + + FLASH_ECCR + FLASH_ECCR + FLASH ECC register + 0x018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC fail double-word address offset + In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory. + 0 + 14 + read-only + + + SYSF_ECC + System Flash memory ECC fail +This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. + 20 + 1 + read-only + + + ECCCIE + ECC correction interrupt enable + 24 + 1 + read-write + + + B_0x0 + ECCC interrupt disabled + 0x0 + + + B_0x1 + ECCC interrupt enabled + 0x1 + + + + + ECCC + ECC correction +Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. +Cleared by writing 1. + 30 + 1 + read-write + + + ECCD + ECC detection +Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. +Cleared by writing 1. + 31 + 1 + read-write + + + + + FLASH_OPTR + FLASH_OPTR + FLASH option register + 0x020 + 0x20 + 0x00000000 + 0x00000000 + + + RDP + Read protection level +Other: Level 1, memories read protection active + 0 + 8 + read-write + + + B_0xAA + Level 0, read protection not active + 0xAA + + + B_0xCC + Level 2, chip read protection active + 0xCC + + + + + BORR_LEV + BOR reset level + 8 + 3 + read-write + + + B_0x0 + BOR rising level 1 with threshold around 2.1 V + 0x0 + + + B_0x1 + BOR rising level 2 with threshold around 2.3 V + 0x1 + + + B_0x2 + BOR rising level 3 with threshold around 2.6 V + 0x2 + + + B_0x3 + BOR rising level 4 with threshold around 2.9 V + 0x3 + + + + + NRST_STOP + Reset generated when entering Stop mode + 13 + 1 + read-write + + + B_0x0 + Reset generated when entering the Stop mode + 0x0 + + + B_0x1 + No reset generated when entering the Stop mode + 0x1 + + + + + NRST_STDBY + Reset generated when entering Standby mode + 14 + 1 + read-write + + + B_0x0 + Reset generated when entering the Standby mode + 0x0 + + + B_0x1 + No reset generate when entering the Standby mode + 0x1 + + + + + NRST_SHDW + Reset generated when entering Shutdown mode + 15 + 1 + read-write + + + B_0x0 + Reset generated when entering the Shutdown mode + 0x0 + + + B_0x1 + No reset generated when entering the Shutdown mode + 0x1 + + + + + IWDG_SW + Independent watchdog selection + 16 + 1 + read-write + + + B_0x0 + Hardware independent watchdog + 0x0 + + + B_0x1 + Software independent watchdog + 0x1 + + + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Stop mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Stop mode + 0x1 + + + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Standby mode + 0x1 + + + + + WWDG_SW + Window watchdog selection + 19 + 1 + read-write + + + B_0x0 + Hardware window watchdog + 0x0 + + + B_0x1 + Software window watchdog + 0x1 + + + + + BDRST + Backup domain reset + 21 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + RAM_PARITY_CHECK + SRAM parity check control enable/disable + 22 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + BKPSRAM_HW_ERASE_DISABLE + Backup SRAM erase prevention + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + NBOOT_SEL + BOOT0 signal source selection +This option bit defines the source of the BOOT0 signal. + 24 + 1 + read-write + + + B_0x0 + BOOT0 pin (legacy mode) + 0x0 + + + B_0x1 + NBOOT0 option bit + 0x1 + + + + + NBOOT1 + Boot configuration +Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration. + 25 + 1 + read-write + + + NBOOT0 + NBOOT0 option bit + 26 + 1 + read-write + + + B_0x0 + NBOOT01=10 + 0x0 + + + B_0x1 + NBOOT01=11 + 0x1 + + + + + NRST_MODE + NRST pin configuration + 27 + 2 + read-write + + + B_0x1 + Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. + 0x1 + + + B_0x2 + Standard GPIO: only internal RESET is possible + 0x2 + + + B_0x3 + Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode + 0x3 + + + + + IRHEN + Internal reset holder enable bit + 29 + 1 + read-write + + + B_0x0 + Internal resets are propagated as simple pulse on NRST pin + 0x0 + + + B_0x1 + Internal resets drives NRST pin low until it is seen as low level + 0x1 + + + + + + + FLASH_WRP1AR + FLASH_WRP1AR + FLASH WRP area A address register + 0x02C + 0x20 + 0x00000000 + 0xFFF0FFF0 + + + WRP1A_STRT + WRP area A start offset +This bitfield contains the offset of the first page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 7 + read-write + + + WRP1A_END + WRP area A end offset +This bitfield contains the offset of the last page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 7 + read-write + + + + + FLASH_WRP1BR + FLASH_WRP1BR + FLASH WRP area B address register + 0x030 + 0x20 + 0x00000000 + 0xFFF0FFF0 + + + WRP1B_STRT + WRP area B start offset +This bitfield contains the offset of the first page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 7 + read-write + + + WRP1B_END + WRP area B end offset +This bitfield contains the offset of the last page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 7 + read-write + + + + + FLASH_SECR + FLASH_SECR + FLASH security register + 0x080 + 0x20 + 0x0 + 0xFFFEFFE0 + + + HDP1_PEND + Last page of the first hide protection area + 0 + 7 + read-write + + + BOOT_LOCK + used to force boot from user area +If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). + 16 + 1 + read-write + + + B_0x0 + Boot based on the pad/option bit configuration + 0x0 + + + B_0x1 + Boot forced from main flash memory + 0x1 + + + + + HDP1EN + Hide protection area enable + 24 + 8 + read-write + + + + + + + GPIOA + GPIOA address block description + GPIO + 0x50000000 + + 0x0 + 0x2C + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOB + GPIOB address block description + GPIO + 0x50000400 + + 0x0 + 0x2C + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOB_LCKR + GPIOB_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOC + GPIOC address block description + GPIO + 0x50000800 + + 0x0 + 0x2C + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOC_LCKR + GPIOC_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOD + GPIOD address block description + GPIO + 0x50000C00 + + 0x0 + 0x2C + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOD_LCKR + GPIOD_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOE + GPIOE address block description + GPIO + 0x50001000 + + 0x0 + 0x2C + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOE_LCKR + GPIOE_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOF + GPIOF address block description + GPIO + 0x50001400 + + 0x0 + 0x2C + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOF_LCKR + GPIOF_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + IWDG + IWDG address block description + IWDG + 0x40003000 + + 0x0 + 0x18 + registers + + + + IWDG_KR + IWDG_KR + IWDG key register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Key value (write only, read 0x0000) +These bits can be used for several functions, depending upon the value written by the application: +- 0xAAAA: reloads the RL[11:0] value into the IWDCNT down-counter (watchdog refresh), and write-protects registers. This value must be written by software at regular intervals, otherwise the watchdog generates a reset when the counter reaches 0. +- 0x5555: enables write-accesses to the registers. +- 0xCCCC: enables the watchdog (except if the hardware watchdog option is selected) and write-protects registers. +- values different from 0x5555: write-protects registers. +Note that only IWDG_PR, IWDG_RLR, IWDG_EWCR and IWDG_WINR registers have a write-protection mechanism. + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG prescaler register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PR + Prescaler divider +These bits are write access protected, see Section126.4.6. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset to be able to change the prescaler divider. +Others: divider / 1024 +Note: Reading this register returns the prescaler value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 4 + read-write + + + B_0x0 + divider / 4 + 0x0 + + + B_0x1 + divider / 8 + 0x1 + + + B_0x2 + divider / 16 + 0x2 + + + B_0x3 + divider / 32 + 0x3 + + + B_0x4 + divider / 64 + 0x4 + + + B_0x5 + divider / 128 + 0x5 + + + B_0x6 + divider / 256 + 0x6 + + + B_0x7 + divider / 512 + 0x7 + + + + + + + IWDG_RLR + IWDG_RLR + IWDG reload register + 0x08 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + RL + Watchdog counter reload value +These bits are write access protected, see Section126.4.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. +The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG status register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVU + Watchdog prescaler value update +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the V<sub>DD</sub> voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). +The prescaler value can be updated only when PVU bit is reset. + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). +The reload value can be updated only when RVU bit is reset. + 1 + 1 + read-only + + + WVU + Watchdog counter window value update +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). +The window value can be updated only when WVU bit is reset. +This bit is generated only if generic window = 1. + 2 + 1 + read-only + + + EWU + Watchdog interrupt comparator value update +This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the V<sub>DD</sub> voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). +The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. + 3 + 1 + read-only + + + ONF + Watchdog enable status bit +Set to 1 by hardware as soon as the IWDG is started. In software mode, it remains to '1' until the IWDG is reset. In hardware mode, this bit is always set to '1'. + 8 + 1 + read-only + + + B_0x0 + The IWDG is not activated + 0x0 + + + B_0x1 + The IWDG is activated and needs to be refreshed regularly by the application + 0x1 + + + + + EWIF + Watchdog early interrupt flag +This bit is set to 1 by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to 1. + 14 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG window register + 0x10 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + WIN + Watchdog counter window value +These bits are write access protected, see Section126.4.6.They contain the high limit of the window value to be compared with the downcounter. +To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0]1+11 and greater than 1. +The WVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_EWCR + IWDG_EWCR + IWDG early wake-up interrupt register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EWIT + Watchdog counter window value +These bits are write access protected (see Section126.4.6). They are written by software to define at which position of the IWDCNT down-counter the early wake-up interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0]1-11. +EWIT[11:0] must be bigger than 1. +An interrupt is generated only if EWIE = 1. +The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the Early wake-up comparator value and the Interrupt enable bit from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + EWIC + Watchdog early interrupt acknowledge +The software must write a 1 into this bit in order to acknowledge the early wake-up interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. + 14 + 1 + write-only + + + EWIE + Watchdog early interrupt enable +Set and reset by software. +The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the value of this bit. + 15 + 1 + read-write + + + B_0x0 + The early interrupt interface is disabled. + 0x0 + + + B_0x1 + The early interrupt interface is enabled. + 0x1 + + + + + + + + + I2C1 + I2C address block description + I2C + 0x40005400 + + 0x0 + 0x2C + registers + + + I2C1 + I2C1 global interrupt (combined with EXTI line 23) + 23 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer complete (TC) +Note: Transfer complete reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer complete interrupt disabled + 0x0 + + + B_0x1 + Transfer complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration loss (ARLO) +Note: Bus error detection (BERR) +Note: Overrun/Underrun (OVR) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + 18 + 1 + read-write + + + B_0x0 + Wake-up from Stop mode disable. + 0x0 + + + B_0x1 + Wake-up from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + FMP + Fast-mode Plus 20 mA drive enable + 24 + 1 + read-write + + + B_0x0 + 20 mA I/O drive disabled + 0x0 + + + B_0x1 + 20 mA I/O drive enabled + 0x1 + + + + + ADDRACLR + Address match flag (ADDR) automatic clear + 30 + 1 + read-write + + + B_0x0 + ADDR flag is set by hardware, cleared by software by setting ADDRCF bit. + 0x0 + + + B_0x1 + ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral. + 0x1 + + + + + STOPFACLR + STOP detection flag (STOPF) automatic clear + 31 + 1 + read-write + + + B_0x0 + STOPF flag is set by hardware, cleared by software by setting STOPCF bit. + 0x0 + + + B_0x1 + STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral. + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] must be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer + 0x0 + + + B_0x1 + Master requests a read transfer + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit address in write direction + Restart + first seven bits of the 10-bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the first seven bits of the 10-bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer. +Otherwise, setting this bit generates a START condition once the bus is free. +Note: Writing 0 to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In master mode: +Note: Writing 0 to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation + 0x0 + + + B_0x1 + Stop generation after current byte transfer + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing 0 to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN = 0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN = 0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN = 0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN = 0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and dont care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and dont care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL + 1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH + 1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL + 1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings) and for SCL high and low level counters (refer to I2C master initialization). +t<sub>PRESC </sub>= (PRESC + 1) x t<sub>I2CCLK</sub> + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE = 0 +t<sub>TIMEOUT</sub>= (TIMEOUTA + 1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE = 1 +t<sub>IDLE</sub>= (TIMEOUTA + 1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN = 0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN = 0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE = 0) or high for more than t<sub>IDLE </sub>(TIDLE = 1), a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT </sub>= (TIMEOUTB + TIDLE = 01) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN = 0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + I2C2 + 0x40005800 + + I2C2_I2C3_I2C4 + I2C2/3/4 global interrupt + 24 + + + + I2C3 + 0x40008800 + + + LCD + LCD address block description + LCDC + 0x40002400 + + 0x0 + 0x54 + registers + + + LCD + LCD global interrupt (combined with EXTI line 32) + 22 + + + + LCD_CR + LCD_CR + LCD control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCDEN + LCD controller enable +This bit is set by software to enable the LCD controller/driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled, all COM and SEG pins are driven to V<sub>SS</sub>. + 0 + 1 + read-write + + + B_0x0 + LCD controller disabled + 0x0 + + + B_0x1 + LCD controller enabled + 0x1 + + + + + VSEL + Voltage source selection +This bit determines the voltage source for the LCD. + 1 + 1 + read-write + + + B_0x0 + Internal source (voltage stepup converter) + 0x0 + + + B_0x1 + External source (VLCD pin) + 0x1 + + + + + DUTY + Duty selection +These bits determine the duty cycle. Values 101, 110 and 111 are forbidden. +Others: Reserved + 2 + 3 + read-write + + + B_0x0 + Static duty + 0x0 + + + B_0x1 + 1/2 duty + 0x1 + + + B_0x2 + 1/3 duty + 0x2 + + + B_0x3 + 1/4 duty + 0x3 + + + B_0x4 + 1/8 duty + 0x4 + + + + + BIAS + Bias selector +These bits determine the bias used. Value 11 is forbidden. + 5 + 2 + read-write + + + B_0x0 + Bias 1/4 + 0x0 + + + B_0x1 + Bias 1/2 + 0x1 + + + B_0x2 + Bias 1/3 + 0x2 + + + + + MUX_SEG + Mux segment enable +This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with1SEG[31:28] or SEG[15:12]. See Section118.3.7. + 7 + 1 + read-write + + + B_0x0 + SEG pin multiplexing disabled + 0x0 + + + B_0x1 + SEG[31:28] multiplexed with SEG[43:40] + 0x1 + + + + + BUFEN + Voltage output buffer enable +This bit is used to enable/disable the voltage output buffer for higher driving capability. + 8 + 1 + read-write + + + B_0x0 + Output buffer disabled + 0x0 + + + B_0x1 + Output buffer enabled + 0x1 + + + + + + + LCD_FCR + LCD_FCR + LCD frame control register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HD + High drive enable +This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated. + 0 + 1 + read-write + + + B_0x0 + Permanent high drive disabled + 0x0 + + + B_0x1 + Permanent high drive enabled. When HD = 1, PON[2:0] must be programmed to 001. + 0x1 + + + + + SOFIE + Start of frame interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + LCD start-of-frame interrupt disabled + 0x0 + + + B_0x1 + LCD start-of-frame interrupt enabled + 0x1 + + + + + UDDIE + Update display done interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + LCD update display done interrupt disabled + 0x0 + + + B_0x1 + LCD update display done interrupt enabled + 0x1 + + + + + PON + Pulse ON duration +These bits are written by software to define the pulse duration in terms of ck_ps pulses. A1short pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. +Note that the pulse is never longer than one half prescaled LCD clock period. +PON duration example with LCDCLK = 32.7681kHz and PS=0x03: + 4 + 3 + read-write + + + B_0x0 + 0 1s + 0x0 + + + B_0x1 + 244 1s + 0x1 + + + B_0x2 + 488 1s + 0x2 + + + B_0x3 + 782 1s + 0x3 + + + B_0x4 + 976 1s + 0x4 + + + B_0x5 + 1.22 ms + 0x5 + + + B_0x6 + 1.46 ms + 0x6 + + + B_0x7 + 1.71 ms + 0x7 + + + + + DEAD + Dead time duration +These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. +...... + 7 + 3 + read-write + + + B_0x0 + No dead time + 0x0 + + + B_0x1 + 1 phase period dead time + 0x1 + + + B_0x2 + 2 phase period dead time + 0x2 + + + B_0x7 + 7 phase period dead time + 0x7 + + + + + CC + Contrast control +These bits specify one of the V<sub>LCD </sub>maximum voltages (independent of V<sub>DD</sub>). It ranges from12.60 V to 3.51V. +Note: Refer to the datasheet for the V<sub>LCDx</sub> values. + 10 + 3 + read-write + + + B_0x0 + V<sub>LCD0</sub> + 0x0 + + + B_0x1 + V<sub>LCD1</sub> + 0x1 + + + B_0x2 + V<sub>LCD2</sub> + 0x2 + + + B_0x3 + V<sub>LCD3</sub> + 0x3 + + + B_0x4 + V<sub>LCD4</sub> + 0x4 + + + B_0x5 + V<sub>LCD5</sub> + 0x5 + + + B_0x6 + V<sub>LCD6</sub> + 0x6 + + + B_0x7 + V<sub>LCD7</sub> + 0x7 + + + + + BLINKF + Blink frequency selection + 13 + 3 + read-write + + + B_0x0 + f<sub>LCD</sub>/8 + 0x0 + + + B_0x1 + f<sub>LCD</sub>/16 + 0x1 + + + B_0x2 + f<sub>LCD</sub>/32 + 0x2 + + + B_0x3 + f<sub>LCD</sub>/64 + 0x3 + + + B_0x4 + f<sub>LCD</sub>/128 + 0x4 + + + B_0x5 + f<sub>LCD</sub>/256 + 0x5 + + + B_0x6 + f<sub>LCD</sub>/512 + 0x6 + + + B_0x7 + f<sub>LCD</sub>/1024 + 0x7 + + + + + BLINK + Blink mode selection + 16 + 2 + read-write + + + B_0x0 + Blink disabled + 0x0 + + + B_0x1 + Blink enabled on SEG[0], COM[0] (1 pixel) + 0x1 + + + B_0x2 + Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) + 0x2 + + + B_0x3 + Blink enabled on all SEGs and all COMs (all pixels) + 0x3 + + + + + DIV + DIV clock divider +These bits are written by software to define the division factor of the DIV divider (see1Section118.3.2.) +... + 18 + 4 + read-write + + + B_0x0 + ck_div = ck_ps/16 + 0x0 + + + B_0x1 + ck_div = ck_ps/17 + 0x1 + + + B_0xF + ck_div = ck_ps/31 + 0xF + + + + + PS + PS 16-bit prescaler +These bits are written by software to define the division factor of the PS 16-bit prescaler. +ck_ps = LCDCLK/(2<sup>PS[3:0]</sup>). See<sub> </sub>Section118.3.2. +... + 22 + 4 + read-write + + + B_0x0 + ck_ps = LCDCLK + 0x0 + + + B_0x1 + ck_ps = LCDCLK/2 + 0x1 + + + B_0xF + ck_ps = LCDCLK/32768 + 0xF + + + + + + + LCD_SR + LCD_SR + LCD status register + 0x08 + 0x20 + 0x00000020 + 0xFFFFFFFF + + + ENS + LCD enabled status +This bit is set and cleared by hardware. It indicates the LCD controller status. +Note: This bit is set immediately when LCDEN in LCD_CR goes from 0 to 1. On deactivation, it reflects the real LCD status. It becomes 0 at the end of the last displayed frame. + 0 + 1 + read-only + + + B_0x0 + LCD controller disabled + 0x0 + + + B_0x1 + LCD controller enabled + 0x1 + + + + + SOF + Start-of-frame flag +This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to SOFC in LCD_CLR. The bit clear has priority over the set. + 1 + 1 + read-only + + + B_0x0 + No event + 0x0 + + + B_0x1 + Start-of-frame event occurred. An LCD SOF interrupt is generated if SOFIE is set. + 0x1 + + + + + UDR + Update display request +Each time software modifies the LCD_RAM, it must set this bit to transfer the updated data to the second level buffer. This bit stays set until the end of the update. During this time, +the LCD_RAM is write protected. +When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, +Note: only the LCD_DISPLAY of COM0 and COM1 are updated. +Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be cleared by hardware only. It can be cleared only when LCDEN = 1 + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Update display request + 0x1 + + + + + UDD + Update display done +This bit is set by hardware. It is cleared by writing 1 to UDDC in LCD_CLR. The bit set has priority over the clear. +Note: If the device is in Stop mode (PCLK not provided), UDD does not generate an interrupt even if UDDIE = 1. If the display is not enabled, the UDD interrupt never occurs. + 3 + 1 + read-only + + + B_0x0 + No event + 0x0 + + + B_0x1 + Update display request done. A UDD interrupt is generated if UDDIE = 1 in LCD_FCR. + 0x1 + + + + + RDY + Ready flag +This bit is set and cleared by hardware. It indicates the status of the stepup converter. + 4 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Stepup converter enabled and ready to provide the correct voltage + 0x1 + + + + + FCRSF + LCD frame control register synchronization flag +This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register. + 5 + 1 + read-only + + + B_0x0 + LCD frame control register not yet synchronized + 0x0 + + + B_0x1 + LCD frame control register synchronized + 0x1 + + + + + + + LCD_CLR + LCD_CLR + LCD clear register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SOFC + Start-of-frame flag clear +This bit is written by software to clear SOF in LCD_SR. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear SOF flag. + 0x1 + + + + + UDDC + Update display done clear +This bit is written by software to clear UDD in LCD_SR. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear UDD flag. + 0x1 + + + + + + + LCD_RAM0 + LCD_RAM0 + LCD display memory + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM1 + LCD_RAM1 + LCD display memory + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM2 + LCD_RAM2 + LCD display memory + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM3 + LCD_RAM3 + LCD display memory + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM4 + LCD_RAM4 + LCD display memory + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM5 + LCD_RAM5 + LCD display memory + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM6 + LCD_RAM6 + LCD display memory + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM7 + LCD_RAM7 + LCD display memory + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM8 + LCD_RAM8 + LCD display memory + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM9 + LCD_RAM9 + LCD display memory + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM10 + LCD_RAM10 + LCD display memory + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM11 + LCD_RAM11 + LCD display memory + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM12 + LCD_RAM12 + LCD display memory + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM13 + LCD_RAM13 + LCD display memory + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM14 + LCD_RAM14 + LCD display memory + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM15 + LCD_RAM15 + LCD display memory + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + + + LPTIM1 + LPTIM1 address block description + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + LPTIM1_ISR_OUTPUT + LPTIM1_ISR_OUTPUT + LPTIM1 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM1_ISR_INPUT + LPTIM1_ISR_INPUT + LPTIM1 interrupt and status register [alternate] + LPTIM1_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM1_ICR_OUTPUT + LPTIM1_ICR_OUTPUT + LPTIM1 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM1_ICR_INPUT + LPTIM1_ICR_INPUT + LPTIM1 interrupt clear register [alternate] + LPTIM1_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM1_DIER_OUTPUT + LPTIM1_DIER_OUTPUT + LPTIM1 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM1_DIER_INPUT + LPTIM1_DIER_INPUT + LPTIM1 interrupt enable register [alternate] + LPTIM1_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM1_CFGR + LPTIM1_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM1_ext_trig0 + 0x0 + + + B_0x1 + LPTIM1_ext_trig1 + 0x1 + + + B_0x2 + LPTIM1_ext_trig2 + 0x2 + + + B_0x3 + LPTIM1_ext_trig3 + 0x3 + + + B_0x4 + LPTIM1_ext_trig4 + 0x4 + + + B_0x5 + LPTIM1_ext_trig5 + 0x5 + + + B_0x6 + LPTIM1_ext_trig6 + 0x6 + + + B_0x7 + LPTIM1_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM1_ARR, LPTIM1_RCR and the LPTIM1_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM1_CR + LPTIM1_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM1_ARR and LPTIM1_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM1_ARR and LPTIM1_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM1_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM1_CNT register asynchronously resets LPTIM1_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM1_CCR1 + LPTIM1_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM1_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_ARR + LPTIM1_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM1_CNT + LPTIM1_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM1_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM1_CFGR2 + LPTIM1_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM1_in1_mux0 + 0x0 + + + B_0x1 + LPTIM1_in1_mux1 + 0x1 + + + B_0x2 + LPTIM1_in1_mux2 + 0x2 + + + B_0x3 + LPTIM1_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM1_in2_mux0 + 0x0 + + + B_0x1 + LPTIM1_in2_mux1 + 0x1 + + + B_0x2 + LPTIM1_in2_mux2 + 0x2 + + + B_0x3 + LPTIM1_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM1_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM1_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM1_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM1_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM1_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM1_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM1_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM1_ic2_mux3 + 0x3 + + + + + + + LPTIM1_RCR + LPTIM1_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM1_CCMR1 + LPTIM1_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM1_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM1_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM1_CCMR2 + LPTIM1_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM1_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM1_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM1_CCR2 + LPTIM1_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM1_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_CCR3 + LPTIM1_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM1_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_CCR4 + LPTIM1_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM1_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPTIM2 + LPTIM2 address block description + LPTIM + 0x40009400 + + 0x0 + 0x400 + registers + + + + LPTIM2_ISR_OUTPUT + LPTIM2_ISR_OUTPUT + LPTIM2 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM2_ISR_INPUT + LPTIM2_ISR_INPUT + LPTIM2 interrupt and status register [alternate] + LPTIM2_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM2_ICR_OUTPUT + LPTIM2_ICR_OUTPUT + LPTIM2 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM2_ICR_INPUT + LPTIM2_ICR_INPUT + LPTIM2 interrupt clear register [alternate] + LPTIM2_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM2_DIER_OUTPUT + LPTIM2_DIER_OUTPUT + LPTIM2 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM2_DIER_INPUT + LPTIM2_DIER_INPUT + LPTIM2 interrupt enable register [alternate] + LPTIM2_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM2_CFGR + LPTIM2_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM2_ext_trig0 + 0x0 + + + B_0x1 + LPTIM2_ext_trig1 + 0x1 + + + B_0x2 + LPTIM2_ext_trig2 + 0x2 + + + B_0x3 + LPTIM2_ext_trig3 + 0x3 + + + B_0x4 + LPTIM2_ext_trig4 + 0x4 + + + B_0x5 + LPTIM2_ext_trig5 + 0x5 + + + B_0x6 + LPTIM2_ext_trig6 + 0x6 + + + B_0x7 + LPTIM2_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM2_ARR, LPTIM2_RCR and the LPTIM2_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM2_CR + LPTIM2_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM2_ARR and LPTIM2_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM2_ARR and LPTIM2_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM2_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM2_CNT register asynchronously resets LPTIM2_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM2_CCR1 + LPTIM2_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM2_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_ARR + LPTIM2_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM2_CNT + LPTIM2_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM2_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM2_CFGR2 + LPTIM2_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM2_in1_mux0 + 0x0 + + + B_0x1 + LPTIM2_in1_mux1 + 0x1 + + + B_0x2 + LPTIM2_in1_mux2 + 0x2 + + + B_0x3 + LPTIM2_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM2_in2_mux0 + 0x0 + + + B_0x1 + LPTIM2_in2_mux1 + 0x1 + + + B_0x2 + LPTIM2_in2_mux2 + 0x2 + + + B_0x3 + LPTIM2_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM2_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM2_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM2_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM2_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM2_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM2_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM2_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM2_ic2_mux3 + 0x3 + + + + + + + LPTIM2_RCR + LPTIM2_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM2_CCMR1 + LPTIM2_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM2_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM2_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM2_CCMR2 + LPTIM2_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM2_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM2_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM2_CCR2 + LPTIM2_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM2_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_CCR3 + LPTIM2_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM2_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_CCR4 + LPTIM2_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM2_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPTIM3 + LPTIM3 address block description + LPTIM + 0x40009000 + + 0x0 + 0x400 + registers + + + + LPTIM3_ISR_OUTPUT + LPTIM3_ISR_OUTPUT + LPTIM3 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM3_ISR_INPUT + LPTIM3_ISR_INPUT + LPTIM3 interrupt and status register [alternate] + LPTIM3_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM3_ICR_OUTPUT + LPTIM3_ICR_OUTPUT + LPTIM3 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM3_ICR_INPUT + LPTIM3_ICR_INPUT + LPTIM3 interrupt clear register [alternate] + LPTIM3_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM3_DIER_OUTPUT + LPTIM3_DIER_OUTPUT + LPTIM3 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM3_DIER_INPUT + LPTIM3_DIER_INPUT + LPTIM3 interrupt enable register [alternate] + LPTIM3_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM3_CFGR + LPTIM3_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM3_ext_trig0 + 0x0 + + + B_0x1 + LPTIM3_ext_trig1 + 0x1 + + + B_0x2 + LPTIM3_ext_trig2 + 0x2 + + + B_0x3 + LPTIM3_ext_trig3 + 0x3 + + + B_0x4 + LPTIM3_ext_trig4 + 0x4 + + + B_0x5 + LPTIM3_ext_trig5 + 0x5 + + + B_0x6 + LPTIM3_ext_trig6 + 0x6 + + + B_0x7 + LPTIM3_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM3_ARR, LPTIM3_RCR and the LPTIM3_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM3_CR + LPTIM3_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM3_ARR and LPTIM3_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM3_ARR and LPTIM3_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM3_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM3_CNT register asynchronously resets LPTIM3_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM3_CCR1 + LPTIM3_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM3_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM3_ARR + LPTIM3_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM3_CNT + LPTIM3_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM3_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM3_CFGR2 + LPTIM3_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM3_in1_mux0 + 0x0 + + + B_0x1 + LPTIM3_in1_mux1 + 0x1 + + + B_0x2 + LPTIM3_in1_mux2 + 0x2 + + + B_0x3 + LPTIM3_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM3_in2_mux0 + 0x0 + + + B_0x1 + LPTIM3_in2_mux1 + 0x1 + + + B_0x2 + LPTIM3_in2_mux2 + 0x2 + + + B_0x3 + LPTIM3_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM3_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM3_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM3_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM3_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM3_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM3_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM3_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM3_ic2_mux3 + 0x3 + + + + + + + LPTIM3_RCR + LPTIM3_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM3_CCMR1 + LPTIM3_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM3_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM3_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM3_CCMR2 + LPTIM3_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM3_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM3_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM3_CCR2 + LPTIM3_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM3_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM3_CCR3 + LPTIM3_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM3_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM3_CCR4 + LPTIM3_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM3_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPUART1 + LPUART address block description + LPUART + 0x40008000 + + 0x0 + 0x30 + registers + + + + LPUART_CR1 + LPUART_CR1 + LPUART control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable +When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode +When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. +When this bit is set, the LPUART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the LPUART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the LPUART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the LPUART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). +This bit can only be written when the LPUART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section132.4.14: RS232 Hardware flow control and RS485 Driver Enable. +If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section131.5.21: RS232 Hardware flow control and RS485 Driver Enable. +This bitfield can only be written when the LPUART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the LPUART is disabled (UE=0). +Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_CR1_ALTERNATE + LPUART_CR1_ALTERNATE + LPUART control register 1 + LPUART_CR1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable +When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode +When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. +When this bit is set, the LPUART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the LPUART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the LPUART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the LPUART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). +This bit can only be written when the LPUART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section132.4.14: RS232 Hardware flow control and RS485 Driver Enable. +If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section131.5.21: RS232 Hardware flow control and RS485 Driver Enable. +This bitfield can only be written when the LPUART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the LPUART is disabled (UE=0). +Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + LPUART_CR2 + LPUART_CR2 + LPUART control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the LPUART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + STOP + STOP bits +These bits are used for programming the stop bits. +This bitfield can only be written when the LPUART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the LPUART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ADD + Address of the LPUART node +These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). + 24 + 8 + read-write + + + + + LPUART_CR3 + LPUART_CR3 + LPUART control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the LPUART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the LPUART is disabled (UE=0). + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the LPUART is disabled (UE=0) + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. +This bit can only be written when the LPUART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data. + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the LPUART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the LPUART is disabled (UE=0). + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the LPUART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). +This bitfield can only be written when the LPUART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). +This bitfield can only be written when the LPUART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved. + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + Receive FIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + Receive FIFO becomes full. + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved. + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + TXFIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + TXFIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + TXFIFO becomes empty. + 0x5 + + + + + + + LPUART_BRR + LPUART_BRR + LPUART baud rate register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BRR + LPUART baud rate division (LPUARTDIV) + 0 + 20 + read-write + + + + + LPUART_RQR + LPUART_RQR + LPUART request register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software must wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit clears the RXNE flag. +This enables discarding the received data without reading it, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + LPUART_ISR + LPUART_ISR + LPUART interrupt and status register + 0x1C + 0x20 + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. +An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. +Note: This error is associated with the character in the LPUART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the LPUART_CR3 register. +Note: This error is associated with the character in the LPUART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag +This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: This error is associated with the character in the LPUART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. +An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. +Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. +The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the LPUART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: +When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXFE is set. +When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. +When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. +When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. +An interrupt is generated if TCIE=1 in the LPUART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the LPUART_ICR register or by writing to the LPUART_TDR register. + 6 + 1 + read-only + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. +The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF must be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). +An interrupt is generated if the TXFNFIE bit =1 in the LPUART_CR1 register. +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. +An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. +An interrupt is generated if CMIE=1in the LPUART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. +It can be used to verify that the LPUART is ready for reception before entering low-power mode. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 22 + 1 + read-only + + + TXFE + TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the LPUART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO is not empty. + 0x0 + + + B_0x1 + TXFIFO is empty. + 0x1 + + + + + RXFF + RXFIFO Full +This bit is set by hardware when the number of received data corresponds to RXFIFO1size1+11 (RXFIFO full + 1 data in the LPUART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the LPUART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO is not Full. + 0x0 + + + B_0x1 + RXFIFO is Full. + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the LPUART_CR3 register. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the LPUART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + LPUART_ISR_ALTERNATE + LPUART_ISR_ALTERNATE + LPUART interrupt and status register + LPUART_ISR + 0x1C + 0x20 + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. +An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the LPUART_CR3 register. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag +This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE/RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the LPUART_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled). It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. +An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. +Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the LPUART_RDR shift register has been transferred to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag is set when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the LPUART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the LPUART_TDR register has been transferred into the shift register. It is cleared by a write to the LPUART_TDR register. +An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register. +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. +An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. +An interrupt is generated if CMIE=1in the LPUART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. +It can be used to verify that the LPUART is ready for reception before entering low-power mode. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 22 + 1 + read-only + + + + + LPUART_ICR + LPUART_ICR + LPUART interrupt flag clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the LPUART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the LPUART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the LPUART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. + 4 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the LPUART_ISR register. + 6 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. + 9 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + write-only + + + + + LPUART_RDR + LPUART_RDR + LPUART receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure1254). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + LPUART_TDR + LPUART_TDR + LPUART transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure1254). +When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + LPUART_PRESC + LPUART_PRESC + LPUART prescaler register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The LPUART input clock can be divided by a prescaler: +Remaining combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + LPUART2 + 0x40008400 + + + LPUART3 + 0x40008C00 + + + OPAMP + OPAMP address block description + OPAMP + 0x40007800 + + 0x0 + 0xC + registers + + + + OPAMP_CSR + OPAMP_CSR + OPAMP control/status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPAEN + Operational amplifier Enable + 0 + 1 + read-write + + + B_0x0 + operational amplifier disabled + 0x0 + + + B_0x1 + operational amplifier enabled + 0x1 + + + + + OPALPM + Operational amplifier Low Power Mode +The operational amplifier must be disable to change this configuration. + 1 + 1 + read-write + + + B_0x0 + operational amplifier in normal mode + 0x0 + + + B_0x1 + operational amplifier in low-power mode + 0x1 + + + + + OPAMODE + Operational amplifier PGA mode + 2 + 2 + read-write + + + B_0x0 + internal PGA disable + 0x0 + + + B_0x1 + internal PGA disable + 0x1 + + + B_0x2 + internal PGA enable, gain programmed in PGA_GAIN + 0x2 + + + B_0x3 + internal follower + 0x3 + + + + + PGA_GAIN + Operational amplifier Programmable amplifier gain value + 4 + 2 + read-write + + + B_0x0 + internal PGA Gain 2 + 0x0 + + + B_0x1 + internal PGA Gain 4 + 0x1 + + + B_0x2 + internal PGA Gain 8 + 0x2 + + + B_0x3 + internal PGA Gain 16 + 0x3 + + + + + VM_SEL + Inverting input selection +These bits are used only when OPAMODE = 00, 01 or 10. +1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) + 8 + 2 + read-write + + + B_0x0 + GPIO connected to VINM (valid also in PGA mode for filtering) + 0x0 + + + + + VP_SEL + Non inverted input selection + 10 + 1 + read-write + + + B_0x0 + GPIO connected to VINP + 0x0 + + + B_0x1 + DAC connected to VINP + 0x1 + + + + + CALON + Calibration mode enabled + 12 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Calibration mode (all switches opened by HW) + 0x1 + + + + + CALSEL + Calibration selection + 13 + 1 + read-write + + + B_0x0 + NMOS calibration (200mV applied on OPAMP inputs) + 0x0 + + + B_0x1 + PMOS calibration (VDDA-200mV applied on OPAMP inputs) + 0x1 + + + + + USERTRIM + allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values +This bit is active for both mode normal and low-power. + 14 + 1 + read-write + + + B_0x0 + factory trim code used + 0x0 + + + B_0x1 + user trim code used + 0x1 + + + + + CALOUT + Operational amplifier calibration output +During calibration mode offset is trimmed when this signal toggle. + 15 + 1 + read-only + + + OPA_RANGE + Operational amplifier power supply range for stability +All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. + 31 + 1 + read-write + + + B_0x0 + Low range (VDDA < 2.4V) + 0x0 + + + B_0x1 + High range (VDDA > 2.4V) + 0x1 + + + + + + + OPAMP_OTR + OPAMP_OTR + OPAMP offset trimming register in normal mode + 0x04 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + read-write + + + + + OPAMP_LPOTR + OPAMP_LPOTR + OPAMP offset trimming register in low-power mode + 0x08 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMLPOFFSETN + Low-power mode trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMLPOFFSETP + Low-power mode trim for PMOS differential pairs + 8 + 5 + read-write + + + + + + + PWR + PWR register block + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Power control register 1 + 0x00 + 0x20 + 0x00000208 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when CPU enters the deepsleep mode. +1xx: Shutdown mode +Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. +Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x2 + Stop 2 mode + 0x2 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + Flash memory powered down during Stop mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. + 3 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_LPRUN + Flash memory powered down during Low-power run mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + 4 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_LPSLP + Flash memory powered down during Low-power sleep mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + 5 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + DBP + Disable backup domain write protection +In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. + 8 + 1 + read-write + + + B_0x0 + Access to RTC and Backup registers disabled + 0x0 + + + B_0x1 + Access to RTC and Backup registers enabled + 0x1 + + + + + VOS + Voltage scaling range selection + 9 + 2 + read-write + + + B_0x0 + Cannot be written (forbidden by hardware) + 0x0 + + + B_0x1 + Range 1 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Cannot be written (forbidden by hardware) + 0x3 + + + + + LPR + Low-power run +When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). +Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. + 14 + 1 + read-write + + + + + PWR_CR2 + PWR_CR2 + Power control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDE + Programmable voltage detector enable +Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. +Note: This bit is reset only by a system reset. + 0 + 1 + read-write + + + B_0x0 + Programmable voltage detector disable. + 0x0 + + + B_0x1 + Programmable voltage detector enable. + 0x1 + + + + + PLS + Programmable voltage detector level selection. +These bits select the voltage threshold detected by the programmable voltage detector: +Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. +Note: These bits are reset only by a system reset. + 1 + 3 + read-write + + + B_0x0 + V<sub>PVD0</sub> around 2.01V + 0x0 + + + B_0x1 + V<sub>PVD1</sub> around 2.21V + 0x1 + + + B_0x2 + V<sub>PVD2</sub> around 2.41V + 0x2 + + + B_0x3 + V<sub>PVD3</sub> around 2.51V + 0x3 + + + B_0x4 + V<sub>PVD4</sub> around 2.61V + 0x4 + + + B_0x5 + V<sub>PVD5</sub> around 2.81V + 0x5 + + + B_0x6 + V<sub>PVD6</sub> around 2.91V + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to VREFINT) + 0x7 + + + + + PVME1 + Peripheral voltage monitoring 1 enable: V<sub>DDUSB</sub> vs. 1.21V + 4 + 1 + read-write + + + B_0x0 + PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V threshold) disable. + 0x0 + + + B_0x1 + PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V threshold) enable. + 0x1 + + + + + PVME3 + Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. 1.621V + 5 + 1 + read-write + + + B_0x0 + PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V threshold) disable. + 0x0 + + + B_0x1 + PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V threshold) enable. + 0x1 + + + + + PVME4 + Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. 1.861V + 6 + 1 + read-write + + + B_0x0 + PVM4 (V<sub>DDA</sub> monitoring vs. 1.861V threshold) disable. + 0x0 + + + B_0x1 + PVM4 (V<sub>DDA</sub> monitoring vs. 1.86 V threshold) enable. + 0x1 + + + + + USV + V<sub>DDUSB</sub> USB supply valid +This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. +Setting this bit is mandatory to use the USB FS peripheral. If V<sub>DDUSB</sub> is not always +present in the application, the PVM can be used to determine whether this supply is ready or +not. + 10 + 1 + read-write + + + B_0x0 + V<sub>DDUSB</sub> is not present. Logical and electrical isolation is applied to ignore this supply. + 0x0 + + + B_0x1 + V<sub>DDUSB</sub> is valid. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + Power control register 3 + 0x08 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable Wake-up pin WKUP1 +When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. + 0 + 1 + read-write + + + EWUP2 + Enable Wake-up pin WKUP2 +When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. + 1 + 1 + read-write + + + EWUP3 + Enable Wake-up pin WKUP3 +When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. + 2 + 1 + read-write + + + EWUP4 + Enable Wake-up pin WKUP4 +When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + 3 + 1 + read-write + + + EWUP5 + Enable Wake-up pin WKUP5 +When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. + 4 + 1 + read-write + + + EWUP7 + Enable Wake-up pin WKUP7. +When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register. + 6 + 1 + read-write + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + read-write + + + B_0x0 + SRAM2 is powered off in Standby mode (SRAM2 content is lost). + 0x0 + + + B_0x1 + SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). + 0x1 + + + + + ENULP + Enable ULP sampling +When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. + 9 + 1 + read-write + + + APC + Apply pull-up and pull-down configuration +When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx +and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode. + 10 + 1 + read-write + + + EIWUL + Enable internal wake-up line + 15 + 1 + read-write + + + B_0x0 + Internal wake-up line disable. + 0x0 + + + B_0x1 + Internal wake-up line enable. + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + Power control register 4 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WP1 + Wake-up pin WKUP1 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP2 + Wake-up pin WKUP2 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP3 + Wake-up pin WKUP3 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP4 + Wake-up pin WKUP4 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP5 + Wake-up pin WKUP5 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP7 + Wake-up pin WKUP7 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP7 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + VBE + V<sub>BAT</sub> battery charging enable + 8 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> battery charging disable + 0x0 + + + B_0x1 + V<sub>BAT</sub> battery charging enable + 0x1 + + + + + VBRS + V<sub>BAT</sub> battery charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge V<sub>BAT</sub> through a 5 kOhms resistor + 0x0 + + + B_0x1 + Charge V<sub>BAT</sub> through a 1.5 kOhms resistor + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + Power status register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wake-up flag 1 +This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. + 0 + 1 + read-only + + + WUF2 + Wake-up flag 2 +This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. + 1 + 1 + read-only + + + WUF3 + Wake-up flag 3 +This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. + 2 + 1 + read-only + + + WUF4 + Wake-up flag 4 +This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. + 3 + 1 + read-only + + + WUF5 + Wake-up flag 5 +This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. + 4 + 1 + read-only + + + WUF7 + Wake-up flag 7 +This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register. + 6 + 1 + read-only + + + SBF + Standby flag +This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 8 + 1 + read-only + + + B_0x0 + The device did not enter the Standby mode + 0x0 + + + B_0x1 + The device entered the Standby mode + 0x1 + + + + + STOPF + Stop Flags +These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 9 + 3 + read-only + + + B_0x0 + The device did not enter any Stop mode. + 0x0 + + + B_0x4 + The device entered in Stop 0 mode. + 0x4 + + + B_0x5 + The device entered in Stop 1 mode. + 0x5 + + + B_0x6 + The device entered in Stop 2 mode. + 0x6 + + + + + WUFI + Wake-up flag internal +This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared. + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + Power status register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FLASH_RDY + Flash ready flag +This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. +Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory. + 7 + 1 + read-only + + + B_0x0 + Flash memory in power down + 0x0 + + + B_0x1 + Flash memory ready to be accessed + 0x1 + + + + + REGLPS + Low-power regulator started +This bit provides the information whether the low-power regulator is ready after a power-on +reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased. + 8 + 1 + read-only + + + B_0x0 + The low-power regulator is not ready + 0x0 + + + B_0x1 + The low-power regulator is ready + 0x1 + + + + + REGLPF + Low-power regulator flag +This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits +from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. +This bit is cleared by hardware when the regulator is ready. + 9 + 1 + read-only + + + B_0x0 + The regulator is ready in main mode (MR) + 0x0 + + + B_0x1 + The regulator is in low-power mode (LPR) + 0x1 + + + + + VOSF + Voltage scaling flag +A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. + 10 + 1 + read-only + + + B_0x0 + The regulator is ready in the selected voltage range + 0x0 + + + B_0x1 + The regulator output voltage is changing to the required voltage level + 0x1 + + + + + PVDO + Programmable voltage detector output + 11 + 1 + read-only + + + B_0x0 + V<sub>DD</sub> is above the selected PVD threshold + 0x0 + + + B_0x1 + V<sub>DD</sub> is below the selected PVD threshold + 0x1 + + + + + PVMO1 + Peripheral voltage monitoring output: V<sub>DDUSB</sub> vs. 1.2 V +Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time. + 12 + 1 + read-only + + + B_0x0 + V<sub>DDUSB</sub> voltage is above PVM1 threshold (around 1.21V). + 0x0 + + + B_0x1 + V<sub>DDUSB</sub> voltage is below PVM1 threshold (around 1.21V). + 0x1 + + + + + PVMO3 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.621V +Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time. + 14 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM3 threshold (around 1.621V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM3 threshold (around 1.621V). + 0x1 + + + + + PVMO4 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 2.21V +Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time. + 15 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM4 threshold (around 2.21V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM4 threshold (around 2.21V). + 0x1 + + + + + + + PWR_SCR + PWR_SCR + Power status clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wake-up flag 1 +Setting this bit clears the WUF1 flag in the PWR_SR1 register. + 0 + 1 + write-only + + + CWUF2 + Clear wake-up flag 2 +Setting this bit clears the WUF2 flag in the PWR_SR1 register. + 1 + 1 + write-only + + + CWUF3 + Clear wake-up flag 3 +Setting this bit clears the WUF3 flag in the PWR_SR1 register. + 2 + 1 + write-only + + + CWUF4 + Clear wake-up flag 4 +Setting this bit clears the WUF4 flag in the PWR_SR1 register. + 3 + 1 + write-only + + + CWUF5 + Clear wake-up flag 5 +Setting this bit clears the WUF5 flag in the PWR_SR1 register. + 4 + 1 + write-only + + + CWUF7 + Clear wake-up flag 7 +Setting this bit clears the WUF7 flag in the PWR_SR1 register. + 6 + 1 + write-only + + + CSBF + Clear standby flag +Setting this bit clears the SBF flag in the PWR_SR1 register. + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU7 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + PU14 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 14 + 1 + read-write + + + PU15 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PU1 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PU2 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PU3 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PU4 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PU5 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PU6 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PU7 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PU8 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PU9 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PU10 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PU11 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PU12 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PU13 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PU14 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PU15 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU7 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + PU14 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 14 + 1 + read-write + + + PU15 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU8 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD8 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU3 + Port E pull-up bit 3 +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU7 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD3 + Port E pull-down bit 3 +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD7 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + + + + + RCC + RCC address block description + RCC + 0x40021000 + + 0x0 + 0x9C + registers + + + RCC_CRS + RCC and CRS global interrupt + 4 + + + + RCC_CR + RCC_CR + Clock control register + 0x00 + 0x20 + 0x00000083 + 0xFFFFFFFF + + + MSION + MSI clock enable +This bit is set and cleared by software. +Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. +Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. +Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator +Set by hardware when used directly or indirectly as system clock. + 0 + 1 + read-write + + + B_0x0 + MSI oscillator OFF + 0x0 + + + B_0x1 + MSI oscillator ON + 0x1 + + + + + MSIRDY + MSI clock ready flag +This bit is set by hardware to indicate that the MSI oscillator is stable. +Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. + 1 + 1 + read-only + + + B_0x0 + MSI oscillator not ready + 0x0 + + + B_0x1 + MSI oscillator ready + 0x1 + + + + + MSIPLLEN + MSI clock PLL enable +Set and cleared by software to enable/ disable the PLL part of the MSI clock source. +MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. +This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). + 2 + 1 + read-write + + + B_0x0 + MSI PLL OFF + 0x0 + + + B_0x1 + MSI PLL ON + 0x1 + + + + + MSIRGSEL + MSI clock range selection +Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. +After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. + 3 + 1 + read-write + + + B_0x0 + MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + 0x0 + + + B_0x1 + MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + 0x1 + + + + + MSIRANGE + MSI clock ranges +These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: +others: not allowed (hardware write protection) +Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0) + 4 + 4 + read-write + + + B_0x0 + range 0 around 1001kHz + 0x0 + + + B_0x1 + range 1 around 2001kHz + 0x1 + + + B_0x2 + range 2 around 4001kHz + 0x2 + + + B_0x3 + range 3 around 8001kHz + 0x3 + + + B_0x4 + range 4 around 1M1Hz + 0x4 + + + B_0x5 + range 5 around 21MHz + 0x5 + + + B_0x6 + range 6 around 41MHz (reset value) + 0x6 + + + B_0x7 + range 7 around 81MHz + 0x7 + + + B_0x8 + range 8 around 161MHz + 0x8 + + + B_0x9 + range 9 around 241MHz + 0x9 + + + B_0xA + range 10 around 321MHz + 0xA + + + B_0xB + range 11 around 481MHz + 0xB + + + + + HSION + HSI16 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. +Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator OFF + 0x0 + + + B_0x1 + HSI16 oscillator ON + 0x1 + + + + + HSIKERON + HSI16 always enable for peripheral kernels. +Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator. + 0x0 + + + B_0x1 + HSI16 oscillator is forced ON even in Stop mode. + 0x1 + + + + + HSIRDY + HSI16 clock ready flag +Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. +Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSIASFS + HSI16 automatic start from Stop +Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI16 is parallel of the system wake-up. + 11 + 1 + read-only + + + B_0x0 + HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wake-up clock. + 0x0 + + + B_0x1 + HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wake-up clock. + 0x1 + + + + + HSEON + HSE clock enable +Set and cleared by software. +Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable. +Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable +Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + 19 + 1 + read-write + + + B_0x0 + Clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + PLLON + PLL enable +Set and cleared by software to enable the PLL. +Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + 24 + 1 + read-write + + + B_0x0 + PLL OFF + 0x0 + + + B_0x1 + PLL ON + 0x1 + + + + + PLLRDY + PLL clock ready flag +Set by hardware to indicate that the PLL is locked. + 25 + 1 + read-only + + + B_0x0 + PLL unlocked + 0x0 + + + B_0x1 + PLL locked + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + Internal clock sources calibration register + 0x04 + 0x20 + 0x40004000 + 0xFF00FF00 + + + MSICAL + MSI clock calibration +These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. + 0 + 8 + read-only + + + MSITRIM + MSI clock trimming +These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. + 8 + 8 + read-write + + + HSICAL + HSI16 clock calibration +These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + 16 + 8 + read-only + + + HSITRIM + HSI16 clock trimming +These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. +The default value is 64 when added to the HSICAL value, trim the HSI16 to 161MHz 1 11%. + 24 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + Clock configuration register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SW + System clock switch +This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: +Others: Reserved +The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + 0 + 3 + read-write + + + B_0x0 + MSI + 0x0 + + + B_0x1 + HSI16 + 0x1 + + + B_0x2 + HSE + 0x2 + + + B_0x3 + PLLRCLK + 0x3 + + + B_0x4 + LSI + 0x4 + + + B_0x5 + LSE + 0x5 + + + + + SWS + System clock switch status +This bitfield is controlled by hardware to indicate the clock source used as system clock: +Others: Reserved + 3 + 3 + read-only + + + B_0x0 + MSI + 0x0 + + + B_0x1 + HSI16 + 0x1 + + + B_0x2 + HSE + 0x2 + + + B_0x3 + PLLRCLK + 0x3 + + + B_0x4 + LSI + 0x4 + + + B_0x5 + LSE + 0x5 + + + + + HPRE + AHB prescaler +This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: +0xxx: 1 +Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. + 8 + 4 + read-write + + + B_0x8 + 2 + 0x8 + + + B_0x9 + 4 + 0x9 + + + B_0xA + 8 + 0xA + + + B_0xB + 16 + 0xB + + + B_0xC + 64 + 0xC + + + B_0xD + 128 + 0xD + + + B_0xE + 256 + 0xE + + + B_0xF + 512 + 0xF + + + + + PPRE + APB prescaler +This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: +0xx: 1 + 12 + 3 + read-write + + + B_0x4 + 2 + 0x4 + + + B_0x5 + 4 + 0x5 + + + B_0x6 + 8 + 0x6 + + + B_0x7 + 16 + 0x7 + + + + + STOPWUCK + Wake-up from Stop and CSS backup clock selection +Set and cleared by software to select the system clock used when exiting Stop mode. +The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10). + 15 + 1 + read-write + + + B_0x0 + MSI oscillator selected as wake-up from stop clock and CSS backup clock. + 0x0 + + + B_0x1 + HSI16 oscillator selected as wake-up from stop clock and CSS backup clock + 0x1 + + + + + MCO2SEL + Microcontroller clock output 2 clock selector +This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. + 16 + 4 + read-write + + + B_0x0 + no clock, MCO2 output disabled + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + MSI + 0x2 + + + B_0x3 + HSI16 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x5 + PLLRCLK + 0x5 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSI48 + 0x8 + + + B_0x9 + RTCCLK + 0x9 + + + B_0xA + RTC WAKEUP + 0xA + + + + + MCO2PRE + Microcontroller clock output 2 prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: +... +Others: reserved +It is highly recommended to set this field before the MCO2 output is enabled. + 20 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + MCOSEL + Microcontroller clock output clock selector +This bitfield is controlled by software. It sets the clock selector for MCO output as follows: +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + 24 + 4 + read-write + + + B_0x0 + no clock, MCO output disabled + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + MSI + 0x2 + + + B_0x3 + HSI16 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x5 + PLLRCLK + 0x5 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSI48 + 0x8 + + + B_0x9 + RTCCLK + 0x9 + + + B_0xA + RTC WAKEUP + 0xA + + + + + MCOPRE + Microcontroller clock output prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: +... +Others: reserved +It is highly recommended to set this field before the MCO output is enabled. + 28 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + + + RCC_PLLCFGR + RCC_PLLCFGR + PLL configuration register + 0x0C + 0x20 + 0x00001000 + 0xFFFFFFFF + + + PLLSRC + PLL input clock source +This bit is controlled by software to select PLL clock source, as follows: +The bitfield can be written only when the PLL is disabled. +When the PLL is not used, selecting 00 allows saving power. + 0 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + MSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + HSE + 0x3 + + + + + PLLM + Division factor M of the PLL input clock divider +This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: +The bitfield can be written only when the PLL is disabled. +Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz. + 4 + 3 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + PLLN + PLL frequency multiplication factor N +This bit is controlled by software to set the division factor of the f<sub>VCO</sub> feedback divider (that determines the PLL multiplication ratio) as follows: +... +... +The bitfield can be written only when the PLL is disabled. +Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz. + 8 + 7 + read-write + + + B_0x0 + Invalid + 0x0 + + + B_0x4 + 4 + 0x4 + + + B_0x5 + 5 + 0x5 + + + B_0x7E + 126 + 0x7E + + + B_0x7F + 127 + 0x7F + + + + + PLLPEN + PLLPCLK clock output enable +This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: +Disabling the PLLPCLK clock output, when not used, allows saving power. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLP + PLL VCO division factor P for PLLPCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: +... +The bitfield can be written only when the PLL is disabled. +Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + 17 + 5 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x1F + 32 + 0x1F + + + + + PLLQEN + PLLQCLK clock output enable +This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: +Disabling the PLLQCLK clock output, when not used, allows saving power. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLQ + PLL VCO division factor Q for PLLQCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: +The bitfield can be written only when the PLL is disabled. +Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + 25 + 3 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + PLLREN + PLLRCLK clock output enable +This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: +This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. +Disabling the PLLRCLK clock output, when not used, allows saving power. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLR + PLL VCO division factor R for PLLRCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: +The bitfield can be written only when the PLL is disabled. +The PLLRCLK clock can be selected as system clock. +Caution: The software must set this bitfield so as not to exceed 122MHz on this clock. + 29 + 3 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + + + RCC_CIER + RCC_CIER + Clock interrupt enable register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MSIRDYIE + MSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. + 2 + 1 + read-write + + + B_0x0 + MSI ready interrupt disabled + 0x0 + + + B_0x1 + MSI ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization: + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLRDYIE + PLL ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by PLL lock: + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSIE + LSE clock security system interrupt enable +Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. + 9 + 1 + read-write + + + B_0x0 + Clock security interrupt caused by LSE clock failure disabled + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + 10 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + Clock interrupt flag register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. +Cleared by software setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. +Cleared by software setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + MSIRDYF + MSI ready interrupt flag +Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. +Cleared by software setting the MSIRDYC bit. + 2 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the MSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the MSI oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag +Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +Set by hardware when the HSE clock becomes stable and HSERDYIE is set. +Cleared by software setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + PLLRDYF + PLL ready interrupt flag +Set by hardware when the PLL locks and PLLRDYIE is set. +Cleared by software setting the PLLRDYC bit. + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL lock + 0x1 + + + + + CSSF + HSE clock security system interrupt flag +Set by hardware when a failure is detected in the HSE oscillator. +Cleared by software setting the CSSC bit. + 8 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + LSECSSF + LSE clock security system interrupt flag +Set by hardware when a failure is detected in the LSE oscillator. +Cleared by software by setting the LSECSSC bit. + 9 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by LSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag +Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). +Cleared by software setting the HSI48RDYC bit. + 10 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + Clock interrupt clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +This bit is set by software to clear the LSIRDYF flag. + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSIRDYF flag + 0x1 + + + + + LSERDYC + LSE ready interrupt clear +This bit is set by software to clear the LSERDYF flag. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSERDYF flag + 0x1 + + + + + MSIRDYC + MSI ready interrupt clear +This bit is set by software to clear the MSIRDYF flag. + 2 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + MSIRDYF cleared + 0x1 + + + + + HSIRDYC + HSI16 ready interrupt clear +This bit is set software to clear the HSIRDYF flag. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear +This bit is set by software to clear the HSERDYF flag. + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + PLLRDYC + PLL ready interrupt clear +This bit is set by software to clear the PLLRDYF flag. + 5 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear PLLRDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear +This bit is set by software to clear the HSECSSF flag. + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear +This bit is set by software to clear the LSECSSF flag. + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + HSI48RDYC + HSI48 oscillator ready interrupt clear +This bit is set by software to clear the HSI48RDYF flag. + 10 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSI48RDYC flag + 0x1 + + + + + + + RCC_AHBRSTR + RCC_AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 and DMAMUX reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 and DMAMUX + 0x1 + + + + + DMA2RST + DMA2 and DMAMUX reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA2 and DMAMUX + 0x1 + + + + + FLASHRST + Flash memory interface reset +Set and cleared by software. +This bit can only be set when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset flash memory interface + 0x1 + + + + + CRCRST + CRC reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + RNGRST + Random number generator reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset RNG + 0x1 + + + + + TSCRST + Touch sensing controller reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TSC + 0x1 + + + + + + + RCC_IOPRSTR + RCC_IOPRSTR + I/O port reset register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + I/O port A reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port A + 0x1 + + + + + GPIOBRST + I/O port B reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port B + 0x1 + + + + + GPIOCRST + I/O port C reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port C + 0x1 + + + + + GPIODRST + I/O port D reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port D + 0x1 + + + + + GPIOERST + I/O port E reset +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port E + 0x1 + + + + + GPIOFRST + I/O port F reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port F + 0x1 + + + + + + + RCC_APBRSTR1 + RCC_APBRSTR1 + APB peripheral reset register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM6RST + TIM6 timer reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM6 + 0x1 + + + + + TIM7RST + TIM7 timer reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + LPUART2RST + LPUART2 reset +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART2 + 0x1 + + + + + LCDRST + LCD reset<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LCD + 0x1 + + + + + LPUART3RST + LPUART3 reset<sup>(1)</sup> +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART3 + 0x1 + + + + + USBRST + USB reset<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB + 0x1 + + + + + SPI2RST + SPI2 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + SPI3RST + SPI3 reset<sup>(1)</sup> +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI3 + 0x1 + + + + + CRSRST + CRS reset<sup>(1)</sup> +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRS + 0x1 + + + + + USART2RST + USART2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + USART3RST + USART3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART3 + 0x1 + + + + + USART4RST + USART4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART4 + 0x1 + + + + + LPUART1RST + LPUART1 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART1 + 0x1 + + + + + I2C1RST + I2C1 reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + I2C3RST + I2C3 reset +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C3 + 0x1 + + + + + OPAMPRST + OPAMP reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OPAMP + 0x1 + + + + + I2C4RST + I2C4 reset<sup>(1)</sup> +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C4 + 0x1 + + + + + LPTIM3RST + LPTIM3 reset +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM3 + 0x1 + + + + + PWRRST + Power interface reset +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + DAC1RST + DAC1 interface reset +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC1 interface + 0x1 + + + + + LPTIM2RST + Low Power Timer 2 reset +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM2 + 0x1 + + + + + LPTIM1RST + Low Power Timer 1 reset +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM1 + 0x1 + + + + + + + RCC_APBRSTR2 + RCC_APBRSTR2 + APB peripheral reset register 2 + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG, COMP and VREFBUF reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + COMP + VREFBUF + 0x1 + + + + + TIM1RST + TIM1 timer reset +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + USART1RST + USART1 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + TIM15RST + TIM15 timer reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM15 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + ADCRST + ADC reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC + 0x1 + + + + + + + RCC_AHBENR + RCC_AHBENR + AHB peripheral clock enable register + 0x48 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMA2EN + DMA2 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHEN + Flash memory interface clock enable +Set and cleared by software. +This bit can only be cleared when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCEN + CRC clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RNGEN + Random number generator clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TSCEN + Touch sensing controller clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + TSC clock disable + 0x0 + + + B_0x1 + TSC clock enable + 0x1 + + + + + + + RCC_IOPENR + RCC_IOPENR + I/O port clock enable register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + I/O port A clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBEN + I/O port B clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCEN + I/O port C clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODEN + I/O port D clock enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOEEN + I/O port E clock enable<sup>(1)</sup> +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFEN + I/O port F clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_DBGCFGR + RCC_DBGCFGR + Debug configuration register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBGEN + Debug support clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DBGRST + Debug support reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DBG + 0x1 + + + + + + + RCC_APBENR1 + RCC_APBENR1 + APB peripheral clock enable register 1 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3EN + TIM3 timer clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM6EN + TIM6 timer clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM7EN + TIM7 timer clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART2EN + LPUART2 clock enable +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LCDEN + LCD clock enable<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBEN + RTC APB clock enable +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGEN + WWDG clock enable +Set by software to enable the window watchdog clock. Cleared by hardware system reset +This bit can also be set by hardware if the WWDG_SW option bit is 0. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART3EN + LPUART3 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBEN + USB clock enable<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2EN + SPI2 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI3EN + SPI3 clock enable<sup>(1)</sup> +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRSEN + CRS clock enable<sup>(1)</sup> +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2EN + USART2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART3EN + USART3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART4EN + USART4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART1EN + LPUART1 clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2EN + I2C2 clock enable +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3EN + I2C3 clock enable +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OPAMPEN + OPAMP clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C4EN + I2C4EN clock enable<sup>(1)</sup> +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM3EN + LPTIM3 clock enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWREN + Power interface clock enable +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DAC1EN + DAC1 interface clock enable +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM2EN + LPTIM2 clock enable +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM1EN + LPTIM1 clock enable +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBENR2 + RCC_APBENR2 + APB peripheral clock enable register 2 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1EN + TIM1 timer clock enable +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1EN + SPI1 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1EN + USART1 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM15EN + TIM15 timer clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16EN + TIM16 timer clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCEN + ADC clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_AHBSMENR + RCC_AHBSMENR + AHB peripheral clock enable in Sleep/Stop mode register + 0x68 + 0x20 + 0x01051303 + 0xFFFFFFFF + + + DMA1SMEN + DMA1 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMA2SMEN + DMA2 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHSMEN + Flash memory interface clock enable during Sleep mode +Set and cleared by software. +This bit can be activated only when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SRAMSMEN + SRAM clock enable during Sleep mode +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCSMEN + CRC clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RNGSMEN + RNG clock enable during Sleep and Stop mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TSCSMEN + TSC clock enable during Sleep and Stop mode +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_IOPSMENR + RCC_IOPSMENR + I/O port in Sleep mode clock enable register + 0x6C + 0x20 + 0x0000003F + 0xFFFFFFFF + + + GPIOASMEN + I/O port A clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBSMEN + I/O port B clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCSMEN + I/O port C clock enable during Sleep mode +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODSMEN + I/O port D clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOESMEN + I/O port E clock enable during Sleep mode +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFSMEN + I/O port F clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR1 + RCC_APBSMENR1 + APB peripheral clock enable in Sleep/Stop mode register 1 + 0x78 + 0x20 + 0xFF7E4C33 + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3SMEN + TIM3 timer clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM6SMEN + TIM6 timer clock enable during Sleep mode +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM7SMEN + TIM7 timer clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART2SMEN + LPUART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LCDSMEN + LCD clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep mode +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGSMEN + WWDG clock enable during Sleep and Stop modes +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART3SMEN + LPUART3 clock enable during Sleep and Stop modes +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBSMEN + USB clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2SMEN + SPI2 clock enable during Sleep mode +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI3SMEN + SPI3 clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRSSMEN + CRS clock enable during Sleep and Stop modes<sup>(1)</sup> +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2SMEN + USART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART3SMEN + USART3 clock enable during Sleep mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART4SMEN + USART4 clock enable during Sleep mode +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART1SMEN + LPUART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1SMEN + I2C1 clock enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2SMEN + I2C2 clock enable during Sleep mode +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3SMEN + I2C3 clock enable during Sleep mode +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OPAMPSMEN + OPAMP clock enable during Sleep and Stop modes +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C4SMEN + I2C4 clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM3SMEN + Low power timer 3 clock enable during Sleep mode +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWRSMEN + Power interface clock enable during Sleep mode +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DAC1SMEN + DAC1 interface clock enable during Sleep and Stop modes +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM2SMEN + Low Power Timer 2 clock enable during Sleep and Stop modes +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM1SMEN + Low Power Timer 1 clock enable during Sleep and Stop modes +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR2 + RCC_APBSMENR2 + APB peripheral clock enable in Sleep/Stop mode register 2 + 0x80 + 0x20 + 0x0017D801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1SMEN + TIM1 timer clock enable during Sleep mode +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1SMEN + SPI1 clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1SMEN + USART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM15SMEN + TIM15 timer clock enable during Sleep mode +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16SMEN + TIM16 timer clock enable during Sleep mode +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCSMEN + ADC clock enable during Sleep mode +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_CCIPR + RCC_CCIPR + Peripherals independent clock configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection +This bitfield is controlled by software to select USART1 clock source as follows: + 0 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + USART2SEL + USART2 clock source selection +This bitfield is controlled by software to select USART2 clock source as follows: + 2 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART3SEL + LPUART3 clock source selection<sup>(1)</sup> +This bitfield is controlled by software to select LPUART3 clock source as follows: + 6 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART2SEL + LPUART2 clock source selection +This bitfield is controlled by software to select LPUART2 clock source as follows: + 8 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART1SEL + LPUART1 clock source selection +This bitfield is controlled by software to select LPUART1 clock source as follows: + 10 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + I2C1SEL + I2C1 clock source selection +This bitfield is controlled by software to select I2C1 clock source as follows: + 12 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + I2C3SEL + I2C3 clock source selection +This bitfield is controlled by software to select I2C3 clock source as follows: + 16 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + LPTIM1SEL + LPTIM1 clock source selection +This bitfield is controlled by software to select LPTIM1 clock source as follows: + 18 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPTIM2SEL + LPTIM2 clock source selection +This bitfield is controlled by software to select LPTIM2 clock source as follows: + 20 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPTIM3SEL + LPTIM3 clock source selection +This bitfield is controlled by software to select LPTIM3 clock source as follows: + 22 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + TIM1SEL + TIM1 clock source selection +This bit is set and cleared by software. It selects TIM1 clock source as follows: + 24 + 1 + read-write + + + B_0x0 + TIMPCLK + 0x0 + + + B_0x1 + PLLQCLK + 0x1 + + + + + TIM15SEL + TIM15 clock source selection +This bit is set and cleared by software. It selects TIM15 clock source as follows: + 25 + 1 + read-write + + + B_0x0 + TIMPCLK + 0x0 + + + B_0x1 + PLLQCLK + 0x1 + + + + + CLK48SEL + 481MHz clock source selection +This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG: + 26 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + MSI + 0x1 + + + B_0x2 + PLLQCLK + 0x2 + + + B_0x3 + HSI48<sup>(1)</sup> + 0x3 + + + + + ADCSEL + ADCs clock source selection +This bitfield is controlled by software to select the clock source for ADC: + 28 + 2 + read-write + + + B_0x0 + System clock + 0x0 + + + B_0x1 + PLLPCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + + + RCC_BDCR + RCC_BDCR + RTC domain control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +Set and cleared by software to enable LSE oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): +After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and cleared by software to bypass the LSE oscillator (in debug mode). +This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0). + 2 + 1 + read-write + + + B_0x0 + Not bypassed + 0x0 + + + B_0x1 + Bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +Set by software to select the LSE oscillator drive capability as follows: +Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. + 3 + 2 + read-write + + + B_0x0 + low driving capability + 0x0 + + + B_0x1 + medium-low driving capability + 0x1 + + + B_0x2 + medium-high driving capability + 0x2 + + + B_0x3 + high driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable +Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: +LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD +=1). In that case the software must disable the LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection +Set by hardware to indicate when a failure is detected by the clock security system +on the external 321kHz oscillator (LSE): + 6 + 1 + read-only + + + B_0x0 + No failure detected + 0x0 + + + B_0x1 + Failure detected + 0x1 + + + + + LSESYSEN + LSE clock enable for system usage +This bit must be set by software to enable the LSE clock for a system usage. + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled, LSE distributed to peripherals including LSCO/MCO/SYSCLK. + 0x1 + + + + + RTCSEL + RTC clock source selection +Set by software to select the clock source for the RTC as follows: +Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00. + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE + 0x1 + + + B_0x2 + LSI + 0x2 + + + B_0x3 + HSE divided by 32 + 0x3 + + + + + LSESYSRDY + LSE clock ready for system usage +This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. +Cleared by hardware to indicate that the LSE clock is not ready to be used by the system. + 11 + 1 + read-only + + + B_0x0 + LSE clock not ready for system + 0x0 + + + B_0x1 + LSE clock ready for system + 0x1 + + + + + RTCEN + RTC clock enable +Set and cleared by software. The bit enables clock to RTC and TAMP. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + BDRST + RTC domain software reset +Set and cleared by software to reset the RTC domain: + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSCOSEL + Low-speed clock output selection +Set and cleared by software to select the low-speed output clock: + 25 + 1 + read-write + + + B_0x0 + LSI + 0x0 + + + B_0x1 + LSE + 0x1 + + + + + + + RCC_CSR + RCC_CSR + Control/status register + 0x94 + 0x20 + 0x00000000 + 0x00FFFFFF + + + LSION + LSI oscillator enable +Set and cleared by software to enable/disable the LSI oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): +After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSIPREDIV + Internal low-speed oscillator pre-divided by 128 +Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit. + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator is not divided + 0x0 + + + B_0x1 + LSI RC oscillator is divided by 128 + 0x1 + + + + + MSISRANGE + MSI range after Standby mode +Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. +Others: Reserved +Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency. + 8 + 4 + read-write + + + B_0x4 + Range 7 around 81MHz + 0x4 + + + + + RMVF + Remove reset flags +Set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag +Set by hardware when a reset from the Option byte loading occurs. +Cleared by setting the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from Option byte loading occurred + 0x0 + + + B_0x1 + Reset from Option byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag +Set by hardware when a reset from the NRST pin occurs. +Cleared by setting the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + PWRRSTF + BOR or POR/PDR flag +Set by hardware when a BOR or POR/PDR occurs. +Cleared by setting the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR or POR occurred + 0x0 + + + B_0x1 + BOR or POR occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Set by hardware when a software reset occurs. +Cleared by setting the RMVF bit. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag +Set by hardware when an independent watchdog reset domain occurs. +Cleared by setting the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +Set by hardware when a window watchdog reset occurs. +Cleared by setting the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. +Cleared by setting the RMVF bit. +This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared. + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x98 + 0x20 + 0x00008800 + 0x0000FFFF + + + HSI48ON + HSI48 RC oscillator enable<sup>(1)</sup> + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag<sup>(1)</sup> +The flag is set when the HSI48 clock is ready for use. + 1 + 1 + read-only + + + HSI48CAL + HSI48 clock calibration +These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + 7 + 9 + read-only + + + + + + + RNG + RNG address block description + RNG + 0x40025000 + + 0x0 + 0x14 + registers + + + + RNG_CR + RNG_CR + RNG control register + 0x000 + 0x20 + 0x00800D00 + 0xFFFFFFFF + + + RNGEN + True random number generator enable + 2 + 1 + read-write + + + B_0x0 + True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. + 0x0 + + + B_0x1 + True random number generator is enabled. + 0x1 + + + + + IE + Interrupt enable + 3 + 1 + read-write + + + B_0x0 + RNG interrupt is disabled + 0x0 + + + B_0x1 + RNG interrupt is enabled. An interrupt is pending as soon as DRDY1=11, SEIS1=11 or CEIS1=11 in the RNG_SR register. + 0x1 + + + + + CED + Clock error detection +The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED, the RNG must be disabled. +Writing this bit is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 5 + 1 + read-write + + + B_0x0 + Clock error detection enabled + 0x0 + + + B_0x1 + Clock error detection is disabled + 0x1 + + + + + ARDIS + Auto reset disable +When auto-reset is enabled the application still need to clear the SEIS bit after a noise source error. +Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 7 + 1 + read-write + + + B_0x0 + When a noise source error occurs RNG performs an automatic reset to clear the SECS bit. + 0x0 + + + B_0x1 + When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation. + 0x1 + + + + + RNG_CONFIG3 + RNG configuration 3 +Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. +If the NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG. + 8 + 4 + read-write + + + NISTC + NIST custom +two conditioning loops are performed and 256 bits of noise source are used. +Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 12 + 1 + read-write + + + B_0x0 + Hardware default values for NIST compliant RNG. In this configuration per 128-bit output + 0x0 + + + B_0x1 + Custom values for NIST compliant RNG. See Section120.6: RNG entropy source validation for proposed configuration. + 0x1 + + + + + RNG_CONFIG2 + RNG configuration 2 +Reserved to the RNG configuration (bitfield 2). Bit 13 can be set when RNG power consumption is critical. See Section120.3.8: RNG low-power use. Refer to the RNG_CONFIG1 bitfield for details. + 13 + 3 + read-write + + + CLKDIV + Clock divider factor +This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN1=10). +... +Writing these bits is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 16 + 4 + read-write + + + B_0x0 + internal RNG clock after divider is similar to incoming RNG clock. + 0x0 + + + B_0x1 + two RNG clock cycles per internal RNG clock. + 0x1 + + + B_0x2 + 2<sup>2</sup> (= 4) RNG clock cycles per internal RNG clock. + 0x2 + + + B_0xF + 2<sup>15</sup> RNG clock cycles per internal clock (for example. an incoming 481MHz RNG clock becomes a 1.51kHz internal RNG clock) + 0xF + + + + + RNG_CONFIG1 + RNG configuration 1 +Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section120.6: RNG entropy source validation. +Writing any bit of RNG_CONFIG1 is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 20 + 6 + read-write + + + CONDRST + Conditioning soft reset +Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_HTCR are not changed by CONDRST. +This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. +When CONDRST is set to 0 by the software, its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles. + 30 + 1 + read-write + + + CONFIGLOCK + RNG Config lock +This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset. + 31 + 1 + read-write + + + B_0x0 + Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. + 0x0 + + + B_0x1 + Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG status register + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DRDY + Data ready +Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. +Note: The DRDY bit can rise when the peripheral is disabled (RNGEN1=10 in the RNG_CR register). +If IE=1 in the RNG_CR register, an interrupt is generated when DRDY1=11. + 0 + 1 + read-only + + + B_0x0 + The RNG_DR register is not yet valid, no random data is available. + 0x0 + + + B_0x1 + The RNG_DR register contains valid random data. + 0x1 + + + + + CECS + Clock error current status +Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. + 1 + 1 + read-only + + + B_0x0 + The RNG clock is correct (f<sub>RNGCLK</sub>> f<sub>HCLK</sub>/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. + 0x0 + + + B_0x1 + The RNG clock is too slow (f<sub>RNGCLK</sub>< f<sub>HCLK</sub>/32). + 0x1 + + + + + SECS + Seed error current status +Runtime repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) +Startup or continuous adaptive proportion test on noise source failed. +Startup post-processing/conditioning sanity check failed. + 2 + 1 + read-only + + + B_0x0 + No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. + 0x0 + + + B_0x1 + At least one of the following faulty sequences has been detected: + 0x1 + + + + + CEIS + Clock error interrupt status +This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 5 + 1 + read-write + + + B_0x0 + The RNG clock is correct (f<sub>RNGCLK</sub>> f<sub>HCLK</sub>/32) + 0x0 + + + B_0x1 + The RNG clock before the internal divider is detected too slow (f<sub>RNGCLK</sub>< f<sub>HCLK</sub>/32) + 0x1 + + + + + SEIS + Seed error interrupt status +This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 6 + 1 + read-write + + + B_0x0 + No faulty sequence detected + 0x0 + + + B_0x1 + At least one faulty sequence is detected. See SECS bit description for details. + 0x1 + + + + + + + RNG_DR + RNG_DR + RNG data register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNDATA + Random data +32-bit random data, which are valid when DRDY1=11. When DRDY1=10, the RNDATA value is1zero. +When DRDY is set, it is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). + 0 + 32 + read-only + + + + + RNG_HTCR + RNG_HTCR + RNG health test control register + 0x010 + 0x20 + 0x000072AC + 0xFFFFFFFF + + + HTCFG + health test configuration +This configuration is used by RNG to configure the health tests. See Section120.6: RNG entropy source validation for the recommended value. +Note: The RNG behavior, including the read to this register, is not guaranteed if a different value from the recommended value is written. + 0 + 32 + read-write + + + + + + + RTC + RTC register block + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP + RTC and TAMP interrupts(combined EXTI lines 19 and 21) + 2 + + + + RTC_TR + RTC_TR + RTC time register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_DR + RTC_DR + RTC date register + 0x04 + 0x20 + 0x00002101 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-write + + + DT + Date tens in BCD format + 4 + 2 + read-write + + + MU + Month units in BCD format + 8 + 4 + read-write + + + MT + Month tens in BCD format + 12 + 1 + read-write + + + WDU + Week day units +... + 13 + 3 + read-write + + + B_0x0 + forbidden + 0x0 + + + B_0x1 + Monday + 0x1 + + + B_0x7 + Sunday + 0x7 + + + + + YU + Year units in BCD format + 16 + 4 + read-write + + + YT + Year tens in BCD format + 20 + 4 + read-write + + + + + RTC_SSR + RTC_SSR + RTC subsecond register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous binary counter +SS[31:16]: Synchronous binary counter MSB values +When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): +SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter. +When BCD mode is selected (BIN=00): +SS[31:16] are forced by hardware to 0x0000. +SS[15:0]: Subsecond value/synchronous binary counter LSB values +When Binary mode is selected (BIN = 01 or 10 or 11): +SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter. +When BCD mode is selected (BIN=00): +SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: +Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) +SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. + 0 + 32 + read-only + + + + + RTC_ICSR + RTC_ICSR + RTC initialization control and status register + 0x0C + 0x20 + 0x00000007 + 0xFFFFFFFF + + + WUTWF + Wake-up timer write flag +This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. + 2 + 1 + read-only + + + B_0x0 + Wake-up timer configuration update not allowed except in initialization mode + 0x0 + + + B_0x1 + Wake-up timer configuration update allowed + 0x1 + + + + + SHPF + Shift operation pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-only + + + B_0x0 + No shift operation is pending + 0x0 + + + B_0x1 + A shift operation is pending + 0x1 + + + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). + 4 + 1 + read-only + + + B_0x0 + Calendar has not been initialized + 0x0 + + + B_0x1 + Calendar has been initialized + 0x1 + + + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. + 5 + 1 + read-write + + + B_0x0 + Calendar shadow registers not yet synchronized + 0x0 + + + B_0x1 + Calendar shadow registers synchronized + 0x1 + + + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. + 6 + 1 + read-only + + + B_0x0 + Calendar registers update is not allowed + 0x0 + + + B_0x1 + Calendar registers update is allowed + 0x1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + + B_0x0 + Free running mode + 0x0 + + + B_0x1 + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. Counters are stopped and start counting from the new value when INIT is reset. + 0x1 + + + + + BIN + Binary mode + 8 + 2 + read-write + + + B_0x0 + Free running BCD calendar mode (Binary mode disabled). + 0x0 + + + B_0x1 + Free running Binary mode (BCD mode disabled) + 0x1 + + + B_0x2 + Free running BCD calendar and Binary modes + 0x2 + + + B_0x3 + Free running BCD calendar and Binary modes + 0x3 + + + + + BCDU + BCD update (BIN = 10 or 11) +In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits. + 10 + 3 + read-write + + + B_0x0 + 1s calendar increment is generated each time SS[7:0] = 0 + 0x0 + + + B_0x1 + 1s calendar increment is generated each time SS[8:0] = 0 + 0x1 + + + B_0x2 + 1s calendar increment is generated each time SS[9:0] = 0 + 0x2 + + + B_0x3 + 1s calendar increment is generated each time SS[10:0] = 0 + 0x3 + + + B_0x4 + 1s calendar increment is generated each time SS[11:0] = 0 + 0x4 + + + B_0x5 + 1s calendar increment is generated each time SS[12:0] = 0 + 0x5 + + + B_0x6 + 1s calendar increment is generated each time SS[13:0] = 0 + 0x6 + + + B_0x7 + 1s calendar increment is generated each time SS[14:0] = 0 + 0x7 + + + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + RTC prescaler register + 0x10 + 0x20 + 0x007F00FF + 0xFFFFFFFF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC wake-up timer register + 0x14 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + WUT + Wake-up auto-reload value bits +When the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]1+11) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. +When WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs between WUT and (WUT + 2) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + WUTOCLR + Wake-up auto-reload output clear value +When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto-reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0]. +When WUTOCLR[15:0] = 0x0000, WUTF is set by hardware when the WUT down-counter +reaches 0 and is cleared by software. + 16 + 16 + read-write + + + + + RTC_CR + RTC_CR + RTC control register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUCKSEL + ck_wut wake-up clock selection +10x: ck_spre (usually 11Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. +11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 2<sup>16</sup> is added to the WUT counter value. + 0 + 3 + read-write + + + B_0x0 + RTC/16 clock is selected + 0x0 + + + B_0x1 + RTC/8 clock is selected + 0x1 + + + B_0x2 + RTC/4 clock is selected + 0x2 + + + B_0x3 + RTC/2 clock is selected + 0x3 + + + + + TSEDGE + Timestamp event active edge +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + B_0x0 + RTC_TS input rising edge generates a timestamp event + 0x0 + + + B_0x1 + RTC_TS input falling edge generates a timestamp event + 0x1 + + + + + REFCKON + RTC_REFIN reference clock detection enable (50 or 601Hz) +Note: BIN must be 0x00 and PREDIV_S must be 0x00FF. + 4 + 1 + read-write + + + B_0x0 + RTC_REFIN detection disabled + 0x0 + + + B_0x1 + RTC_REFIN detection enabled + 0x1 + + + + + BYPSHAD + Bypass the shadow registers +Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. + 5 + 1 + read-write + + + B_0x0 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. + 0x0 + + + B_0x1 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 0x1 + + + + + FMT + Hour format + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + SSRUIE + SSR underflow interrupt enable + 7 + 1 + read-write + + + B_0x0 + SSR underflow interrupt disabled + 0x0 + + + B_0x1 + SSR underflow interrupt enabled + 0x1 + + + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + B_0x0 + Alarm A disabled + 0x0 + + + B_0x1 + Alarm A enabled + 0x1 + + + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + B_0x0 + Alarm B disabled + 0x0 + + + B_0x1 + Alarm B enabled + 0x1 + + + + + WUTE + Wake-up timer enable +Note: When the wake-up timer is disabled, wait for WUTWF = 1 before enabling it again. + 10 + 1 + read-write + + + B_0x0 + Wake-up timer disabled + 0x0 + + + B_0x1 + Wake-up timer enabled + 0x1 + + + + + TSE + timestamp enable + 11 + 1 + read-write + + + B_0x0 + timestamp disable + 0x0 + + + B_0x1 + timestamp enable + 0x1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + B_0x0 + Alarm A interrupt disabled + 0x0 + + + B_0x1 + Alarm A interrupt enabled + 0x1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + B_0x0 + Alarm B interrupt disable + 0x0 + + + B_0x1 + Alarm B interrupt enable + 0x1 + + + + + WUTIE + Wake-up timer interrupt enable + 14 + 1 + read-write + + + B_0x0 + Wake-up timer interrupt disabled + 0x0 + + + B_0x1 + Wake-up timer interrupt enabled + 0x1 + + + + + TSIE + Timestamp interrupt enable + 15 + 1 + read-write + + + B_0x0 + Timestamp interrupt disable + 0x0 + + + B_0x1 + Timestamp interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. + 16 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Adds 1 hour to the current time. This can be used for summer time change + 0x1 + + + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. + 17 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Subtracts 1 hour to the current time. This can be used for winter time change. + 0x1 + + + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE = 1, this bit selects which signal is output on CALIB. +These frequencies are valid for RTCCLK at 32.7681kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section128.3.16: Calibration clock output. + 19 + 1 + read-write + + + B_0x0 + Calibration output is 5121Hz + 0x0 + + + B_0x1 + Calibration output is 11Hz + 0x1 + + + + + POL + Output polarity +This bit is used to configure the polarity of TAMPALRM output. + 20 + 1 + read-write + + + B_0x0 + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x0 + + + B_0x1 + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x1 + + + + + OSEL + Output selection +These bits are used to select the flag to be routed to TAMPALRM output. + 21 + 2 + read-write + + + B_0x0 + Output disabled + 0x0 + + + B_0x1 + Alarm A output enabled + 0x1 + + + B_0x2 + Alarm B output enabled + 0x2 + + + B_0x3 + Wake-up output enabled + 0x3 + + + + + COE + Calibration output enable +This bit enables the CALIB output + 23 + 1 + read-write + + + B_0x0 + Calibration output disabled + 0x0 + + + B_0x1 + Calibration output enabled + 0x1 + + + + + ITSE + timestamp on internal event enable + 24 + 1 + read-write + + + B_0x0 + internal event timestamp disabled + 0x0 + + + B_0x1 + internal event timestamp enabled + 0x1 + + + + + TAMPTS + Activate timestamp on tamper detection event +TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. +Note: TAMPTS must be cleared before entering RTC initialization mode. + 25 + 1 + read-write + + + B_0x0 + Tamper detection event does not cause a RTC timestamp to be saved + 0x0 + + + B_0x1 + Save RTC timestamp on tamper detection event + 0x1 + + + + + TAMPOE + Tamper detection output enable on TAMPALRM + 26 + 1 + read-write + + + B_0x0 + The tamper flag is not routed on TAMPALRM + 0x0 + + + B_0x1 + The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. + 0x1 + + + + + ALRAFCLR + Alarm A flag automatic clear + 27 + 1 + read-write + + + B_0x0 + Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm A event generates a trigger event. ALRAF is automatically cleared by hardware after 1 ck_apre cycle. + 0x1 + + + + + ALRBFCLR + Alarm B flag automatic clear + 28 + 1 + read-write + + + B_0x0 + Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm B event generates a trigger event. ALRBF is automatically cleared by hardware after 1 ck_apre cycle. + 0x1 + + + + + TAMPALRM_PU + TAMPALRM pull-up enable + 29 + 1 + read-write + + + B_0x0 + No pull-up is applied on TAMPALRM output + 0x0 + + + B_0x1 + A pull-up is applied on TAMPALRM output + 0x1 + + + + + TAMPALRM_TYPE + TAMPALRM output type + 30 + 1 + read-write + + + B_0x0 + TAMPALRM is push-pull output + 0x0 + + + B_0x1 + TAMPALRM is open-drain output + 0x1 + + + + + OUT2EN + RTC_OUT2 output enable + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00. +Refer to RTC register write protection for a description of how to unlock RTC register write protection. + 0 + 8 + write-only + + + + + RTC_CALR + RTC_CALR + RTC calibration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 2<sup>20</sup> RTCCLK pulses (321seconds if the input frequency is 327681Hz). This decreases the frequency of the calendar with a resolution of 0.95371ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section128.3.14: RTC smooth digital calibration on page1733. + 0 + 9 + read-write + + + LPCAL + RTC low-power mode + 12 + 1 + read-write + + + B_0x0 + Calibration window is 2<sup>20</sup> RTCCLK, which is a high-consumption mode. This mode must be set only when less than 32s calibration window is required. + 0x0 + + + B_0x1 + Calibration window is 2<sup>20</sup> ck_apre, which is the required configuration for ultra-low consumption mode. + 0x1 + + + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. +Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section128.3.14: RTC smooth digital calibration. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1, the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section128.3.14: RTC smooth digital calibration. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.51ppm. + 15 + 1 + read-write + + + B_0x0 + No RTCCLK pulses are added. + 0x0 + + + B_0x1 + One RTCCLK pulse is effectively inserted every 2<sup>11</sup> pulses (frequency increased by 488.51ppm). + 0x1 + + + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC shift control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / (PREDIV_S + 1) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: +Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). +In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0. +Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. + 0 + 15 + write-only + + + ADD1S + Add one second +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Add one second to the clock/calendar + 0x1 + + + + + + + RTC_TSTR + RTC_TSTR + RTC timestamp time register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-only + + + ST + Second tens in BCD format. + 4 + 3 + read-only + + + MNU + Minute units in BCD format. + 8 + 4 + read-only + + + MNT + Minute tens in BCD format. + 12 + 3 + read-only + + + HU + Hour units in BCD format. + 16 + 4 + read-only + + + HT + Hour tens in BCD format. + 20 + 2 + read-only + + + PM + AM/PM notation + 22 + 1 + read-only + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_TSDR + RTC_TSDR + RTC timestamp date register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-only + + + DT + Date tens in BCD format + 4 + 2 + read-only + + + MU + Month units in BCD format + 8 + 4 + read-only + + + MT + Month tens in BCD format + 12 + 1 + read-only + + + WDU + Week day units + 13 + 3 + read-only + + + + + RTC_TSSSR + RTC_TSSSR + RTC timestamp subsecond register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subsecond value/synchronous binary counter values +SS[31:0] is the value of the synchronous prescaler counter when the timestamp event occurred. + 0 + 32 + read-only + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC alarm A register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm A set if the seconds match + 0x0 + + + B_0x1 + Seconds dont care in alarm A comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm A set if the minutes match + 0x0 + + + B_0x1 + Minutes dont care in alarm A comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm A hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm A set if the hours match + 0x0 + + + B_0x1 + Hours dont care in alarm A comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is dont care. + 0x1 + + + + + MSK4 + Alarm A date mask + 31 + 1 + read-write + + + B_0x0 + Alarm A set if the date/day match + 0x0 + + + B_0x1 + Date/day dont care in alarm A comparison + 0x1 + + + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC alarm A subsecond register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. +This field is the mirror of SS[14:0] in the RTC_ALRABINR, and so can also be read or written through RTC_ALRABINR. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +From 32 to 63: All 32 SS bits are compared and must match to activate alarm. +Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[31:1] are dont care in Alarm A comparison. Only SS[0] is compared. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) +Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRABINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRABINR.SS[31:0]. + 0x1 + + + + + + + RTC_ALRMBR + RTC_ALRMBR + RTC alarm B register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MSK1 + Alarm B seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm B set if the seconds match + 0x0 + + + B_0x1 + Seconds dont care in alarm B comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm B minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm B set if the minutes match + 0x0 + + + B_0x1 + Minutes dont care in alarm B comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm B hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm B set if the hours match + 0x0 + + + B_0x1 + Hours dont care in alarm B comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is dont care. + 0x1 + + + + + MSK4 + Alarm B date mask + 31 + 1 + read-write + + + B_0x0 + Alarm B set if the date and day match + 0x0 + + + B_0x1 + Date and day dont care in alarm B comparison + 0x1 + + + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + RTC alarm B subsecond register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. +This field is the mirror of SS[14:0] in the RTC_ALRBBINR, and so can also be read or written through RTC_ALRBBINR. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +From 32 to 63: All 32 SS bits are compared and must match to activate alarm. +Note: In BCD mode (BIN=00)The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[31:1] are dont care in Alarm B comparison. Only SS[0] is compared. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) +Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRBBINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRBBINR.SS[31:0]. + 0x1 + + + + + + + RTC_SR + RTC_SR + RTC status register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). + 0 + 1 + read-only + + + ALRBF + Alarm B flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR). + 1 + 1 + read-only + + + WUTF + Wake-up timer flag +This flag is set by hardware when the wake-up auto-reload counter reaches 0. +If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wake-up auto-reload counter reaches WUTOCLR value. +If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 2 + 1 + read-only + + + TSF + Timestamp flag +This flag is set by hardware when a timestamp event occurs. +If ITSF flag is set, TSF must be cleared together with ITSF. +Note: TSF is not set if TAMPTS1=11 and the tamper flag is read during the 3 ck_apre cycles following tamper event. Refer to Timestamp on tamper event for more details. + 3 + 1 + read-only + + + TSOVF + Timestamp overflow flag +This flag is set by hardware when a timestamp event occurs while TSF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + ITSF + Internal timestamp flag +This flag is set by hardware when a timestamp on the internal event occurs. + 5 + 1 + read-only + + + SSRUF + SSR underflow flag +This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1. + 6 + 1 + read-only + + + + + RTC_MISR + RTC_MISR + RTC masked interrupt status register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A masked flag +This flag is set by hardware when the alarm A interrupt occurs. + 0 + 1 + read-only + + + ALRBMF + Alarm B masked flag +This flag is set by hardware when the alarm B interrupt occurs. + 1 + 1 + read-only + + + WUTMF + Wake-up timer masked flag +This flag is set by hardware when the wake-up timer interrupt occurs. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 2 + 1 + read-only + + + TSMF + Timestamp masked flag +This flag is set by hardware when a timestamp interrupt occurs. +If ITSF flag is set, TSF must be cleared together with ITSF. + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow masked flag +This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + ITSMF + Internal timestamp masked flag +This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. + 5 + 1 + read-only + + + SSRUMF + SSR underflow masked flag +This flag is set by hardware when the SSR underflow interrupt occurs. + 6 + 1 + read-only + + + + + RTC_SCR + RTC_SCR + RTC status clear register + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALRAF + Clear alarm A flag +Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. + 0 + 1 + write-only + + + CALRBF + Clear alarm B flag +Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. + 1 + 1 + write-only + + + CWUTF + Clear wake-up timer flag +Writing 1 in this bit clears the WUTF bit in the RTC_SR register. + 2 + 1 + write-only + + + CTSF + Clear timestamp flag +Writing 1 in this bit clears the TSF bit in the RTC_SR register. +If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. + 3 + 1 + write-only + + + CTSOVF + Clear timestamp overflow flag +Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + write-only + + + CITSF + Clear internal timestamp flag +Writing 1 in this bit clears the ITSF bit in the RTC_SR register. + 5 + 1 + write-only + + + CSSRUF + Clear SSR underflow flag +Writing 1 in this bit clears the SSRUF in the RTC_SR register. + 6 + 1 + write-only + + + + + RTC_ALRABINR + RTC_ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode +This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. +SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR. + 0 + 32 + read-write + + + + + RTC_ALRBBINR + RTC_ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode +This value is compared with the contents of the synchronous counter to determine if Alarm Bis to be activated. Only bits 0 up MASKSS-1 are compared. +SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMBSSRR, and so can also be read or written through RTC_ALRMBSSR. + 0 + 32 + read-write + + + + + + + SPI1 + SPI address block description + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 25 + + + + SPI_CR1 + SPI_CR1 + SPI control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page1954. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPI_DR register. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPI_CR2 + SPI_CR2 + SPI control register 2 + 0x04 + 16 + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). +Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). +Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPI_SR + SPI_SR + SPI status register + 0x08 + 16 + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPI_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPI_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section1: Mode fault (MODF) on page1964 for the software sequence. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section133.4.10: SPI status flags and Procedure for disabling the SPI on page1954. + 7 + 1 + read-only + + + B_0x0 + SPI not busy + 0x0 + + + B_0x1 + SPI is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode. Refer to Section133.4.11: SPI error flags. +This flag is set by hardware and reset when SPI_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPI_DR + SPI_DR + SPI data register + 0x0C + 16 + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section133.4.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_CRCPR + SPI_CRCPR + SPI CRC polynomial register + 0x10 + 16 + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_RXCRCR + SPI_RXCRCR + SPI Rx CRC register + 0x14 + 16 + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_TXCRCR + SPI_TXCRCR + SPI Tx CRC register + 0x18 + 16 + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + + + SPI2 + 0x40003800 + + SPI2_SPI3 + SPI2/3 global interrupt + 26 + + + + SPI3 + 0x40003C00 + + + SYSCFG + SYSCFG register block + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + SYSCFG configuration register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + MEM_MODE + Memory mapping selection bits +These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. +X0: Main flash memory mapped at 0x000010000 + 0 + 2 + read-write + + + B_0x1 + System flash memory mapped at 0x000010000 + 0x1 + + + B_0x3 + Embedded SRAM mapped at 0x000010000 + 0x3 + + + + + PA11_RMP + PA11 pin remapping +This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. + 3 + 1 + read-write + + + B_0x0 + No remap (PA11) + 0x0 + + + B_0x1 + Remap (PA9) + 0x1 + + + + + PA12_RMP + PA12 pin remapping +This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. + 4 + 1 + read-write + + + B_0x0 + No remap (PA12) + 0x0 + + + B_0x1 + Remap (PA10) + 0x1 + + + + + IR_POL + IR output polarity selection + 5 + 1 + read-write + + + B_0x0 + Output of IRTIM (IR_OUT) is not inverted + 0x0 + + + B_0x1 + Output of IRTIM (IR_OUT) is inverted + 0x1 + + + + + IR_MOD + IR Modulation Envelope signal selection +This bitfield selects the signal for IR modulation envelope: + 6 + 2 + read-write + + + B_0x0 + TIM16 + 0x0 + + + B_0x1 + USART1 + 0x1 + + + B_0x2 + USART2 + 0x2 + + + + + BOOSTEN + I/O analog switch voltage booster enable +This bit selects the way of supplying I/O analog switches: +When using the analog inputs , setting to 0 is recommended for high V<sub>DD</sub>, setting to 1 for low V<sub>DD</sub> (less than 2.4 V). + 8 + 1 + read-write + + + B_0x0 + V<sub>DD</sub> + 0x0 + + + B_0x1 + Dedicated voltage booster (supplied by V<sub>DD</sub>) + 0x1 + + + + + I2C_PB6_FMP + Fast Mode Plus (FM+) enable for PB6 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB6 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB7_FMP + Fast Mode Plus (FM+) enable for PB7 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB7 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB8_FMP + Fast Mode Plus (FM+) enable for PB8 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB8 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB9_FMP + Fast Mode Plus (FM+) enable for PB9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB9 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA9_FMP + Fast Mode Plus (FM+) enable for PA9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA9 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA10_FMP + Fast Mode Plus (FM+) enable for PA10 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA10 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3_FMP + Fast Mode Plus (FM+) enable for I2C3 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + SYSCFG configuration register 2 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCL + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP bit enable bit +This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input. + 0 + 1 + read-write + + + B_0x0 + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP output disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP output connected to TIM1/15/16 Break input + 0x1 + + + + + SPL + SRAM1 parity lock bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input. + 1 + 1 + read-write + + + B_0x0 + SRAM1 parity error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + SRAM1 parity error connected to TIM1/15/16 Break input + 0x1 + + + + + PVDL + PVD lock enable bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. + 2 + 1 + read-write + + + B_0x0 + PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be programmed by the application. + 0x0 + + + B_0x1 + PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read only. + 0x1 + + + + + ECCL + ECC error lock bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input. + 3 + 1 + read-write + + + B_0x0 + ECC error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + ECC error connected to TIM1/15/16 Break input + 0x1 + + + + + BKPL + Backup SRAM2 parity lock +This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input. + 4 + 1 + read-write + + + B_0x0 + SRAM2 parity error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + SRAM2 parity error connected to TIM1/15/16 Break input + 0x1 + + + + + BKPF + Backup SRAM2 parity error flag +This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1. + 7 + 1 + read-write + + + B_0x0 + No SRAM2 parity error detected + 0x0 + + + B_0x1 + SRAM2 parity error detected + 0x1 + + + + + SPF + SRAM1 parity error flag +This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1. + 8 + 1 + read-write + + + B_0x0 + No SRAM1 parity error detected + 0x0 + + + B_0x1 + SRAM1 parity error detected + 0x1 + + + + + + + SYSCFG_SCSR + SYSCFG_SCSR + SYSCFG SRAM2 control and status register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRAM2ER + SRAM2 erase +Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. +Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. + 0 + 1 + read-write + + + SRAM2BSY + SRAM2 busy by erase operation + 1 + 1 + read-only + + + B_0x0 + No SRAM2 erase operation is ongoing + 0x0 + + + B_0x1 + SRAM2 erase operation is ongoing + 0x1 + + + + + + + SYSCFG_SKR + SYSCFG_SKR + SYSCFG SRAM2 key register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + SRAM2 write protection key for software erase +The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: +Write 0xCA into KEY[7:0] +Write 0x53 into KEY[7:0] +Writing a wrong key reactivates the write protection. + 0 + 8 + write-only + + + + + SYSCFG_TSCCR + SYSCFG_TSCCR + SYSCFG TSC comparator register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G2_IO1 + Comparator mode for group 2 on I/O 1 + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PB4 to COMP2 + 0x1 + + + + + G2_IO3 + Comparator mode for group 2 on I/O 3 + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PB6 to COMP2 + 0x1 + + + + + G4_IO3 + Comparator mode for group 4 on I/O 3 + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PC6 to COMP2 + 0x1 + + + + + G6_IO1 + Comparator mode for group 6 on I/O 1 + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PD10 to COMP1 + 0x1 + + + + + G7_IO1 + Comparator mode for group 7 on I/O 1 + 4 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PA9 to COMP1 + 0x1 + + + + + TSC_IOCTRL + I/O control in comparator mode +The I/O control in comparator mode can be overwritten by hardware. + 5 + 1 + read-write + + + B_0x0 + I/O configured through the corresponding control register + 0x0 + + + B_0x1 + I/O configured as analog when TSC AF is activated + 0x1 + + + + + + + SYSCFG_ITLINE0 + SYSCFG_ITLINE0 + SYSCFG interrupt line 0 status register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WWDG + Window watchdog interrupt pending flag + 0 + 1 + read-only + + + + + SYSCFG_ITLINE1 + SYSCFG_ITLINE1 + SYSCFG interrupt line 1 status register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDOUT + PVD supply monitoring interrupt request pending (EXTI line 16). + 0 + 1 + read-only + + + PVMOUT1 + V<sub>DDUSB</sub> supply monitoring interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + PVMOUT3 + ADC supply monitoring interrupt request pending (EXTI line 20) + 2 + 1 + read-only + + + PVMOUT4 + DAC supply monitoring interrupt request pending (EXTI line 21) + 3 + 1 + read-only + + + + + SYSCFG_ITLINE2 + SYSCFG_ITLINE2 + SYSCFG interrupt line 2 status register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP + Tamper interrupt request pending (EXTI line 21) + 0 + 1 + read-only + + + RTC + RTC interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE3 + SYSCFG_ITLINE3 + SYSCFG interrupt line 3 status register + 0x8C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FLASH_ITF + Flash interface interrupt request pending + 0 + 1 + read-only + + + FLASH_ECC + Flash interface ECC interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE4 + SYSCFG_ITLINE4 + SYSCFG interrupt line 4 status register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RCC + Reset and clock control interrupt request pending + 0 + 1 + read-only + + + CRS + CRS interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE5 + SYSCFG_ITLINE5 + SYSCFG interrupt line 5 status register + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI line 0 interrupt request pending + 0 + 1 + read-only + + + EXTI1 + EXTI line 1 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE6 + SYSCFG_ITLINE6 + SYSCFG interrupt line 6 status register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI2 + EXTI line 2 interrupt request pending + 0 + 1 + read-only + + + EXTI3 + EXTI line 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE7 + SYSCFG_ITLINE7 + SYSCFG interrupt line 7 status register + 0x9C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI line 4 interrupt request pending + 0 + 1 + read-only + + + EXTI5 + EXTI line 5 interrupt request pending + 1 + 1 + read-only + + + EXTI6 + EXTI line 6 interrupt request pending + 2 + 1 + read-only + + + EXTI7 + EXTI line 7 interrupt request pending + 3 + 1 + read-only + + + EXTI8 + EXTI line 8 interrupt request pending + 4 + 1 + read-only + + + EXTI9 + EXTI line 9 interrupt request pending + 5 + 1 + read-only + + + EXTI10 + EXTI line 10 interrupt request pending + 6 + 1 + read-only + + + EXTI11 + EXTI line 11 interrupt request pending + 7 + 1 + read-only + + + EXTI12 + EXTI line 12 interrupt request pending + 8 + 1 + read-only + + + EXTI13 + EXTI line 13 interrupt request pending + 9 + 1 + read-only + + + EXTI14 + EXTI line 14 interrupt request pending + 10 + 1 + read-only + + + EXTI15 + EXTI line 15 interrupt request pending + 11 + 1 + read-only + + + + + SYSCFG_ITLINE8 + SYSCFG_ITLINE8 + SYSCFG interrupt line 8 status register + 0xA0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USB + USB interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE9 + SYSCFG_ITLINE9 + SYSCFG interrupt line 9 status register + 0xA4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH1 + DMA1 channel 1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE10 + SYSCFG_ITLINE10 + SYSCFG interrupt line 10 status register + 0xA8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH2 + DMA1 channel 2 interrupt request pending + 0 + 1 + read-only + + + DMA1_CH3 + DMA1 channel 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE11 + SYSCFG_ITLINE11 + SYSCFG interrupt line 11 status register + 0xAC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAMUX + DMAMUX interrupt request pending + 0 + 1 + read-only + + + DMA1_CH4 + DMA1 channel 4 interrupt request pending + 1 + 1 + read-only + + + DMA1_CH5 + DMA1 channel 5 interrupt request pending + 2 + 1 + read-only + + + DMA1_CH6 + DMA1 channel 6 interrupt request pending + 3 + 1 + read-only + + + DMA1_CH7 + DMA1 channel 7 interrupt request pending + 4 + 1 + read-only + + + DMA2_CH1 + DMA2 channel 1 interrupt request pending + 5 + 1 + read-only + + + DMA2_CH2 + DMA2 channel 2 interrupt request pending + 6 + 1 + read-only + + + DMA2_CH3 + DMA2 channel 3 interrupt request pending + 7 + 1 + read-only + + + DMA2_CH4 + DMA2 channel 4 interrupt request pending + 8 + 1 + read-only + + + DMA2_CH5 + DMA2 channel 5 interrupt request pending + 9 + 1 + read-only + + + + + SYSCFG_ITLINE12 + SYSCFG_ITLINE12 + SYSCFG interrupt line 12 status register + 0xB0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC interrupt request pending + 0 + 1 + read-only + + + COMP1 + Comparator 1 interrupt request pending (EXTI line 17) + 1 + 1 + read-only + + + COMP2 + Comparator 2 interrupt request pending (EXTI line 18) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE13 + SYSCFG_ITLINE13 + SYSCFG interrupt line 13 status register + 0xB4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1_CCU + Timer 1 commutation interrupt request pending + 0 + 1 + read-only + + + TIM1_TRG + Timer 1 trigger interrupt request pending + 1 + 1 + read-only + + + TIM1_UPD + Timer 1 update interrupt request pending + 2 + 1 + read-only + + + TIM1_BRK + Timer 1 break interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE14 + SYSCFG_ITLINE14 + SYSCFG interrupt line 14 status register + 0xB8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1_CC1 + Timer 1 capture compare 1 interrupt request pending + 0 + 1 + read-only + + + TIM1_CC2 + Timer 1 capture compare 2 interrupt request pending + 1 + 1 + read-only + + + TIM1_CC3 + Timer 1 capture compare 3 interrupt request pending + 2 + 1 + read-only + + + TIM1_CC4 + Timer 1 capture compare 4 interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE15 + SYSCFG_ITLINE15 + SYSCFG interrupt line 15 status register + 0xBC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2 + Timer 2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE16 + SYSCFG_ITLINE16 + SYSCFG interrupt line 16 status register + 0xC0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM3 + Timer 3 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE17 + SYSCFG_ITLINE17 + SYSCFG interrupt line 17 status register + 0xC4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM6 + Timer 6 interrupt request pending + 0 + 1 + read-only + + + DAC + DAC underrun interrupt request pending + 1 + 1 + read-only + + + LPTIM1 + Low-power timer 1 interrupt request pending (EXTI line 29) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE18 + SYSCFG_ITLINE18 + SYSCFG interrupt line 18 status register + 0xC8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM7 + Timer 7 interrupt request pending + 0 + 1 + read-only + + + LPTIM2 + Low-power timer 2 interrupt request pending (EXTI line 30) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE19 + SYSCFG_ITLINE19 + SYSCFG interrupt line 19 status register + 0xCC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM15 + Timer 15 interrupt request pending + 0 + 1 + read-only + + + LPTIM3 + Low-power timer 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE20 + SYSCFG_ITLINE20 + SYSCFG interrupt line 20 status register + 0xD0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM16 + Timer 16 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE21 + SYSCFG_ITLINE21 + SYSCFG interrupt line 21 status register + 0xD4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSC_MCE + TSC max count error interrupt request pending + 0 + 1 + read-only + + + TSC_EOA + TSC end of acquisition interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE22 + SYSCFG_ITLINE22 + SYSCFG interrupt line 22 status register + 0xD8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCD + LCD interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE23 + SYSCFG_ITLINE23 + SYSCFG interrupt line 23 status register + 0xDC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C1 + I2C1 interrupt request pending (EXTI line 33) + 0 + 1 + read-only + + + + + SYSCFG_ITLINE24 + SYSCFG_ITLINE24 + SYSCFG interrupt line 24 status register + 0xE0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C2 + I2C2 interrupt request pending + 0 + 1 + read-only + + + I2C4 + I2C4 interrupt request pending + 1 + 1 + read-only + + + I2C3 + I2C3 interrupt request pending (EXTI line 23) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE25 + SYSCFG_ITLINE25 + SYSCFG interrupt line 25 status register + 0xE4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI1 + SPI1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE26 + SYSCFG_ITLINE26 + SYSCFG interrupt line 26 status register + 0xE8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI2 + SPI2 interrupt request pending + 0 + 1 + read-only + + + SPI3 + SPI3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE27 + SYSCFG_ITLINE27 + SYSCFG interrupt line 27 status register + 0xEC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1 + USART1 interrupt request pending, combined with EXTI line 25 + 0 + 1 + read-only + + + + + SYSCFG_ITLINE28 + SYSCFG_ITLINE28 + SYSCFG interrupt line 28 status register + 0xF0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART2 + USART2 interrupt request pending (EXTI line 35) + 0 + 1 + read-only + + + LPUART2 + LPUART2 interrupt request pending (EXTI line 31) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE29 + SYSCFG_ITLINE29 + SYSCFG interrupt line 29 status register + 0xF4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART3 + USART3 interrupt request pending + 0 + 1 + read-only + + + LPUART1 + LPUART1 interrupt request pending (EXTI line 30) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE30 + SYSCFG_ITLINE30 + SYSCFG interrupt line 30 status register + 0xF8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART4 + USART4 interrupt request pending + 0 + 1 + read-only + + + LPUART3 + LPUART3 interrupt request pending (EXTI line 32) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE31 + SYSCFG_ITLINE31 + SYSCFG interrupt line 31 status register + 0xFC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNG + RNG interrupt request pending + 0 + 1 + read-only + + + + + + + TAMP + TAMP register block + TAMP + 0x4000B000 + + 0x0 + 0x400 + registers + + + + TAMP_CR1 + TAMP_CR1 + TAMP control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1E + Tamper detection on TAMP_IN1 enable + 0 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN1 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN1 is enabled. + 0x1 + + + + + TAMP2E + Tamper detection on TAMP_IN2 enable<sup>(1)</sup> + 1 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN2 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN2 is enabled. + 0x1 + + + + + TAMP3E + Tamper detection on TAMP_IN3 enable<sup>(1)</sup> + 2 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN3 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN3 is enabled. + 0x1 + + + + + TAMP4E + Tamper detection on TAMP_IN4 enable<sup>(1)</sup> + 3 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN4 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN4 is enabled. + 0x1 + + + + + TAMP5E + Tamper detection on TAMP_IN5 enable<sup>(1)</sup> + 4 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN5 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN5 is enabled. + 0x1 + + + + + ITAMP3E + Internal tamper 3 enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 disabled. + 0x0 + + + B_0x1 + Internal tamper 3 enabled. + 0x1 + + + + + ITAMP4E + Internal tamper 4 enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 disabled. + 0x0 + + + B_0x1 + Internal tamper 4 enabled. + 0x1 + + + + + ITAMP5E + Internal tamper 5 enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 disabled. + 0x0 + + + B_0x1 + Internal tamper 5 enabled. + 0x1 + + + + + ITAMP6E + Internal tamper 6 enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 disabled. + 0x0 + + + B_0x1 + Internal tamper 6 enabled. + 0x1 + + + + + + + TAMP_CR2 + TAMP_CR2 + TAMP control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1POM + Tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Tamper 1 event detection is in potential mode. + 0x1 + + + + + TAMP2POM + Tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 2 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP3POM + Tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 3 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP4POM + Tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 4 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP5POM + Tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 5 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP1MSK + Tamper 1 mask +The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + 16 + 1 + read-write + + + B_0x0 + Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + TAMP2MSK + Tamper 2 mask +The tamper 2 interrupt must not be enabled when TAMP2MSK is set. + 17 + 1 + read-write + + + B_0x0 + Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + TAMP3MSK + Tamper 3 mask +The tamper 3 interrupt must not be enabled when TAMP3MSK is set. + 18 + 1 + read-write + + + B_0x0 + Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + BKBLOCK + Backup registers and device secrets<sup>(1)</sup> access blocked + 22 + 1 + read-write + + + B_0x0 + backup registers and device secrets<sup>(1)</sup> can be accessed if no tamper flag is set + 0x0 + + + B_0x1 + backup registers and device secrets<sup>(1)</sup> cannot be accessed + 0x1 + + + + + BKERASE + Backup registers and device secrets<sup>(1)</sup> erase +Writing 1 to this bit reset the backup registers and device secrets<sup>(1)</sup>. Writing 0 has no effect. This bit is always read as 0. + 23 + 1 + write-only + + + TAMP1TRG + Active level for tamper 1 input +If TAMPFLT1=100 tamper 1 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 1 input falling edge triggers a tamper detection event. + 24 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 1 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 1 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP2TRG + Active level for tamper 2 input +If TAMPFLT = 00 tamper 2 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 2 input falling edge triggers a tamper detection event. + 25 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 2 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 2 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP3TRG + Active level for tamper 3 input +If TAMPFLT1=100 tamper 3 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 3 input falling edge triggers a tamper detection event. + 26 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 3 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 3 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP4TRG + Active level for tamper 4 input (active mode disabled) +If TAMPFLT1=100 tamper 4 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 4 input falling edge triggers a tamper detection event. + 27 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 4 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 4 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP5TRG + Active level for tamper 5 input (active mode disabled) +If TAMPFLT1=100 tamper 5 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 5 input falling edge triggers a tamper detection event. + 28 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 5 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 5 input staying low triggers a tamper detection event + 0x1 + + + + + + + TAMP_CR3 + TAMP_CR3 + TAMP control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ITAMP3POM + Internal tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Internal tamper 3 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 3 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP4POM + Internal tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Internal tamper 4 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 4 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP5POM + Internal tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Internal tamper 5 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 5 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP6POM + Internal tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Internal tamper 6 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Internal tamper 6 event detection is in potential mode. + 0x1 + + + + + + + TAMP_FLTCR + TAMP_FLTCR + TAMP filter control register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMPFREQ + Tamper sampling frequency +Determines the frequency at which each of the TAMP_INx inputs are sampled. + 0 + 3 + read-write + + + B_0x0 + RTCCLK / 32768 (11Hz when RTCCLK = 327681Hz) + 0x0 + + + B_0x1 + RTCCLK / 16384 (21Hz when RTCCLK = 327681Hz) + 0x1 + + + B_0x2 + RTCCLK / 8192 (41Hz when RTCCLK = 327681Hz) + 0x2 + + + B_0x3 + RTCCLK / 4096 (81Hz when RTCCLK = 327681Hz) + 0x3 + + + B_0x4 + RTCCLK / 2048 (161Hz when RTCCLK = 327681Hz) + 0x4 + + + B_0x5 + RTCCLK / 1024 (321Hz when RTCCLK = 327681Hz) + 0x5 + + + B_0x6 + RTCCLK / 512 (641Hz when RTCCLK = 327681Hz) + 0x6 + + + B_0x7 + RTCCLK / 256 (1281Hz when RTCCLK = 327681Hz) + 0x7 + + + + + TAMPFLT + TAMP_INx filter count +These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. + 3 + 2 + read-write + + + B_0x0 + Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). + 0x0 + + + B_0x1 + Tamper event is activated after 2 consecutive samples at the active level. + 0x1 + + + B_0x2 + Tamper event is activated after 4 consecutive samples at the active level. + 0x2 + + + B_0x3 + Tamper event is activated after 8 consecutive samples at the active level. + 0x3 + + + + + TAMPPRCH + TAMP_INx precharge duration +These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. + 5 + 2 + read-write + + + B_0x0 + 1 RTCCLK cycle + 0x0 + + + B_0x1 + 2 RTCCLK cycles + 0x1 + + + B_0x2 + 4 RTCCLK cycles + 0x2 + + + B_0x3 + 8 RTCCLK cycles + 0x3 + + + + + TAMPPUDIS + TAMP_INx pull-up disable +This bit determines if each of the TAMPx pins are precharged before each sample. + 7 + 1 + read-write + + + B_0x0 + Precharge TAMP_INx pins before sampling (enable internal pull-up) + 0x0 + + + B_0x1 + Disable precharge of TAMP_INx pins. + 0x1 + + + + + + + TAMP_IER + TAMP_IER + TAMP interrupt enable register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1IE + Tamper 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 1 interrupt enabled. + 0x1 + + + + + TAMP2IE + Tamper 2 interrupt enable + 1 + 1 + read-write + + + B_0x0 + Tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 2 interrupt enabled. + 0x1 + + + + + TAMP3IE + Tamper 3 interrupt enable + 2 + 1 + read-write + + + B_0x0 + Tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 3 interrupt enabled.. + 0x1 + + + + + TAMP4IE + Tamper 4 interrupt enable + 3 + 1 + read-write + + + B_0x0 + Tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 4 interrupt enabled. + 0x1 + + + + + TAMP5IE + Tamper 5 interrupt enable + 4 + 1 + read-write + + + B_0x0 + Tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP3IE + Internal tamper 3 interrupt enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 3 interrupt enabled. + 0x1 + + + + + ITAMP4IE + Internal tamper 4 interrupt enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 4 interrupt enabled. + 0x1 + + + + + ITAMP5IE + Internal tamper 5 interrupt enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP6IE + Internal tamper 6 interrupt enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 6 interrupt enabled. + 0x1 + + + + + + + TAMP_SR + TAMP_SR + TAMP status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1F + TAMP1 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. + 0 + 1 + read-only + + + TAMP2F + TAMP2 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. + 1 + 1 + read-only + + + TAMP3F + TAMP3 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. + 2 + 1 + read-only + + + TAMP4F + TAMP4 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP4 input. + 3 + 1 + read-only + + + TAMP5F + TAMP5 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP5 input. + 4 + 1 + read-only + + + ITAMP3F + Internal tamper 3 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. + 18 + 1 + read-only + + + ITAMP4F + Internal tamper 4 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. + 19 + 1 + read-only + + + ITAMP5F + Internal tamper 5 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. + 20 + 1 + read-only + + + ITAMP6F + Internal tamper 6 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. + 21 + 1 + read-only + + + + + TAMP_MISR + TAMP_MISR + TAMP masked interrupt status register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 interrupt masked flag +This flag is set by hardware when the tamper 1 interrupt is raised. + 0 + 1 + read-only + + + TAMP2MF + TAMP2 interrupt masked flag +This flag is set by hardware when the tamper 2 interrupt is raised. + 1 + 1 + read-only + + + TAMP3MF + TAMP3 interrupt masked flag +This flag is set by hardware when the tamper 3 interrupt is raised. + 2 + 1 + read-only + + + TAMP4MF + TAMP4 interrupt masked flag +This flag is set by hardware when the tamper 4 interrupt is raised. + 3 + 1 + read-only + + + TAMP5MF + TAMP5 interrupt masked flag +This flag is set by hardware when the tamper 5 interrupt is raised. + 4 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 interrupt masked flag +This flag is set by hardware when the internal tamper 3 interrupt is raised. + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 interrupt masked flag +This flag is set by hardware when the internal tamper 4 interrupt is raised. + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 interrupt masked flag +This flag is set by hardware when the internal tamper 5 interrupt is raised. + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 interrupt masked flag +This flag is set by hardware when the internal tamper 6 interrupt is raised. + 21 + 1 + read-only + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CTAMP1F + Clear TAMP1 detection flag +Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. + 0 + 1 + write-only + + + CTAMP2F + Clear TAMP2 detection flag +Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. + 1 + 1 + write-only + + + CTAMP3F + Clear TAMP3 detection flag +Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. + 2 + 1 + write-only + + + CTAMP4F + Clear TAMP4 detection flag +Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register. + 3 + 1 + write-only + + + CTAMP5F + Clear TAMP5 detection flag +Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register. + 4 + 1 + write-only + + + CITAMP3F + Clear ITAMP3 detection flag +Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. + 18 + 1 + write-only + + + CITAMP4F + Clear ITAMP4 detection flag +Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. + 19 + 1 + write-only + + + CITAMP5F + Clear ITAMP5 detection flag +Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. + 20 + 1 + write-only + + + CITAMP6F + Clear ITAMP6 detection flag +Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. + 21 + 1 + write-only + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + + + TIM1 + TIM1 address block description + TIM + 0x40012C00 + + 0x0 + 0x6C + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 break, update, trigger and commutation interrupts + 13 + + + TIM1_CC + TIM1 Capture Compare interrupt + 14 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (ETR, TIx): +Note: t<sub>DTS</sub> = 1/f<sub>DTS</sub>, t<sub>CK_INT</sub> = 1/f<sub>CK_INT</sub>. + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub>=t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub>=2*t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub>=4*t<sub>CK_INT</sub> + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output Idle state 2 (OC2 output) +Refer to OIS1 bit + 10 + 1 + read-write + + + OIS2N + Output Idle state 2 (OC2N output) +Refer to OIS1N bit + 11 + 1 + read-write + + + OIS3 + Output Idle state 3 (OC3 output) +Refer to OIS1 bit + 12 + 1 + read-write + + + OIS3N + Output Idle state 3 (OC3N output) +Refer to OIS1N bit + 13 + 1 + read-write + + + OIS4 + Output Idle state 4 (OC4 output) +Refer to OIS1 bit + 14 + 1 + read-write + + + OIS5 + Output Idle state 5 (OC5 output) +Refer to OIS1 bit + 16 + 1 + read-write + + + OIS6 + Output Idle state 6 (OC6 output) +Refer to OIS1 bit + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 +These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO2) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO2) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO2) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO2) + 0x7 + + + B_0x8 + Compare - OC5REFC signal is used as trigger output (TRGO2) + 0x8 + + + B_0x9 + Compare - OC6REFC signal is used as trigger output (TRGO2) + 0x9 + + + B_0xA + Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 + 0xA + + + B_0xB + Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 + 0xB + + + B_0xC + Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xC + + + B_0xD + Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xD + + + B_0xE + Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xE + + + B_0xF + Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xF + + + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Codes above 1000: Reserved. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection +This bit is used to select the OCREF clear source. + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[0]: Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See Table1118: TIM1 internal trigger connection on page1561 for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of f<sub>CK_INT</sub> frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to Section122.4.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag +This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + B2IF + Break 2 interrupt flag +This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag +Refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +Refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +Refer to CC1OF description + 12 + 1 + read-write + + + SBIF + System Break interrupt flag +This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. +This flag must be reset to re-start PWM operation. + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag +Refer to CC1IF description (Note: Channel 5 can only be configured as output) + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag +Refer to CC1IF description (Note: Channel 6 can only be configured as output) + 17 + 1 + read-write + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/Compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/Compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware +Note: This bit acts only on channels having a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. + 0x1 + + + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + B2G + Break 2 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. + 0x1 + + + + + + + TIM1_CCMR1_INPUT + TIM1_CCMR1_INPUT + TIM1 capture/compare mode register 1 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC2F + Input capture 2 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR1_OUTPUT + TIM1_CCMR1_OUTPUT + TIM1 capture/compare mode register 1 + TIM1_CCMR1_INPUT + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ocref_clr_int signal + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input) + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output Compare 2 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode +Refer to OC1M[3:0] description. + 12 + 3 + read-write + + + OC2CE + Output Compare 2 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2_INPUT + TIM1_CCMR2_INPUT + TIM1 capture/compare mode register 2 + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +Refer to IC1PSC[1:0] description. + 2 + 2 + read-write + + + IC3F + Input capture 3 filter +Refer to IC1F[3:0] description. + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC4F + Input capture 4 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR2_OUTPUT + TIM1_CCMR2_OUTPUT + TIM1 capture/compare mode register 1 + TIM1_CCMR2_INPUT + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode +Refer to OC1M[3:0] description. + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode +Refer to OC3M[3:0] description. + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table1119 for details. +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (channel configured as output). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/Compare 2 complementary output enable +Refer to CC1NE description + 6 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output polarity +Refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/Compare 3 complementary output enable +Refer to CC1NE description + 10 + 1 + read-write + + + CC3NP + Capture/Compare 3 complementary output polarity +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable +Refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output polarity +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 complementary output polarity +Refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/Compare 5 output enable +Refer to CC1E description + 16 + 1 + read-write + + + CC5P + Capture/Compare 5 output polarity +Refer to CC1P description + 17 + 1 + read-write + + + CC6E + Capture/Compare 6 output enable +Refer to CC1E description + 20 + 1 + read-write + + + CC6P + Capture/Compare 6 output polarity +Refer to CC1P description + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section122.3.1: Time-base unit on page1497 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x30 + 16 + 0x0000 + 0xFFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to: +the number of PWM periods in edge-aligned mode +the number of half PWM period in center-aligned mode. + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x34 + 16 + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x38 + 16 + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. +If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x3C + 16 + 0x0000 + 0xFFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x40 + 16 + 0x0000 + 0xFFFF + + + CCR4 + Capture/Compare value +If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +This bit enables the complete break protection (including all sources connected to bk_acth and BRK sources, as per Figure1152: Break and Break2 circuitry overview). +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. OC and OCN outputs are disabled + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter +This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 20 + 4 + read-write + + + B_0x0 + No filter, BRK2 acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable +Note: The BRK2 must only be used with OSSR = OSSI = 1. +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 24 + 1 + read-write + + + B_0x0 + Break input BRK2 disabled + 0x0 + + + B_0x1 + Break input BRK2 enabled + 0x1 + + + + + BK2P + Break 2 polarity +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 25 + 1 + read-write + + + B_0x0 + Break input BRK2 is active low + 0x0 + + + B_0x1 + Break input BRK2 is active high + 0x1 + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BK2DSRM + Break2 Disarm +Refer to BKDSRM description + 27 + 1 + read-write + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional +Refer to BKBID description + 29 + 1 + read-write + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x48 + 16 + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... +Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. +If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: +(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL +In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA +According to the configuration of the DMA Data Size, several cases may occur: +If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. +If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x11 + 18 transfers + 0x11 + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 32 + read-write + + + + + TIM1_OR1 + TIM1_OR1 + TIM1 option register 1 + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection +This bit selects the ocref_clr input source. +Others: Reserved +Note: COMP3 is available on STM32G0B1xx and STM32G0C1xx salestypes only. + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC5M + OC5M[0]: Output compare 5 mode +Refer to OC1M description. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC6M + OC6M[0]: Output compare 6 mode +Refer to OC1M description. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/Compare 5 value +CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. + 0 + 16 + read-write + + + GC5C1 + Group Channel 5 and Channel 1 +Distortion on Channel 1 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC1REFC5 + 0x0 + + + B_0x1 + OC1REFC is the logical AND of OC1REFC and OC5REF + 0x1 + + + + + GC5C2 + Group Channel 5 and Channel 2 +Distortion on Channel 2 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC2REFC + 0x0 + + + B_0x1 + OC2REFC is the logical AND of OC2REFC and OC5REF + 0x1 + + + + + GC5C3 + Group Channel 5 and Channel 3 +Distortion on Channel 3 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). +Note: it is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC3REFC + 0x0 + + + B_0x1 + OC3REFC is the logical AND of OC3REFC and OC5REF + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x5C + 16 + 0x0000 + 0xFFFF + + + CCR6 + Capture/Compare 6 value +CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. + 0 + 16 + read-write + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x60 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable +This bit enables the COMP1 for the timers BRK input. COMP1 output is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable +This bit enables the COMP2 for the timers BRK input. COMP2 output is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + B_0x2 + COMP2 output + 0x2 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + B_0x6 + COMP3 output (available on STM32G0B1xx and STM32G0C1xx salestypes only) + 0x6 + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 Alternate function register 2 + 0x64 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BK2INE + BRK2 BKIN input enable +This bit enables the BKIN2 alternate function input for the timers BRK2 input. BKIN2 input is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN2 input disabled + 0x0 + + + B_0x1 + BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + BRK2 COMP1 enable +This bit enables the COMP1 for the timers BRK2 input. COMP1 output is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BK2CMP2E + BRK2 COMP2 enable +This bit enables the COMP2 for the timers BRK2 input. COMP2 output is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BK2INP + BRK2 BKIN2 input polarity +This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + BK2CMP1P + BRK2 COMP1 input polarity +This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + BK2CMP2P + BRK2 COMP2 input polarity +This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM1_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM1_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM1_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM1_CH4 input + 0x0 + + + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40000000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 global interrupt + 15 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section23. + 0x1 + + + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1_ALTERNATE1 + TIM2 capture/compare mode register 1 + TIM2_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2_ALTERNATE1 + TIM2 capture/compare mode register 2 + TIM2_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM2_CNT_ALTERNATE1 + TIM2_CNT_ALTERNATE1 + TIM2 counter + TIM2_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM2_OR1 + TIM2_OR1 + TIM2 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection + + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 + 0x1 + + + B_0x2 + COMP2 + 0x2 + + + B_0x3 + LSE + 0x3 + + + B_0x4 + MCO + 0x4 + + + B_0x5 + MCO2 + 0x5 + + + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM2_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM2_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM2_CH3 input + 0x0 + + + + + + + + + TIM3 + TIM3 address block description + TIM3 + 0x40000400 + + 0x0 + 0x6C + registers + + + TIM3 + TIM3 global interrupt + 16 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section23. + 0x1 + + + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_ALTERNATE1 + TIM3_CCMR1_ALTERNATE1 + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_ALTERNATE1 + TIM3_CCMR2_ALTERNATE1 + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM3_CNT_ALTERNATE1 + TIM3_CNT_ALTERNATE1 + TIM3 counter + TIM3_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM3_OR1 + TIM3_OR1 + TIM3 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection + + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + B_0x2 + COMP2 output + 0x2 + + + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM3_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM3_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM3_CH3 input + 0x0 + + + + + + + + + TIM6 + TIM6 address block description + TIM + 0x40001000 + + 0x0 + 0x30 + registers + + + TIM6_DAC_LPTIM1 + TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) + 17 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable + Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + This bit is set and cleared by software to enable/disable UEV event generation. + Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source + This bit is set and cleared by software to select the UEV event sources. + Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x04 + 16 + 0x0000 + 0xFFFF + + + MMS + Master mode selection + These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: + When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). + Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/Interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 16 + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + This bit is set by hardware on an update event. It is cleared by software. + At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. + When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation + This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). + 0x1 + + + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value + The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). + PSC contains the value to be loaded into the active prescaler register at each update event. + (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Prescaler value + ARR is the value to be loaded into the actual auto-reload register. + Refer to Section123.3.1: Time-base unit on page1596 for more details about ARR update and behavior. + The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + + + TIM7 + TIM7 address block description + TIM + 0x40001400 + + 0x0 + 0x30 + registers + + + TIM7_LPTIM2 + TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) + 18 + + + + TIM7_CR1 + TIM7_CR1 + TIM7 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. +CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM7_CR2 + TIM7_CR2 + TIM7 control register 2 + 0x04 + 16 + 0x0000 + 0xFFFF + + + MMS + Master mode selection +These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + + + + + TIM7_DIER + TIM7_DIER + TIM7 DMA/Interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM7_SR + TIM7_SR + TIM7 status register + 0x10 + 16 + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + + + TIM7_EGR + TIM7_EGR + TIM7 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). + 0x1 + + + + + + + TIM7_CNT + TIM7_CNT + TIM7 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM7_PSC + TIM7_PSC + TIM7 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded into the active prescaler register at each update event. +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM7_ARR + TIM7_ARR + TIM7 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Prescaler value +ARR is the value to be loaded into the actual auto-reload register. +Refer to Section123.3.1: Time-base unit on page1596 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + + + TIM15 + TIM15 address block description + TIM15 + 0x40014000 + + 0x0 + 0x6C + registers + + + TIM15_LPTIM3 + TIM15 and LPTIM3 global interrupt (combined with EXTI line 29) + 19 + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt if enabled + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO). + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO). + 0x5 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) + + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) + + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (OC2 output) + + 10 + 1 + read-write + + + B_0x0 + OC2=0 when MOE=0 + 0x0 + + + B_0x1 + OC2=1 when MOE=0 + 0x1 + + + + + + + TIM15_SMCR + TIM15_SMCR + TIM15 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred + 0x0 + + + B_0x1 + Trigger interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag + + 10 + 1 + read-write + + + + + TIM15_EGR + TIM15_EGR + TIM15 event generation register + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation + + 2 + 1 + write-only + + + COMG + Capture/Compare control update generation + + 5 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM15_CCMR1 + TIM15_CCMR1 + TIM15 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM15_CCMR1_ALTERNATE1 + TIM15_CCMR1_ALTERNATE1 + TIM15 capture/compare mode register 1 + TIM15_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + CC2E + Capture/Compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity + + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity + + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value + + 0 + 16 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value + + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value + + 0 + 16 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register 2 + 0x38 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value + + 0 + 16 + read-write + + + + + TIM15_BDTR + TIM15_BDTR + TIM15 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable + + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable + + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity + + 10 + 1 + read-write + + + B_0x0 + COMP1 input is active low + 0x0 + + + B_0x1 + COMP1 input is active high + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity + + 11 + 1 + read-write + + + B_0x0 + COMP2 input is active low + 0x0 + + + B_0x1 + COMP2 input is active high + 0x1 + + + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input + + 0 + 4 + read-write + + + B_0x0 + TIM15_CH1 input + 0x0 + + + B_0x1 + TIM2_IC1 + 0x1 + + + B_0x2 + TIM3_IC1 + 0x2 + + + + + TI2SEL + selects TI2[0] to TI2[15] input + + 8 + 4 + read-write + + + B_0x0 + TIM15_CH2 input + 0x0 + + + B_0x1 + TIM2_IC2 + 0x1 + + + B_0x2 + TIM3_IC2 + 0x2 + + + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40014400 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 global interrupt + 20 + + + + TIM16_CR1 + TIM16_CR1 + TIM16 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM16_CR2 + TIM16_CR2 + TIM16 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) + + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) + + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + + + TIM16_DIER + TIM16_DIER + TIM16 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + + + TIM16_SR + TIM16_SR + TIM16 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM16_EGR + TIM16_EGR + TIM16 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + COMG + Capture/Compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM16_CCMR1 + TIM16_CCMR1 + TIM16 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input. + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N= + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + + + TIM16_CCMR1_ALTERNATE1 + TIM16_CCMR1_ALTERNATE1 + TIM16 capture/compare mode register 1 + TIM16_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM16_CCER + TIM16_CCER + TIM16 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + + + TIM16_CNT + TIM16_CNT + TIM16 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM16_PSC + TIM16_PSC + TIM16 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM16_ARR + TIM16_ARR + TIM16 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value + + 0 + 16 + read-write + + + + + TIM16_RCR + TIM16_RCR + TIM16 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value + + 0 + 8 + read-write + + + + + TIM16_CCR1 + TIM16_CCR1 + TIM16 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value + + 0 + 16 + read-write + + + + + TIM16_BDTR + TIM16_BDTR + TIM16 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM16_DCR + TIM16_DCR + TIM16 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM16_DMAR + TIM16_DMAR + TIM16 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable + + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable + + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity + + 10 + 1 + read-write + + + B_0x0 + COMP1 input is active low + 0x0 + + + B_0x1 + COMP1 input is active high + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity + + 11 + 1 + read-write + + + B_0x0 + COMP2 input is active low + 0x0 + + + B_0x1 + COMP2 input is active high + 0x1 + + + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input + + 0 + 4 + read-write + + + B_0x0 + TIM16_CH1 input + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + LSE + 0x2 + + + B_0x3 + RTC wakeup + 0x3 + + + B_0x4 + MCO2 + 0x4 + + + + + + + + + TSC + TSC address block description + TSC + 0x40024000 + + 0x0 + 0x50 + registers + + + TSC + TSC global interrupt + 21 + + + + TSC_CR + TSC_CR + TSC control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSCE + Touch sensing controller enable +This bit is set and cleared by software to enable/disable the touch sensing controller. +Note: When the touch sensing controller is disabled, TSC registers settings have no effect. + 0 + 1 + read-write + + + B_0x0 + Touch sensing controller disabled + 0x0 + + + B_0x1 + Touch sensing controller enabled + 0x1 + + + + + START + Start a new acquisition +This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. + 1 + 1 + read-write + + + B_0x0 + Acquisition not started + 0x0 + + + B_0x1 + Start a new acquisition + 0x1 + + + + + AM + Acquisition mode +This bit is set and cleared by software to select the acquisition mode. +Note: This bit must not be modified when an acquisition is ongoing. + 2 + 1 + read-write + + + B_0x0 + Normal acquisition mode (acquisition starts as soon as START bit is set) + 0x0 + + + B_0x1 + Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) + 0x1 + + + + + SYNCPOL + Synchronization pin polarity +This bit is set and cleared by software to select the polarity of the synchronization input pin. + 3 + 1 + read-write + + + B_0x0 + Falling edge only + 0x0 + + + B_0x1 + Rising edge and high level + 0x1 + + + + + IODEF + I/O Default mode +This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). +Note: This bit must not be modified when an acquisition is ongoing. + 4 + 1 + read-write + + + B_0x0 + I/Os are forced to output push-pull low + 0x0 + + + B_0x1 + I/Os are in input floating + 0x1 + + + + + MCV + Max count value +These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. +Note: These bits must not be modified when an acquisition is ongoing. + 5 + 3 + read-write + + + B_0x0 + 255 + 0x0 + + + B_0x1 + 511 + 0x1 + + + B_0x2 + 1023 + 0x2 + + + B_0x3 + 2047 + 0x3 + + + B_0x4 + 4095 + 0x4 + + + B_0x5 + 8191 + 0x5 + + + B_0x6 + 16383 + 0x6 + + + + + PGPSC + Pulse generator prescaler +These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. + 12 + 3 + read-write + + + B_0x0 + f<sub>HCLK</sub> + 0x0 + + + B_0x1 + f<sub>HCLK</sub> /2 + 0x1 + + + B_0x2 + f<sub>HCLK</sub> /4 + 0x2 + + + B_0x3 + f<sub>HCLK</sub> /8 + 0x3 + + + B_0x4 + f<sub>HCLK</sub> /16 + 0x4 + + + B_0x5 + f<sub>HCLK</sub> /32 + 0x5 + + + B_0x6 + f<sub>HCLK</sub> /64 + 0x6 + + + B_0x7 + f<sub>HCLK</sub> /128 + 0x7 + + + + + SSPSC + Spread spectrum prescaler +This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). +Note: This bit must not be modified when an acquisition is ongoing. + 15 + 1 + read-write + + + B_0x0 + f<sub>HCLK</sub> + 0x0 + + + B_0x1 + f<sub>HCLK</sub> /2 + 0x1 + + + + + SSE + Spread spectrum enable +This bit is set and cleared by software to enable/disable the spread spectrum feature. +Note: This bit must not be modified when an acquisition is ongoing. + 16 + 1 + read-write + + + B_0x0 + Spread spectrum disabled + 0x0 + + + B_0x1 + Spread spectrum enabled + 0x1 + + + + + SSD + Spread spectrum deviation +These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. +... +Note: These bits must not be modified when an acquisition is ongoing. + 17 + 7 + read-write + + + B_0x0 + 1x t<sub>SSCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>SSCLK</sub> + 0x1 + + + B_0x7F + 128x t<sub>SSCLK</sub> + 0x7F + + + + + CTPL + Charge transfer pulse low +These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from C<sub>X</sub> to C<sub>S</sub>). +... +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. + 24 + 4 + read-write + + + B_0x0 + 1x t<sub>PGCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>PGCLK</sub> + 0x1 + + + B_0xF + 16x t<sub>PGCLK</sub> + 0xF + + + + + CTPH + Charge transfer pulse high +These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of C<sub>X</sub>). +... +Note: These bits must not be modified when an acquisition is ongoing. + 28 + 4 + read-write + + + B_0x0 + 1x t<sub>PGCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>PGCLK</sub> + 0x1 + + + B_0xF + 16x t<sub>PGCLK</sub> + 0xF + + + + + + + TSC_IER + TSC_IER + TSC interrupt enable register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIE + End of acquisition interrupt enable +This bit is set and cleared by software to enable/disable the end of acquisition interrupt. + 0 + 1 + read-write + + + B_0x0 + End of acquisition interrupt disabled + 0x0 + + + B_0x1 + End of acquisition interrupt enabled + 0x1 + + + + + MCEIE + Max count error interrupt enable +This bit is set and cleared by software to enable/disable the max count error interrupt. + 1 + 1 + read-write + + + B_0x0 + Max count error interrupt disabled + 0x0 + + + B_0x1 + Max count error interrupt enabled + 0x1 + + + + + + + TSC_ICR + TSC_ICR + TSC interrupt clear register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIC + End of acquisition interrupt clear +This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding EOAF of the TSC_ISR register + 0x1 + + + + + MCEIC + Max count error interrupt clear +This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding MCEF of the TSC_ISR register + 0x1 + + + + + + + TSC_ISR + TSC_ISR + TSC interrupt status register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAF + End of acquisition flag +This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register. + 0 + 1 + read-only + + + B_0x0 + Acquisition is ongoing or not started + 0x0 + + + B_0x1 + Acquisition is complete + 0x1 + + + + + MCEF + Max count error flag +This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register. + 1 + 1 + read-only + + + B_0x0 + No max count error (MCE) detected + 0x0 + + + B_0x1 + Max count error (MCE) detected + 0x1 + + + + + + + TSC_IOHCR + TSC_IOHCR + TSC I/O hysteresis control register + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 0 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 1 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 2 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 3 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 4 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 5 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 6 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 7 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 8 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 9 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 10 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 11 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 12 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 13 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 14 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 15 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 16 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 17 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 18 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 19 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 20 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 21 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 22 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 23 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 24 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 25 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 26 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 27 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + + + TSC_IOASCR + TSC_IOASCR + TSC I/O analog switch control register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 0 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 1 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 2 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 3 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 4 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 5 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 6 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 7 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 8 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 9 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 10 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 11 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 12 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 13 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 14 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 15 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 16 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 17 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 18 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 19 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 20 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 21 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 22 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 23 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 24 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 25 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 26 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 27 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + + + TSC_IOSCR + TSC_IOSCR + TSC I/O sampling control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 0 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 1 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 2 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 3 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 4 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 5 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 6 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 7 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 8 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 9 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 10 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 11 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 12 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 13 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 14 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 15 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 16 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 17 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 18 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 19 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 20 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 21 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 22 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 23 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 24 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 25 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 26 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 27 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + + + TSC_IOCCR + TSC_IOCCR + TSC I/O channel control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 0 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 1 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 2 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 3 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 4 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 5 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 6 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 7 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 8 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 9 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 10 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 11 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 12 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 13 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 14 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 15 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 16 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 17 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 18 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 19 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 20 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 21 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 22 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 23 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 24 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 25 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 26 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 27 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + + + TSC_IOGCSR + TSC_IOGCSR + TSC I/O group control status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 0 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G2E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 1 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G3E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 2 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G4E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 3 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G5E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 4 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G6E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 5 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G7E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 6 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G1S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 16 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G2S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 17 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G3S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 18 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G4S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 19 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G5S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 20 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G6S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 21 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G7S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 22 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + + + TSC_IOG1CR + TSC_IOG1CR + TSC I/O group 1 counter register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG2CR + TSC_IOG2CR + TSC I/O group 2 counter register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG3CR + TSC_IOG3CR + TSC I/O group 3 counter register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG4CR + TSC_IOG4CR + TSC I/O group 4 counter register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG5CR + TSC_IOG5CR + TSC I/O group 5 counter register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG6CR + TSC_IOG6CR + TSC I/O group 6 counter register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG7CR + TSC_IOG7CR + TSC I/O group 7 counter register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + + + USART1 + USART address block description + USART + 0x40013800 + + 0x0 + 0x30 + registers + + + USART1 + USART1 global interrupt (combined with EXTI line 25) + 27 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + None + 31 + 1 + read-write + + + + + USART_CR1_ALTERNATE + USART_CR1_ALTERNATE + USART control register 1 + USART_CR1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous Slave mode enable +When the SLVEN bit is set, the Synchronous slave mode is enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the USART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +This bit can only be written when the USART is disabled (UE=0). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in Synchronous mode. +The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase +This bit is used to select the phase of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure1233 and Figure1234) +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +This bit enables the user to select the polarity of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable +This bit enables the user to enable the CK pin. +This bit can only be written when the USART is disabled (UE=0). +Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. +In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +Note: UE = 1 + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits +These bits are used for programming the stop bits. +This bitfield can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0.5 stop bit. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1.5 stop bits + 0x3 + + + + + LINEN + LIN mode enable +This bit is set and cleared by software. +The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable +This bit is set and cleared by software. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode +These bits are set and cleared by software. +This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). +Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable +This bit is set and cleared by software. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node +These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1or UDR = 1 in the USART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable +This bit is set and cleared by software. +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable +This bit is used for enabling Smartcard mode. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the USART is disabled (UE=0). +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the USART is disabled (UE=0) +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable +This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data are written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the USART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode) + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count +This bitfield specifies the number of retries for transmission and reception in Smartcard mode. +In Transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). +In Reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). +This bitfield must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. +0x1 to 0x7: number of automatic retransmission attempts (before signaling error) +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in Transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate +BRR[15:4] +BRR[15:4] correspond to USARTDIV[15:4] +BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared. + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value +PSC[7:0] = IrDA Normal and Low-power baud rate +This bitfield is used for programming the prescaler for dividing the USART source clock to achieve the low-power frequency: +The source clock is divided by the value given in the register (8 significant bits): +... +PSC[4:0]: Prescaler value +This bitfield is used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: +... +This bitfield can only be written when the USART is disabled (UE=0). +Note: Bits [7:5] must be kept cleared if Smartcard mode is used. +Note: This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to Section131.4: USART implementation on page1826. + 0 + 8 + read-write + + + B_0x0_SMARTCARD_MODE + Reserved - do not program this value + 0x0 + + + B_0x1_SMARTCARD_MODE + divides the source clock by 2 + 0x1 + + + B_0x2_SMARTCARD_MODE + divides the source clock by 4 + 0x2 + + + B_0x3_SMARTCARD_MODE + divides the source clock by 6 + 0x3 + + + + + GT + Guard time value +This bitfield is used to program the Guard time value in terms of number of baud clock periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value +This bitfield gives the Receiver timeout value in terms of number of bit duration. +In Standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. +Note: This value must only be programmed once per received character. + 0 + 24 + read-write + + + BLEN + Block Length +This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). +This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. +Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request +Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 0 + 1 + write-only + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software must wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This enables to discard the received data without reading them, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section131.5.9: Tolerance of the USART receiver to clock deviation on page1845). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. +RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: +When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXE/TXFE is set. +When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. +When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. +When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. +An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF must be checked prior to writing in TXFIFO (TXFNF and TXFE is set at the same time). +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if EOBIE1=11 in the USART_CR1 register. +It is cleared by software, writing 1 to EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-only + + + TXFE + TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO Full +This bit is set by hardware when the number of received data corresponds to RXFIFO1size1+11 (RXFIFO full + 1 data in the USART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section131.4: USART implementation on page1826. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. +Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section131.5.9: Tolerance of the USART receiver to clock deviation on page1845). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag is set when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). +An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if EOBIE1=11 in the USART_CR1 register. +It is cleared by software, writing 1 to EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section131.4: USART implementation on page1826. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register. + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register. + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 11 + 1 + write-only + + + EOBCF + End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register. +Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826 + 13 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure1227). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure1227). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The USART input clock can be divided by a prescaler factor: +Remaining combinations: Reserved +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + USART2 + 0x40004400 + + USART2_LPUART2 + USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) + 28 + + + + USART3 + 0x40004800 + + USART3_LPUART1 + USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) + 29 + + + + USART4 + 0x40004C00 + + USART4_LPUART3 + USART4 and LPUART3 global interrupt (combined with EXTI lines 20 and 34) + 30 + + + + USB + USB address block description + USB + 0x40005C00 + + 0x0 + 0x5C + registers + + + USB + USB global interrupt (combined with EXTI line 33) + 8 + + + + USB_CHEP0R + USB_CHEP0R + USB endpoint/channel 0 register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP1R + USB_CHEP1R + USB endpoint/channel 1 register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP2R + USB_CHEP2R + USB endpoint/channel 2 register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP3R + USB_CHEP3R + USB endpoint/channel 3 register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP4R + USB_CHEP4R + USB endpoint/channel 4 register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP5R + USB_CHEP5R + USB endpoint/channel 5 register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP6R + USB_CHEP6R + USB endpoint/channel 6 register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP7R + USB_CHEP7R + USB endpoint/channel 7 register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CNTR + USB_CNTR + USB control register + 0x40 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + USBRST + USB Reset +Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. +Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software. + 0 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + USB core is under reset + 0x1 + + + + + PDWN + Power down +This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. + 1 + 1 + read-write + + + B_0x0 + Exit power down + 0x0 + + + B_0x1 + Enter power down mode + 0x1 + + + + + SUSPRDY + Suspend state effective +This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wake-up logic and single ended receiver is kept alive to detect remote wake-up or resume events. +Software must poll this bit to confirm it to be set before any STOP mode entry. +This bit is cleared by hardware simultaneously to the WAKEUP flag being set. + 2 + 1 + read-only + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Suspend state + 0x1 + + + + + SUSPEN + Suspend state enable +Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 31ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. +As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY1=11 acknowledge the suspend request. +This bit is cleared by hardware simultaneous with the WAKEUP flag set. +Software can set this bit when host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. +As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. +This bit is cleared by hardware simultaneous with the WAKEUP flag set. + 3 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + Enter L1/L2 suspend + 0x1 + + + + + L2RES + L2 remote wake-up / resume driver +Device mode +The microcontroller can set this bit to send remote wake-up signaling to the host. It must be activated, according to USB specifications, for no less than 11ms and no more than 151ms after which the host PC is ready to drive the resume sequence up to its end. +Host mode +Software sets this bit to send resume signaling to the device. +Software clears this bit to send end of resume to device and restart SOF generation. +In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send L2 resume signaling to device + 0x1 + + + + + L1RES + L1 remote wake-up / resume driver + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + send 50 micro s remote wake up signaling to host + 0x1 + + + + + L1REQM + LPM L1 state request interrupt mask + 7 + 1 + read-write + + + B_0x0 + LPM L1 state request (L1REQ) interrupt disabled. + 0x0 + + + B_0x1 + L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ESOFM + Expected start of frame interrupt mask + 8 + 1 + read-write + + + B_0x0 + Expected start of frame (ESOF) interrupt disabled. + 0x0 + + + B_0x1 + ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SOFM + Start of frame interrupt mask + 9 + 1 + read-write + + + B_0x0 + SOF interrupt disabled. + 0x0 + + + B_0x1 + SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + RST_DCONM + USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask + 10 + 1 + read-write + + + B_0x0 + RESET interrupt disabled. + 0x0 + + + B_0x1 + RESET interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SUSPM + Suspend mode interrupt mask + 11 + 1 + read-write + + + B_0x0 + Suspend mode request (SUSP) interrupt disabled. + 0x0 + + + B_0x1 + SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + WKUPM + Wake-up interrupt mask + 12 + 1 + read-write + + + B_0x0 + WKUP interrupt disabled. + 0x0 + + + B_0x1 + WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ERRM + Error interrupt mask + 13 + 1 + read-write + + + B_0x0 + ERR interrupt disabled. + 0x0 + + + B_0x1 + ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + PMAOVRM + Packet memory area over / underrun interrupt mask + 14 + 1 + read-write + + + B_0x0 + PMAOVR interrupt disabled. + 0x0 + + + B_0x1 + PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + CTRM + Correct transfer interrupt mask + 15 + 1 + read-write + + + B_0x0 + Correct transfer (CTR) interrupt disabled. + 0x0 + + + B_0x1 + CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + THR512M + 512 byte threshold interrupt mask + 16 + 1 + read-write + + + B_0x0 + 512 byte threshold interrupt disabled + 0x0 + + + B_0x1 + 512 byte threshold interrupt enabled + 0x1 + + + + + DDISCM + Device disconnection mask +Host mode + 17 + 1 + read-write + + + B_0x0 + Device disconnection interrupt disabled + 0x0 + + + B_0x1 + Device disconnection interrupt enabled + 0x1 + + + + + HOST + HOST mode +HOST bit selects betweens host or device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. + 31 + 1 + read-write + + + B_0x0 + USB Device function + 0x0 + + + B_0x1 + USB host function (Reserved, host function is not available in these products, see Section134.3: USB implementation) + 0x1 + + + + + + + USB_ISTR + USB_ISTR + USB interrupt status register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDN + Device Endpoint / host channel identification number +These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: two levels are defined, in order of priority: isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only. + 0 + 4 + read-only + + + DIR + Direction of transaction +This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. +If DIR bit1=10, VTTX bit is set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). +If DIR bit1=11, VTRX bit or both VTTX/VTRX are set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. +This information can be used by the application software to access the USB_CHEPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. + 4 + 1 + read-only + + + L1REQ + LPM L1 state request +Device mode +This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only 0 can be written and writing 1 has no effect. + 7 + 1 + read-write + + + ESOF + Expected start of frame +Device mode +This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 11ms, but if the device does not receive it properly, the suspend timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the suspend timer is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect. + 8 + 1 + read-write + + + SOF + Start of frame +This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 11ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this can be useful for isochronous applications). This bit is read/write but only 0 can be written and writing 1 has no effect. + 9 + 1 + read-write + + + RST_DCON + USB reset request (Device mode) or device connect/disconnect (Host mode) +Device mode +This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. +Host mode +This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22 cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times consecutively from connected state. + 10 + 1 + read-write + + + SUSP + Suspend mode request +Device mode +This bit is set by the hardware when no traffic has been received for 31ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can be written and writing 1 has no effect. + 11 + 1 + read-write + + + WKUP + Wake-up +This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (for example wake-up unit) about the start of the resume process. This bit is read/write but only 0 can be written and writing 1 has no effect. + 12 + 1 + read-write + + + ERR + Error +This flag is set whenever one of the errors listed below has occurred: +NANS: No ANSwer. The timeout for a host response has expired. +CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in the data, was wrong. +BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. +FVIO: Framing format violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). +The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (for example loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only 0 can be written and writing 1 has no effect. + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / underrun +This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host retries the transaction. The PMAOVR interrupt must never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only 0 can be written and writing 1 has no effect. + 14 + 1 + read-write + + + CTR + Completed transfer in host mode +This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and IDN bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. + 15 + 1 + read-only + + + THR512 + 512 byte threshold interrupt +This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. + 16 + 1 + read-write + + + DDISC + Device connection +Host mode +This bit is set when a device connection is detected. This bit is read/write but only 0 can be written and writing 1 has no effect. + 17 + 1 + read-write + + + DCON_STAT + Device connection status +Host mode: +This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected. + 29 + 1 + read-only + + + B_0x0 + No device connected + 0x0 + + + B_0x1 + FS or LS device connected to the host + 0x1 + + + + + LS_DCON + Low speed device connected +Host mode: +This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (481MHz) from the unconnected state. + 30 + 1 + read-only + + + + + USB_FNR + USB_FNR + USB frame number register + 0x48 + 0x20 + 0x00000000 + 0xFFFFF000 + + + FN + Frame number +This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for isochronous transfers. This bit field is updated on the generation of an SOF interrupt. + 0 + 11 + read-only + + + LSOF + Lost SOF +Device mode +These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. + 11 + 2 + read-only + + + LCK + Locked +Device mode +This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. + 13 + 1 + read-only + + + RXDM + Receive data - line status +This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wake-up event. + 14 + 1 + read-only + + + RXDP + Receive data + line status +This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wake-up event. + 15 + 1 + read-only + + + + + USB_DADDR + USB_DADDR + USB Device address + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADD + Device address +Device mode +These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel address (EA) field in the associated USB_CHEPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. +Host mode +These bits contain the address transmitted with the LPM transaction + 0 + 7 + read-write + + + EF + Enable function +This bit is set by the software to enable the USB Device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at 0 no transactions are handled, irrespective of the settings of USB_CHEPnR registers. + 7 + 1 + read-write + + + + + USB_LPMCSR + USB_LPMCSR + LPM control and status register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPMEN + LPM support enable +Device mode +This bit is set by the software to enable the LPM support within the USB Device. If this bit is at 0 no LPM transactions are handled. + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable +Device mode: +The NYET/ACK is returned only on a successful LPM transaction: +No errors in both the EXT token and the LPM token (else ERROR) +A valid bLinkState = 0001B (L1) is received (else STALL) + 1 + 1 + read-write + + + B_0x0 + the valid LPM token is NYET. + 0x0 + + + B_0x1 + the valid LPM token is ACK. + 0x1 + + + + + REMWAKE + bRemoteWake value +Device mode +This bit contains the bRemoteWake value received with last ACKed LPM Token + 3 + 1 + read-only + + + BESL + BESL value +Device mode +These bits contain the BESL value received with last ACKed LPM Token + 4 + 4 + read-only + + + + + USB_BCDR + USB_BCDR + Battery charging detector + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BCDEN + Battery charging detector (BCD) enable +Device mode +This bit is set by the software to enable the BCD support within the USB Device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD must be placed in OFF mode by clearing this bit to 0 in order to allow the normal USB operation. + 0 + 1 + read-write + + + DCDEN + Data contact detection (DCD) mode enable +Device mode +This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) must be selected to work correctly. + 1 + 1 + read-write + + + PDEN + Primary detection (PD) mode enable +Device mode +This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) must be selected to work correctly. + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode enable +Device mode +This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) must be selected to work correctly. + 3 + 1 + read-write + + + DCDET + Data contact detection (DCD) status +Device mode +This bit gives the result of DCD. + 4 + 1 + read-only + + + B_0x0 + data lines contact not detected. + 0x0 + + + B_0x1 + data lines contact detected. + 0x1 + + + + + PDET + Primary detection (PD) status +Device mode +This bit gives the result of PD. + 5 + 1 + read-only + + + B_0x0 + no BCD support detected (connected to SDP or proprietary device). + 0x0 + + + B_0x1 + BCD support detected (connected to ACA, CDP or DCP). + 0x1 + + + + + SDET + Secondary detection (SD) status +Device mode +This bit gives the result of SD. + 6 + 1 + read-only + + + B_0x0 + CDP detected. + 0x0 + + + B_0x1 + DCP detected. + 0x1 + + + + + PS2DET + DM pull-up detection status +Device mode +This bit is active only during PD and gives the result of comparison between DM voltage level and V<sub>LGC</sub> threshold. In normal situation, the DM level must be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. + 7 + 1 + read-only + + + B_0x0 + Normal port detected (connected to SDP, ACA, CDP or DCP). + 0x0 + + + B_0x1 + PS2 port or proprietary charger detected. + 0x1 + + + + + DPPU_DPD + DP pull-up / DPDM pull-down +Device mode +This bit is set by software to enable the embedded pull-up on DP line. Clearing it to 0 can be used to signal disconnect to the host when needed by the user software. +Host mode +This bit is set by software to enable the embedded pull-down on DP and DM lines. + 15 + 1 + read-write + + + + + + + VREFBUF + VREFBUF address block description + VREFBUF + 0x40010030 + + 0x0 + 0x8 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x00 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + ENVR + Voltage reference buffer mode enable +This bit is used to enable the voltage reference buffer mode. + 0 + 1 + read-write + + + B_0x0 + Internal voltage reference mode disable (external voltage reference mode). + 0x0 + + + B_0x1 + Internal voltage reference mode (reference buffer enable or hold mode) enable. + 0x1 + + + + + HIZ + High impedance mode +This bit controls the analog switch to connect or not the V<sub>REF+</sub> pin. +Refer to Table172: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. + 1 + 1 + read-write + + + B_0x0 + V<sub>REF+</sub> pin is internally connected to the voltage reference buffer output. + 0x0 + + + B_0x1 + V<sub>REF+</sub> pin is high impedance. + 0x1 + + + + + VRS + Voltage reference scale +This bit selects the value generated by the voltage reference buffer. + 2 + 1 + read-write + + + B_0x0 + Voltage reference set to V<sub>REF_OUT1</sub> (around 2.0481V). + 0x0 + + + B_0x1 + Voltage reference set to V<sub>REF_OUT2</sub> (around 2.51V). + 0x1 + + + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + B_0x0 + the voltage reference buffer output is not ready. + 0x0 + + + B_0x1 + the voltage reference buffer output reached the requested level. + 0x1 + + + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + TRIM + None + 0 + 6 + read-write + + + + + + + WWDG + WWDG address block description + WWDG + 0x40002C00 + + 0x0 + 0xC + registers + + + WWDG + Window watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + WWDG control register + 0x000 + 0x20 + 0x0000007F + 0xFFFFFFFF + + + T + 7-bit counter (MSB to LSB) +These bits contain the value of the watchdog counter, decremented every +(4096 x 2<sup>WDGTB[2:0]</sup>) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). + 0 + 7 + read-write + + + WDGA + Activation bit +This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset. + 7 + 1 + read-write + + + B_0x0 + Watchdog disabled + 0x0 + + + B_0x1 + Watchdog enabled + 0x1 + + + + + + + WWDG_CFR + WWDG_CFR + WWDG configuration register + 0x004 + 0x20 + 0x0000007F + 0xFFFFFFFF + + + W + 7-bit window value +These bits contain the window value to be compared with the down-counter. + 0 + 7 + read-write + + + EWI + Early wake-up interrupt enable +Set by software and cleared by hardware after a reset. When set, an interrupt occurs whenever the counter reaches the value 0x40. + 9 + 1 + read-write + + + WDGTB + Timer base +The timebase of the prescaler can be modified as follows: + 11 + 3 + read-write + + + B_0x0 + CK counter clock (PCLK div 4096) div 1 + 0x0 + + + B_0x1 + CK counter clock (PCLK div 4096) div 2 + 0x1 + + + B_0x2 + CK counter clock (PCLK div 4096) div 4 + 0x2 + + + B_0x3 + CK counter clock (PCLK div 4096) div 8 + 0x3 + + + B_0x4 + CK counter clock (PCLK div 4096) div 16 + 0x4 + + + B_0x5 + CK counter clock (PCLK div 4096) div 32 + 0x5 + + + B_0x6 + CK counter clock (PCLK div 4096) div 64 + 0x6 + + + B_0x7 + CK counter clock (PCLK div 4096) div 128 + 0x7 + + + + + + + WWDG_SR + WWDG_SR + WWDG status register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EWIF + Early wake-up interrupt flag +This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled. + 0 + 1 + read-write + + + + + + + diff --git a/svd/STM32U0xx/STM32U083.svd b/svd/STM32U0xx/STM32U083.svd new file mode 100644 index 0000000..da29127 --- /dev/null +++ b/svd/STM32U0xx/STM32U083.svd @@ -0,0 +1,98312 @@ + + + + STM32U083 + 1.0 + STM32U083 + + CM0+ + r0p1 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x40012400 + + 0x0 + 0x30C + registers + + + ADC_COMP + ADC and COMP interrupts (ADC combined with EXTI lines 17 and 18) + 12 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready +This bit is set by hardware after the ADC has been enabled (ADEN+1) and when the ADC reaches a state where it is ready to accept conversion requests. +It is cleared by software writing 1 to it. + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag +This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1. + 1 + 1 + read-write + + + B_0x0 + Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag +This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. + 2 + 1 + read-write + + + B_0x0 + Channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Channel conversion complete + 0x1 + + + + + EOS + End of sequence flag +This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. + 3 + 1 + read-write + + + B_0x0 + Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Conversion sequence complete + 0x1 + + + + + OVR + ADC overrun +This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + AWD1 + Analog watchdog 1 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. + 7 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it. + 8 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag +This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1. + 9 + 1 + read-write + + + B_0x0 + No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog event occurred + 0x1 + + + + + EOCAL + End Of Calibration flag +This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. + 11 + 1 + read-write + + + B_0x0 + Calibration is not complete + 0x0 + + + B_0x1 + Calibration is complete + 0x1 + + + + + CCRDY + Channel Configuration Ready flag +This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. +Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration. + 13 + 1 + read-write + + + B_0x0 + Channel configuration update not applied. + 0x0 + + + B_0x1 + Channel configuration update is applied. + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable +This bit is set and cleared by software to enable/disable the ADC Ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled. + 0x0 + + + B_0x1 + ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable +This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. + 0x1 + + + + + EOCIE + End of conversion interrupt enable +This bit is set and cleared by software to enable/disable the end of conversion interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled + 0x0 + + + B_0x1 + EOC interrupt enabled. An interrupt is generated when the EOC bit is set. + 0x1 + + + + + EOSIE + End of conversion sequence interrupt enable +This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. An interrupt is generated when the EOS bit is set. + 0x1 + + + + + OVRIE + Overrun interrupt enable +This bit is set and cleared by software to enable/disable the overrun interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable +This bit is set and cleared by software to enable/disable the analog watchdog interrupt. +Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Analog watchdog interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog interrupt enabled + 0x1 + + + + + EOCALIE + End of calibration interrupt enable +This bit is set and cleared by software to enable/disable the end of calibration interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + End of calibration interrupt disabled + 0x0 + + + B_0x1 + End of calibration interrupt enabled + 0x1 + + + + + CCRDYIE + Channel Configuration Ready Interrupt enable +This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. +Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Channel configuration ready interrupt disabled + 0x0 + + + B_0x1 + Channel configuration ready interrupt enabled + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADEN + ADC enable command +This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. +It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command + 1 + 1 + read-write + + + B_0x0 + No ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. + 0x1 + + + + + ADSTART + ADC start conversion command + 2 + 1 + read-write + + + B_0x0 + No ADC conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. + 0x1 + + + + + ADSTP + ADC stop conversion command + 4 + 1 + read-write + + + B_0x0 + No ADC stop conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. + 0x1 + + + + + ADVREGEN + ADC Voltage Regulator Enable + 28 + 1 + read-write + + + B_0x0 + ADC voltage regulator disabled + 0x0 + + + B_0x1 + ADC voltage regulator enabled + 0x1 + + + + + ADCAL + ADC calibration +This bit is set by software to start the calibration of the ADC. + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. + 0x1 + + + + + + + ADC_CFGR1 + ADC_CFGR1 + ADC configuration register 1 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable +This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration +This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN1=11. +For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. + 1 + 1 + read-write + + + B_0x0 + DMA one shot mode selected + 0x0 + + + B_0x1 + DMA circular mode selected + 0x1 + + + + + SCANDIR + Scan sequence direction +This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Upward scan (from CHSEL0 to CHSEL) + 0x0 + + + B_0x1 + Backward scan (from CHSEL to CHSEL0) + 0x1 + + + + + RES + Data resolution +These bits are written by software to select the resolution of the conversion. + 3 + 2 + read-write + + + B_0x0 + 12 bits + 0x0 + + + B_0x1 + 10 bits + 0x1 + + + B_0x2 + 8 bits + 0x2 + + + B_0x3 + 6 bits + 0x3 + + + + + ALIGN + Data alignment +This bit is set and cleared by software to select right or left alignment. Refer to Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332 + 5 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + EXTSEL + External trigger selection +These bits select the external event used to trigger the start of conversion (refer to Table160: External triggers for details): + 6 + 3 + read-write + + + B_0x0 + TRG0 + 0x0 + + + B_0x1 + TRG1 + 0x1 + + + B_0x2 + TRG2 + 0x2 + + + B_0x3 + TRG3 + 0x3 + + + B_0x4 + TRG4 + 0x4 + + + B_0x5 + TRG5 + 0x5 + + + B_0x6 + TRG6 + 0x6 + + + B_0x7 + TRG7 + 0x7 + + + + + EXTEN + External trigger enable and polarity selection +These bits are set and cleared by software to select the external trigger polarity and enable the trigger. + 10 + 2 + read-write + + + B_0x0 + Hardware trigger detection disabled (conversions can be started by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + OVRMOD + Overrun management mode +This bit is set and cleared by software and configure the way data overruns are managed. + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / continuous conversion mode +This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + WAIT + Wait conversion mode +This bit is set and cleared by software to enable/disable wait conversion mode.<sup>.</sup> + 14 + 1 + read-write + + + B_0x0 + Wait conversion mode off + 0x0 + + + B_0x1 + Wait conversion mode on + 0x1 + + + + + AUTOFF + Auto-off mode +This bit is set and cleared by software to enable/disable auto-off mode.<sup>.</sup> + 15 + 1 + read-write + + + B_0x0 + Auto-off mode disabled + 0x0 + + + B_0x1 + Auto-off mode enabled + 0x1 + + + + + DISCEN + Discontinuous mode +This bit is set and cleared by software to enable/disable discontinuous mode. +Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode disabled + 0x0 + + + B_0x1 + Discontinuous mode enabled + 0x1 + + + + + CHSELRMOD + Mode selection of the ADC_CHSELR register +This bit is set and cleared by software to control the ADC_CHSELR feature: +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 21 + 1 + read-write + + + B_0x0 + Each bit of the ADC_CHSELR register enables an input + 0x0 + + + B_0x1 + ADC_CHSELR register is able to sequence up to 8 channels + 0x1 + + + + + AWD1SGL + Enable the watchdog on a single channel or on all channels +This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled + 0x0 + + + B_0x1 + Analog watchdog 1 enabled + 0x1 + + + + + AWD1CH + Analog watchdog channel selection +These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. +..... +Others: Reserved +Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. + 26 + 5 + read-write + + + B_0x0 + ADC analog input Channel 0 monitored by AWD + 0x0 + + + B_0x1 + ADC analog input Channel 1 monitored by AWD + 0x1 + + + B_0x13 + ADC analog input Channel 19 monitored by AWD + 0x13 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OVSE + Oversampler Enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 0 + 1 + read-write + + + B_0x0 + Oversampler disabled + 0x0 + + + B_0x1 + Oversampler enabled + 0x1 + + + + + OVSR + Oversampling ratio +This bit filed defines the number of oversampling ratio. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift +This bit is set and cleared by software. +Others: Reserved +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TOVS + Triggered Oversampling +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively after a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a trigger + 0x1 + + + + + LFTRIG + Low frequency trigger mode enable +This bit is set and cleared by software. +Note: The software is allowed to write this bit only when ADEN bit is cleared. + 29 + 1 + read-write + + + B_0x0 + Low Frequency Trigger Mode disabled + 0x0 + + + B_0x1 + Low Frequency Trigger Mode enabled + 0x1 + + + + + CKMODE + ADC clock mode +These bits are set and cleared by software to define how the analog ADC is clocked: +In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. +Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10). + 30 + 2 + read-write + + + B_0x0 + ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) + 0x0 + + + B_0x1 + PCLK/2 (Synchronous clock mode) + 0x1 + + + B_0x2 + PCLK/4 (Synchronous clock mode) + 0x2 + + + + + + + ADC_SMPR + ADC_SMPR + ADC sampling time register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMP1 + Sampling time selection 1 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMP2 + Sampling time selection 2 +These bits are written by software to select the sampling time that applies to all channels. +Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 3 + read-write + + + B_0x0 + 1.5 ADC clock cycles + 0x0 + + + B_0x1 + 3.5 ADC clock cycles + 0x1 + + + B_0x2 + 7.5 ADC clock cycles + 0x2 + + + B_0x3 + 12.5 ADC clock cycles + 0x3 + + + B_0x4 + 19.5 ADC clock cycles + 0x4 + + + B_0x5 + 39.5 ADC clock cycles + 0x5 + + + B_0x6 + 79.5 ADC clock cycles + 0x6 + + + B_0x7 + 160.5 ADC clock cycles + 0x7 + + + + + SMPSEL0 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL1 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL2 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL3 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL4 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL5 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL6 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL7 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL8 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL9 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL10 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL11 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL12 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 20 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL13 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 21 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL14 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL15 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL16 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 24 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL17 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 25 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL18 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 26 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + SMPSEL19 + Channel-x sampling time selection (x1=119 to 0) +These bits are written by software to define which sampling time is used. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 27 + 1 + read-write + + + B_0x0 + Sampling time of CHANNELx use the setting of SMP1[2:0] register. + 0x0 + + + B_0x1 + Sampling time of CHANNELx use the setting of SMP2[2:0] register. + 0x1 + + + + + + + ADC_AWD1TR + ADC_AWD1TR + ADC watchdog threshold register + 0x20 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT1 + Analog watchdog 1 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_AWD2TR + ADC_AWD2TR + ADC watchdog threshold register + 0x24 + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT2 + Analog watchdog 2 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_CHSELR + ADC_CHSELR + ADC channel selection register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CHSEL0 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 0 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL1 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 1 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL2 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 2 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL3 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 3 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL4 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 4 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL5 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 5 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL6 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 6 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL7 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 7 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL8 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 8 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL9 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 9 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL10 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 10 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL11 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 11 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL12 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 12 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL13 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 13 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL14 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 14 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL15 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 15 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL16 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 16 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL17 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 17 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL18 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 18 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + CHSEL19 + Channel-x selection +These bits are written by software and define which channels are part of the sequence of channels to be converted. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). +Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. + 19 + 1 + read-write + + + B_0x0 + Input Channel-x is not selected for conversion + 0x0 + + + B_0x1 + Input Channel-x is selected for conversion + 0x1 + + + + + + + ADC_CHSELR_ALTERNATE + ADC_CHSELR_ALTERNATE + ADC channel selection register + ADC_CHSELR + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SQ1 + 1st conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 0 + 4 + read-write + + + SQ2 + 2nd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 4 + 4 + read-write + + + SQ3 + 3rd conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 4 + read-write + + + SQ4 + 4th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 4 + read-write + + + SQ5 + 5th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 4 + read-write + + + SQ6 + 6th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 20 + 4 + read-write + + + SQ7 + 7th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +Refer to SQ8[3:0] for a definition of channel selection. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 24 + 4 + read-write + + + SQ8 + 8th conversion of the sequence +These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. +When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. +... +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 28 + 4 + read-write + + + B_0x0 + CH0 + 0x0 + + + B_0x1 + CH1 + 0x1 + + + B_0xC + CH12 + 0xC + + + B_0xD + CH13 + 0xD + + + B_0xE + CH14 + 0xE + + + B_0xF + No channel selected (End of sequence) + 0xF + + + + + + + ADC_AWD3TR + ADC_AWD3TR + ADC watchdog threshold register + 0x2C + 0x20 + 0x0FFF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3lower threshold +These bits are written by software to define the lower threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 0 + 12 + read-write + + + HT3 + Analog watchdog 3 higher threshold +These bits are written by software to define the higher threshold for the analog watchdog. +Refer to Section113.8: Analog window watchdogs on page1337. + 16 + 12 + read-write + + + + + ADC_DR + ADC_DR + ADC data register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DATA + Converted data +These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD2CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + AWD2CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). +Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD2 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD2 + 0x1 + + + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC Analog Watchdog 3 Configuration register + 0xA4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AWD3CH0 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 0 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH1 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 1 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH2 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 2 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH3 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 3 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH4 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 4 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH5 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 5 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH6 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 6 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH7 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 7 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH8 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 8 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH9 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 9 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH10 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 10 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH11 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 11 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH12 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 12 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH13 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 13 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH14 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 14 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH15 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 15 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH16 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 16 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH17 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 17 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH18 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 18 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + AWD3CH19 + Analog watchdog channel selection +These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). +Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). + 19 + 1 + read-write + + + B_0x0 + ADC analog channel-x is not monitored by AWD3 + 0x0 + + + B_0x1 + ADC analog channel-x is monitored by AWD3 + 0x1 + + + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factor + 0xB4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALFACT + Calibration factor +These bits are written by hardware or by software. +Once a calibration is complete,1they are updated by hardware with the calibration factors. +Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new conversion is launched. +Just after a calibration is complete, DATA[6:0] contains the calibration factor. +Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). + 0 + 7 + read-write + + + + + ADC_CCR + ADC_CCR + ADC common configuration register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESC + ADC prescaler +Set and cleared by software to select the frequency of the clock to the ADC. +Other: Reserved +Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10). + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + V<sub>REFINT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>REFINT</sub>. +Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 22 + 1 + read-write + + + B_0x0 + V<sub>REFINT</sub> disabled + 0x0 + + + B_0x1 + V<sub>REFINT</sub> enabled + 0x1 + + + + + TSEN + Temperature sensor enable +This bit is set and cleared by software to enable/disable the temperature sensor. +Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). + 23 + 1 + read-write + + + B_0x0 + Temperature sensor disabled + 0x0 + + + B_0x1 + Temperature sensor enabled + 0x1 + + + + + VBATEN + V<sub>BAT</sub> enable +This bit is set and cleared by software to enable/disable the V<sub>BAT</sub> channel. +Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing) + 24 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> channel disabled + 0x0 + + + B_0x1 + V<sub>BAT</sub> channel enabled + 0x1 + + + + + + + + + AES + AES register block + AES + 0x40026000 + + 0x0 + 0x400 + registers + + + AES_RNG + AES and RNG global interrupts + 31 + + + + AES_CR + AES_CR + AES control register + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Enable +This bit enables/disables the AES peripheral. +At any moment, clearing then setting the bit re-initializes the AES peripheral. +This bit is automatically cleared by hardware upon the completion of the key preparation (MODE[1:0] at 0x1) and upon the completion of GCM/GMAC/CCM initialization phase. +The bit cannot be set as long as KEYVALID1is cleared + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DATATYPE + Data type +This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping. This swapping is defined in Section121.4.14: AES data registers and data swapping. +Attempts to write the bitfield are ignored when EN is set before the write access and it is not cleared by that write access. + 1 + 2 + read-write + + + B_0x0 + No swapping (32-bit data). + 0x0 + + + B_0x1 + Half-word swapping (16-bit data) + 0x1 + + + B_0x2 + Byte swapping (8-bit data) + 0x2 + + + B_0x3 + Bit-level swapping + 0x3 + + + + + MODE + Operating mode +This bitfield selects the AES operating mode: +Attempts to write the bitfield are ignored when EN is set before the write access and it is not cleared by that write access. + 3 + 2 + read-write + + + B_0x0 + Encryption + 0x0 + + + B_0x1 + Key derivation (or key preparation), for ECB/CBC decryption only + 0x1 + + + B_0x2 + Decryption + 0x2 + + + + + CHMOD + CHMOD[1:0]: Chaining mode +This bitfield selects the AES chaining mode: +others: Reserved +Attempts to write the bitfield are ignored when EN is set before the write access and it is not cleared by that write access. + 5 + 2 + read-write + + + B_0x0 + Electronic codebook (ECB) + 0x0 + + + B_0x1 + Cipher-block chaining (CBC) + 0x1 + + + B_0x2 + Counter mode (CTR) + 0x2 + + + B_0x3 + Galois counter mode (GCM) and Galois message authentication code (GMAC) + 0x3 + + + + + DMAINEN + DMA input enable +This bit enables automatic generation of DMA requests during the data phase, for incoming data transfers to AES via DMA. +Setting this bit is ignored when MODE[1:0] is at 0x1 (key derivation). + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMAOUTEN + DMA output enable +This bit enables automatic generation of DMA requests during the data phase, for outgoing data transfers from AES via DMA. +Setting this bit is ignored when MODE[1:0] is at 0x1 (key derivation). + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GCMPH + GCM or CCM phase selection +This bitfield selects the phase, applicable only with GCM, GMAC or CCM chaining modes. + 13 + 2 + read-write + + + B_0x0 + Initialization phase + 0x0 + + + B_0x1 + Header phase + 0x1 + + + B_0x2 + Payload phase + 0x2 + + + B_0x3 + Final phase + 0x3 + + + + + CHMOD_1 + CHMOD[2] + 16 + 1 + read-write + + + KEYSIZE + Key size selection +This bitfield defines the key length in bits of the key used by AES. +Attempts to write the bit are ignored when the EN is set before the write access and it is not cleared by that write access. + 18 + 1 + read-write + + + B_0x0 + 128-bit + 0x0 + + + B_0x1 + 256-bit + 0x1 + + + + + NPBLB + Number of padding bytes in last block +This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. +... + 20 + 4 + read-write + + + B_0x0 + All bytes are valid (no padding) + 0x0 + + + B_0x1 + Padding for the last LSB byte + 0x1 + + + B_0xF + Padding for the 15 LSB bytes of last block. + 0xF + + + + + IPRST + AES peripheral software reset +Setting the bit resets the AES peripheral, putting all registers to their default values, except the IPRST bit itself. Hence, any key-relative data are lost. For this reason, it is recommended to set the bit before handing over the AES to a less secure application. +The bit must be kept low while writing any configuration registers. + 31 + 1 + read-write + + + + + AES_SR + AES_SR + AES status register + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDERRF + Read error flag +This bit is set when an unexpected read to the AES_DOUTR register occurred. When set RDERRF bit has no impact on the AES operations. +The flag setting generates an interrupt if the RWEIE bit of the AES_IER register is set. +The flag is cleared by setting the RWEIF bit of the AES_ICR register. + 1 + 1 + read-only + + + B_0x0 + No error + 0x0 + + + B_0x1 + Unexpected read to AES_DOUTR register occurred during computation or data input phase. + 0x1 + + + + + WRERRF + Write error flag +This bit is set when an unexpected write to the AES_DINR register occurred. When set WRERRF bit has no impact on the AES operations. +The flag setting generates an interrupt if the RWEIE bit of the AES_IER register is set. +The flag is cleared by setting the RWEIF bit of the AES_ICR register. + 2 + 1 + read-only + + + B_0x0 + No error + 0x0 + + + B_0x1 + Unexpected write to AES_DINR register occurred during computation or data output phase. + 0x1 + + + + + BUSY + Busy +This flag indicates whether AES is idle or busy. +AES is flagged as idle when disabled (when EN is low) or when the last processing is completed. +AES is flagged as busy when processing a block data, preparing a key (ECB or CBC decryption only). +When GCM encryption is selected, this flag must be at zero before suspending current process to manage a higher-priority message. + 3 + 1 + read-only + + + B_0x0 + Idle + 0x0 + + + B_0x1 + Busy + 0x1 + + + + + KEYVALID + Key valid flag +This bit is set by hardware when the key of size defined by KEYSIZE is loaded in AES_KEYRx key registers. +The EN bit can only be set when KEYVALID is set. +The key must be written in the key registers in the correct sequence, otherwise the KEIF flag is set and KEYVALID remains cleared. +If set, KEIF must be cleared through the AES_ICR register, otherwise KEYVALID cannot be set. See the KEIF flag description for more details. +For further information on key loading, refer to Section121.4.15: AES key registers. + 7 + 1 + read-only + + + B_0x0 + Key not valid + 0x0 + + + B_0x1 + Key valid + 0x1 + + + + + + + AES_DINR + AES_DINR + AES data input register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DIN + Data input +A four-fold sequential write to this bitfield during the Input phase results in writing a complete 16-bytes block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 16-bytes input buffer. +Reads return zero. + 0 + 32 + write-only + + + + + AES_DOUTR + AES_DOUTR + AES data output register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DOUT + Data output +This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon +the computation completion (CCF flag set), virtually reads a complete 16-byte block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are +handled by the data swap block according to the DATATYPE[1:0] bitfield. +Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. + 0 + 32 + read-only + + + + + AES_KEYR0 + AES_KEYR0 + AES key register 0 + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [31:0] +These are bits [31:0] of the write-only bitfield KEY[255:0] AES encryption or decryption key, depending on the MODE[1:0] bitfield of the AES_CR register. +Writes to AES_KEYRx registers are ignored when AES is enabled (EN bit set). + A special writing sequence is required. In this sequence, any valid write to AES_KEYRx register clears the KEYVALID flag except for the sequence-completing write that sets it. Also refer to the description of the KEYVALID flag in the AES_SR register. + 0 + 32 + write-only + + + + + AES_KEYR1 + AES_KEYR1 + AES key register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [63:32] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_KEYR2 + AES_KEYR2 + AES key register 2 + 0x018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [95:64] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_KEYR3 + AES_KEYR3 + AES key register 3 + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [127:96] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_IVR0 + AES_IVR0 + AES initialization vector register 0 + 0x020 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [31:0] +AES_IVRx registers store the 128-bit initialization vector or the nonce, depending on the chaining mode selected. This value is updated by hardware after each computation round (when applicable). +Write to this register is ignored when EN bit is set in AES_SR register + 0 + 32 + read-write + + + + + AES_IVR1 + AES_IVR1 + AES initialization vector register 1 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [63:32] +Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. + 0 + 32 + read-write + + + + + AES_IVR2 + AES_IVR2 + AES initialization vector register 2 + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [95:64] +Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. + 0 + 32 + read-write + + + + + AES_IVR3 + AES_IVR3 + AES initialization vector register 3 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [127:96] +Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. + 0 + 32 + read-write + + + + + AES_KEYR4 + AES_KEYR4 + AES key register 4 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [159:128] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_KEYR5 + AES_KEYR5 + AES key register 5 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [191:160] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_KEYR6 + AES_KEYR6 + AES key register 6 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [223:192] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_KEYR7 + AES_KEYR7 + AES key register 7 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [255:224] +Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield and for information relative to writing AES_KEYRx registers. + 0 + 32 + write-only + + + + + AES_SUSPR0 + AES_SUSPR0 + AES suspend registers + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR1 + AES_SUSPR1 + AES suspend registers + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR2 + AES_SUSPR2 + AES suspend registers + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR3 + AES_SUSPR3 + AES suspend registers + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR4 + AES_SUSPR4 + AES suspend registers + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR5 + AES_SUSPR5 + AES suspend registers + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR6 + AES_SUSPR6 + AES suspend registers + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_SUSPR7 + AES_SUSPR7 + AES suspend registers + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data +AES_SUSPRx registers contain the complete internal register states of the AES when the GCM, GMAC or CCM processing of the current task is suspended to process a higher-priority task. Refer to Section121.4.8: AES suspend and resume operations for more details. +Read to this register returns zero when EN bit is cleared in AES_SR register. +AES_SUSPRx registers are not used in other chaining modes than GCM, GMAC or CCM. + 0 + 32 + read-write + + + + + AES_IER + AES_IER + AES interrupt enable register + 0x300 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCFIE + Computation complete flag interrupt enable +This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set. + 0 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + RWEIE + Read or write error interrupt enable +This bit enables or disables (masks) the AES interrupt generation when RWEIF (read and/or write error flag) is set. + 1 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + KEIE + Key error interrupt enable +This bit enables or disables (masks) the AES interrupt generation when KEIF (key error flag) is set. + 2 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + + + AES_ISR + AES_ISR + AES interrupt status register + 0x304 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag +This flag indicates whether the computation is completed. It is significant only when the DMAOUTEN bit is cleared, and it may stay high when DMAOUTEN is set. +The flag setting generates an interrupt if the CCFIE bit of the AES_IER register is set. +The flag is cleared by setting the corresponding bit of the AES_ICR register. + 0 + 1 + read-only + + + B_0x0 + Not completed + 0x0 + + + B_0x1 + Completed + 0x1 + + + + + RWEIF + Read or write error interrupt flag +This read-only bit is set by hardware when a RDERRF or a WRERRF error flag is set in the AES_SR register. +The flag setting generates an interrupt if the RWEIE bit of the AES_IER register is set. +The flag is cleared by setting the corresponding bit of the AES_ICR register. +The flags has no meaning when key derivation mode is selected. +See the AES_SR register for details. + 1 + 1 + read-only + + + B_0x0 + No read or write error detected + 0x0 + + + B_0x1 + Read or write error detected + 0x1 + + + + + KEIF + Key error interrupt flag +This read-only bit is set by hardware when the key information fails to load into key registers. +The flag setting generates an interrupt if the KEIE bit of the AES_IER register is set. +The flag is cleared by setting the corresponding bit of the AES_ICR register. +KEIF is raised upon any of the following events: +AES_KEYRx register write does not respect the correct order. (For KEYSIZE1cleared, AES_KEYR0 then AES_KEYR1 then AES_KEYR2 then AES_KEYR3 register, or reverse. For KEYSIZE set, AES_KEYR0 then AES_KEYR1 then AES_KEYR2 then AES_KEYR3 then AES_KEYR4 then AES_KEYR5 then AES_KEYR6 then AES_KEYR7, or reverse). +KEIF must be cleared by the application software, otherwise KEYVALID cannot be set. + 2 + 1 + read-only + + + B_0x0 + No key error detected + 0x0 + + + B_0x1 + Key information failed to load into key registers + 0x1 + + + + + + + AES_ICR + AES_ICR + AES interrupt clear register + 0x308 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag clear +Setting this bit clears the CCF status bit of the AES_ISR register. + 0 + 1 + write-only + + + RWEIF + Read or write error interrupt flag clear +Setting this bit clears the RWEIF status bit of the AES_ISR register, and clears both RDERRF and WRERRF flags in the AES_SR register. + 1 + 1 + write-only + + + KEIF + Key error interrupt flag clear +Setting this bit clears the KEIF status bit of the AES_ISR register. + 2 + 1 + write-only + + + + + + + COMP + COMP address block description + COMP + 0x40010200 + + 0x0 + 0x8 + registers + + + + COMP1_CSR + COMP1_CSR + Comparator 1 control and status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Comparator 1 enable bit +This bit is controlled by software (if not locked). It enables the comparator 1: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + INMSEL + Comparator 1 signal selector for inverting input INM +This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 1: +Refer to Table176: COMP1 inverting input assignment. + 4 + 4 + read-write + + + INPSEL + Comparator 1 signal selector for noninverting input +This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 1 (also see the WINMODE bit): +Refer to Table175: COMP1 noninverting input assignment. + 8 + 3 + read-write + + + WINMODE + Comparator 1 noninverting input selector for window mode +This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 1: + 11 + 1 + read-write + + + B_0x0 + Signal selected with INPSEL[2:0] bitfield of this register + 0x0 + + + B_0x1 + COMP_INP signal of the comparator 2 (required for window mode, see Figure164) + 0x1 + + + + + WINOUT + Comparator 1 output selector +This bit is controlled by software (if not locked). It selects the comparator 1 output: + 14 + 1 + read-write + + + B_0x0 + COMP_VALUE + 0x0 + + + B_0x1 + COMP_VALUE XOR COMP_VALUE (required for window mode, see Figure164) + 0x1 + + + + + POLARITY + Comparator 1 polarity selector +This bit is controlled by software (if not locked). It selects the comparator 1 output polarity: + 15 + 1 + read-write + + + B_0x0 + Non-inverted + 0x0 + + + B_0x1 + Inverted + 0x1 + + + + + HYST + Comparator 1 hysteresis selector +This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1: + 16 + 2 + read-write + + + B_0x0 + No hysteresis + 0x0 + + + B_0x1 + Low hysteresis + 0x1 + + + B_0x2 + Medium hysteresis + 0x2 + + + B_0x3 + High hysteresis + 0x3 + + + + + PWRMODE + Comparator 1 power mode selector +This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1: + 18 + 2 + read-write + + + B_0x0 + High speed/high power + 0x0 + + + B_0x1 + Medium speed/medium power + 0x1 + + + B_0x2 + Medium speed/medium power + 0x2 + + + B_0x3 + Low speed/low power + 0x3 + + + + + BLANKSEL + Comparator 1 blanking source selector +This bitfield is controlled by software (if not locked). It selects the blanking source: +Others: Reserved, must not be used + 20 + 5 + read-write + + + B_0x0 + No blanking + 0x0 + + + B_0x1 + TIM1 OC4 enabled as blanking source + 0x1 + + + B_0x2 + TIM1 OC5 enabled as blanking source + 0x2 + + + B_0x4 + TIM2 OC3 enabled as blanking source + 0x4 + + + B_0x8 + TIM3 OC3 enabled as blanking source + 0x8 + + + B_0x10 + TIM15 OC2 enabled as blanking source + 0x10 + + + + + VALUE + Comparator 1 output status +This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in Figure163. + 30 + 1 + read-only + + + LOCK + COMP_CSR register lock +This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. + 31 + 1 + read-write + + + B_0x0 + Not locked + 0x0 + + + B_0x1 + Locked + 0x1 + + + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Comparator 2 enable bit +This bit is controlled by software (if not locked). It enables the comparator 2: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + INMSEL + Comparator 2 signal selector for inverting input INM +This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 2: +Refer to Table178: COMP2 inverting input assignment. + 4 + 4 + read-write + + + INPSEL + Comparator 2 signal selector for noninverting input +This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 2 (also see the WINMODE bit): +Refer to Table177: COMP2 noninverting input assignment. + 8 + 2 + read-write + + + WINMODE + Comparator 2 noninverting input selector for window mode +This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 2: + 11 + 1 + read-write + + + B_0x0 + Signal selected with INPSEL[1:0] bitfield of this register + 0x0 + + + B_0x1 + COMP_INP signal of the comparator 1 (required for window mode, see Figure164) + 0x1 + + + + + WINOUT + Comparator 2 output selector +This bit is controlled by software (if not locked). It selects the comparator 2 output: + 14 + 1 + read-write + + + B_0x0 + COMP_VALUE + 0x0 + + + B_0x1 + COMP_VALUE XOR COMP_VALUE (required for window mode, see Figure164) + 0x1 + + + + + POLARITY + Comparator 2 polarity selector +This bit is controlled by software (if not locked). It selects the comparator 2 output polarity: + 15 + 1 + read-write + + + B_0x0 + Non-inverted + 0x0 + + + B_0x1 + Inverted + 0x1 + + + + + HYST + Comparator 2 hysteresis selector +This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2: + 16 + 2 + read-write + + + B_0x0 + No hysteresis + 0x0 + + + B_0x1 + Low hysteresis + 0x1 + + + B_0x2 + Medium hysteresis + 0x2 + + + B_0x3 + High hysteresis + 0x3 + + + + + PWRMODE + Comparator 2 power mode selector +This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2: + 18 + 2 + read-write + + + B_0x0 + High speed/high power + 0x0 + + + B_0x1 + Medium speed/medium power + 0x1 + + + B_0x2 + Medium speed/medium power + 0x2 + + + B_0x3 + Low speed/low power + 0x3 + + + + + BLANKSEL + Comparator 2 blanking source selector +This bitfield is controlled by software (if not locked). It selects the blanking source: +Others: Reserved, must not be used + 20 + 5 + read-write + + + B_0x0 + No blanking + 0x0 + + + B_0x1 + TIM1 OC4 enabled as blanking source + 0x1 + + + B_0x2 + TIM1 OC5 enabled as blanking source + 0x2 + + + B_0x4 + TIM2 OC3 enabled as blanking source + 0x4 + + + B_0x8 + TIM3 OC3 enabled as blanking source + 0x8 + + + B_0x10 + TIM15 OC2 enabled as blanking source + 0x10 + + + + + VALUE + Comparator 2 output status +This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in Figure163. + 30 + 1 + read-only + + + LOCK + COMP_CSR register lock +This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. + 31 + 1 + read-write + + + B_0x0 + Not locked + 0x0 + + + B_0x1 + Locked + 0x1 + + + + + + + + + CRC + CRC address block description + CRC + 0x40023000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected (RTYPE_IN1=10 or 1) + 0x0 + + + B_0x1 + Bit reversal done by byte (RTYPE_IN1=10) or half-word reversal done by word (RTYPE_IN1=11) + 0x1 + + + B_0x2 + Bit reversal done by half-word (RTYPE_IN1=10) or byte reversal done by word (RTYPE_IN1=11) + 0x2 + + + B_0x3 + Bit reversal done by word (RTYPE_IN1=10) or bit order is not affected (RTYPE_IN1=11) + 0x3 + + + + + REV_OUT + Reverse output data +This bitfield controls the reversal of the bit order of the output data. + 7 + 2 + read-write + + + B_0x0 + Bit order not affected (RTYPE_OUT1=10 or 1) + 0x0 + + + B_0x1 + Bit-reversed output format (RTYPE_OUT1=10) or half-word reversal done by word (RTYPE_OUT1=11) + 0x1 + + + B_0x2 + Bit order not affected (RTYPE_OUT1=10) or byte reversal done by word (RTYPE_OUT1=11) + 0x2 + + + B_0x3 + Bit order not affected (RTYPE_OUT1=10 or 1) + 0x3 + + + + + RTYPE_IN + Reverse type input +This bit controls the reversal granularity of the input data. + 9 + 1 + read-write + + + B_0x0 + Bit level input + 0x0 + + + B_0x1 + Byte or half-word level input + 0x1 + + + + + RTYPE_OUT + Reverse type output +This bit controls the reversal granularity of the output data. + 10 + 1 + read-write + + + B_0x0 + Bit level output + 0x0 + + + B_0x1 + Byte or half-word level output + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + CRS + CRS address block description + CRS + 0x40006C00 + + 0x0 + 0x10 + registers + + + + CRS_CR + CRS_CR + CRS control register + 0x00 + 0x20 + 0x00004000 + 0xFFFFFFFF + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + B_0x0 + SYNC event OK (SYNCOKF) interrupt disabled + 0x0 + + + B_0x1 + SYNC event OK (SYNCOKF) interrupt enabled + 0x1 + + + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + B_0x0 + SYNC warning (SYNCWARNF) interrupt disabled + 0x0 + + + B_0x1 + SYNC warning (SYNCWARNF) interrupt enabled + 0x1 + + + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + B_0x0 + Synchronization or trimming error (ERRF) interrupt disabled + 0x0 + + + B_0x1 + Synchronization or trimming error (ERRF) interrupt enabled + 0x1 + + + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + B_0x0 + Expected SYNC (ESYNCF) interrupt disabled + 0x0 + + + B_0x1 + Expected SYNC (ESYNCF) interrupt enabled + 0x1 + + + + + CEN + Frequency error counter enable +This bit enables the oscillator clock for the frequency error counter. +When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + B_0x0 + Frequency error counter disabled + 0x0 + + + B_0x1 + Frequency error counter enabled + 0x1 + + + + + AUTOTRIMEN + Automatic trimming enable +This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section15.4.4 for more details. + 6 + 1 + read-write + + + B_0x0 + Automatic trimming disabled, TRIM bits can be adjusted by the user. + 0x0 + + + B_0x1 + Automatic trimming enabled, TRIM bits are read-only and under hardware control. + 0x1 + + + + + SWSYNC + Generate software SYNC event +This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + A software SYNC event is generated. + 0x1 + + + + + TRIM + HSI48 oscillator smooth trimming +The default value of the HSI48 oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval. + 8 + 7 + read-write + + + + + CRS_CFGR + CRS_CFGR + CRS configuration register + 0x04 + 0x20 + 0x2022BB7F + 0xFFFFFFFF + + + RELOAD + Counter reload value +RELOAD is the value to be loaded in the frequency error counter with each SYNC event. +Refer to Section15.4.3 for more details about counter behavior. + 0 + 16 + read-write + + + FELIM + Frequency error limit +FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section15.4.4 for more details about FECAP evaluation. + 16 + 8 + read-write + + + SYNCDIV + SYNC divider +These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + read-write + + + B_0x0 + SYNC not divided (default) + 0x0 + + + B_0x1 + SYNC divided by 2 + 0x1 + + + B_0x2 + SYNC divided by 4 + 0x2 + + + B_0x3 + SYNC divided by 8 + 0x3 + + + B_0x4 + SYNC divided by 16 + 0x4 + + + B_0x5 + SYNC divided by 32 + 0x5 + + + B_0x6 + SYNC divided by 64 + 0x6 + + + B_0x7 + SYNC divided by 128 + 0x7 + + + + + SYNCSRC + SYNC signal source selection +These bits are set and cleared by software to select the SYNC signal source (see Table122): +Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF is not generated by the host. No SYNC signal is therefore provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs must be used as SYNC signal. + 28 + 2 + read-write + + + B_0x0 + crs_sync_in_1 selected as SYNC signal source + 0x0 + + + B_0x1 + crs_sync_in_2 selected as SYNC signal source + 0x1 + + + B_0x2 + crs_sync_in_3 selected as SYNC signal source + 0x2 + + + B_0x3 + crs_sync_in_4 selected as SYNC signal source + 0x3 + + + + + SYNCPOL + SYNC polarity selection +This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + read-write + + + B_0x0 + SYNC active on rising edge (default) + 0x0 + + + B_0x1 + SYNC active on falling edge + 0x1 + + + + + + + CRS_ISR + CRS_ISR + CRS interrupt and status register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYNCOKF + SYNC event OK flag +This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + read-only + + + B_0x0 + No SYNC event OK signaled + 0x0 + + + B_0x1 + SYNC event OK signaled + 0x1 + + + + + SYNCWARNF + SYNC warning flag +This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + read-only + + + B_0x0 + No SYNC warning signaled + 0x0 + + + B_0x1 + SYNC warning signaled + 0x1 + + + + + ERRF + Error flag +This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + read-only + + + B_0x0 + No synchronization or trimming error signaled + 0x0 + + + B_0x1 + Synchronization or trimming error signaled + 0x1 + + + + + ESYNCF + Expected SYNC flag +This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + read-only + + + B_0x0 + No expected SYNC signaled + 0x0 + + + B_0x1 + Expected SYNC signaled + 0x1 + + + + + SYNCERR + SYNC error +This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action has to be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + read-only + + + B_0x0 + No SYNC error signaled + 0x0 + + + B_0x1 + SYNC error signaled + 0x1 + + + + + SYNCMISS + SYNC missed +This flag is set by hardware when the frequency error counter reaches value FELIM * 128 and no SYNC is detected, meaning either that a SYNC pulse was missed, or the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, hence some other action must be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC), and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + read-only + + + B_0x0 + No SYNC missed error signaled + 0x0 + + + B_0x1 + SYNC missed error signaled + 0x1 + + + + + TRIMOVF + Trimming overflow or underflow +This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + read-only + + + B_0x0 + No trimming error signaled + 0x0 + + + B_0x1 + Trimming error signaled + 0x1 + + + + + FEDIR + Frequency error direction +FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + read-only + + + B_0x0 + Up-counting direction, the actual frequency is above the target + 0x0 + + + B_0x1 + Down-counting direction, the actual frequency is below the target + 0x1 + + + + + FECAP + Frequency error capture +FECAP is the frequency error counter value latched in the time of the last SYNC event. +Refer to Section15.4.4 for more details about FECAP usage. + 16 + 16 + read-only + + + + + CRS_ICR + CRS_ICR + CRS interrupt flag clear register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYNCOKC + SYNC event OK clear flag +Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + read-write + + + SYNCWARNC + SYNC warning clear flag +Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + read-write + + + ERRC + Error clear flag +Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + read-write + + + ESYNCC + Expected SYNC clear flag +Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + read-write + + + + + + + DAC + DAC address block description + DAC + 0x40007400 + + 0x0 + 0x50 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN1 + DAC channel1 enable +This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + read-write + + + B_0x0 + DAC channel1 disabled + 0x0 + + + B_0x1 + DAC channel1 enabled + 0x1 + + + + + TEN1 + DAC channel1 trigger enable +This bit is set and cleared by software to enable/disable DAC channel1 trigger. +Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle. + 1 + 1 + read-write + + + B_0x0 + DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register + 0x0 + + + B_0x1 + DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register + 0x1 + + + + + TSEL1 + DAC channel1 trigger selection +These bits select the external event used to trigger DAC channel1 +... +Refer to the trigger selection tables in Section114.4.2: DAC pins and internal signals for details on trigger configuration and mapping. +Note: Only used if bit TEN11=11 (DAC channel1 trigger enabled). + 2 + 4 + read-write + + + B_0x0 + SWTRIG1 + 0x0 + + + B_0x1 + dac_ch1_trg1 + 0x1 + + + B_0x2 + dac_ch1_trg2 + 0x2 + + + B_0xF + dac_ch1_trg15 + 0xF + + + + + WAVE1 + DAC channel1 noise/triangle wave generation enable +These bits are set and cleared by software. +1x: Triangle wave generation enabled +Only used if bit TEN11=11 (DAC channel1 trigger enabled). + 6 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP1 + DAC channel1 mask/amplitude selector + 8 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN1 + DAC channel1 DMA enable +This bit is set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + DAC channel1 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel1 DMA mode enabled + 0x1 + + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable +This bit is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + DAC channel1 DMA Underrun Interrupt disabled + 0x0 + + + B_0x1 + DAC channel1 DMA Underrun Interrupt enabled + 0x1 + + + + + CEN1 + DAC channel1 calibration enable +This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN11=10 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + read-write + + + B_0x0 + DAC channel1 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel1 in calibration mode + 0x1 + + + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWTRIG1 + DAC channel1 software trigger +This bit is set by software to trigger the DAC in software trigger mode. +Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data +These bits are written by software. They specify 12-bit data for DAC channel1. + 0 + 12 + read-write + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data +These bits are written by software. +They specify 12-bit data for DAC channel1. + 4 + 12 + read-write + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data +These bits are written by software. They specify 8-bit data for DAC channel1. + 0 + 8 + read-write + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DACC1DOR + DAC channel1 data output +These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + read-only + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAUDR1 + DAC channel1 DMA underrun flag +This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel1 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) + 0x1 + + + + + CAL_FLAG1 + DAC channel1 calibration offset status +This bit is set and cleared by hardware + 14 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST1 + DAC channel1 busy writing sample time flag +This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization). + 15 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written + 0x1 + + + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + OTRIM1 + DAC channel1 offset trimming value + 0 + 5 + read-write + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MODE1 + DAC channel1 mode +These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN11=10 and bit CEN11=10 in the DAC_CR register). If EN11=11 or CEN11=11 the write operation is ignored. +They can be set and cleared by software to select the DAC channel1 mode: +DAC channel1 in Normal mode +DAC channel1 in sample & hold mode +Note: This register can be modified only when EN11=10. + 0 + 3 + read-write + + + B_0x0 + DAC channel1 is connected to external pin with Buffer enabled + 0x0 + + + B_0x1 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled + 0x1 + + + B_0x2 + DAC channel1 is connected to external pin with Buffer disabled + 0x2 + + + B_0x3 + DAC channel1 is connected to on chip peripherals with Buffer disabled + 0x3 + + + B_0x4 + DAC channel1 is connected to external pin with Buffer enabled + 0x4 + + + B_0x5 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled + 0x5 + + + B_0x6 + DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled + 0x6 + + + B_0x7 + DAC channel1 is connected to on chip peripherals with Buffer disabled + 0x7 + + + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC channel1 sample and hold sample time register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE1 + DAC channel1 sample time (only valid in Sample and hold mode) +These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST11=11, the write operation is ignored. + 0 + 10 + read-write + + + + + DAC_SHHR + DAC_SHHR + DAC sample and hold time register + 0x48 + 0x20 + 0x00010001 + 0xFFFFFFFF + + + THOLD1 + DAC channel1 hold time (only valid in Sample and hold mode) +Hold time1=1(THOLD[9:0]) x LSI clock period +Note: This register can be modified only when EN11=10. + 0 + 10 + read-write + + + + + DAC_SHRR + DAC_SHRR + DAC sample and hold refresh time register + 0x4C + 0x20 + 0x00010001 + 0xFFFFFFFF + + + TREFRESH1 + DAC channel1 refresh time (only valid in Sample and hold mode) +Refresh time1=1(TREFRESH[7:0]) x LSI clock period +Note: This register can be modified only when EN11=10. + 0 + 8 + read-write + + + + + + + DBGMCU + DBGMCU register block + DBGMCU + 0x40015800 + + 0x0 + 0x1000 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + DBGMCU device ID code register + 0x00 + 0x20 + 0x00006000 + 0x0000F000 + + + DEV_ID + Device identifier +This field indicates the device ID. + 0 + 12 + read-only + + + B_0x459 + STM32U031xx + 0x459 + + + B_0x489 + STM32U073/083xx + 0x489 + + + + + REV_ID + Revision identifier +This field indicates the revision of the device. + 16 + 16 + read-only + + + B_0x1000 + Revision A for STM32U031/73/83xx + 0x1000 + + + + + + + DBGMCU_CR + DBGMCU_CR + DBGMCU configuration register + 0x00000004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_STOP + Debug Stop mode +Debug options in Stop mode. + 1 + 1 + read-write + + + B_0x0 + All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. + 0x0 + + + B_0x1 + FCLK and HCLK running, derived from the internal RC oscillator remaining active. If SysTick is enabled, it may generate periodic interrupt and wake up events.Upon Stop mode exit, the software must re-establish the desired clock configuration. + 0x1 + + + + + DBG_STANDBY + Debug Standby and Shutdown modes +Debug options in Standby or Shutdown mode. + 2 + 1 + read-write + + + B_0x0 + Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby) + 0x0 + + + B_0x1 + Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset. + 0x1 + + + + + + + DBGMCU_APB1FZR + DBGMCU_APB1FZR + DBGMCU APB1 freeze register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM2_STOP + TIM2 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. TIM2 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM2 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM3_STOP + TIM3 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. TIM3 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM3 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM4_STOP + TIM4 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. TIM4 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM34 is frozen while CPU is in debug mode + 0x1 + + + + + DBG_TIM6_STOP + TIM6 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. TIM6 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM6 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM7_STOP + TIM7 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. TIM7 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM7 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_RTC_STOP + RTC stop in debug + 10 + 1 + read-write + + + B_0x0 + normal operation. RTC counter continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. RTC counter is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_WWDG_STOP + WWDG stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. WWDG continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. WWDG is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_IWDG_STOP + IWDG stop in debug + 12 + 1 + read-write + + + B_0x0 + normal operation. IWDG continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. IWDG is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_I2C3_STOP + I2C3 SMBUS timeout stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. I2C3 SMBUS timeout continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C3 SMBUS timeout is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM2_STOP + LPTIM2 stop in debug + 30 + 1 + read-write + + + B_0x0 + normal operation. LPTIM2 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM2 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM1_STOP + LPTIM1 stop in debug + 31 + 1 + read-write + + + B_0x0 + normal operation. LPTIM1 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM1 is frozen while CPU is in debug mode. + 0x1 + + + + + + + DBGMCU_APB2FZR + DBGMCU_APB2FZR + DBG APB2 freeze register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM1_STOP + TIM1 stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. TIM1 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM1 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM14_STOP + TIM14 stop in debug + 15 + 1 + read-write + + + B_0x0 + normal operation. TIM14 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM14 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM15_STOP + TIM15 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. TIM15 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM15 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_TIM16_STOP + TIM16 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. TIM16 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. TIM16 is frozen while CPU is in debug mode. + 0x1 + + + + + DBG_LPTIM3_STOP + LPTIM3 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. LPTIM3 continues to operate while CPU is in debug mode. + 0x0 + + + B_0x1 + stop in debug. LPTIM3 is frozen while CPU is in debug mode. + 0x1 + + + + + + + DBGMCU_SR + DBGMCU_SR + DBGMCU status register + 0xFC + 0x20 + 0x00010003 + 0xFFFFFFFF + + + AP1_PRESENT + Identifies whether access port AP1 is present in device + 0 + 1 + read-only + + + B_0x1 + AP1 present + 0x1 + + + + + AP0_PRESENT + Identifies whether access port AP0 is present in device + 1 + 1 + read-only + + + B_0x1 + AP0 present + 0x1 + + + + + AP1_ENABLED + Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + 16 + 1 + read-only + + + B_0x0 + AP1 locked + 0x0 + + + B_0x1 + AP1 enabled + 0x1 + + + + + AP0_ENABLED + Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + 17 + 1 + read-only + + + B_0x0 + AP0 locked + 0x0 + + + B_0x1 + AP0 enabled + 0x1 + + + + + + + DBGMCU_DBG_AUTH_HOST + DBGMCU_DBG_AUTH_HOST + DBGMCU debug authentication mailbox host register + 0x100 + 0x20 + 0x00000000 + 0x00000000 + + + MESSAGE + Debug host to device mailbox message. +During debug authentication the debug host communicates with the device via this register. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_DEVICE + DBGMCU_DBG_AUTH_DEVICE + DBGMCU debug authentication mailbox device register + 0x104 + 0x20 + 0x00000000 + 0x00000000 + + + MESSAGE + Device to debug host mailbox message. +During debug authentication the device communicates with the debug host via this register. + 0 + 32 + read-only + + + + + DBGMCU_PIDR4 + DBGMCU_PIDR4 + DBGMCU CoreSight peripheral identity register 4 + 0xFD0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + JEP106CON + JEP106 continuation code + 0 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + SIZE + register file size + 4 + 4 + read-only + + + B_0x0 + The register file occupies a single 4-Kbyte region. + 0x0 + + + + + + + DBGMCU_PIDR0 + DBGMCU_PIDR0 + DBGMCU CoreSight peripheral identity register 0 + 0xFE0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [7:0] + 0 + 8 + read-only + + + B_0x00 + DBGMCU part number + 0x00 + + + + + + + DBGMCU_PIDR1 + DBGMCU_PIDR1 + DBGMCU CoreSight peripheral identity register 1 + 0xFE4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [11:8] + 0 + 4 + read-only + + + B_0x0 + DBGMCU part number + 0x0 + + + + + JEP106ID + JEP106 identity code bits [3:0] + 4 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + + + DBGMCU_PIDR2 + DBGMCU_PIDR2 + DBGMCU CoreSight peripheral identity register 2 + 0xFE8 + 0x20 + 0x0000000A + 0xFFFFFFFF + + + JEP106ID + JEP106 identity code bits [6:4] + 0 + 3 + read-only + + + B_0x2 + STMicroelectronics JEDEC code + 0x2 + + + + + JEDEC + JEDEC assigned value + 3 + 1 + read-only + + + B_0x1 + designer identification specified by JEDEC + 0x1 + + + + + REVISION + component revision number + 4 + 4 + read-only + + + B_0x0 + r0p0 + 0x0 + + + + + + + DBGMCU_PIDR3 + DBGMCU_PIDR3 + DBGMCU CoreSight peripheral identity register 3 + 0xFEC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified + 0 + 4 + read-only + + + B_0x0 + no customer modifications + 0x0 + + + + + REVAND + metal fix version + 4 + 4 + read-only + + + B_0x0 + no metal fix + 0x0 + + + + + + + DBGMCU_CIDR0 + DBGMCU_CIDR0 + DBGMCU CoreSight component identity register 0 + 0xFF0 + 0x20 + 0x0000000D + 0xFFFFFFFF + + + PREAMBLE + component identification bits [7:0] + 0 + 8 + read-only + + + B_0x0D + common identification value + 0x0D + + + + + + + DBGMCU_CIDR1 + DBGMCU_CIDR1 + DBGMCU CoreSight component identity register 1 + 0xFF4 + 0x20 + 0x000000F0 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [11:8] + 0 + 4 + read-only + + + B_0x0 + common identification value + 0x0 + + + + + CLASS + component identification bits [15:12] - component class + 4 + 4 + read-only + + + B_0xF + Non-CoreSight component + 0xF + + + + + + + DBGMCU_CIDR2 + DBGMCU_CIDR2 + DBGMCU CoreSight component identity register 2 + 0xFF8 + 0x20 + 0x00000005 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [23:16] + 0 + 8 + read-only + + + B_0x05 + common identification value + 0x05 + + + + + + + DBGMCU_CIDR3 + DBGMCU_CIDR3 + DBGMCU CoreSight component identity register 3 + 0xFFC + 0x20 + 0x000000B1 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [31:24] + 0 + 8 + read-only + + + B_0xB1 + common identification value + 0xB1 + + + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x40020800 + + 0x0 + 0x148 + registers + + + + DMAMUX_C0CR + DMAMUX_C0CR + DMAMUX request line multiplexer channel 0 configuration register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C1CR + DMAMUX_C1CR + DMAMUX request line multiplexer channel 1 configuration register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C2CR + DMAMUX_C2CR + DMAMUX request line multiplexer channel 2 configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C3CR + DMAMUX_C3CR + DMAMUX request line multiplexer channel 3 configuration register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C4CR + DMAMUX_C4CR + DMAMUX request line multiplexer channel 4 configuration register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C5CR + DMAMUX_C5CR + DMAMUX request line multiplexer channel 5 configuration register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C6CR + DMAMUX_C6CR + DMAMUX request line multiplexer channel 6 configuration register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C7CR + DMAMUX_C7CR + DMAMUX request line multiplexer channel 7 configuration register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C8CR + DMAMUX_C8CR + DMAMUX request line multiplexer channel 8 configuration register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C9CR + DMAMUX_C9CR + DMAMUX request line multiplexer channel 9 configuration register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C10CR + DMAMUX_C10CR + DMAMUX request line multiplexer channel 10 configuration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_C11CR + DMAMUX_C11CR + DMAMUX request line multiplexer channel 11 configuration register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAREQ_ID + DMA request identification +Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. + 0 + 7 + read-write + + + SOIE + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EGE + Event generation enable + 9 + 1 + read-write + + + B_0x0 + Event generation disabled + 0x0 + + + B_0x1 + Event generation enabled + 0x1 + + + + + SE + Synchronization enable + 16 + 1 + read-write + + + B_0x0 + Synchronization disabled + 0x0 + + + B_0x1 + Synchronization enabled + 0x1 + + + + + SPOL + Synchronization polarity +Defines the edge polarity of the selected synchronization input: + 17 + 2 + read-write + + + B_0x0 + No event (no synchronization, no detection). + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + NBREQ + Number of DMA requests minus 1 to forward +Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. +This field must only be written when both SE and EGE bits are low. + 19 + 5 + read-write + + + SYNC_ID + Synchronization identification +Selects the synchronization input (see Table137: DMAMUX: assignment of synchronization inputs to resources). + 24 + 5 + read-write + + + + + DMAMUX_CSR + DMAMUX_CSR + DMAMUX request line multiplexer interrupt channel status register + 0x080 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SOF0 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 0 + 1 + read-only + + + SOF1 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 1 + 1 + read-only + + + SOF2 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 2 + 1 + read-only + + + SOF3 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 3 + 1 + read-only + + + SOF4 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 4 + 1 + read-only + + + SOF5 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 5 + 1 + read-only + + + SOF6 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 6 + 1 + read-only + + + SOF7 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 7 + 1 + read-only + + + SOF8 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 8 + 1 + read-only + + + SOF9 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 9 + 1 + read-only + + + SOF10 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 10 + 1 + read-only + + + SOF11 + Synchronization overrun event flag +The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. +The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register. + 11 + 1 + read-only + + + + + DMAMUX_CFR + DMAMUX_CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CSOF0 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 0 + 1 + write-only + + + CSOF1 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 1 + 1 + write-only + + + CSOF2 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 2 + 1 + write-only + + + CSOF3 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 3 + 1 + write-only + + + CSOF4 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 4 + 1 + write-only + + + CSOF5 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 5 + 1 + write-only + + + CSOF6 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 6 + 1 + write-only + + + CSOF7 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 7 + 1 + write-only + + + CSOF8 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 8 + 1 + write-only + + + CSOF9 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 9 + 1 + write-only + + + CSOF10 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 10 + 1 + write-only + + + CSOF11 + Clear synchronization overrun event flag +Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register. + 11 + 1 + write-only + + + + + DMAMUX_RG0CR + DMAMUX_RG0CR + DMAMUX request generator channel 0 configuration register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG1CR + DMAMUX_RG1CR + DMAMUX request generator channel 1 configuration register + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG2CR + DMAMUX_RG2CR + DMAMUX request generator channel 2 configuration register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RG3CR + DMAMUX_RG3CR + DMAMUX request generator channel 3 configuration register + 0x10C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SIG_ID + Signal identification +Selects the DMA request trigger input used for the channel x of the DMA request generator + 0 + 5 + read-write + + + OIE + Trigger overrun interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt on a trigger overrun event occurrence is disabled + 0x0 + + + B_0x1 + Interrupt on a trigger overrun event occurrence is enabled + 0x1 + + + + + GE + DMA request generator channel x enable + 16 + 1 + read-write + + + B_0x0 + DMA request generator channel x disabled + 0x0 + + + B_0x1 + DMA request generator channel x enabled + 0x1 + + + + + GPOL + DMA request generator trigger polarity +Defines the edge polarity of the selected trigger input + 17 + 2 + read-write + + + B_0x0 + No event, i.e. no trigger detection nor generation. + 0x0 + + + B_0x1 + Rising edge + 0x1 + + + B_0x2 + Falling edge + 0x2 + + + B_0x3 + Rising and falling edges + 0x3 + + + + + GNBREQ + Number of DMA requests to be generated (minus 1) +Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. +Note: This field must be written only when GE bit is disabled. + 19 + 5 + read-write + + + + + DMAMUX_RGSR + DMAMUX_RGSR + DMAMUX request generator interrupt status register + 0x140 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OF0 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 0 + 1 + read-only + + + OF1 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 1 + 1 + read-only + + + OF2 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 2 + 1 + read-only + + + OF3 + Trigger overrun event flag +The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). +The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register. + 3 + 1 + read-only + + + + + DMAMUX_RGCFR + DMAMUX_RGCFR + DMAMUX request generator interrupt clear flag register + 0x144 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + COF0 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 0 + 1 + write-only + + + COF1 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 1 + 1 + write-only + + + COF2 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 2 + 1 + write-only + + + COF3 + Clear trigger overrun event flag +Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register. + 3 + 1 + write-only + + + + + + + DMA1 + DMA register bank + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CHannel1 + DMA1 channel 1 interrupt + 9 + + + DMA1_Channel2_3 + DMA1 channel 2 and 3 interrupts + 10 + + + DMA1_Channel4_5_6_7 + DMA1 channel 4, 5, 6, 7, DMAMUX, DMA2 channel 1, 2, 3, 4, 5 interrupts + 11 + + + + DMA_ISR + DMA_ISR + DMA interrupt status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GIF1 + Global interrupt flag for channel 1 + 0 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF1 + Transfer complete (TC) flag for channel 1 + 1 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF1 + Half transfer (HT) flag for channel 1 + 2 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF1 + Transfer error (TE) flag for channel 1 + 3 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF2 + Global interrupt flag for channel 2 + 4 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF2 + Transfer complete (TC) flag for channel 2 + 5 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF2 + Half transfer (HT) flag for channel 2 + 6 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF2 + Transfer error (TE) flag for channel 2 + 7 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF3 + Global interrupt flag for channel 3 + 8 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF3 + Transfer complete (TC) flag for channel 3 + 9 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF3 + Half transfer (HT) flag for channel 3 + 10 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF3 + Transfer error (TE) flag for channel 3 + 11 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF4 + global interrupt flag for channel 4 + 12 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF4 + Transfer complete (TC) flag for channel 4 + 13 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF4 + Half transfer (HT) flag for channel 4 + 14 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF4 + Transfer error (TE) flag for channel 4 + 15 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF5 + global interrupt flag for channel 5 + 16 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF5 + Transfer complete (TC) flag for channel 5 + 17 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF5 + Half transfer (HT) flag for channel 5 + 18 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF5 + Transfer error (TE) flag for channel 5 + 19 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF6 + Global interrupt flag for channel 6 + 20 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF6 + Transfer complete (TC) flag for channel 6 + 21 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF6 + Half transfer (HT) flag for channel 6 + 22 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF6 + Transfer error (TE) flag for channel 6 + 23 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + GIF7 + Global interrupt flag for channel 7 + 24 + 1 + read-only + + + B_0x0 + No TE, HT, or TC event + 0x0 + + + B_0x1 + A TE, HT, or TC event occurred. + 0x1 + + + + + TCIF7 + Transfer complete (TC) flag for channel 7 + 25 + 1 + read-only + + + B_0x0 + No TC event + 0x0 + + + B_0x1 + A TC event occurred. + 0x1 + + + + + HTIF7 + Half transfer (HT) flag for channel 7 + 26 + 1 + read-only + + + B_0x0 + No HT event + 0x0 + + + B_0x1 + An HT event occurred. + 0x1 + + + + + TEIF7 + Transfer error (TE) flag for channel 7 + 27 + 1 + read-only + + + B_0x0 + No TE event + 0x0 + + + B_0x1 + A TE event occurred. + 0x1 + + + + + + + DMA_IFCR + DMA_IFCR + DMA interrupt flag clear register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CGIF1 + Global interrupt flag clear for channel 1 + 0 + 1 + write-only + + + CTCIF1 + Transfer complete flag clear for channel 1 + 1 + 1 + write-only + + + CHTIF1 + Half transfer flag clear for channel 1 + 2 + 1 + write-only + + + CTEIF1 + Transfer error flag clear for channel 1 + 3 + 1 + write-only + + + CGIF2 + Global interrupt flag clear for channel 2 + 4 + 1 + write-only + + + CTCIF2 + Transfer complete flag clear for channel 2 + 5 + 1 + write-only + + + CHTIF2 + Half transfer flag clear for channel 2 + 6 + 1 + write-only + + + CTEIF2 + Transfer error flag clear for channel 2 + 7 + 1 + write-only + + + CGIF3 + Global interrupt flag clear for channel 3 + 8 + 1 + write-only + + + CTCIF3 + Transfer complete flag clear for channel 3 + 9 + 1 + write-only + + + CHTIF3 + Half transfer flag clear for channel 3 + 10 + 1 + write-only + + + CTEIF3 + Transfer error flag clear for channel 3 + 11 + 1 + write-only + + + CGIF4 + Global interrupt flag clear for channel 4 + 12 + 1 + write-only + + + CTCIF4 + Transfer complete flag clear for channel 4 + 13 + 1 + write-only + + + CHTIF4 + Half transfer flag clear for channel 4 + 14 + 1 + write-only + + + CTEIF4 + Transfer error flag clear for channel 4 + 15 + 1 + write-only + + + CGIF5 + Global interrupt flag clear for channel 5 + 16 + 1 + write-only + + + CTCIF5 + Transfer complete flag clear for channel 5 + 17 + 1 + write-only + + + CHTIF5 + Half transfer flag clear for channel 5 + 18 + 1 + write-only + + + CTEIF5 + Transfer error flag clear for channel 5 + 19 + 1 + write-only + + + CGIF6 + Global interrupt flag clear for channel 6 + 20 + 1 + write-only + + + CTCIF6 + Transfer complete flag clear for channel 6 + 21 + 1 + write-only + + + CHTIF6 + Half transfer flag clear for channel 6 + 22 + 1 + write-only + + + CTEIF6 + Transfer error flag clear for channel 6 + 23 + 1 + write-only + + + CGIF7 + Global interrupt flag clear for channel 7 + 24 + 1 + write-only + + + CTCIF7 + Transfer complete flag clear for channel 7 + 25 + 1 + write-only + + + CHTIF7 + Half transfer flag clear for channel 7 + 26 + 1 + write-only + + + CTEIF7 + Transfer error flag clear for channel 7 + 27 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA channel 1 number of data to transfer register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA channel 1 peripheral address register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA channel 1 memory address register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA channel 2 number of data to transfer register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA channel 2 peripheral address register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA channel 2 memory address register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA channel 3 peripheral address register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA channel 3 memory address register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA channel 4 configuration register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA channel 4 peripheral address register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA channel 4 memory address register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA channel 5 configuration register + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA channel 5 peripheral address register + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA channel 5 memory address register + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA channel 6 configuration register + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA channel 6 peripheral address register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA channel 6 memory address register + 0x78 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA channel 7 configuration register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EN + Channel enable +When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). +Note: This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + HTIE + Half transfer interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + TEIE + Transfer error interrupt enable +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + DIR + Data transfer direction +This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. +Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. +Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 4 + 1 + read-write + + + B_0x0 + Read from peripheral + 0x0 + + + B_0x1 + Read from memory + 0x1 + + + + + CIRC + Circular mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 5 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PINC + Peripheral increment mode +Defines the increment mode for each DMA transfer to the identified peripheral. +n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 6 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + MINC + Memory increment mode +Defines the increment mode for each DMA transfer to the identified memory. +In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + PSIZE + Peripheral size +Defines the data size of each DMA transfer to the identified peripheral. +In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 8 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + MSIZE + Memory size +Defines the data size of each DMA transfer to the identified memory. +In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 10 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + B_0x2 + 32 bits + 0x2 + + + + + PL + Priority level +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 12 + 2 + read-write + + + B_0x0 + Low + 0x0 + + + B_0x1 + Medium + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Very high + 0x3 + + + + + MEM2MEM + Memory-to-memory mode +Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). + 14 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled + 0x1 + + + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA channel 7 peripheral address register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PA + Peripheral address +It contains the base address of the peripheral data register from/to which the data is read/written. +When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. +When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA channel 7 memory address register + 0x8C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MA + Peripheral address +It contains the base address of the memory from/to which the data is read/written. +When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. +When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. +In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. +In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. +Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). + 0 + 32 + read-write + + + + + + + DMA2 + 0x40020400 + + + EXTI + EXTI register block + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) + 1 + + + EXTI0_1 + EXTI lines 0 and 1 interrupt + 5 + + + EXTI2_3 + EXTI lines 2 and 3 interrupt + 6 + + + EXTI4_15 + EXTI lines 4 to 15 interrupt + 7 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT16 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT17 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT18 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT19 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT20 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RT21 + Rising trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register 1 + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT16 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT17 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT18 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT19 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT20 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FT21 + Falling trigger event configuration bit of configurable line x (x1=1211to10) +Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register 1 + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI1 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI2 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI3 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI4 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI5 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI6 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI7 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI8 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI9 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI10 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI11 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI12 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI13 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI14 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI15 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI16 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI17 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI18 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI19 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI20 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + SWI21 + Software rising edge event trigger on line x (x1=1211to10) +Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rising edge event generated on the corresponding line, followed by an interrupt + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register 1 + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF16 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF17 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF18 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF19 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF20 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF21 + Rising edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register 1 + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF16 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF17 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF18 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF19 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF20 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF21 + Falling edge event pending for configurable line x (x1=1211to10) +Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it. +Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register 1 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI0 GPIO port selection +These bits are written by software to select the source input for EXTI0 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[0] pin + 0x00 + + + B_0x01 + PB[0] pin + 0x01 + + + B_0x02 + PC[0] pin + 0x02 + + + B_0x03 + PD[0] pin + 0x03 + + + B_0x05 + PF[0] pin + 0x05 + + + + + EXTI1 + EXTI1 GPIO port selection +These bits are written by software to select the source input for EXTI1 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[1] pin + 0x00 + + + B_0x01 + PB[1] pin + 0x01 + + + B_0x02 + PC[1] pin + 0x02 + + + B_0x03 + PD[1] pin + 0x03 + + + B_0x05 + PF[1] pin + 0x05 + + + + + EXTI2 + EXTI2 GPIO port selection +These bits are written by software to select the source input for EXTI2 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[2] pin + 0x00 + + + B_0x01 + PB[2] pin + 0x01 + + + B_0x02 + PC[2] pin + 0x02 + + + B_0x03 + PD[2] pin + 0x03 + + + B_0x05 + PF[2] pin + 0x05 + + + + + EXTI3 + EXTI3 GPIO port selection +These bits are written by software to select the source input for EXTI3 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[3] pin + 0x00 + + + B_0x01 + PB[3] pin + 0x01 + + + B_0x02 + PC[3] pin + 0x02 + + + B_0x03 + PD[3] pin + 0x03 + + + B_0x05 + PF[3] pin + 0x05 + + + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register 2 + 0x64 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI4 GPIO port selection +These bits are written by software to select the source input for EXTI4 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[4] pin + 0x00 + + + B_0x01 + PB[4] pin + 0x01 + + + B_0x02 + PC[4] pin + 0x02 + + + B_0x03 + PD[4] pin + 0x03 + + + B_0x05 + PF[4] pin + 0x05 + + + + + EXTI5 + EXTI5 GPIO port selection +These bits are written by software to select the source input for EXTI5 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[5] pin + 0x00 + + + B_0x01 + PB[5] pin + 0x01 + + + B_0x02 + PC[5] pin + 0x02 + + + B_0x03 + PD[5] pin + 0x03 + + + B_0x05 + PF[5] pin + 0x05 + + + + + EXTI6 + EXTI6 GPIO port selection +These bits are written by software to select the source input for EXTI6 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[6] pin + 0x00 + + + B_0x01 + PB[6] pin + 0x01 + + + B_0x02 + PC[6] pin + 0x02 + + + B_0x03 + PD[6] pin + 0x03 + + + B_0x05 + PF[6] pin + 0x05 + + + + + EXTI7 + EXTI7 GPIO port selection +These bits are written by software to select the source input for EXTI7 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[7] pin + 0x00 + + + B_0x01 + PB[7] pin + 0x01 + + + B_0x02 + PC[7] pin + 0x02 + + + B_0x03 + PD[7] pin + 0x03 + + + B_0x05 + PF[7] pin + 0x05 + + + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register 3 + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTI8 GPIO port selection +These bits are written by software to select the source input for EXTI8 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[8] pin + 0x00 + + + B_0x01 + PB[8] pin + 0x01 + + + B_0x02 + PC[8] pin + 0x02 + + + B_0x03 + PD[8] pin + 0x03 + + + B_0x05 + PF[8] pin + 0x05 + + + + + EXTI9 + EXTI9 GPIO port selection +These bits are written by software to select the source input for EXTI9 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[9] pin + 0x00 + + + B_0x01 + PB[9] pin + 0x01 + + + B_0x02 + PC[9] pin + 0x02 + + + B_0x03 + PD[9] pin + 0x03 + + + B_0x05 + PF[9] pin + 0x05 + + + + + EXTI10 + EXTI10 GPIO port selection +These bits are written by software to select the source input for EXTI10 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[10] pin + 0x00 + + + B_0x01 + PB[10] pin + 0x01 + + + B_0x02 + PC[10] pin + 0x02 + + + B_0x03 + PD[10] pin + 0x03 + + + B_0x05 + PF[10] pin + 0x05 + + + + + EXTI11 + EXTI11 GPIO port selection +These bits are written by software to select the source input for EXTI11 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[11] pin + 0x00 + + + B_0x01 + PB[11] pin + 0x01 + + + B_0x02 + PC[11] pin + 0x02 + + + B_0x03 + PD[11] pin + 0x03 + + + B_0x05 + PF[11] pin + 0x05 + + + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register 4 + 0x6C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTI12 GPIO port selection +These bits are written by software to select the source input for EXTI12 external interrupt. +Others reserved + 0 + 8 + read-write + + + B_0x00 + PA[12] pin + 0x00 + + + B_0x01 + PB[12] pin + 0x01 + + + B_0x02 + PC[12] pin + 0x02 + + + B_0x03 + PD[12] pin + 0x03 + + + B_0x05 + PF[12] pin + 0x05 + + + + + EXTI13 + EXTI13 GPIO port selection +These bits are written by software to select the source input for EXTI13 external interrupt. +Others reserved + 8 + 8 + read-write + + + B_0x00 + PA[13] pin + 0x00 + + + B_0x01 + PB[13] pin + 0x01 + + + B_0x02 + PC[13] pin + 0x02 + + + B_0x03 + PD[13] pin + 0x03 + + + B_0x05 + PF[13] pin + 0x05 + + + + + EXTI14 + EXTI14 GPIO port selection +These bits are written by software to select the source input for EXTI14 external interrupt. +Others reserved + 16 + 8 + read-write + + + B_0x00 + PA[14] pin + 0x00 + + + B_0x01 + PB[14] pin + 0x01 + + + B_0x02 + PC[14] pin + 0x02 + + + B_0x03 + PD[14] pin + 0x03 + + + B_0x05 + PF[14] pin + 0x05 + + + + + EXTI15 + EXTI15 GPIO port selection +These bits are written by software to select the source input for EXTI15 external interrupt. +Others reserved + 24 + 8 + read-write + + + B_0x00 + PA[15] pin + 0x00 + + + B_0x01 + PB[15] pin + 0x01 + + + B_0x02 + PC[15] pin + 0x02 + + + B_0x03 + PD[15] pin + 0x03 + + + B_0x05 + PF[15] pin + 0x05 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wake-up with interrupt mask register + 0x080 + 0x20 + 0xFFF80000 + 0xFFFFFFFF + + + IM0 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM1 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM2 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM3 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM4 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM5 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM6 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM7 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM8 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM9 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM10 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM11 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM12 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM13 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM14 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM15 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM16 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM17 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM18 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM19 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM20 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM21 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM22 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 22 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM23 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 23 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM24 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 24 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM25 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 25 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM26 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 26 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM27 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 27 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM28 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 28 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM29 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 29 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM30 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 30 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + IM31 + CPU wake-up with interrupt mask on line x (x1=131 to 0) +Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 31 + 1 + read-write + + + B_0x0 + wake-up with interrupt masked + 0x0 + + + B_0x1 + wake-up with interrupt unasked + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wake-up with event mask register + 0x084 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM1 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM2 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM3 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM4 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM5 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM6 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 6 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM7 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 7 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM8 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 8 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM9 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 9 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM10 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 10 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM11 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 11 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM12 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 12 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM13 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 13 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM14 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 14 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM15 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 15 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM16 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 16 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM17 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 17 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM18 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 18 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM19 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 19 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM20 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 20 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM21 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 21 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM22 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 22 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM23 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 23 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM24 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 24 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM25 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 25 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM26 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 26 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM27 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 27 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM28 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 28 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM29 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 29 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM30 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 30 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM31 + CPU wake-up with event generation mask on line x (x1=1311to10) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. + 31 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + EXTI_IMR2 + EXTI_IMR2 + EXTI CPU wake-up with interrupt mask register + 0x090 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + IM32 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM33 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM34 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM35 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM36 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + IM37 + CPU wake-up with interrupt mask on line x (x1=1371to132) +Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with interrupt request from Line x is masked + 0x0 + + + B_0x1 + wake-up with interrupt request from Line x is unmasked + 0x1 + + + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wake-up with event mask register + 0x094 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EM32 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 0 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM33 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 1 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM34 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 2 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM35 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 3 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM36 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 4 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + EM37 + CPU wake-up with event generation mask on line x, (x1=1371to132) +Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. +Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. + 5 + 1 + read-write + + + B_0x0 + wake-up with event generation masked + 0x0 + + + B_0x1 + wake-up with event generation unmasked + 0x1 + + + + + + + + + FLASH + Mamba FLASH register block + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global interrupt + 3 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x000 + 0x20 + 0x00040600 + 0xFFFFFFFF + + + LATENCY + Flash memory access latency +The value in this bitfield represents the number of CPU wait states when accessing the flash memory. +Other: Reserved +A new write into the bitfield becomes effective when it returns the same value upon read. + 0 + 3 + read-write + + + B_0x0 + Zero wait states + 0x0 + + + B_0x1 + One wait state + 0x1 + + + + + PRFTEN + CPU Prefetch enable + 8 + 1 + read-write + + + B_0x0 + CPU Prefetch disabled + 0x0 + + + B_0x1 + CPU Prefetch enabled + 0x1 + + + + + ICEN + CPU Instruction cache enable + 9 + 1 + read-write + + + B_0x0 + CPU Instruction cache is disabled + 0x0 + + + B_0x1 + CPU Instruction cache is enabled + 0x1 + + + + + ICRST + CPU Instruction cache reset +This bit can be written only when the instruction cache is disabled. + 11 + 1 + read-write + + + B_0x0 + CPU Instruction cache is not reset + 0x0 + + + B_0x1 + CPU Instruction cache is reset + 0x1 + + + + + EMPTY + Main flash memory area empty +This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. +The bit can be set and reset by software. + 16 + 1 + read-write + + + B_0x0 + Main flash memory area programmed + 0x0 + + + B_0x1 + Main flash memory area empty + 0x1 + + + + + DBG_SWEN + Debug access software enable +Software may use this bit to enable/disable the debugger read access. + 18 + 1 + read-write + + + B_0x0 + Debugger disabled + 0x0 + + + B_0x1 + Debugger enabled + 0x1 + + + + + + + FLASH_KEYR + FLASH_KEYR + FLASH key register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + FLASH key +The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: +KEY1: 0x4567 0123 +KEY2: 0xCDEF 89AB + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + Option byte key +The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: +KEY1: 0x0819 2A3B +KEY2: 0x4C5D 6E7F + 0 + 32 + write-only + + + + + FLASH_SR + FLASH_SR + FLASH status register + 0x010 + 0x20 + 0x00000000 + 0xFFF0FFFF + + + EOP + End of operation +Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. +This bit is set only if the end of operation interrupts are enabled (EOPIE=1). +Cleared by writing 1. + 0 + 1 + read-write + + + OPERR + Operation error +Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. +This bit is set only if error interrupts are enabled (ERRIE=1). +Cleared by writing 1. + 1 + 1 + read-write + + + PROGERR + Programming error +Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. +Cleared by writing 1. + 3 + 1 + read-write + + + WRPERR + Write protection error +Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. +Cleared by writing 1. + 4 + 1 + read-write + + + PGAERR + Programming alignment error +Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. +Cleared by writing 1. + 5 + 1 + read-write + + + SIZERR + Size error +Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). +Cleared by writing 1. + 6 + 1 + read-write + + + PGSERR + Programming sequence error +Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. +Cleared by writing 1. + 7 + 1 + read-write + + + MISSERR + Fast programming data miss error +In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. +Cleared by writing 1. + 8 + 1 + read-write + + + FASTERR + Fast programming error +Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. +Cleared by writing 1. + 9 + 1 + read-write + + + RDERR + PCROP read error +Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. +Cleared by writing 1. + 14 + 1 + read-write + + + OPTVERR + Option and Engineering bits loading validity error + 15 + 1 + read-write + + + BSY1 + Busy +This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. + 16 + 1 + read-only + + + CFGBSY + Programming or erase configuration busy. +This flag is set and cleared by hardware. It is set when the first word is sent for program or when setting the STRT bit of FLASH control register (FLASH_CR) for erase. It is cleared when the flash memory program or erase operation completes or ends with an error. +When set, launching any other operation through the FLASH control register (FLASH_CR) is impossible, and must be postponed (a programming or erase operation is ongoing). +When cleared, the program and erase settings in the FLASH control register (FLASH_CR) can be modified. + 18 + 1 + read-only + + + + + FLASH_CR + FLASH_CR + FLASH control register + 0x014 + 0x20 + 0xC0000000 + 0xFFFFFFFF + + + PG + Flash memory programming enable + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PER + Page erase enable + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MER1 + Mass erase +When set, this bit triggers the mass erase, that is, all user pages. + 2 + 1 + read-write + + + PNB + Page number selection +These bits select the page to erase: +... +Note: Values corresponding to addresses outside the main memory are not allowed. + 3 + 7 + read-write + + + B_0x0 + page 0 + 0x0 + + + B_0x1 + page 1 + 0x1 + + + B_0xF + page 15 + 0xF + + + + + STRT + Start erase operation +This bit triggers an erase operation when set. +This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. + 16 + 1 + read-write + + + OPTSTRT + Start of modification of option bytes +This bit triggers an options operation when set. +This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. + 17 + 1 + read-write + + + FSTPG + Fast programming enable + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + EOPIE + End-of-operation interrupt enable +This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ERRIE + Error interrupt enable +This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RDERRIE + PCROP read error interrupt enable +This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OBL_LAUNCH + Option byte load launch +When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. +The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. + 27 + 1 + read-write + + + SEC_PROT + Securable memory area protection enable +This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. +This bit is possible to set only by software and to clear only through a system reset. + 28 + 1 + read-write + + + B_0x0 + Disable (securable area accessible) + 0x0 + + + B_0x1 + Enable (securable area not accessible) + 0x1 + + + + + OPTLOCK + Options Lock +This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. +In case of an unsuccessful unlock operation, this bit remains set until the next reset. + 30 + 1 + read-write + + + LOCK + FLASH_CR Lock +This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. +In case of an unsuccessful unlock operation, this bit remains set until the next system reset. + 31 + 1 + read-write + + + + + FLASH_ECCR + FLASH_ECCR + FLASH ECC register + 0x018 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC fail double-word address offset + In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory. + 0 + 14 + read-only + + + SYSF_ECC + System Flash memory ECC fail +This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. + 20 + 1 + read-only + + + ECCCIE + ECC correction interrupt enable + 24 + 1 + read-write + + + B_0x0 + ECCC interrupt disabled + 0x0 + + + B_0x1 + ECCC interrupt enabled + 0x1 + + + + + ECCC + ECC correction +Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. +Cleared by writing 1. + 30 + 1 + read-write + + + ECCD + ECC detection +Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. +Cleared by writing 1. + 31 + 1 + read-write + + + + + FLASH_OPTR + FLASH_OPTR + FLASH option register + 0x020 + 0x20 + 0x00000000 + 0x00000000 + + + RDP + Read protection level +Other: Level 1, memories read protection active + 0 + 8 + read-write + + + B_0xAA + Level 0, read protection not active + 0xAA + + + B_0xCC + Level 2, chip read protection active + 0xCC + + + + + BORR_LEV + BOR reset level + 8 + 3 + read-write + + + B_0x0 + BOR rising level 1 with threshold around 2.1 V + 0x0 + + + B_0x1 + BOR rising level 2 with threshold around 2.3 V + 0x1 + + + B_0x2 + BOR rising level 3 with threshold around 2.6 V + 0x2 + + + B_0x3 + BOR rising level 4 with threshold around 2.9 V + 0x3 + + + + + NRST_STOP + Reset generated when entering Stop mode + 13 + 1 + read-write + + + B_0x0 + Reset generated when entering the Stop mode + 0x0 + + + B_0x1 + No reset generated when entering the Stop mode + 0x1 + + + + + NRST_STDBY + Reset generated when entering Standby mode + 14 + 1 + read-write + + + B_0x0 + Reset generated when entering the Standby mode + 0x0 + + + B_0x1 + No reset generate when entering the Standby mode + 0x1 + + + + + NRST_SHDW + Reset generated when entering Shutdown mode + 15 + 1 + read-write + + + B_0x0 + Reset generated when entering the Shutdown mode + 0x0 + + + B_0x1 + No reset generated when entering the Shutdown mode + 0x1 + + + + + IWDG_SW + Independent watchdog selection + 16 + 1 + read-write + + + B_0x0 + Hardware independent watchdog + 0x0 + + + B_0x1 + Software independent watchdog + 0x1 + + + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Stop mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Stop mode + 0x1 + + + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + read-write + + + B_0x0 + Independent watchdog counter is frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog counter is running in Standby mode + 0x1 + + + + + WWDG_SW + Window watchdog selection + 19 + 1 + read-write + + + B_0x0 + Hardware window watchdog + 0x0 + + + B_0x1 + Software window watchdog + 0x1 + + + + + BDRST + Backup domain reset + 21 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + RAM_PARITY_CHECK + SRAM parity check control enable/disable + 22 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + BKPSRAM_HW_ERASE_DISABLE + Backup SRAM erase prevention + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + NBOOT_SEL + BOOT0 signal source selection +This option bit defines the source of the BOOT0 signal. + 24 + 1 + read-write + + + B_0x0 + BOOT0 pin (legacy mode) + 0x0 + + + B_0x1 + NBOOT0 option bit + 0x1 + + + + + NBOOT1 + Boot configuration +Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration. + 25 + 1 + read-write + + + NBOOT0 + NBOOT0 option bit + 26 + 1 + read-write + + + B_0x0 + NBOOT01=10 + 0x0 + + + B_0x1 + NBOOT01=11 + 0x1 + + + + + NRST_MODE + NRST pin configuration + 27 + 2 + read-write + + + B_0x1 + Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. + 0x1 + + + B_0x2 + Standard GPIO: only internal RESET is possible + 0x2 + + + B_0x3 + Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode + 0x3 + + + + + IRHEN + Internal reset holder enable bit + 29 + 1 + read-write + + + B_0x0 + Internal resets are propagated as simple pulse on NRST pin + 0x0 + + + B_0x1 + Internal resets drives NRST pin low until it is seen as low level + 0x1 + + + + + + + FLASH_WRP1AR + FLASH_WRP1AR + FLASH WRP area A address register + 0x02C + 0x20 + 0x00000000 + 0xFFF0FFF0 + + + WRP1A_STRT + WRP area A start offset +This bitfield contains the offset of the first page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 7 + read-write + + + WRP1A_END + WRP area A end offset +This bitfield contains the offset of the last page of the WRP area A. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 7 + read-write + + + + + FLASH_WRP1BR + FLASH_WRP1BR + FLASH WRP area B address register + 0x030 + 0x20 + 0x00000000 + 0xFFF0FFF0 + + + WRP1B_STRT + WRP area B start offset +This bitfield contains the offset of the first page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 0 + 7 + read-write + + + WRP1B_END + WRP area B end offset +This bitfield contains the offset of the last page of the WRP area B. +Note: The number of effective bits depends on the size of the flash memory in the device. + 16 + 7 + read-write + + + + + FLASH_SECR + FLASH_SECR + FLASH security register + 0x080 + 0x20 + 0x0 + 0xFFFEFFE0 + + + HDP1_PEND + Last page of the first hide protection area + 0 + 7 + read-write + + + BOOT_LOCK + used to force boot from user area +If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). + 16 + 1 + read-write + + + B_0x0 + Boot based on the pad/option bit configuration + 0x0 + + + B_0x1 + Boot forced from main flash memory + 0x1 + + + + + HDP1EN + Hide protection area enable + 24 + 8 + read-write + + + + + + + GPIOA + GPIOA address block description + GPIO + 0x50000000 + + 0x0 + 0x2C + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOB + GPIOB address block description + GPIO + 0x50000400 + + 0x0 + 0x2C + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOB_LCKR + GPIOB_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOC + GPIOC address block description + GPIO + 0x50000800 + + 0x0 + 0x2C + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOC_LCKR + GPIOC_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOD + GPIOD address block description + GPIO + 0x50000C00 + + 0x0 + 0x2C + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOD_LCKR + GPIOD_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOE + GPIOE address block description + GPIO + 0x50001000 + + 0x0 + 0x2C + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOE_LCKR + GPIOE_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + GPIOF + GPIOF address block description + GPIO + 0x50001400 + + 0x0 + 0x2C + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x00 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Sets the corresponding ODx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Resets the corresponding ODx bit + 0x1 + + + + + + + GPIOF_LCKR + GPIOF_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is 0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + IWDG + IWDG address block description + IWDG + 0x40003000 + + 0x0 + 0x18 + registers + + + + IWDG_KR + IWDG_KR + IWDG key register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Key value (write only, read 0x0000) +These bits can be used for several functions, depending upon the value written by the application: +- 0xAAAA: reloads the RL[11:0] value into the IWDCNT down-counter (watchdog refresh), and write-protects registers. This value must be written by software at regular intervals, otherwise the watchdog generates a reset when the counter reaches 0. +- 0x5555: enables write-accesses to the registers. +- 0xCCCC: enables the watchdog (except if the hardware watchdog option is selected) and write-protects registers. +- values different from 0x5555: write-protects registers. +Note that only IWDG_PR, IWDG_RLR, IWDG_EWCR and IWDG_WINR registers have a write-protection mechanism. + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG prescaler register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PR + Prescaler divider +These bits are write access protected, see Section126.4.6. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset to be able to change the prescaler divider. +Others: divider / 1024 +Note: Reading this register returns the prescaler value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 4 + read-write + + + B_0x0 + divider / 4 + 0x0 + + + B_0x1 + divider / 8 + 0x1 + + + B_0x2 + divider / 16 + 0x2 + + + B_0x3 + divider / 32 + 0x3 + + + B_0x4 + divider / 64 + 0x4 + + + B_0x5 + divider / 128 + 0x5 + + + B_0x6 + divider / 256 + 0x6 + + + B_0x7 + divider / 512 + 0x7 + + + + + + + IWDG_RLR + IWDG_RLR + IWDG reload register + 0x08 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + RL + Watchdog counter reload value +These bits are write access protected, see Section126.4.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the prescaler.clock. It is not recommended to set RL[11:0] to a value lower than 2. +The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG status register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVU + Watchdog prescaler value update +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the V<sub>DD</sub> voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). +The prescaler value can be updated only when PVU bit is reset. + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to six periods of the IWDG kernel clock iwdg_ker_ck). +The reload value can be updated only when RVU bit is reset. + 1 + 1 + read-only + + + WVU + Watchdog counter window value update +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). +The window value can be updated only when WVU bit is reset. +This bit is generated only if generic window = 1. + 2 + 1 + read-only + + + EWU + Watchdog interrupt comparator value update +This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the V<sub>DD</sub> voltage domain (takes up to one period of presc_ck and two periods of the IWDG kernel clock iwdg_ker_ck). +The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset. + 3 + 1 + read-only + + + ONF + Watchdog enable status bit +Set to 1 by hardware as soon as the IWDG is started. In software mode, it remains to '1' until the IWDG is reset. In hardware mode, this bit is always set to '1'. + 8 + 1 + read-only + + + B_0x0 + The IWDG is not activated + 0x0 + + + B_0x1 + The IWDG is activated and needs to be refreshed regularly by the application + 0x1 + + + + + EWIF + Watchdog early interrupt flag +This bit is set to 1 by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to 1. + 14 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG window register + 0x10 + 0x20 + 0x00000FFF + 0xFFFFFFFF + + + WIN + Watchdog counter window value +These bits are write access protected, see Section126.4.6.They contain the high limit of the window value to be compared with the downcounter. +To prevent a reset, the IWDCNT downcounter must be reloaded when its value is lower than WIN[11:0]1+11 and greater than 1. +The WVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + + + IWDG_EWCR + IWDG_EWCR + IWDG early wake-up interrupt register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EWIT + Watchdog counter window value +These bits are write access protected (see Section126.4.6). They are written by software to define at which position of the IWDCNT down-counter the early wake-up interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0]1-11. +EWIT[11:0] must be bigger than 1. +An interrupt is generated only if EWIE = 1. +The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. +Note: Reading this register returns the Early wake-up comparator value and the Interrupt enable bit from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the IWDG status register (IWDG_SR) is reset. + 0 + 12 + read-write + + + EWIC + Watchdog early interrupt acknowledge +The software must write a 1 into this bit in order to acknowledge the early wake-up interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0. + 14 + 1 + write-only + + + EWIE + Watchdog early interrupt enable +Set and reset by software. +The EWU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the value of this bit. + 15 + 1 + read-write + + + B_0x0 + The early interrupt interface is disabled. + 0x0 + + + B_0x1 + The early interrupt interface is enabled. + 0x1 + + + + + + + + + I2C1 + I2C address block description + I2C + 0x40005400 + + 0x0 + 0x2C + registers + + + I2C1 + I2C1 global interrupt (combined with EXTI line 23) + 23 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer complete (TC) +Note: Transfer complete reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer complete interrupt disabled + 0x0 + + + B_0x1 + Transfer complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration loss (ARLO) +Note: Bus error detection (BERR) +Note: Overrun/Underrun (OVR) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can be programmed only when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + 18 + 1 + read-write + + + B_0x0 + Wake-up from Stop mode disable. + 0x0 + + + B_0x1 + Wake-up from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + FMP + Fast-mode Plus 20 mA drive enable + 24 + 1 + read-write + + + B_0x0 + 20 mA I/O drive disabled + 0x0 + + + B_0x1 + 20 mA I/O drive enabled + 0x1 + + + + + ADDRACLR + Address match flag (ADDR) automatic clear + 30 + 1 + read-write + + + B_0x0 + ADDR flag is set by hardware, cleared by software by setting ADDRCF bit. + 0x0 + + + B_0x1 + ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral. + 0x1 + + + + + STOPFACLR + STOP detection flag (STOPF) automatic clear + 31 + 1 + read-write + + + B_0x0 + STOPF flag is set by hardware, cleared by software by setting STOPCF bit. + 0x0 + + + B_0x1 + STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral. + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] must be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer + 0x0 + + + B_0x1 + Master requests a read transfer + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit address in write direction + Restart + first seven bits of the 10-bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the first seven bits of the 10-bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer. +Otherwise, setting this bit generates a START condition once the bus is free. +Note: Writing 0 to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In master mode: +Note: Writing 0 to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation + 0x0 + + + B_0x1 + Stop generation after current byte transfer + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing 0 to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN = 0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN = 0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN = 0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN = 0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and dont care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and dont care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL + 1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH + 1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL + 1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings) and for SCL high and low level counters (refer to I2C master initialization). +t<sub>PRESC </sub>= (PRESC + 1) x t<sub>I2CCLK</sub> + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE = 0 +t<sub>TIMEOUT</sub>= (TIMEOUTA + 1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE = 1 +t<sub>IDLE</sub>= (TIMEOUTA + 1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN = 0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN = 0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE = 0) or high for more than t<sub>IDLE </sub>(TIDLE = 1), a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT </sub>= (TIMEOUTB + TIDLE = 01) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN = 0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT = 1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + I2C2 + 0x40005800 + + I2C2_I2C3_I2C4 + I2C2/3/4 global interrupt + 24 + + + + I2C3 + 0x40008800 + + + LCD + LCD address block description + LCDC + 0x40002400 + + 0x0 + 0x54 + registers + + + LCD + LCD global interrupt (combined with EXTI line 32) + 22 + + + + LCD_CR + LCD_CR + LCD control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCDEN + LCD controller enable +This bit is set by software to enable the LCD controller/driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled, all COM and SEG pins are driven to V<sub>SS</sub>. + 0 + 1 + read-write + + + B_0x0 + LCD controller disabled + 0x0 + + + B_0x1 + LCD controller enabled + 0x1 + + + + + VSEL + Voltage source selection +This bit determines the voltage source for the LCD. + 1 + 1 + read-write + + + B_0x0 + Internal source (voltage stepup converter) + 0x0 + + + B_0x1 + External source (VLCD pin) + 0x1 + + + + + DUTY + Duty selection +These bits determine the duty cycle. Values 101, 110 and 111 are forbidden. +Others: Reserved + 2 + 3 + read-write + + + B_0x0 + Static duty + 0x0 + + + B_0x1 + 1/2 duty + 0x1 + + + B_0x2 + 1/3 duty + 0x2 + + + B_0x3 + 1/4 duty + 0x3 + + + B_0x4 + 1/8 duty + 0x4 + + + + + BIAS + Bias selector +These bits determine the bias used. Value 11 is forbidden. + 5 + 2 + read-write + + + B_0x0 + Bias 1/4 + 0x0 + + + B_0x1 + Bias 1/2 + 0x1 + + + B_0x2 + Bias 1/3 + 0x2 + + + + + MUX_SEG + Mux segment enable +This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with1SEG[31:28] or SEG[15:12]. See Section118.3.7. + 7 + 1 + read-write + + + B_0x0 + SEG pin multiplexing disabled + 0x0 + + + B_0x1 + SEG[31:28] multiplexed with SEG[43:40] + 0x1 + + + + + BUFEN + Voltage output buffer enable +This bit is used to enable/disable the voltage output buffer for higher driving capability. + 8 + 1 + read-write + + + B_0x0 + Output buffer disabled + 0x0 + + + B_0x1 + Output buffer enabled + 0x1 + + + + + + + LCD_FCR + LCD_FCR + LCD frame control register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + HD + High drive enable +This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated. + 0 + 1 + read-write + + + B_0x0 + Permanent high drive disabled + 0x0 + + + B_0x1 + Permanent high drive enabled. When HD = 1, PON[2:0] must be programmed to 001. + 0x1 + + + + + SOFIE + Start of frame interrupt enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + LCD start-of-frame interrupt disabled + 0x0 + + + B_0x1 + LCD start-of-frame interrupt enabled + 0x1 + + + + + UDDIE + Update display done interrupt enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + LCD update display done interrupt disabled + 0x0 + + + B_0x1 + LCD update display done interrupt enabled + 0x1 + + + + + PON + Pulse ON duration +These bits are written by software to define the pulse duration in terms of ck_ps pulses. A1short pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. +Note that the pulse is never longer than one half prescaled LCD clock period. +PON duration example with LCDCLK = 32.7681kHz and PS=0x03: + 4 + 3 + read-write + + + B_0x0 + 0 1s + 0x0 + + + B_0x1 + 244 1s + 0x1 + + + B_0x2 + 488 1s + 0x2 + + + B_0x3 + 782 1s + 0x3 + + + B_0x4 + 976 1s + 0x4 + + + B_0x5 + 1.22 ms + 0x5 + + + B_0x6 + 1.46 ms + 0x6 + + + B_0x7 + 1.71 ms + 0x7 + + + + + DEAD + Dead time duration +These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. +...... + 7 + 3 + read-write + + + B_0x0 + No dead time + 0x0 + + + B_0x1 + 1 phase period dead time + 0x1 + + + B_0x2 + 2 phase period dead time + 0x2 + + + B_0x7 + 7 phase period dead time + 0x7 + + + + + CC + Contrast control +These bits specify one of the V<sub>LCD </sub>maximum voltages (independent of V<sub>DD</sub>). It ranges from12.60 V to 3.51V. +Note: Refer to the datasheet for the V<sub>LCDx</sub> values. + 10 + 3 + read-write + + + B_0x0 + V<sub>LCD0</sub> + 0x0 + + + B_0x1 + V<sub>LCD1</sub> + 0x1 + + + B_0x2 + V<sub>LCD2</sub> + 0x2 + + + B_0x3 + V<sub>LCD3</sub> + 0x3 + + + B_0x4 + V<sub>LCD4</sub> + 0x4 + + + B_0x5 + V<sub>LCD5</sub> + 0x5 + + + B_0x6 + V<sub>LCD6</sub> + 0x6 + + + B_0x7 + V<sub>LCD7</sub> + 0x7 + + + + + BLINKF + Blink frequency selection + 13 + 3 + read-write + + + B_0x0 + f<sub>LCD</sub>/8 + 0x0 + + + B_0x1 + f<sub>LCD</sub>/16 + 0x1 + + + B_0x2 + f<sub>LCD</sub>/32 + 0x2 + + + B_0x3 + f<sub>LCD</sub>/64 + 0x3 + + + B_0x4 + f<sub>LCD</sub>/128 + 0x4 + + + B_0x5 + f<sub>LCD</sub>/256 + 0x5 + + + B_0x6 + f<sub>LCD</sub>/512 + 0x6 + + + B_0x7 + f<sub>LCD</sub>/1024 + 0x7 + + + + + BLINK + Blink mode selection + 16 + 2 + read-write + + + B_0x0 + Blink disabled + 0x0 + + + B_0x1 + Blink enabled on SEG[0], COM[0] (1 pixel) + 0x1 + + + B_0x2 + Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) + 0x2 + + + B_0x3 + Blink enabled on all SEGs and all COMs (all pixels) + 0x3 + + + + + DIV + DIV clock divider +These bits are written by software to define the division factor of the DIV divider (see1Section118.3.2.) +... + 18 + 4 + read-write + + + B_0x0 + ck_div = ck_ps/16 + 0x0 + + + B_0x1 + ck_div = ck_ps/17 + 0x1 + + + B_0xF + ck_div = ck_ps/31 + 0xF + + + + + PS + PS 16-bit prescaler +These bits are written by software to define the division factor of the PS 16-bit prescaler. +ck_ps = LCDCLK/(2<sup>PS[3:0]</sup>). See<sub> </sub>Section118.3.2. +... + 22 + 4 + read-write + + + B_0x0 + ck_ps = LCDCLK + 0x0 + + + B_0x1 + ck_ps = LCDCLK/2 + 0x1 + + + B_0xF + ck_ps = LCDCLK/32768 + 0xF + + + + + + + LCD_SR + LCD_SR + LCD status register + 0x08 + 0x20 + 0x00000020 + 0xFFFFFFFF + + + ENS + LCD enabled status +This bit is set and cleared by hardware. It indicates the LCD controller status. +Note: This bit is set immediately when LCDEN in LCD_CR goes from 0 to 1. On deactivation, it reflects the real LCD status. It becomes 0 at the end of the last displayed frame. + 0 + 1 + read-only + + + B_0x0 + LCD controller disabled + 0x0 + + + B_0x1 + LCD controller enabled + 0x1 + + + + + SOF + Start-of-frame flag +This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to SOFC in LCD_CLR. The bit clear has priority over the set. + 1 + 1 + read-only + + + B_0x0 + No event + 0x0 + + + B_0x1 + Start-of-frame event occurred. An LCD SOF interrupt is generated if SOFIE is set. + 0x1 + + + + + UDR + Update display request +Each time software modifies the LCD_RAM, it must set this bit to transfer the updated data to the second level buffer. This bit stays set until the end of the update. During this time, +the LCD_RAM is write protected. +When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, +Note: only the LCD_DISPLAY of COM0 and COM1 are updated. +Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be cleared by hardware only. It can be cleared only when LCDEN = 1 + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Update display request + 0x1 + + + + + UDD + Update display done +This bit is set by hardware. It is cleared by writing 1 to UDDC in LCD_CLR. The bit set has priority over the clear. +Note: If the device is in Stop mode (PCLK not provided), UDD does not generate an interrupt even if UDDIE = 1. If the display is not enabled, the UDD interrupt never occurs. + 3 + 1 + read-only + + + B_0x0 + No event + 0x0 + + + B_0x1 + Update display request done. A UDD interrupt is generated if UDDIE = 1 in LCD_FCR. + 0x1 + + + + + RDY + Ready flag +This bit is set and cleared by hardware. It indicates the status of the stepup converter. + 4 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Stepup converter enabled and ready to provide the correct voltage + 0x1 + + + + + FCRSF + LCD frame control register synchronization flag +This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register. + 5 + 1 + read-only + + + B_0x0 + LCD frame control register not yet synchronized + 0x0 + + + B_0x1 + LCD frame control register synchronized + 0x1 + + + + + + + LCD_CLR + LCD_CLR + LCD clear register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SOFC + Start-of-frame flag clear +This bit is written by software to clear SOF in LCD_SR. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear SOF flag. + 0x1 + + + + + UDDC + Update display done clear +This bit is written by software to clear UDD in LCD_SR. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear UDD flag. + 0x1 + + + + + + + LCD_RAM0 + LCD_RAM0 + LCD display memory + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM1 + LCD_RAM1 + LCD display memory + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM2 + LCD_RAM2 + LCD display memory + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM3 + LCD_RAM3 + LCD display memory + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM4 + LCD_RAM4 + LCD display memory + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM5 + LCD_RAM5 + LCD display memory + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM6 + LCD_RAM6 + LCD display memory + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM7 + LCD_RAM7 + LCD display memory + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 20 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM8 + LCD_RAM8 + LCD display memory + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM9 + LCD_RAM9 + LCD display memory + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM10 + LCD_RAM10 + LCD display memory + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM11 + LCD_RAM11 + LCD display memory + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM12 + LCD_RAM12 + LCD display memory + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM13 + LCD_RAM13 + LCD display memory + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM14 + LCD_RAM14 + LCD display memory + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 32 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + LCD_RAM15 + LCD_RAM15 + LCD display memory + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + B_0x0 + Pixel inactive + 0x0 + + + B_0x1 + Pixel active + 0x1 + + + + + + + + + LPTIM1 + LPTIM1 address block description + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + LPTIM1_ISR_OUTPUT + LPTIM1_ISR_OUTPUT + LPTIM1 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM1_ISR_INPUT + LPTIM1_ISR_INPUT + LPTIM1 interrupt and status register [alternate] + LPTIM1_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM1_ICR_OUTPUT + LPTIM1_ICR_OUTPUT + LPTIM1 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM1_ICR_INPUT + LPTIM1_ICR_INPUT + LPTIM1 interrupt clear register [alternate] + LPTIM1_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM1_DIER_OUTPUT + LPTIM1_DIER_OUTPUT + LPTIM1 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM1_DIER_INPUT + LPTIM1_DIER_INPUT + LPTIM1 interrupt enable register [alternate] + LPTIM1_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM1_CFGR + LPTIM1_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM1_ext_trig0 + 0x0 + + + B_0x1 + LPTIM1_ext_trig1 + 0x1 + + + B_0x2 + LPTIM1_ext_trig2 + 0x2 + + + B_0x3 + LPTIM1_ext_trig3 + 0x3 + + + B_0x4 + LPTIM1_ext_trig4 + 0x4 + + + B_0x5 + LPTIM1_ext_trig5 + 0x5 + + + B_0x6 + LPTIM1_ext_trig6 + 0x6 + + + B_0x7 + LPTIM1_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM1_ARR, LPTIM1_RCR and the LPTIM1_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM1_CR + LPTIM1_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM1_ARR and LPTIM1_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM1_ARR and LPTIM1_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM1_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM1_CNT register asynchronously resets LPTIM1_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM1_CCR1 + LPTIM1_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM1_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_ARR + LPTIM1_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM1_CNT + LPTIM1_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM1_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM1_CFGR2 + LPTIM1_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM1_in1_mux0 + 0x0 + + + B_0x1 + LPTIM1_in1_mux1 + 0x1 + + + B_0x2 + LPTIM1_in1_mux2 + 0x2 + + + B_0x3 + LPTIM1_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM1_in2_mux0 + 0x0 + + + B_0x1 + LPTIM1_in2_mux1 + 0x1 + + + B_0x2 + LPTIM1_in2_mux2 + 0x2 + + + B_0x3 + LPTIM1_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM1_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM1_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM1_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM1_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM1_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM1_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM1_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM1_ic2_mux3 + 0x3 + + + + + + + LPTIM1_RCR + LPTIM1_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM1_CCMR1 + LPTIM1_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM1_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM1_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM1_CCMR2 + LPTIM1_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM1_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM1_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM1_CCR2 + LPTIM1_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM1_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_CCR3 + LPTIM1_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM1_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM1_CCR4 + LPTIM1_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM1_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM1_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPTIM2 + LPTIM2 address block description + LPTIM + 0x40009400 + + 0x0 + 0x400 + registers + + + + LPTIM2_ISR_OUTPUT + LPTIM2_ISR_OUTPUT + LPTIM2 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM2_ISR_INPUT + LPTIM2_ISR_INPUT + LPTIM2 interrupt and status register [alternate] + LPTIM2_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM2_ICR_OUTPUT + LPTIM2_ICR_OUTPUT + LPTIM2 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM2_ICR_INPUT + LPTIM2_ICR_INPUT + LPTIM2 interrupt clear register [alternate] + LPTIM2_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM2_DIER_OUTPUT + LPTIM2_DIER_OUTPUT + LPTIM2 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM2_DIER_INPUT + LPTIM2_DIER_INPUT + LPTIM2 interrupt enable register [alternate] + LPTIM2_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM2_CFGR + LPTIM2_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM2_ext_trig0 + 0x0 + + + B_0x1 + LPTIM2_ext_trig1 + 0x1 + + + B_0x2 + LPTIM2_ext_trig2 + 0x2 + + + B_0x3 + LPTIM2_ext_trig3 + 0x3 + + + B_0x4 + LPTIM2_ext_trig4 + 0x4 + + + B_0x5 + LPTIM2_ext_trig5 + 0x5 + + + B_0x6 + LPTIM2_ext_trig6 + 0x6 + + + B_0x7 + LPTIM2_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM2_ARR, LPTIM2_RCR and the LPTIM2_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM2_CR + LPTIM2_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM2_ARR and LPTIM2_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM2_ARR and LPTIM2_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM2_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM2_CNT register asynchronously resets LPTIM2_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM2_CCR1 + LPTIM2_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM2_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_ARR + LPTIM2_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM2_CNT + LPTIM2_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM2_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM2_CFGR2 + LPTIM2_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM2_in1_mux0 + 0x0 + + + B_0x1 + LPTIM2_in1_mux1 + 0x1 + + + B_0x2 + LPTIM2_in1_mux2 + 0x2 + + + B_0x3 + LPTIM2_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM2_in2_mux0 + 0x0 + + + B_0x1 + LPTIM2_in2_mux1 + 0x1 + + + B_0x2 + LPTIM2_in2_mux2 + 0x2 + + + B_0x3 + LPTIM2_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM2_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM2_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM2_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM2_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM2_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM2_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM2_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM2_ic2_mux3 + 0x3 + + + + + + + LPTIM2_RCR + LPTIM2_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM2_CCMR1 + LPTIM2_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM2_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM2_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM2_CCMR2 + LPTIM2_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM2_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM2_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM2_CCR2 + LPTIM2_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM2_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_CCR3 + LPTIM2_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM2_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM2_CCR4 + LPTIM2_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM2_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM2_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPTIM3 + LPTIM3 address block description + LPTIM + 0x40009000 + + 0x0 + 0x400 + registers + + + + LPTIM3_ISR_OUTPUT + LPTIM3_ISR_OUTPUT + LPTIM3 interrupt and status register [alternate] + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag +If channel CC1 is configured as output: +The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK +CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + 3 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. The corresponding interrupt or DMA request is generated if enabled. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. The UE flag is automatically cleared by hardware once the LPTIM_ARR register is written by any bus master like CPU or DMA. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag +If channel CC2 is configured as output: +The CC2IF flag is set by hardware to inform application that LPTIM_CNT register value matches the +compare register's value. CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CC3IF + Compare 3 interrupt flag +If channel CC3 is configured as output: +The CC3IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR3 register's value. + 0x1 + + + + + CC4IF + Compare 4 interrupt flag +If channel CC4 is configured as output: +The CC4IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR4 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK +CMP2OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR2 register has been successfully completed. CMP2OK flag can be cleared by writing 1 to the CMP2OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-only + + + CMP3OK + Compare register 3 update OK +CMP3OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR3 register has been successfully completed. CMP3OK flag can be cleared by writing 1 to the CMP3OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-only + + + CMP4OK + Compare register 4 update OK +CMP4OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR4 register has been successfully completed. CMP4OK flag can be cleared by writing 1 to the CMP4OKCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-only + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM3_ISR_INPUT + LPTIM3_ISR_INPUT + LPTIM3 interrupt and status register [alternate] + LPTIM3_ISR_OUTPUT + 0x000 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag +If channel CC1 is configured as input: +CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + 0x1 + + + + + ARRM + Autoreload match +ARRM is set by hardware to inform application that LPTIM_CNT registers value reached the LPTIM_ARR registers value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event +EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + 2 + 1 + read-only + + + ARROK + Autoreload register update OK +ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + 4 + 1 + read-only + + + UP + Counter direction change down to up +In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-only + + + DOWN + Counter direction change up to down +In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-only + + + UE + LPTIM update event occurred +UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + 7 + 1 + read-only + + + REPOK + Repetition register update OK +REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag +If channel CC2 is configured as input: +CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC3IF + Capture 3 interrupt flag +If channel CC3 is configured as input: +CC3IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR3 register. The corresponding interrupt or DMA request is generated if enabled. The CC3OF flag is set if the CC3IF flag was already high. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR3 register. (An edge has been detected on IC3 which matches the selected polarity). The CC3IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC3IF flag can be cleared by writing 1 to the CC3CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC4IF + Capture 4 interrupt flag +If channel CC4 is configured as input: +CC4IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR4 register. The corresponding interrupt or DMA request is generated if enabled. The CC4OF flag is set if the CC4IF flag was already high. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR4 register. (An edge has been detected on IC4 which matches the selected polarity). The CC4IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC4IF flag can be cleared by writing 1 to the CC4CF bit in the LPTIM_ICR register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + CC3OF + Capture 3 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC3OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR3 register while CC3IF flag was already set + 0x1 + + + + + CC4OF + Capture 4 over-capture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC4OCF bit in the LPTIM_ICR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR4 register while CC4IF flag was already set + 0x1 + + + + + DIEROK + Interrupt enable register update OK +DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + 24 + 1 + read-only + + + + + LPTIM3_ICR_OUTPUT + LPTIM3_ICR_OUTPUT + LPTIM3 interrupt clear register [alternate] + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag +Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag +Writing 1 to this bit clears the CMP2OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + write-only + + + CMP3OKCF + Compare register 3 update OK clear flag +Writing 1 to this bit clears the CMP3OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + write-only + + + CMP4OKCF + Compare register 4 update OK clear flag +Writing 1 to this bit clears the CMP4OK flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM3_ICR_INPUT + LPTIM3_ICR_INPUT + LPTIM3 interrupt clear register [alternate] + LPTIM3_ICR_OUTPUT + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag +Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag +Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag +Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag +Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag +Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag +Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + write-only + + + UECF + Update event clear flag +Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag +Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag +Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + write-only + + + CC3CF + Capture/compare 3 clear flag +Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + write-only + + + CC4CF + Capture/compare 4 clear flag +Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag +Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag +Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + write-only + + + CC3OCF + Capture/compare 3 over-capture clear flag +Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + write-only + + + CC4OCF + Capture/compare 4 over-capture clear flag +Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag +Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + 24 + 1 + write-only + + + + + LPTIM3_DIER_OUTPUT + LPTIM3_DIER_OUTPUT + LPTIM3 interrupt enable register [alternate] + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + CMP3OKIE + Compare register 3 update OK interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 20 + 1 + read-write + + + B_0x0 + CMPOK register 3 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 3 interrupt enabled + 0x1 + + + + + CMP4OKIE + Compare register 4 update OK interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 21 + 1 + read-write + + + B_0x0 + CMPOK register 4 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 4 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM3_DIER_INPUT + LPTIM3_DIER_INPUT + LPTIM3 interrupt enable register [alternate] + LPTIM3_DIER_OUTPUT + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 10 + 1 + read-write + + + B_0x0 + Capture/compare 3 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 11 + 1 + read-write + + + B_0x0 + Capture/compare 4 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 4 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC3OIE + Capture/compare 3 over-capture interrupt enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 14 + 1 + read-write + + + B_0x0 + CC3 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC3 over-capture interrupt enabled + 0x1 + + + + + CC4OIE + Capture/compare 4 over-capture interrupt enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 15 + 1 + read-write + + + B_0x0 + CC4 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC4 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. Writing '0' to the CC1DE bit resets the associated ic1_dma_req signal. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable +Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. Writing '0' to the UEDE bit resets the associated ue_dma_req signal. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable +Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. Writing '0' to the CC2DE bit resets the associated ic2_dma_req signal. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable +Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. + 26 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. Writing '0' to the CC3DE bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable +Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. + 27 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. Writing '0' to the CC4DE bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + + + LPTIM3_CFGR + LPTIM3_CFGR + LPTIM configuration register + 0x00C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector +The CKSEL bit selects which clock source the LPTIM uses: + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity +When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. +If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. +Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock +The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger +The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler +The PRESC bits configure the prescaler division factor. It can be one among the following division factors: + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector +The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: +See Section125.4.3: LPTIM input and trigger mapping for details. + 13 + 3 + read-write + + + B_0x0 + LPTIM3_ext_trig0 + 0x0 + + + B_0x1 + LPTIM3_ext_trig1 + 0x1 + + + B_0x2 + LPTIM3_ext_trig2 + 0x2 + + + B_0x3 + LPTIM3_ext_trig3 + 0x3 + + + B_0x4 + LPTIM3_ext_trig4 + 0x4 + + + B_0x5 + LPTIM3_ext_trig5 + 0x5 + + + B_0x6 + LPTIM3_ext_trig6 + 0x6 + + + B_0x7 + LPTIM3_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity +The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable +The TIMOUT bit controls the Timeout feature + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape +The WAVE bit controls the output shape + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + PRELOAD + Registers update mode +The PRELOAD bit controls the LPTIM3_ARR, LPTIM3_RCR and the LPTIM3_CCRx registers update modality + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled +The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable +The ENC bit controls the Encoder mode +Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM3_CR + LPTIM3_CR + LPTIM control register + 0x010 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable +The ENABLE bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. Writing '0' to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. +If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM3_ARR and LPTIM3_CNT registers. +This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode +This bit is set by software and cleared by hardware. +In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. +If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. +If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM3_ARR and LPTIM3_CNT registers and the LPTIM counter keeps counting in Continuous mode. +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + 2 + 1 + read-write + + + COUNTRST + Counter reset +This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM3_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). +This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. +COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software must consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + 3 + 1 + read-write + + + RSTARE + Reset after read enable +This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM3_CNT register asynchronously resets LPTIM3_CNT register content. +This bit can be set only when the LPTIM is enabled. + 4 + 1 + read-write + + + + + LPTIM3_CCR1 + LPTIM3_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value +If channel CC1 is configured as output: +CCR1 is the value to be loaded in the capture/compare 1 register. +Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 1 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC1 output. +If channel CC1 is configured as input: +CCR1 becomes read-only, it contains the counter value transferred by the last input capture 1 event. The LPTIM3_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM3_ARR + LPTIM3_ARR + LPTIM autoreload register + 0x018 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value +ARR is the autoreload value for the LPTIM. +This value must be strictly greater than the CCRx[15:0] value. + 0 + 16 + read-write + + + + + LPTIM3_CNT + LPTIM3_CNT + LPTIM counter register + 0x01C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +When the LPTIM is running with an asynchronous clock, reading the LPTIM3_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + 0 + 16 + read-only + + + + + LPTIM3_CFGR2 + LPTIM3_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection +The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 0 + 2 + read-write + + + B_0x0 + LPTIM3_in1_mux0 + 0x0 + + + B_0x1 + LPTIM3_in1_mux1 + 0x1 + + + B_0x2 + LPTIM3_in1_mux2 + 0x2 + + + B_0x3 + LPTIM3_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection +The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 4 + 2 + read-write + + + B_0x0 + LPTIM3_in2_mux0 + 0x0 + + + B_0x1 + LPTIM3_in2_mux1 + 0x1 + + + B_0x2 + LPTIM3_in2_mux2 + 0x2 + + + B_0x3 + LPTIM3_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection +The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture +1 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 16 + 2 + read-write + + + B_0x0 + LPTIM3_ic1_mux0 + 0x0 + + + B_0x1 + LPTIM3_ic1_mux1 + 0x1 + + + B_0x2 + LPTIM3_ic1_mux2 + 0x2 + + + B_0x3 + LPTIM3_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection +The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture +2 to one of the available inputs. +For connection details refer to Section125.4.3: LPTIM input and trigger mapping. + 20 + 2 + read-write + + + B_0x0 + LPTIM3_ic2_mux0 + 0x0 + + + B_0x1 + LPTIM3_ic2_mux1 + 0x1 + + + B_0x2 + LPTIM3_ic2_mux2 + 0x2 + + + B_0x3 + LPTIM3_ic2_mux3 + 0x3 + + + + + + + LPTIM3_RCR + LPTIM3_RCR + LPTIM repetition register + 0x028 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value +REP is the repetition value for the LPTIM. + 0 + 8 + read-write + + + + + LPTIM3_CCMR1 + LPTIM3_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM3_CCR1) or not. + 1 + 1 + read-write + + + CC1P + Capture/compare 1 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC1 polarity for capture operations. + 2 + 2 + read-write + + + IC1PSC + Input capture 1 prescaler +This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM3_CCR2) or not. + 17 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity. +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +This field is used to select the IC2 polarity for capture operations. + 18 + 2 + read-write + + + IC2PSC + Input capture 2 prescaler +This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter +This bitfield defines the number of consecutive equal samples that are detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM3_CCMR2 + LPTIM3_CCMR2 + LPTIM capture/compare mode register 2 + 0x030 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3SEL + Capture/compare 3 selection +This bitfield defines the direction of the channel input (capture) or output mode. + 0 + 1 + read-write + + + B_0x0 + CC3 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC3 channel is configured in input capture mode + 0x1 + + + + + CC3E + Capture/compare 3 output enable. +Condition: CC3 as output: +Condition: CC3 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM3_CCR3) or not. + 1 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC3E bit resets the associated ic3_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC3P + Capture/compare 3 output polarity. +Condition: CC3 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC3 as input: +This field is used to select the IC3 polarity for capture operations. + 2 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC3 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC3 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC3 rising and falling edges. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC3F + Input capture 3 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC4SEL + Capture/compare 4 selection +This bitfield defines the direction of the channel, input (capture) or output mode. + 16 + 1 + read-write + + + B_0x0 + CC4 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC4 channel is configured in input capture mode + 0x1 + + + + + CC4E + Capture/compare 4 output enable. +Condition: CC4 as output: +Condition: CC4 as input: +This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM3_CCR4) or not. + 17 + 1 + read-write + + + B_0x0 + Capture disabled. Writing '0' to the CC4E bit resets the associated ic4_dma_req signal. + 0x0 + + + B_0x1 + Capture enabled. + 0x1 + + + + + CC4P + Capture/compare 4 output polarity. +Condition: CC4 as output: +Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. +Condition: CC4 as input: +This field is used to select the IC4 polarity for capture operations. + 18 + 2 + read-write + + + B_0x0 + rising edge, circuit is sensitive to IC4 rising edge + 0x0 + + + B_0x1 + falling edge, circuit is sensitive to IC4 falling edge + 0x1 + + + B_0x2 + reserved, do not use this configuration. + 0x2 + + + B_0x3 + both edges, circuit is sensitive to both IC4 rising and falling edges. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC4F + Input capture 4 filter +This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM3_CCR2 + LPTIM3_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value +If channel CC2 is configured as output: +CCR2 is the value to be loaded in the capture/compare 2 register. +Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 2 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC2 output. +If channel CC2 is configured as input: +CCR2 becomes read-only, it contains the counter value transferred by the last input capture 2 event. The LPTIM3_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM3_CCR3 + LPTIM3_CCR3 + LPTIM compare register 3 + 0x038 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value +If channel CC3 is configured as output: +CCR3 is the value to be loaded in the capture/compare 3 register. +Depending on the PRELOAD option, the CCR3 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 3 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC3 output. +If channel CC3 is configured as input: +CCR3 becomes read-only, it contains the counter value transferred by the last input capture 3 event. The LPTIM3_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + LPTIM3_CCR4 + LPTIM3_CCR4 + LPTIM compare register 4 + 0x03C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value +If channel CC4 is configured as output: +CCR4 is the value to be loaded in the capture/compare 4 register. +Depending on the PRELOAD option, the CCR4 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. +The capture/compare register 4 contains the value to be compared to the counter LPTIM3_CNT and signaled on OC4 output. +If channel CC4 is configured as input: +CCR4 becomes read-only, it contains the counter value transferred by the last input capture 4 event. The LPTIM3_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + + + LPUART1 + LPUART address block description + LPUART + 0x40008000 + + 0x0 + 0x30 + registers + + + + LPUART_CR1 + LPUART_CR1 + LPUART control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable +When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode +When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. +When this bit is set, the LPUART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the LPUART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the LPUART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the LPUART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). +This bit can only be written when the LPUART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section132.4.14: RS232 Hardware flow control and RS485 Driver Enable. +If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section131.5.21: RS232 Hardware flow control and RS485 Driver Enable. +This bitfield can only be written when the LPUART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the LPUART is disabled (UE=0). +Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_CR1_ALTERNATE + LPUART_CR1_ALTERNATE + LPUART control register 1 + LPUART_CR1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable +When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode +When this bit is cleared, the LPUART cannot wake up the MCU from low-power mode. +When this bit is set, the LPUART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the LPUART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the LPUART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the LPUART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). +This bit can only be written when the LPUART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section132.4.14: RS232 Hardware flow control and RS485 Driver Enable. +If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section131.5.21: RS232 Hardware flow control and RS485 Driver Enable. +This bitfield can only be written when the LPUART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the LPUART is disabled (UE=0). +Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + LPUART_CR2 + LPUART_CR2 + LPUART control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the LPUART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + STOP + STOP bits +These bits are used for programming the stop bits. +This bitfield can only be written when the LPUART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the LPUART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the LPUART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the LPUART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ADD + Address of the LPUART node +These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). + 24 + 8 + read-write + + + + + LPUART_CR3 + LPUART_CR3 + LPUART control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the LPUART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the LPUART is disabled (UE=0). + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the LPUART is disabled (UE=0) + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. +This bit can only be written when the LPUART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data. + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the LPUART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the LPUART is disabled (UE=0). + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the LPUART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). +This bitfield can only be written when the LPUART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). +This bitfield can only be written when the LPUART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved. + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + Receive FIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + Receive FIFO becomes full. + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved. + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + TXFIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + TXFIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + TXFIFO becomes empty. + 0x5 + + + + + + + LPUART_BRR + LPUART_BRR + LPUART baud rate register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BRR + LPUART baud rate division (LPUARTDIV) + 0 + 20 + read-write + + + + + LPUART_RQR + LPUART_RQR + LPUART request register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software must wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit clears the RXNE flag. +This enables discarding the received data without reading it, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + LPUART_ISR + LPUART_ISR + LPUART interrupt and status register + 0x1C + 0x20 + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. +An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. +Note: This error is associated with the character in the LPUART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the LPUART_CR3 register. +Note: This error is associated with the character in the LPUART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag +This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: This error is associated with the character in the LPUART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. +An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. +Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. +The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +An interrupt is generated if RXFNEIE=1 in the LPUART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the LPUART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: +When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXFE is set. +When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. +When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. +When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. +An interrupt is generated if TCIE=1 in the LPUART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the LPUART_ICR register or by writing to the LPUART_TDR register. + 6 + 1 + read-only + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. +The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF must be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). +An interrupt is generated if the TXFNFIE bit =1 in the LPUART_CR1 register. +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. +An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. +An interrupt is generated if CMIE=1in the LPUART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. +It can be used to verify that the LPUART is ready for reception before entering low-power mode. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 22 + 1 + read-only + + + TXFE + TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the LPUART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO is not empty. + 0x0 + + + B_0x1 + TXFIFO is empty. + 0x1 + + + + + RXFF + RXFIFO Full +This bit is set by hardware when the number of received data corresponds to RXFIFO1size1+11 (RXFIFO full + 1 data in the LPUART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the LPUART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO is not Full. + 0x0 + + + B_0x1 + RXFIFO is Full. + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the LPUART_CR3 register. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the LPUART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + LPUART_ISR_ALTERNATE + LPUART_ISR_ALTERNATE + LPUART interrupt and status register + LPUART_ISR + 0x1C + 0x20 + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. +An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the LPUART_CR3 register. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag +This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE/RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: In FIFO mode, this error is associated with the character in the LPUART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the LPUART_RDR register while RXNE=1 (RXFF = 1 in case FIFO mode is enabled). It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. +An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. +Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the LPUART_RDR shift register has been transferred to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. +An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag is set when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the LPUART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the LPUART_TDR register has been transferred into the shift register. It is cleared by a write to the LPUART_TDR register. +An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register. +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. +An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. +An interrupt is generated if CMIE=1in the LPUART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. +It can be used to verify that the LPUART is ready for reception before entering low-power mode. +Note: If the LPUART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. + 22 + 1 + read-only + + + + + LPUART_ICR + LPUART_ICR + LPUART interrupt flag clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the LPUART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the LPUART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the LPUART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. + 4 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the LPUART_ISR register. + 6 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. + 9 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. + 20 + 1 + write-only + + + + + LPUART_RDR + LPUART_RDR + LPUART receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure1254). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + LPUART_TDR + LPUART_TDR + LPUART transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure1254). +When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + LPUART_PRESC + LPUART_PRESC + LPUART prescaler register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The LPUART input clock can be divided by a prescaler: +Remaining combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + LPUART2 + 0x40008400 + + + LPUART3 + 0x40008C00 + + + OPAMP + OPAMP address block description + OPAMP + 0x40007800 + + 0x0 + 0xC + registers + + + + OPAMP_CSR + OPAMP_CSR + OPAMP control/status register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OPAEN + Operational amplifier Enable + 0 + 1 + read-write + + + B_0x0 + operational amplifier disabled + 0x0 + + + B_0x1 + operational amplifier enabled + 0x1 + + + + + OPALPM + Operational amplifier Low Power Mode +The operational amplifier must be disable to change this configuration. + 1 + 1 + read-write + + + B_0x0 + operational amplifier in normal mode + 0x0 + + + B_0x1 + operational amplifier in low-power mode + 0x1 + + + + + OPAMODE + Operational amplifier PGA mode + 2 + 2 + read-write + + + B_0x0 + internal PGA disable + 0x0 + + + B_0x1 + internal PGA disable + 0x1 + + + B_0x2 + internal PGA enable, gain programmed in PGA_GAIN + 0x2 + + + B_0x3 + internal follower + 0x3 + + + + + PGA_GAIN + Operational amplifier Programmable amplifier gain value + 4 + 2 + read-write + + + B_0x0 + internal PGA Gain 2 + 0x0 + + + B_0x1 + internal PGA Gain 4 + 0x1 + + + B_0x2 + internal PGA Gain 8 + 0x2 + + + B_0x3 + internal PGA Gain 16 + 0x3 + + + + + VM_SEL + Inverting input selection +These bits are used only when OPAMODE = 00, 01 or 10. +1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) + 8 + 2 + read-write + + + B_0x0 + GPIO connected to VINM (valid also in PGA mode for filtering) + 0x0 + + + + + VP_SEL + Non inverted input selection + 10 + 1 + read-write + + + B_0x0 + GPIO connected to VINP + 0x0 + + + B_0x1 + DAC connected to VINP + 0x1 + + + + + CALON + Calibration mode enabled + 12 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Calibration mode (all switches opened by HW) + 0x1 + + + + + CALSEL + Calibration selection + 13 + 1 + read-write + + + B_0x0 + NMOS calibration (200mV applied on OPAMP inputs) + 0x0 + + + B_0x1 + PMOS calibration (VDDA-200mV applied on OPAMP inputs) + 0x1 + + + + + USERTRIM + allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values +This bit is active for both mode normal and low-power. + 14 + 1 + read-write + + + B_0x0 + factory trim code used + 0x0 + + + B_0x1 + user trim code used + 0x1 + + + + + CALOUT + Operational amplifier calibration output +During calibration mode offset is trimmed when this signal toggle. + 15 + 1 + read-only + + + OPA_RANGE + Operational amplifier power supply range for stability +All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. + 31 + 1 + read-write + + + B_0x0 + Low range (VDDA < 2.4V) + 0x0 + + + B_0x1 + High range (VDDA > 2.4V) + 0x1 + + + + + + + OPAMP_OTR + OPAMP_OTR + OPAMP offset trimming register in normal mode + 0x04 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMOFFSETN + Trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMOFFSETP + Trim for PMOS differential pairs + 8 + 5 + read-write + + + + + OPAMP_LPOTR + OPAMP_LPOTR + OPAMP offset trimming register in low-power mode + 0x08 + 0x20 + 0x00000000 + 0xFFFF0000 + + + TRIMLPOFFSETN + Low-power mode trim for NMOS differential pairs + 0 + 5 + read-write + + + TRIMLPOFFSETP + Low-power mode trim for PMOS differential pairs + 8 + 5 + read-write + + + + + + + PWR + PWR register block + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + PWR_CR1 + PWR_CR1 + Power control register 1 + 0x00 + 0x20 + 0x00000208 + 0xFFFFFFFF + + + LPMS + Low-power mode selection +These bits select the low-power mode entered when CPU enters the deepsleep mode. +1xx: Shutdown mode +Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. +Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. + 0 + 3 + read-write + + + B_0x0 + Stop 0 mode + 0x0 + + + B_0x1 + Stop 1 mode + 0x1 + + + B_0x2 + Stop 2 mode + 0x2 + + + B_0x3 + Standby mode + 0x3 + + + + + FPD_STOP + Flash memory powered down during Stop mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode. + 3 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_LPRUN + Flash memory powered down during Low-power run mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + 4 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + FPD_LPSLP + Flash memory powered down during Low-power sleep mode. +This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode. + 5 + 1 + read-write + + + B_0x0 + Flash memory idle + 0x0 + + + B_0x1 + Flash memory powered down + 0x1 + + + + + DBP + Disable backup domain write protection +In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. + 8 + 1 + read-write + + + B_0x0 + Access to RTC and Backup registers disabled + 0x0 + + + B_0x1 + Access to RTC and Backup registers enabled + 0x1 + + + + + VOS + Voltage scaling range selection + 9 + 2 + read-write + + + B_0x0 + Cannot be written (forbidden by hardware) + 0x0 + + + B_0x1 + Range 1 + 0x1 + + + B_0x2 + Range 2 + 0x2 + + + B_0x3 + Cannot be written (forbidden by hardware) + 0x3 + + + + + LPR + Low-power run +When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). +Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. + 14 + 1 + read-write + + + + + PWR_CR2 + PWR_CR2 + Power control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDE + Programmable voltage detector enable +Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. +Note: This bit is reset only by a system reset. + 0 + 1 + read-write + + + B_0x0 + Programmable voltage detector disable. + 0x0 + + + B_0x1 + Programmable voltage detector enable. + 0x1 + + + + + PLS + Programmable voltage detector level selection. +These bits select the voltage threshold detected by the programmable voltage detector: +Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. +Note: These bits are reset only by a system reset. + 1 + 3 + read-write + + + B_0x0 + V<sub>PVD0</sub> around 2.01V + 0x0 + + + B_0x1 + V<sub>PVD1</sub> around 2.21V + 0x1 + + + B_0x2 + V<sub>PVD2</sub> around 2.41V + 0x2 + + + B_0x3 + V<sub>PVD3</sub> around 2.51V + 0x3 + + + B_0x4 + V<sub>PVD4</sub> around 2.61V + 0x4 + + + B_0x5 + V<sub>PVD5</sub> around 2.81V + 0x5 + + + B_0x6 + V<sub>PVD6</sub> around 2.91V + 0x6 + + + B_0x7 + External input analog voltage PVD_IN (compared internally to VREFINT) + 0x7 + + + + + PVME1 + Peripheral voltage monitoring 1 enable: V<sub>DDUSB</sub> vs. 1.21V + 4 + 1 + read-write + + + B_0x0 + PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V threshold) disable. + 0x0 + + + B_0x1 + PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V threshold) enable. + 0x1 + + + + + PVME3 + Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. 1.621V + 5 + 1 + read-write + + + B_0x0 + PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V threshold) disable. + 0x0 + + + B_0x1 + PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V threshold) enable. + 0x1 + + + + + PVME4 + Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. 1.861V + 6 + 1 + read-write + + + B_0x0 + PVM4 (V<sub>DDA</sub> monitoring vs. 1.861V threshold) disable. + 0x0 + + + B_0x1 + PVM4 (V<sub>DDA</sub> monitoring vs. 1.86 V threshold) enable. + 0x1 + + + + + USV + V<sub>DDUSB</sub> USB supply valid +This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. +Setting this bit is mandatory to use the USB FS peripheral. If V<sub>DDUSB</sub> is not always +present in the application, the PVM can be used to determine whether this supply is ready or +not. + 10 + 1 + read-write + + + B_0x0 + V<sub>DDUSB</sub> is not present. Logical and electrical isolation is applied to ignore this supply. + 0x0 + + + B_0x1 + V<sub>DDUSB</sub> is valid. + 0x1 + + + + + + + PWR_CR3 + PWR_CR3 + Power control register 3 + 0x08 + 0x20 + 0x00008000 + 0xFFFFFFFF + + + EWUP1 + Enable Wake-up pin WKUP1 +When this bit is set, the external wake-up pin WKUP1 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. + 0 + 1 + read-write + + + EWUP2 + Enable Wake-up pin WKUP2 +When this bit is set, the external wake-up pin WKUP2 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. + 1 + 1 + read-write + + + EWUP3 + Enable Wake-up pin WKUP3 +When this bit is set, the external wake-up pin WKUP3 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. + 2 + 1 + read-write + + + EWUP4 + Enable Wake-up pin WKUP4 +When this bit is set, the external wake-up pin WKUP4 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. + 3 + 1 + read-write + + + EWUP5 + Enable Wake-up pin WKUP5 +When this bit is set, the external wake-up pin WKUP5 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. + 4 + 1 + read-write + + + EWUP7 + Enable Wake-up pin WKUP7. +When this bit is set, the external wake-up pin WKUP7 is enabled and triggers a wake-up from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP7 bit in the PWR_CR4 register. + 6 + 1 + read-write + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + read-write + + + B_0x0 + SRAM2 is powered off in Standby mode (SRAM2 content is lost). + 0x0 + + + B_0x1 + SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). + 0x1 + + + + + ENULP + Enable ULP sampling +When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. + 9 + 1 + read-write + + + APC + Apply pull-up and pull-down configuration +When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx +and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode. + 10 + 1 + read-write + + + EIWUL + Enable internal wake-up line + 15 + 1 + read-write + + + B_0x0 + Internal wake-up line disable. + 0x0 + + + B_0x1 + Internal wake-up line enable. + 0x1 + + + + + + + PWR_CR4 + PWR_CR4 + Power control register 4 + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WP1 + Wake-up pin WKUP1 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP2 + Wake-up pin WKUP2 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP3 + Wake-up pin WKUP3 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP4 + Wake-up pin WKUP4 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP5 + Wake-up pin WKUP5 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WP7 + Wake-up pin WKUP7 polarity +This bit defines the polarity used for an event detection on external wake-up pin, WKUP7 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + VBE + V<sub>BAT</sub> battery charging enable + 8 + 1 + read-write + + + B_0x0 + V<sub>BAT</sub> battery charging disable + 0x0 + + + B_0x1 + V<sub>BAT</sub> battery charging enable + 0x1 + + + + + VBRS + V<sub>BAT</sub> battery charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge V<sub>BAT</sub> through a 5 kOhms resistor + 0x0 + + + B_0x1 + Charge V<sub>BAT</sub> through a 1.5 kOhms resistor + 0x1 + + + + + + + PWR_SR1 + PWR_SR1 + Power status register 1 + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUF1 + Wake-up flag 1 +This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register. + 0 + 1 + read-only + + + WUF2 + Wake-up flag 2 +This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register. + 1 + 1 + read-only + + + WUF3 + Wake-up flag 3 +This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register. + 2 + 1 + read-only + + + WUF4 + Wake-up flag 4 +This bit is set when a wake-up event is detected on wake-up pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register. + 3 + 1 + read-only + + + WUF5 + Wake-up flag 5 +This bit is set when a wake-up event is detected on wake-up pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register. + 4 + 1 + read-only + + + WUF7 + Wake-up flag 7 +This bit is set when a wake-up event is detected on wake-up pin, WKUP7. It is cleared by writing 1 in the CWUF7 bit of the PWR_SCR register. + 6 + 1 + read-only + + + SBF + Standby flag +This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 8 + 1 + read-only + + + B_0x0 + The device did not enter the Standby mode + 0x0 + + + B_0x1 + The device entered the Standby mode + 0x1 + + + + + STOPF + Stop Flags +These bits are set by hardware when the device enters any stop mode and are cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. + 9 + 3 + read-only + + + B_0x0 + The device did not enter any Stop mode. + 0x0 + + + B_0x4 + The device entered in Stop 0 mode. + 0x4 + + + B_0x5 + The device entered in Stop 1 mode. + 0x5 + + + B_0x6 + The device entered in Stop 2 mode. + 0x6 + + + + + WUFI + Wake-up flag internal +This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared. + 15 + 1 + read-only + + + + + PWR_SR2 + PWR_SR2 + Power status register 2 + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FLASH_RDY + Flash ready flag +This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. +Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory. + 7 + 1 + read-only + + + B_0x0 + Flash memory in power down + 0x0 + + + B_0x1 + Flash memory ready to be accessed + 0x1 + + + + + REGLPS + Low-power regulator started +This bit provides the information whether the low-power regulator is ready after a power-on +reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased. + 8 + 1 + read-only + + + B_0x0 + The low-power regulator is not ready + 0x0 + + + B_0x1 + The low-power regulator is ready + 0x1 + + + + + REGLPF + Low-power regulator flag +This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits +from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. +This bit is cleared by hardware when the regulator is ready. + 9 + 1 + read-only + + + B_0x0 + The regulator is ready in main mode (MR) + 0x0 + + + B_0x1 + The regulator is in low-power mode (LPR) + 0x1 + + + + + VOSF + Voltage scaling flag +A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. + 10 + 1 + read-only + + + B_0x0 + The regulator is ready in the selected voltage range + 0x0 + + + B_0x1 + The regulator output voltage is changing to the required voltage level + 0x1 + + + + + PVDO + Programmable voltage detector output + 11 + 1 + read-only + + + B_0x0 + V<sub>DD</sub> is above the selected PVD threshold + 0x0 + + + B_0x1 + V<sub>DD</sub> is below the selected PVD threshold + 0x1 + + + + + PVMO1 + Peripheral voltage monitoring output: V<sub>DDUSB</sub> vs. 1.2 V +Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time. + 12 + 1 + read-only + + + B_0x0 + V<sub>DDUSB</sub> voltage is above PVM1 threshold (around 1.21V). + 0x0 + + + B_0x1 + V<sub>DDUSB</sub> voltage is below PVM1 threshold (around 1.21V). + 0x1 + + + + + PVMO3 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.621V +Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time. + 14 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM3 threshold (around 1.621V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM3 threshold (around 1.621V). + 0x1 + + + + + PVMO4 + Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 2.21V +Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time. + 15 + 1 + read-only + + + B_0x0 + V<sub>DDA</sub> voltage is above PVM4 threshold (around 2.21V). + 0x0 + + + B_0x1 + V<sub>DDA</sub> voltage is below PVM4 threshold (around 2.21V). + 0x1 + + + + + + + PWR_SCR + PWR_SCR + Power status clear register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + Clear wake-up flag 1 +Setting this bit clears the WUF1 flag in the PWR_SR1 register. + 0 + 1 + write-only + + + CWUF2 + Clear wake-up flag 2 +Setting this bit clears the WUF2 flag in the PWR_SR1 register. + 1 + 1 + write-only + + + CWUF3 + Clear wake-up flag 3 +Setting this bit clears the WUF3 flag in the PWR_SR1 register. + 2 + 1 + write-only + + + CWUF4 + Clear wake-up flag 4 +Setting this bit clears the WUF4 flag in the PWR_SR1 register. + 3 + 1 + write-only + + + CWUF5 + Clear wake-up flag 5 +Setting this bit clears the WUF5 flag in the PWR_SR1 register. + 4 + 1 + write-only + + + CWUF7 + Clear wake-up flag 7 +Setting this bit clears the WUF7 flag in the PWR_SR1 register. + 6 + 1 + write-only + + + CSBF + Clear standby flag +Setting this bit clears the SBF flag in the PWR_SR1 register. + 8 + 1 + write-only + + + + + PWR_PUCRA + PWR_PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU7 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + PU14 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 14 + 1 + read-write + + + PU15 + Port A pull-up bit y (y1=115 to 0) +When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 15 + 1 + read-write + + + + + PWR_PDCRA + PWR_PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port A pull-down bit y +When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRB + PWR_PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PU1 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PU2 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PU3 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PU4 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PU5 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PU6 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PU7 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PU8 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PU9 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PU10 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PU11 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PU12 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PU13 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PU14 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PU15 + Port B pull-up bit y +When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PDCRB + PWR_PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port B pull-down bit y +When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRC + PWR_PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU7 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + PU14 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 14 + 1 + read-write + + + PU15 + Port C pull-up bit y +When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 15 + 1 + read-write + + + + + PWR_PDCRC + PWR_PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD7 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + PD14 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 14 + 1 + read-write + + + PD15 + Port C pull-down bit y +When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. + 15 + 1 + read-write + + + + + PWR_PUCRD + PWR_PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU4 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 4 + 1 + read-write + + + PU5 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 5 + 1 + read-write + + + PU6 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 6 + 1 + read-write + + + PU8 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + PU10 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 10 + 1 + read-write + + + PU11 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 11 + 1 + read-write + + + PU12 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 12 + 1 + read-write + + + PU13 + Port D pull-up bit y +When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 13 + 1 + read-write + + + + + PWR_PDCRD + PWR_PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD4 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 4 + 1 + read-write + + + PD5 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 5 + 1 + read-write + + + PD6 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 6 + 1 + read-write + + + PD8 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + PD10 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 10 + 1 + read-write + + + PD11 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 11 + 1 + read-write + + + PD12 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 12 + 1 + read-write + + + PD13 + Port D pull-down bit y +When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. + 13 + 1 + read-write + + + + + PWR_PUCRE + PWR_PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU3 + Port E pull-up bit 3 +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + PU7 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 7 + 1 + read-write + + + PU8 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 8 + 1 + read-write + + + PU9 + Port E pull-up bit y +When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 9 + 1 + read-write + + + + + PWR_PDCRE + PWR_PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD3 + Port E pull-down bit 3 +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + PD7 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 7 + 1 + read-write + + + PD8 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 8 + 1 + read-write + + + PD9 + Port E pull-down bit y +When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. + 9 + 1 + read-write + + + + + PWR_PUCRF + PWR_PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PU0 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 0 + 1 + read-write + + + PU1 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 1 + 1 + read-write + + + PU2 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 2 + 1 + read-write + + + PU3 + Port F pull-up bit y +When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. +If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. + 3 + 1 + read-write + + + + + PWR_PDCRF + PWR_PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PD0 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 0 + 1 + read-write + + + PD1 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 1 + 1 + read-write + + + PD2 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 2 + 1 + read-write + + + PD3 + Port F pull-down bit y +When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. + 3 + 1 + read-write + + + + + + + RCC + RCC address block description + RCC + 0x40021000 + + 0x0 + 0x9C + registers + + + RCC_CRS + RCC and CRS global interrupt + 4 + + + + RCC_CR + RCC_CR + Clock control register + 0x00 + 0x20 + 0x00000083 + 0xFFFFFFFF + + + MSION + MSI clock enable +This bit is set and cleared by software. +Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. +Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. +Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator +Set by hardware when used directly or indirectly as system clock. + 0 + 1 + read-write + + + B_0x0 + MSI oscillator OFF + 0x0 + + + B_0x1 + MSI oscillator ON + 0x1 + + + + + MSIRDY + MSI clock ready flag +This bit is set by hardware to indicate that the MSI oscillator is stable. +Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. + 1 + 1 + read-only + + + B_0x0 + MSI oscillator not ready + 0x0 + + + B_0x1 + MSI oscillator ready + 0x1 + + + + + MSIPLLEN + MSI clock PLL enable +Set and cleared by software to enable/ disable the PLL part of the MSI clock source. +MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. +This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). + 2 + 1 + read-write + + + B_0x0 + MSI PLL OFF + 0x0 + + + B_0x1 + MSI PLL ON + 0x1 + + + + + MSIRGSEL + MSI clock range selection +Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. +After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. + 3 + 1 + read-write + + + B_0x0 + MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register + 0x0 + + + B_0x1 + MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register + 0x1 + + + + + MSIRANGE + MSI clock ranges +These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: +others: not allowed (hardware write protection) +Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0) + 4 + 4 + read-write + + + B_0x0 + range 0 around 1001kHz + 0x0 + + + B_0x1 + range 1 around 2001kHz + 0x1 + + + B_0x2 + range 2 around 4001kHz + 0x2 + + + B_0x3 + range 3 around 8001kHz + 0x3 + + + B_0x4 + range 4 around 1M1Hz + 0x4 + + + B_0x5 + range 5 around 21MHz + 0x5 + + + B_0x6 + range 6 around 41MHz (reset value) + 0x6 + + + B_0x7 + range 7 around 81MHz + 0x7 + + + B_0x8 + range 8 around 161MHz + 0x8 + + + B_0x9 + range 9 around 241MHz + 0x9 + + + B_0xA + range 10 around 321MHz + 0xA + + + B_0xB + range 11 around 481MHz + 0xB + + + + + HSION + HSI16 clock enable +Set and cleared by software. +Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. +Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). + 8 + 1 + read-write + + + B_0x0 + HSI16 oscillator OFF + 0x0 + + + B_0x1 + HSI16 oscillator ON + 0x1 + + + + + HSIKERON + HSI16 always enable for peripheral kernels. +Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. + 9 + 1 + read-write + + + B_0x0 + No effect on HSI16 oscillator. + 0x0 + + + B_0x1 + HSI16 oscillator is forced ON even in Stop mode. + 0x1 + + + + + HSIRDY + HSI16 clock ready flag +Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. +Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. + 10 + 1 + read-only + + + B_0x0 + HSI16 oscillator not ready + 0x0 + + + B_0x1 + HSI16 oscillator ready + 0x1 + + + + + HSIASFS + HSI16 automatic start from Stop +Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI16 is parallel of the system wake-up. + 11 + 1 + read-only + + + B_0x0 + HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wake-up clock. + 0x0 + + + B_0x1 + HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wake-up clock. + 0x1 + + + + + HSEON + HSE clock enable +Set and cleared by software. +Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + HSE clock ready flag +Set by hardware to indicate that the HSE oscillator is stable. +Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + HSEBYP + HSE crystal oscillator bypass +Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + 18 + 1 + read-write + + + B_0x0 + HSE crystal oscillator not bypassed + 0x0 + + + B_0x1 + HSE crystal oscillator bypassed with external clock + 0x1 + + + + + CSSON + Clock security system enable +Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. + 19 + 1 + read-write + + + B_0x0 + Clock security system OFF (clock detector OFF) + 0x0 + + + B_0x1 + Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + PLLON + PLL enable +Set and cleared by software to enable the PLL. +Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. + 24 + 1 + read-write + + + B_0x0 + PLL OFF + 0x0 + + + B_0x1 + PLL ON + 0x1 + + + + + PLLRDY + PLL clock ready flag +Set by hardware to indicate that the PLL is locked. + 25 + 1 + read-only + + + B_0x0 + PLL unlocked + 0x0 + + + B_0x1 + PLL locked + 0x1 + + + + + + + RCC_ICSCR + RCC_ICSCR + Internal clock sources calibration register + 0x04 + 0x20 + 0x40004000 + 0xFF00FF00 + + + MSICAL + MSI clock calibration +These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. + 0 + 8 + read-only + + + MSITRIM + MSI clock trimming +These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. + 8 + 8 + read-write + + + HSICAL + HSI16 clock calibration +These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + 16 + 8 + read-only + + + HSITRIM + HSI16 clock trimming +These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. +The default value is 64 when added to the HSICAL value, trim the HSI16 to 161MHz 1 11%. + 24 + 7 + read-write + + + + + RCC_CFGR + RCC_CFGR + Clock configuration register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SW + System clock switch +This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: +Others: Reserved +The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. + 0 + 3 + read-write + + + B_0x0 + MSI + 0x0 + + + B_0x1 + HSI16 + 0x1 + + + B_0x2 + HSE + 0x2 + + + B_0x3 + PLLRCLK + 0x3 + + + B_0x4 + LSI + 0x4 + + + B_0x5 + LSE + 0x5 + + + + + SWS + System clock switch status +This bitfield is controlled by hardware to indicate the clock source used as system clock: +Others: Reserved + 3 + 3 + read-only + + + B_0x0 + MSI + 0x0 + + + B_0x1 + HSI16 + 0x1 + + + B_0x2 + HSE + 0x2 + + + B_0x3 + PLLRCLK + 0x3 + + + B_0x4 + LSI + 0x4 + + + B_0x5 + LSE + 0x5 + + + + + HPRE + AHB prescaler +This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: +0xxx: 1 +Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. + 8 + 4 + read-write + + + B_0x8 + 2 + 0x8 + + + B_0x9 + 4 + 0x9 + + + B_0xA + 8 + 0xA + + + B_0xB + 16 + 0xB + + + B_0xC + 64 + 0xC + + + B_0xD + 128 + 0xD + + + B_0xE + 256 + 0xE + + + B_0xF + 512 + 0xF + + + + + PPRE + APB prescaler +This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: +0xx: 1 + 12 + 3 + read-write + + + B_0x4 + 2 + 0x4 + + + B_0x5 + 4 + 0x5 + + + B_0x6 + 8 + 0x6 + + + B_0x7 + 16 + 0x7 + + + + + STOPWUCK + Wake-up from Stop and CSS backup clock selection +Set and cleared by software to select the system clock used when exiting Stop mode. +The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10). + 15 + 1 + read-write + + + B_0x0 + MSI oscillator selected as wake-up from stop clock and CSS backup clock. + 0x0 + + + B_0x1 + HSI16 oscillator selected as wake-up from stop clock and CSS backup clock + 0x1 + + + + + MCO2SEL + Microcontroller clock output 2 clock selector +This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. + 16 + 4 + read-write + + + B_0x0 + no clock, MCO2 output disabled + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + MSI + 0x2 + + + B_0x3 + HSI16 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x5 + PLLRCLK + 0x5 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSI48 + 0x8 + + + B_0x9 + RTCCLK + 0x9 + + + B_0xA + RTC WAKEUP + 0xA + + + + + MCO2PRE + Microcontroller clock output 2 prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: +... +Others: reserved +It is highly recommended to set this field before the MCO2 output is enabled. + 20 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + MCOSEL + Microcontroller clock output clock selector +This bitfield is controlled by software. It sets the clock selector for MCO output as follows: +Others: Reserved +Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. + 24 + 4 + read-write + + + B_0x0 + no clock, MCO output disabled + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + MSI + 0x2 + + + B_0x3 + HSI16 + 0x3 + + + B_0x4 + HSE + 0x4 + + + B_0x5 + PLLRCLK + 0x5 + + + B_0x6 + LSI + 0x6 + + + B_0x7 + LSE + 0x7 + + + B_0x8 + HSI48 + 0x8 + + + B_0x9 + RTCCLK + 0x9 + + + B_0xA + RTC WAKEUP + 0xA + + + + + MCOPRE + Microcontroller clock output prescaler +This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: +... +Others: reserved +It is highly recommended to set this field before the MCO output is enabled. + 28 + 4 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x7 + 128 + 0x7 + + + B_0x8 + 256 + 0x8 + + + B_0x9 + 512 + 0x9 + + + B_0xA + 1024 + 0xA + + + + + + + RCC_PLLCFGR + RCC_PLLCFGR + PLL configuration register + 0x0C + 0x20 + 0x00001000 + 0xFFFFFFFF + + + PLLSRC + PLL input clock source +This bit is controlled by software to select PLL clock source, as follows: +The bitfield can be written only when the PLL is disabled. +When the PLL is not used, selecting 00 allows saving power. + 0 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + MSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + HSE + 0x3 + + + + + PLLM + Division factor M of the PLL input clock divider +This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: +The bitfield can be written only when the PLL is disabled. +Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz. + 4 + 3 + read-write + + + B_0x0 + 1 + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + PLLN + PLL frequency multiplication factor N +This bit is controlled by software to set the division factor of the f<sub>VCO</sub> feedback divider (that determines the PLL multiplication ratio) as follows: +... +... +The bitfield can be written only when the PLL is disabled. +Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz. + 8 + 7 + read-write + + + B_0x0 + Invalid + 0x0 + + + B_0x4 + 4 + 0x4 + + + B_0x5 + 5 + 0x5 + + + B_0x7E + 126 + 0x7E + + + B_0x7F + 127 + 0x7F + + + + + PLLPEN + PLLPCLK clock output enable +This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: +Disabling the PLLPCLK clock output, when not used, allows saving power. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLP + PLL VCO division factor P for PLLPCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: +... +The bitfield can be written only when the PLL is disabled. +Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + 17 + 5 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x1F + 32 + 0x1F + + + + + PLLQEN + PLLQCLK clock output enable +This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: +Disabling the PLLQCLK clock output, when not used, allows saving power. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLQ + PLL VCO division factor Q for PLLQCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: +The bitfield can be written only when the PLL is disabled. +Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. + 25 + 3 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + PLLREN + PLLRCLK clock output enable +This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: +This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. +Disabling the PLLRCLK clock output, when not used, allows saving power. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLR + PLL VCO division factor R for PLLRCLK clock output +This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: +The bitfield can be written only when the PLL is disabled. +The PLLRCLK clock can be selected as system clock. +Caution: The software must set this bitfield so as not to exceed 122MHz on this clock. + 29 + 3 + read-write + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 3 + 0x2 + + + B_0x3 + 4 + 0x3 + + + B_0x4 + 5 + 0x4 + + + B_0x5 + 6 + 0x5 + + + B_0x6 + 7 + 0x6 + + + B_0x7 + 8 + 0x7 + + + + + + + RCC_CIER + RCC_CIER + Clock interrupt enable register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + MSIRDYIE + MSI ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. + 2 + 1 + read-write + + + B_0x0 + MSI ready interrupt disabled + 0x0 + + + B_0x1 + MSI ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI16 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization: + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PLLRDYIE + PLL ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by PLL lock: + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSIE + LSE clock security system interrupt enable +Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. + 9 + 1 + read-write + + + B_0x0 + Clock security interrupt caused by LSE clock failure disabled + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable +Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. + 10 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + Clock interrupt flag register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag +Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. +Cleared by software setting the LSIRDYC bit. + 0 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSI oscillator + 0x1 + + + + + LSERDYF + LSE ready interrupt flag +Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. +Cleared by software setting the LSERDYC bit. + 1 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + MSIRDYF + MSI ready interrupt flag +Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. +Cleared by software setting the MSIRDYC bit. + 2 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the MSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the MSI oscillator + 0x1 + + + + + HSIRDYF + HSI16 ready interrupt flag +Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. +Cleared by software setting the HSIRDYC bit. + 3 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI16 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI16 oscillator + 0x1 + + + + + HSERDYF + HSE ready interrupt flag +Set by hardware when the HSE clock becomes stable and HSERDYIE is set. +Cleared by software setting the HSERDYC bit. + 4 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + PLLRDYF + PLL ready interrupt flag +Set by hardware when the PLL locks and PLLRDYIE is set. +Cleared by software setting the PLLRDYC bit. + 5 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by PLL lock + 0x0 + + + B_0x1 + Clock ready interrupt caused by PLL lock + 0x1 + + + + + CSSF + HSE clock security system interrupt flag +Set by hardware when a failure is detected in the HSE oscillator. +Cleared by software setting the CSSC bit. + 8 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by HSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by HSE clock failure + 0x1 + + + + + LSECSSF + LSE clock security system interrupt flag +Set by hardware when a failure is detected in the LSE oscillator. +Cleared by software by setting the LSECSSC bit. + 9 + 1 + read-only + + + B_0x0 + No clock security interrupt caused by LSE clock failure + 0x0 + + + B_0x1 + Clock security interrupt caused by LSE clock failure + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag +Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)). +Cleared by software setting the HSI48RDYC bit. + 10 + 1 + read-only + + + B_0x0 + No clock ready interrupt caused by the HSI48 oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + + + RCC_CICR + RCC_CICR + Clock interrupt clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear +This bit is set by software to clear the LSIRDYF flag. + 0 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSIRDYF flag + 0x1 + + + + + LSERDYC + LSE ready interrupt clear +This bit is set by software to clear the LSERDYF flag. + 1 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSERDYF flag + 0x1 + + + + + MSIRDYC + MSI ready interrupt clear +This bit is set by software to clear the MSIRDYF flag. + 2 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + MSIRDYF cleared + 0x1 + + + + + HSIRDYC + HSI16 ready interrupt clear +This bit is set software to clear the HSIRDYF flag. + 3 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSIRDYF flag + 0x1 + + + + + HSERDYC + HSE ready interrupt clear +This bit is set by software to clear the HSERDYF flag. + 4 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear HSERDYF flag + 0x1 + + + + + PLLRDYC + PLL ready interrupt clear +This bit is set by software to clear the PLLRDYF flag. + 5 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear PLLRDYF flag + 0x1 + + + + + CSSC + Clock security system interrupt clear +This bit is set by software to clear the HSECSSF flag. + 8 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear CSSF flag + 0x1 + + + + + LSECSSC + LSE Clock security system interrupt clear +This bit is set by software to clear the LSECSSF flag. + 9 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear LSECSSF flag + 0x1 + + + + + HSI48RDYC + HSI48 oscillator ready interrupt clear +This bit is set by software to clear the HSI48RDYF flag. + 10 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear the HSI48RDYC flag + 0x1 + + + + + + + RCC_AHBRSTR + RCC_AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1RST + DMA1 and DMAMUX reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA1 and DMAMUX + 0x1 + + + + + DMA2RST + DMA2 and DMAMUX reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DMA2 and DMAMUX + 0x1 + + + + + FLASHRST + Flash memory interface reset +Set and cleared by software. +This bit can only be set when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset flash memory interface + 0x1 + + + + + CRCRST + CRC reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRC + 0x1 + + + + + AESRST + AES hardware accelerator reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset AES + 0x1 + + + + + RNGRST + Random number generator reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset RNG + 0x1 + + + + + TSCRST + Touch sensing controller reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TSC + 0x1 + + + + + + + RCC_IOPRSTR + RCC_IOPRSTR + I/O port reset register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + I/O port A reset +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port A + 0x1 + + + + + GPIOBRST + I/O port B reset +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port B + 0x1 + + + + + GPIOCRST + I/O port C reset +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port C + 0x1 + + + + + GPIODRST + I/O port D reset +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port D + 0x1 + + + + + GPIOERST + I/O port E reset +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port E + 0x1 + + + + + GPIOFRST + I/O port F reset +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Reset I/O port F + 0x1 + + + + + + + RCC_APBRSTR1 + RCC_APBRSTR1 + APB peripheral reset register 1 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 timer reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM2 + 0x1 + + + + + TIM3RST + TIM3 timer reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM3 + 0x1 + + + + + TIM6RST + TIM6 timer reset +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM6 + 0x1 + + + + + TIM7RST + TIM7 timer reset +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM7 + 0x1 + + + + + LPUART2RST + LPUART2 reset +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART2 + 0x1 + + + + + LCDRST + LCD reset<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LCD + 0x1 + + + + + LPUART3RST + LPUART3 reset<sup>(1)</sup> +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART3 + 0x1 + + + + + USBRST + USB reset<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USB + 0x1 + + + + + SPI2RST + SPI2 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI2 + 0x1 + + + + + SPI3RST + SPI3 reset<sup>(1)</sup> +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI3 + 0x1 + + + + + CRSRST + CRS reset<sup>(1)</sup> +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset CRS + 0x1 + + + + + USART2RST + USART2 reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART2 + 0x1 + + + + + USART3RST + USART3 reset +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART3 + 0x1 + + + + + USART4RST + USART4 reset +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART4 + 0x1 + + + + + LPUART1RST + LPUART1 reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPUART1 + 0x1 + + + + + I2C1RST + I2C1 reset +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C1 + 0x1 + + + + + I2C2RST + I2C2 reset +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C2 + 0x1 + + + + + I2C3RST + I2C3 reset +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C3 + 0x1 + + + + + OPAMPRST + OPAMP reset +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset the OPAMP + 0x1 + + + + + I2C4RST + I2C4 reset<sup>(1)</sup> +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset I2C4 + 0x1 + + + + + LPTIM3RST + LPTIM3 reset +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM3 + 0x1 + + + + + PWRRST + Power interface reset +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset PWR + 0x1 + + + + + DAC1RST + DAC1 interface reset +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DAC1 interface + 0x1 + + + + + LPTIM2RST + Low Power Timer 2 reset +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM2 + 0x1 + + + + + LPTIM1RST + Low Power Timer 1 reset +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset LPTIM1 + 0x1 + + + + + + + RCC_APBRSTR2 + RCC_APBRSTR2 + APB peripheral reset register 2 + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGRST + SYSCFG, COMP and VREFBUF reset +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SYSCFG + COMP + VREFBUF + 0x1 + + + + + TIM1RST + TIM1 timer reset +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM1 timer + 0x1 + + + + + SPI1RST + SPI1 reset +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset SPI1 + 0x1 + + + + + USART1RST + USART1 reset +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset USART1 + 0x1 + + + + + TIM15RST + TIM15 timer reset +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM15 timer + 0x1 + + + + + TIM16RST + TIM16 timer reset +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset TIM16 timer + 0x1 + + + + + ADCRST + ADC reset +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset ADC + 0x1 + + + + + + + RCC_AHBENR + RCC_AHBENR + AHB peripheral clock enable register + 0x48 + 0x20 + 0x00000100 + 0xFFFFFFFF + + + DMA1EN + DMA1 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMA2EN + DMA2 and DMAMUX clock enable +Set and cleared by software. +DMAMUX is enabled as long as at least one DMA peripheral is enabled. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHEN + Flash memory interface clock enable +Set and cleared by software. +This bit can only be cleared when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCEN + CRC clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + AESEN + AES hardware accelerator +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RNGEN + Random number generator clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TSCEN + Touch sensing controller clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + TSC clock disable + 0x0 + + + B_0x1 + TSC clock enable + 0x1 + + + + + + + RCC_IOPENR + RCC_IOPENR + I/O port clock enable register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + GPIOAEN + I/O port A clock enable +This bit is set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBEN + I/O port B clock enable +This bit is set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCEN + I/O port C clock enable +This bit is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODEN + I/O port D clock enable +This bit is set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOEEN + I/O port E clock enable<sup>(1)</sup> +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFEN + I/O port F clock enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_DBGCFGR + RCC_DBGCFGR + Debug configuration register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DBGEN + Debug support clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DBGRST + Debug support reset +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset DBG + 0x1 + + + + + + + RCC_APBENR1 + RCC_APBENR1 + APB peripheral clock enable register 1 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 timer clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3EN + TIM3 timer clock enable +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM6EN + TIM6 timer clock enable +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM7EN + TIM7 timer clock enable +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART2EN + LPUART2 clock enable +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LCDEN + LCD clock enable<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBEN + RTC APB clock enable +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGEN + WWDG clock enable +Set by software to enable the window watchdog clock. Cleared by hardware system reset +This bit can also be set by hardware if the WWDG_SW option bit is 0. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART3EN + LPUART3 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBEN + USB clock enable<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2EN + SPI2 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI3EN + SPI3 clock enable<sup>(1)</sup> +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRSEN + CRS clock enable<sup>(1)</sup> +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2EN + USART2 clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART3EN + USART3 clock enable +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART4EN + USART4 clock enable +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART1EN + LPUART1 clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2EN + I2C2 clock enable +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3EN + I2C3 clock enable +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OPAMPEN + OPAMP clock enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C4EN + I2C4EN clock enable<sup>(1)</sup> +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM3EN + LPTIM3 clock enable +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWREN + Power interface clock enable +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DAC1EN + DAC1 interface clock enable +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM2EN + LPTIM2 clock enable +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM1EN + LPTIM1 clock enable +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBENR2 + RCC_APBENR2 + APB peripheral clock enable register 2 + 0x60 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock enable +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1EN + TIM1 timer clock enable +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1EN + SPI1 clock enable +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1EN + USART1 clock enable +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM15EN + TIM15 timer clock enable +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16EN + TIM16 timer clock enable +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCEN + ADC clock enable +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_AHBSMENR + RCC_AHBSMENR + AHB peripheral clock enable in Sleep/Stop mode register + 0x68 + 0x20 + 0x01051303 + 0xFFFFFFFF + + + DMA1SMEN + DMA1 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMA2SMEN + DMA2 and DMAMUX clock enable during Sleep mode +Set and cleared by software. +Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FLASHSMEN + Flash memory interface clock enable during Sleep mode +Set and cleared by software. +This bit can be activated only when the flash memory is in power down mode. + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SRAMSMEN + SRAM clock enable during Sleep mode +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRCSMEN + CRC clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + AESSMEN + AES hardware accelerator clock enable during Sleep mode +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RNGSMEN + RNG clock enable during Sleep and Stop mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TSCSMEN + TSC clock enable during Sleep and Stop mode +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_IOPSMENR + RCC_IOPSMENR + I/O port in Sleep mode clock enable register + 0x6C + 0x20 + 0x0000003F + 0xFFFFFFFF + + + GPIOASMEN + I/O port A clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOBSMEN + I/O port B clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOCSMEN + I/O port C clock enable during Sleep mode +Set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIODSMEN + I/O port D clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOESMEN + I/O port E clock enable during Sleep mode +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GPIOFSMEN + I/O port F clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR1 + RCC_APBSMENR1 + APB peripheral clock enable in Sleep/Stop mode register 1 + 0x78 + 0x20 + 0xFF7E4C33 + 0xFFFFFFFF + + + TIM2SMEN + TIM2 timer clock enable during Sleep mode +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM3SMEN + TIM3 timer clock enable during Sleep mode +Set and cleared by software. + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM6SMEN + TIM6 timer clock enable during Sleep mode +Set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM7SMEN + TIM7 timer clock enable during Sleep mode +Set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART2SMEN + LPUART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LCDSMEN + LCD clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RTCAPBSMEN + RTC APB clock enable during Sleep mode +Set and cleared by software. + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + WWDGSMEN + WWDG clock enable during Sleep and Stop modes +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART3SMEN + LPUART3 clock enable during Sleep and Stop modes +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USBSMEN + USB clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI2SMEN + SPI2 clock enable during Sleep mode +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI3SMEN + SPI3 clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + CRSSMEN + CRS clock enable during Sleep and Stop modes<sup>(1)</sup> +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART2SMEN + USART2 clock enable during Sleep and Stop modes +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART3SMEN + USART3 clock enable during Sleep mode +Set and cleared by software. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART4SMEN + USART4 clock enable during Sleep mode +Set and cleared by software. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPUART1SMEN + LPUART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C1SMEN + I2C1 clock enable during Sleep and Stop modes +Set and cleared by software. + 21 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C2SMEN + I2C2 clock enable during Sleep mode +Set and cleared by software. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3SMEN + I2C3 clock enable during Sleep mode +Set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + OPAMPSMEN + OPAMP clock enable during Sleep and Stop modes +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C4SMEN + I2C4 clock enable during Sleep mode<sup>(1)</sup> +Set and cleared by software. + 25 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM3SMEN + Low power timer 3 clock enable during Sleep mode +Set and cleared by software. + 26 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PWRSMEN + Power interface clock enable during Sleep mode +Set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DAC1SMEN + DAC1 interface clock enable during Sleep and Stop modes +Set and cleared by software. + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM2SMEN + Low Power Timer 2 clock enable during Sleep and Stop modes +Set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LPTIM1SMEN + Low Power Timer 1 clock enable during Sleep and Stop modes +Set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_APBSMENR2 + RCC_APBSMENR2 + APB peripheral clock enable in Sleep/Stop mode register 2 + 0x80 + 0x20 + 0x0017D801 + 0xFFFFFFFF + + + SYSCFGSMEN + SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes +Set and cleared by software. + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM1SMEN + TIM1 timer clock enable during Sleep mode +Set and cleared by software. + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + SPI1SMEN + SPI1 clock enable during Sleep mode +Set and cleared by software. + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + USART1SMEN + USART1 clock enable during Sleep and Stop modes +Set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM15SMEN + TIM15 timer clock enable during Sleep mode +Set and cleared by software. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TIM16SMEN + TIM16 timer clock enable during Sleep mode +Set and cleared by software. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + ADCSMEN + ADC clock enable during Sleep mode +Set and cleared by software. + 20 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + RCC_CCIPR + RCC_CCIPR + Peripherals independent clock configuration register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 clock source selection +This bitfield is controlled by software to select USART1 clock source as follows: + 0 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + USART2SEL + USART2 clock source selection +This bitfield is controlled by software to select USART2 clock source as follows: + 2 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART3SEL + LPUART3 clock source selection<sup>(1)</sup> +This bitfield is controlled by software to select LPUART3 clock source as follows: + 6 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART2SEL + LPUART2 clock source selection +This bitfield is controlled by software to select LPUART2 clock source as follows: + 8 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPUART1SEL + LPUART1 clock source selection +This bitfield is controlled by software to select LPUART1 clock source as follows: + 10 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + I2C1SEL + I2C1 clock source selection +This bitfield is controlled by software to select I2C1 clock source as follows: + 12 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + I2C3SEL + I2C3 clock source selection +This bitfield is controlled by software to select I2C3 clock source as follows: + 16 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + SYSCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + LPTIM1SEL + LPTIM1 clock source selection +This bitfield is controlled by software to select LPTIM1 clock source as follows: + 18 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPTIM2SEL + LPTIM2 clock source selection +This bitfield is controlled by software to select LPTIM2 clock source as follows: + 20 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + LPTIM3SEL + LPTIM3 clock source selection +This bitfield is controlled by software to select LPTIM3 clock source as follows: + 22 + 2 + read-write + + + B_0x0 + PCLK + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + B_0x3 + LSE + 0x3 + + + + + TIM1SEL + TIM1 clock source selection +This bit is set and cleared by software. It selects TIM1 clock source as follows: + 24 + 1 + read-write + + + B_0x0 + TIMPCLK + 0x0 + + + B_0x1 + PLLQCLK + 0x1 + + + + + TIM15SEL + TIM15 clock source selection +This bit is set and cleared by software. It selects TIM15 clock source as follows: + 25 + 1 + read-write + + + B_0x0 + TIMPCLK + 0x0 + + + B_0x1 + PLLQCLK + 0x1 + + + + + CLK48SEL + 481MHz clock source selection +This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG: + 26 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + MSI + 0x1 + + + B_0x2 + PLLQCLK + 0x2 + + + B_0x3 + HSI48<sup>(1)</sup> + 0x3 + + + + + ADCSEL + ADCs clock source selection +This bitfield is controlled by software to select the clock source for ADC: + 28 + 2 + read-write + + + B_0x0 + System clock + 0x0 + + + B_0x1 + PLLPCLK + 0x1 + + + B_0x2 + HSI16 + 0x2 + + + + + + + RCC_BDCR + RCC_BDCR + RTC domain control register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enable +Set and cleared by software to enable LSE oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSERDY + LSE oscillator ready +Set and cleared by hardware to indicate when the external 321kHz oscillator is ready (stable): +After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass +Set and cleared by software to bypass the LSE oscillator (in debug mode). +This bit can be written only when the external 321kHz oscillator is disabled (LSEON=0 and LSERDY=0). + 2 + 1 + read-write + + + B_0x0 + Not bypassed + 0x0 + + + B_0x1 + Bypassed + 0x1 + + + + + LSEDRV + LSE oscillator drive capability +Set by software to select the LSE oscillator drive capability as follows: +Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. + 3 + 2 + read-write + + + B_0x0 + low driving capability + 0x0 + + + B_0x1 + medium-low driving capability + 0x1 + + + B_0x2 + medium-high driving capability + 0x2 + + + B_0x3 + high driving capability + 0x3 + + + + + LSECSSON + CSS on LSE enable +Set by software to enable the clock security system on LSE (321kHz) oscillator as follows: +LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. +Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD +=1). In that case the software must disable the LSECSSON bit. + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSECSSD + CSS on LSE failure Detection +Set by hardware to indicate when a failure is detected by the clock security system +on the external 321kHz oscillator (LSE): + 6 + 1 + read-only + + + B_0x0 + No failure detected + 0x0 + + + B_0x1 + Failure detected + 0x1 + + + + + LSESYSEN + LSE clock enable for system usage +This bit must be set by software to enable the LSE clock for a system usage. + 7 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enabled, LSE distributed to peripherals including LSCO/MCO/SYSCLK. + 0x1 + + + + + RTCSEL + RTC clock source selection +Set by software to select the clock source for the RTC as follows: +Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00. + 8 + 2 + read-write + + + B_0x0 + No clock + 0x0 + + + B_0x1 + LSE + 0x1 + + + B_0x2 + LSI + 0x2 + + + B_0x3 + HSE divided by 32 + 0x3 + + + + + LSESYSRDY + LSE clock ready for system usage +This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON1=11 and LSERDY1=11) and two LSE clock cycles after that LSESYSEN is set. +Cleared by hardware to indicate that the LSE clock is not ready to be used by the system. + 11 + 1 + read-only + + + B_0x0 + LSE clock not ready for system + 0x0 + + + B_0x1 + LSE clock ready for system + 0x1 + + + + + RTCEN + RTC clock enable +Set and cleared by software. The bit enables clock to RTC and TAMP. + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + BDRST + RTC domain software reset +Set and cleared by software to reset the RTC domain: + 16 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Reset + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable +Set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSCOSEL + Low-speed clock output selection +Set and cleared by software to select the low-speed output clock: + 25 + 1 + read-write + + + B_0x0 + LSI + 0x0 + + + B_0x1 + LSE + 0x1 + + + + + + + RCC_CSR + RCC_CSR + Control/status register + 0x94 + 0x20 + 0x00000000 + 0x00FFFFFF + + + LSION + LSI oscillator enable +Set and cleared by software to enable/disable the LSI oscillator: + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + LSIRDY + LSI oscillator ready +Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): +After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. + 1 + 1 + read-only + + + B_0x0 + Not ready + 0x0 + + + B_0x1 + Ready + 0x1 + + + + + LSIPREDIV + Internal low-speed oscillator pre-divided by 128 +Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit. + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator is not divided + 0x0 + + + B_0x1 + LSI RC oscillator is divided by 128 + 0x1 + + + + + MSISRANGE + MSI range after Standby mode +Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 41MHz. MSISRANGE[3:0] can be written only when MSIRGSEL1=11. +Others: Reserved +Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency. + 8 + 4 + read-write + + + B_0x4 + Range 7 around 81MHz + 0x4 + + + + + RMVF + Remove reset flags +Set by software to clear the reset flags. + 23 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clear reset flags + 0x1 + + + + + OBLRSTF + Option byte loader reset flag +Set by hardware when a reset from the Option byte loading occurs. +Cleared by setting the RMVF bit. + 25 + 1 + read-only + + + B_0x0 + No reset from Option byte loading occurred + 0x0 + + + B_0x1 + Reset from Option byte loading occurred + 0x1 + + + + + PINRSTF + Pin reset flag +Set by hardware when a reset from the NRST pin occurs. +Cleared by setting the RMVF bit. + 26 + 1 + read-only + + + B_0x0 + No reset from NRST pin occurred + 0x0 + + + B_0x1 + Reset from NRST pin occurred + 0x1 + + + + + PWRRSTF + BOR or POR/PDR flag +Set by hardware when a BOR or POR/PDR occurs. +Cleared by setting the RMVF bit. + 27 + 1 + read-only + + + B_0x0 + No BOR or POR occurred + 0x0 + + + B_0x1 + BOR or POR occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Set by hardware when a software reset occurs. +Cleared by setting the RMVF bit. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + IWDGRSTF + Independent window watchdog reset flag +Set by hardware when an independent watchdog reset domain occurs. +Cleared by setting the RMVF bit. + 29 + 1 + read-only + + + B_0x0 + No independent watchdog reset occurred + 0x0 + + + B_0x1 + Independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + Window watchdog reset flag +Set by hardware when a window watchdog reset occurs. +Cleared by setting the RMVF bit. + 30 + 1 + read-only + + + B_0x0 + No window watchdog reset occurred + 0x0 + + + B_0x1 + Window watchdog reset occurred + 0x1 + + + + + LPWRRSTF + Low-power reset flag +Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. +Cleared by setting the RMVF bit. +This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared. + 31 + 1 + read-only + + + B_0x0 + No illegal mode reset occurred + 0x0 + + + B_0x1 + Illegal mode reset occurred + 0x1 + + + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x98 + 0x20 + 0x00008800 + 0x0000FFFF + + + HSI48ON + HSI48 RC oscillator enable<sup>(1)</sup> + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag<sup>(1)</sup> +The flag is set when the HSI48 clock is ready for use. + 1 + 1 + read-only + + + HSI48CAL + HSI48 clock calibration +These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + 7 + 9 + read-only + + + + + + + RNG + RNG address block description + RNG + 0x40025000 + + 0x0 + 0x14 + registers + + + + RNG_CR + RNG_CR + RNG control register + 0x000 + 0x20 + 0x00800D00 + 0xFFFFFFFF + + + RNGEN + True random number generator enable + 2 + 1 + read-write + + + B_0x0 + True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. + 0x0 + + + B_0x1 + True random number generator is enabled. + 0x1 + + + + + IE + Interrupt enable + 3 + 1 + read-write + + + B_0x0 + RNG interrupt is disabled + 0x0 + + + B_0x1 + RNG interrupt is enabled. An interrupt is pending as soon as DRDY1=11, SEIS1=11 or CEIS1=11 in the RNG_SR register. + 0x1 + + + + + CED + Clock error detection +The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED, the RNG must be disabled. +Writing this bit is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 5 + 1 + read-write + + + B_0x0 + Clock error detection enabled + 0x0 + + + B_0x1 + Clock error detection is disabled + 0x1 + + + + + ARDIS + Auto reset disable +When auto-reset is enabled the application still need to clear the SEIS bit after a noise source error. +Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 7 + 1 + read-write + + + B_0x0 + When a noise source error occurs RNG performs an automatic reset to clear the SECS bit. + 0x0 + + + B_0x1 + When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation. + 0x1 + + + + + RNG_CONFIG3 + RNG configuration 3 +Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. +If the NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG. + 8 + 4 + read-write + + + NISTC + NIST custom +two conditioning loops are performed and 256 bits of noise source are used. +Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 12 + 1 + read-write + + + B_0x0 + Hardware default values for NIST compliant RNG. In this configuration per 128-bit output + 0x0 + + + B_0x1 + Custom values for NIST compliant RNG. See Section120.6: RNG entropy source validation for proposed configuration. + 0x1 + + + + + RNG_CONFIG2 + RNG configuration 2 +Reserved to the RNG configuration (bitfield 2). Bit 13 can be set when RNG power consumption is critical. See Section120.3.8: RNG low-power use. Refer to the RNG_CONFIG1 bitfield for details. + 13 + 3 + read-write + + + CLKDIV + Clock divider factor +This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN1=10). +... +Writing these bits is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 16 + 4 + read-write + + + B_0x0 + internal RNG clock after divider is similar to incoming RNG clock. + 0x0 + + + B_0x1 + two RNG clock cycles per internal RNG clock. + 0x1 + + + B_0x2 + 2<sup>2</sup> (= 4) RNG clock cycles per internal RNG clock. + 0x2 + + + B_0xF + 2<sup>15</sup> RNG clock cycles per internal clock (for example. an incoming 481MHz RNG clock becomes a 1.51kHz internal RNG clock) + 0xF + + + + + RNG_CONFIG1 + RNG configuration 1 +Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section120.6: RNG entropy source validation. +Writing any bit of RNG_CONFIG1 is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11. + 20 + 6 + read-write + + + CONDRST + Conditioning soft reset +Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_HTCR are not changed by CONDRST. +This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. +When CONDRST is set to 0 by the software, its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles. + 30 + 1 + read-write + + + CONFIGLOCK + RNG Config lock +This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset. + 31 + 1 + read-write + + + B_0x0 + Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. + 0x0 + + + B_0x1 + Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG status register + 0x004 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DRDY + Data ready +Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. +Note: The DRDY bit can rise when the peripheral is disabled (RNGEN1=10 in the RNG_CR register). +If IE=1 in the RNG_CR register, an interrupt is generated when DRDY1=11. + 0 + 1 + read-only + + + B_0x0 + The RNG_DR register is not yet valid, no random data is available. + 0x0 + + + B_0x1 + The RNG_DR register contains valid random data. + 0x1 + + + + + CECS + Clock error current status +Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0. + 1 + 1 + read-only + + + B_0x0 + The RNG clock is correct (f<sub>RNGCLK</sub>> f<sub>HCLK</sub>/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered. + 0x0 + + + B_0x1 + The RNG clock is too slow (f<sub>RNGCLK</sub>< f<sub>HCLK</sub>/32). + 0x1 + + + + + SECS + Seed error current status +Runtime repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) +Startup or continuous adaptive proportion test on noise source failed. +Startup post-processing/conditioning sanity check failed. + 2 + 1 + read-only + + + B_0x0 + No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. + 0x0 + + + B_0x1 + At least one of the following faulty sequences has been detected: + 0x1 + + + + + CEIS + Clock error interrupt status +This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 5 + 1 + read-write + + + B_0x0 + The RNG clock is correct (f<sub>RNGCLK</sub>> f<sub>HCLK</sub>/32) + 0x0 + + + B_0x1 + The RNG clock before the internal divider is detected too slow (f<sub>RNGCLK</sub>< f<sub>HCLK</sub>/32) + 0x1 + + + + + SEIS + Seed error interrupt status +This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. +An interrupt is pending if IE = 1 in the RNG_CR register. + 6 + 1 + read-write + + + B_0x0 + No faulty sequence detected + 0x0 + + + B_0x1 + At least one faulty sequence is detected. See SECS bit description for details. + 0x1 + + + + + + + RNG_DR + RNG_DR + RNG data register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNDATA + Random data +32-bit random data, which are valid when DRDY1=11. When DRDY1=10, the RNDATA value is1zero. +When DRDY is set, it is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event). + 0 + 32 + read-only + + + + + RNG_HTCR + RNG_HTCR + RNG health test control register + 0x010 + 0x20 + 0x000072AC + 0xFFFFFFFF + + + HTCFG + health test configuration +This configuration is used by RNG to configure the health tests. See Section120.6: RNG entropy source validation for the recommended value. +Note: The RNG behavior, including the read to this register, is not guaranteed if a different value from the recommended value is written. + 0 + 32 + read-write + + + + + + + RTC + RTC register block + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP + RTC and TAMP interrupts(combined EXTI lines 19 and 21) + 2 + + + + RTC_TR + RTC_TR + RTC time register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_DR + RTC_DR + RTC date register + 0x04 + 0x20 + 0x00002101 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-write + + + DT + Date tens in BCD format + 4 + 2 + read-write + + + MU + Month units in BCD format + 8 + 4 + read-write + + + MT + Month tens in BCD format + 12 + 1 + read-write + + + WDU + Week day units +... + 13 + 3 + read-write + + + B_0x0 + forbidden + 0x0 + + + B_0x1 + Monday + 0x1 + + + B_0x7 + Sunday + 0x7 + + + + + YU + Year units in BCD format + 16 + 4 + read-write + + + YT + Year tens in BCD format + 20 + 4 + read-write + + + + + RTC_SSR + RTC_SSR + RTC subsecond register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous binary counter +SS[31:16]: Synchronous binary counter MSB values +When Binary or Mixed mode is selected (BIN = 01 or 10 or 11): +SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter. +When BCD mode is selected (BIN=00): +SS[31:16] are forced by hardware to 0x0000. +SS[15:0]: Subsecond value/synchronous binary counter LSB values +When Binary mode is selected (BIN = 01 or 10 or 11): +SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter. +When BCD mode is selected (BIN=00): +SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: +Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) +SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. + 0 + 32 + read-only + + + + + RTC_ICSR + RTC_ICSR + RTC initialization control and status register + 0x0C + 0x20 + 0x00000007 + 0xFFFFFFFF + + + WUTWF + Wake-up timer write flag +This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. + 2 + 1 + read-only + + + B_0x0 + Wake-up timer configuration update not allowed except in initialization mode + 0x0 + + + B_0x1 + Wake-up timer configuration update allowed + 0x1 + + + + + SHPF + Shift operation pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-only + + + B_0x0 + No shift operation is pending + 0x0 + + + B_0x1 + A shift operation is pending + 0x1 + + + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). + 4 + 1 + read-only + + + B_0x0 + Calendar has not been initialized + 0x0 + + + B_0x1 + Calendar has been initialized + 0x1 + + + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. + 5 + 1 + read-write + + + B_0x0 + Calendar shadow registers not yet synchronized + 0x0 + + + B_0x1 + Calendar shadow registers synchronized + 0x1 + + + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. + 6 + 1 + read-only + + + B_0x0 + Calendar registers update is not allowed + 0x0 + + + B_0x1 + Calendar registers update is allowed + 0x1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + + B_0x0 + Free running mode + 0x0 + + + B_0x1 + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. Counters are stopped and start counting from the new value when INIT is reset. + 0x1 + + + + + BIN + Binary mode + 8 + 2 + read-write + + + B_0x0 + Free running BCD calendar mode (Binary mode disabled). + 0x0 + + + B_0x1 + Free running Binary mode (BCD mode disabled) + 0x1 + + + B_0x2 + Free running BCD calendar and Binary modes + 0x2 + + + B_0x3 + Free running BCD calendar and Binary modes + 0x3 + + + + + BCDU + BCD update (BIN = 10 or 11) +In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits. + 10 + 3 + read-write + + + B_0x0 + 1s calendar increment is generated each time SS[7:0] = 0 + 0x0 + + + B_0x1 + 1s calendar increment is generated each time SS[8:0] = 0 + 0x1 + + + B_0x2 + 1s calendar increment is generated each time SS[9:0] = 0 + 0x2 + + + B_0x3 + 1s calendar increment is generated each time SS[10:0] = 0 + 0x3 + + + B_0x4 + 1s calendar increment is generated each time SS[11:0] = 0 + 0x4 + + + B_0x5 + 1s calendar increment is generated each time SS[12:0] = 0 + 0x5 + + + B_0x6 + 1s calendar increment is generated each time SS[13:0] = 0 + 0x6 + + + B_0x7 + 1s calendar increment is generated each time SS[14:0] = 0 + 0x7 + + + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly. + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + RTC prescaler register + 0x10 + 0x20 + 0x007F00FF + 0xFFFFFFFF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC wake-up timer register + 0x14 + 0x20 + 0x0000FFFF + 0xFFFFFFFF + + + WUT + Wake-up auto-reload value bits +When the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]1+11) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. +When WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs between WUT and (WUT + 2) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + WUTOCLR + Wake-up auto-reload output clear value +When WUTOCLR[15:0] is different from 0x0000, WUTF is set by hardware when the auto-reload down-counter reaches 0 and is cleared by hardware when the auto-reload downcounter reaches WUTOCLR[15:0]. +When WUTOCLR[15:0] = 0x0000, WUTF is set by hardware when the WUT down-counter +reaches 0 and is cleared by software. + 16 + 16 + read-write + + + + + RTC_CR + RTC_CR + RTC control register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WUCKSEL + ck_wut wake-up clock selection +10x: ck_spre (usually 11Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. +11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 2<sup>16</sup> is added to the WUT counter value. + 0 + 3 + read-write + + + B_0x0 + RTC/16 clock is selected + 0x0 + + + B_0x1 + RTC/8 clock is selected + 0x1 + + + B_0x2 + RTC/4 clock is selected + 0x2 + + + B_0x3 + RTC/2 clock is selected + 0x3 + + + + + TSEDGE + Timestamp event active edge +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + B_0x0 + RTC_TS input rising edge generates a timestamp event + 0x0 + + + B_0x1 + RTC_TS input falling edge generates a timestamp event + 0x1 + + + + + REFCKON + RTC_REFIN reference clock detection enable (50 or 601Hz) +Note: BIN must be 0x00 and PREDIV_S must be 0x00FF. + 4 + 1 + read-write + + + B_0x0 + RTC_REFIN detection disabled + 0x0 + + + B_0x1 + RTC_REFIN detection enabled + 0x1 + + + + + BYPSHAD + Bypass the shadow registers +Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1. + 5 + 1 + read-write + + + B_0x0 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. + 0x0 + + + B_0x1 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 0x1 + + + + + FMT + Hour format + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + SSRUIE + SSR underflow interrupt enable + 7 + 1 + read-write + + + B_0x0 + SSR underflow interrupt disabled + 0x0 + + + B_0x1 + SSR underflow interrupt enabled + 0x1 + + + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + B_0x0 + Alarm A disabled + 0x0 + + + B_0x1 + Alarm A enabled + 0x1 + + + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + B_0x0 + Alarm B disabled + 0x0 + + + B_0x1 + Alarm B enabled + 0x1 + + + + + WUTE + Wake-up timer enable +Note: When the wake-up timer is disabled, wait for WUTWF = 1 before enabling it again. + 10 + 1 + read-write + + + B_0x0 + Wake-up timer disabled + 0x0 + + + B_0x1 + Wake-up timer enabled + 0x1 + + + + + TSE + timestamp enable + 11 + 1 + read-write + + + B_0x0 + timestamp disable + 0x0 + + + B_0x1 + timestamp enable + 0x1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + B_0x0 + Alarm A interrupt disabled + 0x0 + + + B_0x1 + Alarm A interrupt enabled + 0x1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + B_0x0 + Alarm B interrupt disable + 0x0 + + + B_0x1 + Alarm B interrupt enable + 0x1 + + + + + WUTIE + Wake-up timer interrupt enable + 14 + 1 + read-write + + + B_0x0 + Wake-up timer interrupt disabled + 0x0 + + + B_0x1 + Wake-up timer interrupt enabled + 0x1 + + + + + TSIE + Timestamp interrupt enable + 15 + 1 + read-write + + + B_0x0 + Timestamp interrupt disable + 0x0 + + + B_0x1 + Timestamp interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. + 16 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Adds 1 hour to the current time. This can be used for summer time change + 0x1 + + + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. + 17 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Subtracts 1 hour to the current time. This can be used for winter time change. + 0x1 + + + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE = 1, this bit selects which signal is output on CALIB. +These frequencies are valid for RTCCLK at 32.7681kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section128.3.16: Calibration clock output. + 19 + 1 + read-write + + + B_0x0 + Calibration output is 5121Hz + 0x0 + + + B_0x1 + Calibration output is 11Hz + 0x1 + + + + + POL + Output polarity +This bit is used to configure the polarity of TAMPALRM output. + 20 + 1 + read-write + + + B_0x0 + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x0 + + + B_0x1 + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x1 + + + + + OSEL + Output selection +These bits are used to select the flag to be routed to TAMPALRM output. + 21 + 2 + read-write + + + B_0x0 + Output disabled + 0x0 + + + B_0x1 + Alarm A output enabled + 0x1 + + + B_0x2 + Alarm B output enabled + 0x2 + + + B_0x3 + Wake-up output enabled + 0x3 + + + + + COE + Calibration output enable +This bit enables the CALIB output + 23 + 1 + read-write + + + B_0x0 + Calibration output disabled + 0x0 + + + B_0x1 + Calibration output enabled + 0x1 + + + + + ITSE + timestamp on internal event enable + 24 + 1 + read-write + + + B_0x0 + internal event timestamp disabled + 0x0 + + + B_0x1 + internal event timestamp enabled + 0x1 + + + + + TAMPTS + Activate timestamp on tamper detection event +TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. +Note: TAMPTS must be cleared before entering RTC initialization mode. + 25 + 1 + read-write + + + B_0x0 + Tamper detection event does not cause a RTC timestamp to be saved + 0x0 + + + B_0x1 + Save RTC timestamp on tamper detection event + 0x1 + + + + + TAMPOE + Tamper detection output enable on TAMPALRM + 26 + 1 + read-write + + + B_0x0 + The tamper flag is not routed on TAMPALRM + 0x0 + + + B_0x1 + The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. + 0x1 + + + + + ALRAFCLR + Alarm A flag automatic clear + 27 + 1 + read-write + + + B_0x0 + Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm A event generates a trigger event. ALRAF is automatically cleared by hardware after 1 ck_apre cycle. + 0x1 + + + + + ALRBFCLR + Alarm B flag automatic clear + 28 + 1 + read-write + + + B_0x0 + Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm B event generates a trigger event. ALRBF is automatically cleared by hardware after 1 ck_apre cycle. + 0x1 + + + + + TAMPALRM_PU + TAMPALRM pull-up enable + 29 + 1 + read-write + + + B_0x0 + No pull-up is applied on TAMPALRM output + 0x0 + + + B_0x1 + A pull-up is applied on TAMPALRM output + 0x1 + + + + + TAMPALRM_TYPE + TAMPALRM output type + 30 + 1 + read-write + + + B_0x0 + TAMPALRM is push-pull output + 0x0 + + + B_0x1 + TAMPALRM is open-drain output + 0x1 + + + + + OUT2EN + RTC_OUT2 output enable + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00. +Refer to RTC register write protection for a description of how to unlock RTC register write protection. + 0 + 8 + write-only + + + + + RTC_CALR + RTC_CALR + RTC calibration register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 2<sup>20</sup> RTCCLK pulses (321seconds if the input frequency is 327681Hz). This decreases the frequency of the calendar with a resolution of 0.95371ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section128.3.14: RTC smooth digital calibration on page1733. + 0 + 9 + read-write + + + LPCAL + RTC low-power mode + 12 + 1 + read-write + + + B_0x0 + Calibration window is 2<sup>20</sup> RTCCLK, which is a high-consumption mode. This mode must be set only when less than 32s calibration window is required. + 0x0 + + + B_0x1 + Calibration window is 2<sup>20</sup> ck_apre, which is the required configuration for ultra-low consumption mode. + 0x1 + + + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. +Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section128.3.14: RTC smooth digital calibration. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1, the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section128.3.14: RTC smooth digital calibration. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.51ppm. + 15 + 1 + read-write + + + B_0x0 + No RTCCLK pulses are added. + 0x0 + + + B_0x1 + One RTCCLK pulse is effectively inserted every 2<sup>11</sup> pulses (frequency increased by 488.51ppm). + 0x1 + + + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC shift control register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / (PREDIV_S + 1) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: +Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). +In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0. +Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time. + 0 + 15 + write-only + + + ADD1S + Add one second +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Add one second to the clock/calendar + 0x1 + + + + + + + RTC_TSTR + RTC_TSTR + RTC timestamp time register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-only + + + ST + Second tens in BCD format. + 4 + 3 + read-only + + + MNU + Minute units in BCD format. + 8 + 4 + read-only + + + MNT + Minute tens in BCD format. + 12 + 3 + read-only + + + HU + Hour units in BCD format. + 16 + 4 + read-only + + + HT + Hour tens in BCD format. + 20 + 2 + read-only + + + PM + AM/PM notation + 22 + 1 + read-only + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_TSDR + RTC_TSDR + RTC timestamp date register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-only + + + DT + Date tens in BCD format + 4 + 2 + read-only + + + MU + Month units in BCD format + 8 + 4 + read-only + + + MT + Month tens in BCD format + 12 + 1 + read-only + + + WDU + Week day units + 13 + 3 + read-only + + + + + RTC_TSSSR + RTC_TSSSR + RTC timestamp subsecond register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subsecond value/synchronous binary counter values +SS[31:0] is the value of the synchronous prescaler counter when the timestamp event occurred. + 0 + 32 + read-only + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC alarm A register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm A set if the seconds match + 0x0 + + + B_0x1 + Seconds dont care in alarm A comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm A set if the minutes match + 0x0 + + + B_0x1 + Minutes dont care in alarm A comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm A hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm A set if the hours match + 0x0 + + + B_0x1 + Hours dont care in alarm A comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is dont care. + 0x1 + + + + + MSK4 + Alarm A date mask + 31 + 1 + read-write + + + B_0x0 + Alarm A set if the date/day match + 0x0 + + + B_0x1 + Date/day dont care in alarm A comparison + 0x1 + + + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC alarm A subsecond register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. +This field is the mirror of SS[14:0] in the RTC_ALRABINR, and so can also be read or written through RTC_ALRABINR. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +From 32 to 63: All 32 SS bits are compared and must match to activate alarm. +Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[31:1] are dont care in Alarm A comparison. Only SS[0] is compared. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) +Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRABINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRABINR.SS[31:0]. + 0x1 + + + + + + + RTC_ALRMBR + RTC_ALRMBR + RTC alarm B register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MSK1 + Alarm B seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm B set if the seconds match + 0x0 + + + B_0x1 + Seconds dont care in alarm B comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm B minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm B set if the minutes match + 0x0 + + + B_0x1 + Minutes dont care in alarm B comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm B hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm B set if the hours match + 0x0 + + + B_0x1 + Hours dont care in alarm B comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. DT[1:0] is dont care. + 0x1 + + + + + MSK4 + Alarm B date mask + 31 + 1 + read-write + + + B_0x0 + Alarm B set if the date and day match + 0x0 + + + B_0x1 + Date and day dont care in alarm B comparison + 0x1 + + + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + RTC alarm B subsecond register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value +This value is compared with the contents of the synchronous prescaler counter to determine if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. +This field is the mirror of SS[14:0] in the RTC_ALRBBINR, and so can also be read or written through RTC_ALRBBINR. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +... +From 32 to 63: All 32 SS bits are compared and must match to activate alarm. +Note: In BCD mode (BIN=00)The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). + 0x0 + + + B_0x1 + SS[31:1] are dont care in Alarm B comparison. Only SS[0] is compared. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) +Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRBBINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRBBINR.SS[31:0]. + 0x1 + + + + + + + RTC_SR + RTC_SR + RTC status register + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). + 0 + 1 + read-only + + + ALRBF + Alarm B flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm B register (RTC_ALRMBR). + 1 + 1 + read-only + + + WUTF + Wake-up timer flag +This flag is set by hardware when the wake-up auto-reload counter reaches 0. +If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wake-up auto-reload counter reaches WUTOCLR value. +If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 2 + 1 + read-only + + + TSF + Timestamp flag +This flag is set by hardware when a timestamp event occurs. +If ITSF flag is set, TSF must be cleared together with ITSF. +Note: TSF is not set if TAMPTS1=11 and the tamper flag is read during the 3 ck_apre cycles following tamper event. Refer to Timestamp on tamper event for more details. + 3 + 1 + read-only + + + TSOVF + Timestamp overflow flag +This flag is set by hardware when a timestamp event occurs while TSF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + ITSF + Internal timestamp flag +This flag is set by hardware when a timestamp on the internal event occurs. + 5 + 1 + read-only + + + SSRUF + SSR underflow flag +This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1. + 6 + 1 + read-only + + + + + RTC_MISR + RTC_MISR + RTC masked interrupt status register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A masked flag +This flag is set by hardware when the alarm A interrupt occurs. + 0 + 1 + read-only + + + ALRBMF + Alarm B masked flag +This flag is set by hardware when the alarm B interrupt occurs. + 1 + 1 + read-only + + + WUTMF + Wake-up timer masked flag +This flag is set by hardware when the wake-up timer interrupt occurs. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 2 + 1 + read-only + + + TSMF + Timestamp masked flag +This flag is set by hardware when a timestamp interrupt occurs. +If ITSF flag is set, TSF must be cleared together with ITSF. + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow masked flag +This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + read-only + + + ITSMF + Internal timestamp masked flag +This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. + 5 + 1 + read-only + + + SSRUMF + SSR underflow masked flag +This flag is set by hardware when the SSR underflow interrupt occurs. + 6 + 1 + read-only + + + + + RTC_SCR + RTC_SCR + RTC status clear register + 0x5C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CALRAF + Clear alarm A flag +Writing 1 in this bit clears the ALRAF bit in the RTC_SR register. + 0 + 1 + write-only + + + CALRBF + Clear alarm B flag +Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. + 1 + 1 + write-only + + + CWUTF + Clear wake-up timer flag +Writing 1 in this bit clears the WUTF bit in the RTC_SR register. + 2 + 1 + write-only + + + CTSF + Clear timestamp flag +Writing 1 in this bit clears the TSF bit in the RTC_SR register. +If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF. + 3 + 1 + write-only + + + CTSOVF + Clear timestamp overflow flag +Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. + 4 + 1 + write-only + + + CITSF + Clear internal timestamp flag +Writing 1 in this bit clears the ITSF bit in the RTC_SR register. + 5 + 1 + write-only + + + CSSRUF + Clear SSR underflow flag +Writing 1 in this bit clears the SSRUF in the RTC_SR register. + 6 + 1 + write-only + + + + + RTC_ALRABINR + RTC_ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode +This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. +SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR. + 0 + 32 + read-write + + + + + RTC_ALRBBINR + RTC_ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode +This value is compared with the contents of the synchronous counter to determine if Alarm Bis to be activated. Only bits 0 up MASKSS-1 are compared. +SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMBSSRR, and so can also be read or written through RTC_ALRMBSSR. + 0 + 32 + read-write + + + + + + + SPI1 + SPI address block description + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 25 + + + + SPI_CR1 + SPI_CR1 + SPI control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page1954. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPI_DR register. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPI_CR2 + SPI_CR2 + SPI control register 2 + 0x04 + 16 + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). +Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). +Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPI_SR + SPI_SR + SPI status register + 0x08 + 16 + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPI_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPI_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section1: Mode fault (MODF) on page1964 for the software sequence. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section133.4.10: SPI status flags and Procedure for disabling the SPI on page1954. + 7 + 1 + read-only + + + B_0x0 + SPI not busy + 0x0 + + + B_0x1 + SPI is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode. Refer to Section133.4.11: SPI error flags. +This flag is set by hardware and reset when SPI_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPI_DR + SPI_DR + SPI data register + 0x0C + 16 + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section133.4.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_CRCPR + SPI_CRCPR + SPI CRC polynomial register + 0x10 + 16 + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_RXCRCR + SPI_RXCRCR + SPI Rx CRC register + 0x14 + 16 + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_TXCRCR + SPI_TXCRCR + SPI Tx CRC register + 0x18 + 16 + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + + + SPI2 + 0x40003800 + + SPI2_SPI3 + SPI2/3 global interrupt + 26 + + + + SPI3 + 0x40003C00 + + + SYSCFG + SYSCFG register block + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + SYSCFG configuration register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFF0 + + + MEM_MODE + Memory mapping selection bits +These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. +X0: Main flash memory mapped at 0x000010000 + 0 + 2 + read-write + + + B_0x1 + System flash memory mapped at 0x000010000 + 0x1 + + + B_0x3 + Embedded SRAM mapped at 0x000010000 + 0x3 + + + + + PA11_RMP + PA11 pin remapping +This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. + 3 + 1 + read-write + + + B_0x0 + No remap (PA11) + 0x0 + + + B_0x1 + Remap (PA9) + 0x1 + + + + + PA12_RMP + PA12 pin remapping +This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. + 4 + 1 + read-write + + + B_0x0 + No remap (PA12) + 0x0 + + + B_0x1 + Remap (PA10) + 0x1 + + + + + IR_POL + IR output polarity selection + 5 + 1 + read-write + + + B_0x0 + Output of IRTIM (IR_OUT) is not inverted + 0x0 + + + B_0x1 + Output of IRTIM (IR_OUT) is inverted + 0x1 + + + + + IR_MOD + IR Modulation Envelope signal selection +This bitfield selects the signal for IR modulation envelope: + 6 + 2 + read-write + + + B_0x0 + TIM16 + 0x0 + + + B_0x1 + USART1 + 0x1 + + + B_0x2 + USART2 + 0x2 + + + + + BOOSTEN + I/O analog switch voltage booster enable +This bit selects the way of supplying I/O analog switches: +When using the analog inputs , setting to 0 is recommended for high V<sub>DD</sub>, setting to 1 for low V<sub>DD</sub> (less than 2.4 V). + 8 + 1 + read-write + + + B_0x0 + V<sub>DD</sub> + 0x0 + + + B_0x1 + Dedicated voltage booster (supplied by V<sub>DD</sub>) + 0x1 + + + + + I2C_PB6_FMP + Fast Mode Plus (FM+) enable for PB6 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB6 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 16 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB7_FMP + Fast Mode Plus (FM+) enable for PB7 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB7 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 17 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB8_FMP + Fast Mode Plus (FM+) enable for PB8 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB8 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 18 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PB9_FMP + Fast Mode Plus (FM+) enable for PB9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB9 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 19 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA9_FMP + Fast Mode Plus (FM+) enable for PA9 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA9 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 22 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C_PA10_FMP + Fast Mode Plus (FM+) enable for PA10 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA10 I/O port. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 23 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + I2C3_FMP + Fast Mode Plus (FM+) enable for I2C3 +This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. +With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. +Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. + 24 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + SYSCFG configuration register 2 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCL + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP bit enable bit +This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input. + 0 + 1 + read-write + + + B_0x0 + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP output disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP output connected to TIM1/15/16 Break input + 0x1 + + + + + SPL + SRAM1 parity lock bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input. + 1 + 1 + read-write + + + B_0x0 + SRAM1 parity error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + SRAM1 parity error connected to TIM1/15/16 Break input + 0x1 + + + + + PVDL + PVD lock enable bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. + 2 + 1 + read-write + + + B_0x0 + PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be programmed by the application. + 0x0 + + + B_0x1 + PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read only. + 0x1 + + + + + ECCL + ECC error lock bit +This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input. + 3 + 1 + read-write + + + B_0x0 + ECC error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + ECC error connected to TIM1/15/16 Break input + 0x1 + + + + + BKPL + Backup SRAM2 parity lock +This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input. + 4 + 1 + read-write + + + B_0x0 + SRAM2 parity error disconnected from TIM1/15/16 Break input + 0x0 + + + B_0x1 + SRAM2 parity error connected to TIM1/15/16 Break input + 0x1 + + + + + BKPF + Backup SRAM2 parity error flag +This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1. + 7 + 1 + read-write + + + B_0x0 + No SRAM2 parity error detected + 0x0 + + + B_0x1 + SRAM2 parity error detected + 0x1 + + + + + SPF + SRAM1 parity error flag +This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1. + 8 + 1 + read-write + + + B_0x0 + No SRAM1 parity error detected + 0x0 + + + B_0x1 + SRAM1 parity error detected + 0x1 + + + + + + + SYSCFG_SCSR + SYSCFG_SCSR + SYSCFG SRAM2 control and status register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SRAM2ER + SRAM2 erase +Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. +Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. + 0 + 1 + read-write + + + SRAM2BSY + SRAM2 busy by erase operation + 1 + 1 + read-only + + + B_0x0 + No SRAM2 erase operation is ongoing + 0x0 + + + B_0x1 + SRAM2 erase operation is ongoing + 0x1 + + + + + + + SYSCFG_SKR + SYSCFG_SKR + SYSCFG SRAM2 key register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + KEY + SRAM2 write protection key for software erase +The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: +Write 0xCA into KEY[7:0] +Write 0x53 into KEY[7:0] +Writing a wrong key reactivates the write protection. + 0 + 8 + write-only + + + + + SYSCFG_TSCCR + SYSCFG_TSCCR + SYSCFG TSC comparator register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G2_IO1 + Comparator mode for group 2 on I/O 1 + 0 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PB4 to COMP2 + 0x1 + + + + + G2_IO3 + Comparator mode for group 2 on I/O 3 + 1 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PB6 to COMP2 + 0x1 + + + + + G4_IO3 + Comparator mode for group 4 on I/O 3 + 2 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PC6 to COMP2 + 0x1 + + + + + G6_IO1 + Comparator mode for group 6 on I/O 1 + 3 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PD10 to COMP1 + 0x1 + + + + + G7_IO1 + Comparator mode for group 7 on I/O 1 + 4 + 1 + read-write + + + B_0x0 + Disabled + 0x0 + + + B_0x1 + Enable connection of PA9 to COMP1 + 0x1 + + + + + TSC_IOCTRL + I/O control in comparator mode +The I/O control in comparator mode can be overwritten by hardware. + 5 + 1 + read-write + + + B_0x0 + I/O configured through the corresponding control register + 0x0 + + + B_0x1 + I/O configured as analog when TSC AF is activated + 0x1 + + + + + + + SYSCFG_ITLINE0 + SYSCFG_ITLINE0 + SYSCFG interrupt line 0 status register + 0x80 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + WWDG + Window watchdog interrupt pending flag + 0 + 1 + read-only + + + + + SYSCFG_ITLINE1 + SYSCFG_ITLINE1 + SYSCFG interrupt line 1 status register + 0x84 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PVDOUT + PVD supply monitoring interrupt request pending (EXTI line 16). + 0 + 1 + read-only + + + PVMOUT1 + V<sub>DDUSB</sub> supply monitoring interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + PVMOUT3 + ADC supply monitoring interrupt request pending (EXTI line 20) + 2 + 1 + read-only + + + PVMOUT4 + DAC supply monitoring interrupt request pending (EXTI line 21) + 3 + 1 + read-only + + + + + SYSCFG_ITLINE2 + SYSCFG_ITLINE2 + SYSCFG interrupt line 2 status register + 0x88 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP + Tamper interrupt request pending (EXTI line 21) + 0 + 1 + read-only + + + RTC + RTC interrupt request pending (EXTI line 19) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE3 + SYSCFG_ITLINE3 + SYSCFG interrupt line 3 status register + 0x8C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + FLASH_ITF + Flash interface interrupt request pending + 0 + 1 + read-only + + + FLASH_ECC + Flash interface ECC interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE4 + SYSCFG_ITLINE4 + SYSCFG interrupt line 4 status register + 0x90 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RCC + Reset and clock control interrupt request pending + 0 + 1 + read-only + + + CRS + CRS interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE5 + SYSCFG_ITLINE5 + SYSCFG interrupt line 5 status register + 0x94 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI line 0 interrupt request pending + 0 + 1 + read-only + + + EXTI1 + EXTI line 1 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE6 + SYSCFG_ITLINE6 + SYSCFG interrupt line 6 status register + 0x98 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI2 + EXTI line 2 interrupt request pending + 0 + 1 + read-only + + + EXTI3 + EXTI line 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE7 + SYSCFG_ITLINE7 + SYSCFG interrupt line 7 status register + 0x9C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI line 4 interrupt request pending + 0 + 1 + read-only + + + EXTI5 + EXTI line 5 interrupt request pending + 1 + 1 + read-only + + + EXTI6 + EXTI line 6 interrupt request pending + 2 + 1 + read-only + + + EXTI7 + EXTI line 7 interrupt request pending + 3 + 1 + read-only + + + EXTI8 + EXTI line 8 interrupt request pending + 4 + 1 + read-only + + + EXTI9 + EXTI line 9 interrupt request pending + 5 + 1 + read-only + + + EXTI10 + EXTI line 10 interrupt request pending + 6 + 1 + read-only + + + EXTI11 + EXTI line 11 interrupt request pending + 7 + 1 + read-only + + + EXTI12 + EXTI line 12 interrupt request pending + 8 + 1 + read-only + + + EXTI13 + EXTI line 13 interrupt request pending + 9 + 1 + read-only + + + EXTI14 + EXTI line 14 interrupt request pending + 10 + 1 + read-only + + + EXTI15 + EXTI line 15 interrupt request pending + 11 + 1 + read-only + + + + + SYSCFG_ITLINE8 + SYSCFG_ITLINE8 + SYSCFG interrupt line 8 status register + 0xA0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USB + USB interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE9 + SYSCFG_ITLINE9 + SYSCFG interrupt line 9 status register + 0xA4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH1 + DMA1 channel 1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE10 + SYSCFG_ITLINE10 + SYSCFG interrupt line 10 status register + 0xA8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMA1_CH2 + DMA1 channel 2 interrupt request pending + 0 + 1 + read-only + + + DMA1_CH3 + DMA1 channel 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE11 + SYSCFG_ITLINE11 + SYSCFG interrupt line 11 status register + 0xAC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAMUX + DMAMUX interrupt request pending + 0 + 1 + read-only + + + DMA1_CH4 + DMA1 channel 4 interrupt request pending + 1 + 1 + read-only + + + DMA1_CH5 + DMA1 channel 5 interrupt request pending + 2 + 1 + read-only + + + DMA1_CH6 + DMA1 channel 6 interrupt request pending + 3 + 1 + read-only + + + DMA1_CH7 + DMA1 channel 7 interrupt request pending + 4 + 1 + read-only + + + DMA2_CH1 + DMA2 channel 1 interrupt request pending + 5 + 1 + read-only + + + DMA2_CH2 + DMA2 channel 2 interrupt request pending + 6 + 1 + read-only + + + DMA2_CH3 + DMA2 channel 3 interrupt request pending + 7 + 1 + read-only + + + DMA2_CH4 + DMA2 channel 4 interrupt request pending + 8 + 1 + read-only + + + DMA2_CH5 + DMA2 channel 5 interrupt request pending + 9 + 1 + read-only + + + + + SYSCFG_ITLINE12 + SYSCFG_ITLINE12 + SYSCFG interrupt line 12 status register + 0xB0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC interrupt request pending + 0 + 1 + read-only + + + COMP1 + Comparator 1 interrupt request pending (EXTI line 17) + 1 + 1 + read-only + + + COMP2 + Comparator 2 interrupt request pending (EXTI line 18) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE13 + SYSCFG_ITLINE13 + SYSCFG interrupt line 13 status register + 0xB4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1_CCU + Timer 1 commutation interrupt request pending + 0 + 1 + read-only + + + TIM1_TRG + Timer 1 trigger interrupt request pending + 1 + 1 + read-only + + + TIM1_UPD + Timer 1 update interrupt request pending + 2 + 1 + read-only + + + TIM1_BRK + Timer 1 break interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE14 + SYSCFG_ITLINE14 + SYSCFG interrupt line 14 status register + 0xB8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM1_CC1 + Timer 1 capture compare 1 interrupt request pending + 0 + 1 + read-only + + + TIM1_CC2 + Timer 1 capture compare 2 interrupt request pending + 1 + 1 + read-only + + + TIM1_CC3 + Timer 1 capture compare 3 interrupt request pending + 2 + 1 + read-only + + + TIM1_CC4 + Timer 1 capture compare 4 interrupt request pending + 3 + 1 + read-only + + + + + SYSCFG_ITLINE15 + SYSCFG_ITLINE15 + SYSCFG interrupt line 15 status register + 0xBC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM2 + Timer 2 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE16 + SYSCFG_ITLINE16 + SYSCFG interrupt line 16 status register + 0xC0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM3 + Timer 3 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE17 + SYSCFG_ITLINE17 + SYSCFG interrupt line 17 status register + 0xC4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM6 + Timer 6 interrupt request pending + 0 + 1 + read-only + + + DAC + DAC underrun interrupt request pending + 1 + 1 + read-only + + + LPTIM1 + Low-power timer 1 interrupt request pending (EXTI line 29) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE18 + SYSCFG_ITLINE18 + SYSCFG interrupt line 18 status register + 0xC8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM7 + Timer 7 interrupt request pending + 0 + 1 + read-only + + + LPTIM2 + Low-power timer 2 interrupt request pending (EXTI line 30) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE19 + SYSCFG_ITLINE19 + SYSCFG interrupt line 19 status register + 0xCC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM15 + Timer 15 interrupt request pending + 0 + 1 + read-only + + + LPTIM3 + Low-power timer 3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE20 + SYSCFG_ITLINE20 + SYSCFG interrupt line 20 status register + 0xD0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TIM16 + Timer 16 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE21 + SYSCFG_ITLINE21 + SYSCFG interrupt line 21 status register + 0xD4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSC_MCE + TSC max count error interrupt request pending + 0 + 1 + read-only + + + TSC_EOA + TSC end of acquisition interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE22 + SYSCFG_ITLINE22 + SYSCFG interrupt line 22 status register + 0xD8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LCD + LCD interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE23 + SYSCFG_ITLINE23 + SYSCFG interrupt line 23 status register + 0xDC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C1 + I2C1 interrupt request pending (EXTI line 33) + 0 + 1 + read-only + + + + + SYSCFG_ITLINE24 + SYSCFG_ITLINE24 + SYSCFG interrupt line 24 status register + 0xE0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + I2C2 + I2C2 interrupt request pending + 0 + 1 + read-only + + + I2C4 + I2C4 interrupt request pending + 1 + 1 + read-only + + + I2C3 + I2C3 interrupt request pending (EXTI line 23) + 2 + 1 + read-only + + + + + SYSCFG_ITLINE25 + SYSCFG_ITLINE25 + SYSCFG interrupt line 25 status register + 0xE4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI1 + SPI1 interrupt request pending + 0 + 1 + read-only + + + + + SYSCFG_ITLINE26 + SYSCFG_ITLINE26 + SYSCFG interrupt line 26 status register + 0xE8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SPI2 + SPI2 interrupt request pending + 0 + 1 + read-only + + + SPI3 + SPI3 interrupt request pending + 1 + 1 + read-only + + + + + SYSCFG_ITLINE27 + SYSCFG_ITLINE27 + SYSCFG interrupt line 27 status register + 0xEC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART1 + USART1 interrupt request pending, combined with EXTI line 25 + 0 + 1 + read-only + + + + + SYSCFG_ITLINE28 + SYSCFG_ITLINE28 + SYSCFG interrupt line 28 status register + 0xF0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART2 + USART2 interrupt request pending (EXTI line 35) + 0 + 1 + read-only + + + LPUART2 + LPUART2 interrupt request pending (EXTI line 31) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE29 + SYSCFG_ITLINE29 + SYSCFG interrupt line 29 status register + 0xF4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART3 + USART3 interrupt request pending + 0 + 1 + read-only + + + LPUART1 + LPUART1 interrupt request pending (EXTI line 30) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE30 + SYSCFG_ITLINE30 + SYSCFG interrupt line 30 status register + 0xF8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + USART4 + USART4 interrupt request pending + 0 + 1 + read-only + + + LPUART3 + LPUART3 interrupt request pending (EXTI line 32) + 1 + 1 + read-only + + + + + SYSCFG_ITLINE31 + SYSCFG_ITLINE31 + SYSCFG interrupt line 31 status register + 0xFC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RNG + RNG interrupt request pending + 0 + 1 + read-only + + + AES + AES interrupt request pending + 1 + 1 + read-only + + + + + + + TAMP + TAMP register block + TAMP + 0x4000B000 + + 0x0 + 0x400 + registers + + + + TAMP_CR1 + TAMP_CR1 + TAMP control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1E + Tamper detection on TAMP_IN1 enable + 0 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN1 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN1 is enabled. + 0x1 + + + + + TAMP2E + Tamper detection on TAMP_IN2 enable<sup>(1)</sup> + 1 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN2 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN2 is enabled. + 0x1 + + + + + TAMP3E + Tamper detection on TAMP_IN3 enable<sup>(1)</sup> + 2 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN3 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN3 is enabled. + 0x1 + + + + + TAMP4E + Tamper detection on TAMP_IN4 enable<sup>(1)</sup> + 3 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN4 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN4 is enabled. + 0x1 + + + + + TAMP5E + Tamper detection on TAMP_IN5 enable<sup>(1)</sup> + 4 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN5 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN5 is enabled. + 0x1 + + + + + ITAMP3E + Internal tamper 3 enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 disabled. + 0x0 + + + B_0x1 + Internal tamper 3 enabled. + 0x1 + + + + + ITAMP4E + Internal tamper 4 enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 disabled. + 0x0 + + + B_0x1 + Internal tamper 4 enabled. + 0x1 + + + + + ITAMP5E + Internal tamper 5 enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 disabled. + 0x0 + + + B_0x1 + Internal tamper 5 enabled. + 0x1 + + + + + ITAMP6E + Internal tamper 6 enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 disabled. + 0x0 + + + B_0x1 + Internal tamper 6 enabled. + 0x1 + + + + + + + TAMP_CR2 + TAMP_CR2 + TAMP control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1POM + Tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Tamper 1 event detection is in potential mode. + 0x1 + + + + + TAMP2POM + Tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 2 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP3POM + Tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 3 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP4POM + Tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 4 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP5POM + Tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Tamper 5 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + TAMP1MSK + Tamper 1 mask +The tamper 1 interrupt must not be enabled when TAMP1MSK is set. + 16 + 1 + read-write + + + B_0x0 + Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + TAMP2MSK + Tamper 2 mask +The tamper 2 interrupt must not be enabled when TAMP2MSK is set. + 17 + 1 + read-write + + + B_0x0 + Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + TAMP3MSK + Tamper 3 mask +The tamper 3 interrupt must not be enabled when TAMP3MSK is set. + 18 + 1 + read-write + + + B_0x0 + Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers and device secrets<sup>(1)</sup> are not erased. + 0x1 + + + + + BKBLOCK + Backup registers and device secrets<sup>(1)</sup> access blocked + 22 + 1 + read-write + + + B_0x0 + backup registers and device secrets<sup>(1)</sup> can be accessed if no tamper flag is set + 0x0 + + + B_0x1 + backup registers and device secrets<sup>(1)</sup> cannot be accessed + 0x1 + + + + + BKERASE + Backup registers and device secrets<sup>(1)</sup> erase +Writing 1 to this bit reset the backup registers and device secrets<sup>(1)</sup>. Writing 0 has no effect. This bit is always read as 0. + 23 + 1 + write-only + + + TAMP1TRG + Active level for tamper 1 input +If TAMPFLT1=100 tamper 1 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 1 input falling edge triggers a tamper detection event. + 24 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 1 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 1 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP2TRG + Active level for tamper 2 input +If TAMPFLT = 00 tamper 2 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 2 input falling edge triggers a tamper detection event. + 25 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 2 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 2 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP3TRG + Active level for tamper 3 input +If TAMPFLT1=100 tamper 3 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 3 input falling edge triggers a tamper detection event. + 26 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 3 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 3 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP4TRG + Active level for tamper 4 input (active mode disabled) +If TAMPFLT1=100 tamper 4 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 4 input falling edge triggers a tamper detection event. + 27 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 4 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 4 input staying low triggers a tamper detection event + 0x1 + + + + + TAMP5TRG + Active level for tamper 5 input (active mode disabled) +If TAMPFLT1=100 tamper 5 input rising edge triggers a tamper detection event. +If TAMPFLT1=100 tamper 5 input falling edge triggers a tamper detection event. + 28 + 1 + read-write + + + B_0x0 + If TAMPFLT different from 00 tamper 5 input staying low triggers a tamper detection event + 0x0 + + + B_0x1 + If TAMPFLT different from 00 tamper 5 input staying low triggers a tamper detection event + 0x1 + + + + + + + TAMP_CR3 + TAMP_CR3 + TAMP control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ITAMP3POM + Internal tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Internal tamper 3 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 3 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP4POM + Internal tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Internal tamper 4 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 4 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP5POM + Internal tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Internal tamper 5 event detection is in confirmed mode<sup>(1)</sup>. + 0x0 + + + B_0x1 + Internal tamper 5 event detection is in potential mode<sup>(2)</sup>. + 0x1 + + + + + ITAMP6POM + Internal tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Internal tamper 6 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Internal tamper 6 event detection is in potential mode. + 0x1 + + + + + + + TAMP_FLTCR + TAMP_FLTCR + TAMP filter control register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMPFREQ + Tamper sampling frequency +Determines the frequency at which each of the TAMP_INx inputs are sampled. + 0 + 3 + read-write + + + B_0x0 + RTCCLK / 32768 (11Hz when RTCCLK = 327681Hz) + 0x0 + + + B_0x1 + RTCCLK / 16384 (21Hz when RTCCLK = 327681Hz) + 0x1 + + + B_0x2 + RTCCLK / 8192 (41Hz when RTCCLK = 327681Hz) + 0x2 + + + B_0x3 + RTCCLK / 4096 (81Hz when RTCCLK = 327681Hz) + 0x3 + + + B_0x4 + RTCCLK / 2048 (161Hz when RTCCLK = 327681Hz) + 0x4 + + + B_0x5 + RTCCLK / 1024 (321Hz when RTCCLK = 327681Hz) + 0x5 + + + B_0x6 + RTCCLK / 512 (641Hz when RTCCLK = 327681Hz) + 0x6 + + + B_0x7 + RTCCLK / 256 (1281Hz when RTCCLK = 327681Hz) + 0x7 + + + + + TAMPFLT + TAMP_INx filter count +These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs. + 3 + 2 + read-write + + + B_0x0 + Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). + 0x0 + + + B_0x1 + Tamper event is activated after 2 consecutive samples at the active level. + 0x1 + + + B_0x2 + Tamper event is activated after 4 consecutive samples at the active level. + 0x2 + + + B_0x3 + Tamper event is activated after 8 consecutive samples at the active level. + 0x3 + + + + + TAMPPRCH + TAMP_INx precharge duration +These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs. + 5 + 2 + read-write + + + B_0x0 + 1 RTCCLK cycle + 0x0 + + + B_0x1 + 2 RTCCLK cycles + 0x1 + + + B_0x2 + 4 RTCCLK cycles + 0x2 + + + B_0x3 + 8 RTCCLK cycles + 0x3 + + + + + TAMPPUDIS + TAMP_INx pull-up disable +This bit determines if each of the TAMPx pins are precharged before each sample. + 7 + 1 + read-write + + + B_0x0 + Precharge TAMP_INx pins before sampling (enable internal pull-up) + 0x0 + + + B_0x1 + Disable precharge of TAMP_INx pins. + 0x1 + + + + + + + TAMP_IER + TAMP_IER + TAMP interrupt enable register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1IE + Tamper 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 1 interrupt enabled. + 0x1 + + + + + TAMP2IE + Tamper 2 interrupt enable + 1 + 1 + read-write + + + B_0x0 + Tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 2 interrupt enabled. + 0x1 + + + + + TAMP3IE + Tamper 3 interrupt enable + 2 + 1 + read-write + + + B_0x0 + Tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 3 interrupt enabled.. + 0x1 + + + + + TAMP4IE + Tamper 4 interrupt enable + 3 + 1 + read-write + + + B_0x0 + Tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 4 interrupt enabled. + 0x1 + + + + + TAMP5IE + Tamper 5 interrupt enable + 4 + 1 + read-write + + + B_0x0 + Tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP3IE + Internal tamper 3 interrupt enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 3 interrupt enabled. + 0x1 + + + + + ITAMP4IE + Internal tamper 4 interrupt enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 4 interrupt enabled. + 0x1 + + + + + ITAMP5IE + Internal tamper 5 interrupt enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP6IE + Internal tamper 6 interrupt enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 6 interrupt enabled. + 0x1 + + + + + + + TAMP_SR + TAMP_SR + TAMP status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1F + TAMP1 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP1 input. + 0 + 1 + read-only + + + TAMP2F + TAMP2 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP2 input. + 1 + 1 + read-only + + + TAMP3F + TAMP3 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP3 input. + 2 + 1 + read-only + + + TAMP4F + TAMP4 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP4 input. + 3 + 1 + read-only + + + TAMP5F + TAMP5 detection flag +This flag is set by hardware when a tamper detection event is detected on the TAMP5 input. + 4 + 1 + read-only + + + ITAMP3F + Internal tamper 3 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 3. + 18 + 1 + read-only + + + ITAMP4F + Internal tamper 4 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 4. + 19 + 1 + read-only + + + ITAMP5F + Internal tamper 5 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 5. + 20 + 1 + read-only + + + ITAMP6F + Internal tamper 6 flag +This flag is set by hardware when a tamper detection event is detected on the internal tamper 6. + 21 + 1 + read-only + + + + + TAMP_MISR + TAMP_MISR + TAMP masked interrupt status register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 interrupt masked flag +This flag is set by hardware when the tamper 1 interrupt is raised. + 0 + 1 + read-only + + + TAMP2MF + TAMP2 interrupt masked flag +This flag is set by hardware when the tamper 2 interrupt is raised. + 1 + 1 + read-only + + + TAMP3MF + TAMP3 interrupt masked flag +This flag is set by hardware when the tamper 3 interrupt is raised. + 2 + 1 + read-only + + + TAMP4MF + TAMP4 interrupt masked flag +This flag is set by hardware when the tamper 4 interrupt is raised. + 3 + 1 + read-only + + + TAMP5MF + TAMP5 interrupt masked flag +This flag is set by hardware when the tamper 5 interrupt is raised. + 4 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 interrupt masked flag +This flag is set by hardware when the internal tamper 3 interrupt is raised. + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 interrupt masked flag +This flag is set by hardware when the internal tamper 4 interrupt is raised. + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 interrupt masked flag +This flag is set by hardware when the internal tamper 5 interrupt is raised. + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 interrupt masked flag +This flag is set by hardware when the internal tamper 6 interrupt is raised. + 21 + 1 + read-only + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CTAMP1F + Clear TAMP1 detection flag +Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register. + 0 + 1 + write-only + + + CTAMP2F + Clear TAMP2 detection flag +Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register. + 1 + 1 + write-only + + + CTAMP3F + Clear TAMP3 detection flag +Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register. + 2 + 1 + write-only + + + CTAMP4F + Clear TAMP4 detection flag +Writing 1 in this bit clears the TAMP4F bit in the TAMP_SR register. + 3 + 1 + write-only + + + CTAMP5F + Clear TAMP5 detection flag +Writing 1 in this bit clears the TAMP5F bit in the TAMP_SR register. + 4 + 1 + write-only + + + CITAMP3F + Clear ITAMP3 detection flag +Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register. + 18 + 1 + write-only + + + CITAMP4F + Clear ITAMP4 detection flag +Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register. + 19 + 1 + write-only + + + CITAMP5F + Clear ITAMP5 detection flag +Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register. + 20 + 1 + write-only + + + CITAMP6F + Clear ITAMP6 detection flag +Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register. + 21 + 1 + write-only + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. +In the default (ERASE) configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled. + 0 + 32 + read-write + + + + + + + TIM1 + TIM1 address block description + TIM + 0x40012C00 + + 0x0 + 0x6C + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 break, update, trigger and commutation interrupts + 13 + + + TIM1_CC + TIM1 Capture Compare interrupt + 14 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable +Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable +This bit is set and cleared by software to enable/disable UEV event generation. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller +Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source +This bit is set and cleared by software to select the UEV event sources. +Counter overflow/underflow +Setting the UG bit +Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection +Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0x0 + + + B_0x1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 0x1 + + + B_0x2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 0x2 + + + B_0x3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (ETR, TIx): +Note: t<sub>DTS</sub> = 1/f<sub>DTS</sub>, t<sub>CK_INT</sub> = 1/f<sub>CK_INT</sub>. + 8 + 2 + read-write + + + B_0x0 + t<sub>DTS</sub>=t<sub>CK_INT</sub> + 0x0 + + + B_0x1 + t<sub>DTS</sub>=2*t<sub>CK_INT</sub> + 0x1 + + + B_0x2 + t<sub>DTS</sub>=4*t<sub>CK_INT</sub> + 0x2 + + + B_0x3 + Reserved, do not program this value + 0x3 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection +These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output Idle state 2 (OC2 output) +Refer to OIS1 bit + 10 + 1 + read-write + + + OIS2N + Output Idle state 2 (OC2N output) +Refer to OIS1N bit + 11 + 1 + read-write + + + OIS3 + Output Idle state 3 (OC3 output) +Refer to OIS1 bit + 12 + 1 + read-write + + + OIS3N + Output Idle state 3 (OC3N output) +Refer to OIS1N bit + 13 + 1 + read-write + + + OIS4 + Output Idle state 4 (OC4 output) +Refer to OIS1 bit + 14 + 1 + read-write + + + OIS5 + Output Idle state 5 (OC5 output) +Refer to OIS1 bit + 16 + 1 + read-write + + + OIS6 + Output Idle state 6 (OC6 output) +Refer to OIS1 bit + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 +These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: +Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO2) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO2) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO2) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO2) + 0x7 + + + B_0x8 + Compare - OC5REFC signal is used as trigger output (TRGO2) + 0x8 + + + B_0x9 + Compare - OC6REFC signal is used as trigger output (TRGO2) + 0x9 + + + B_0xA + Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 + 0xA + + + B_0xB + Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 + 0xB + + + B_0xC + Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xC + + + B_0xD + Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xD + + + B_0xE + Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 + 0xE + + + B_0xF + Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 + 0xF + + + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Codes above 1000: Reserved. +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection +This bit is used to select the OCREF clear source. + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[0]: Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See Table1118: TIM1 internal trigger connection on page1561 for more details on ITRx meaning for each Timer. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + ETF + External trigger filter +This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler +External trigger signal ETRP frequency must be at most 1/4 of f<sub>CK_INT</sub> frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable +This bit enables External clock mode 2. +Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). +It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). +Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. + 0x1 + + + + + ETP + External trigger polarity +This bit selects whether ETR or ETR is used for trigger operations + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag +This bit is set by hardware on an update event. It is cleared by software. +At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. +When CNT is reinitialized by a trigger event (refer to Section122.4.3: TIM1 slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag +This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). +If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. +If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred. + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag +Refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag +Refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag +Refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag +This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag +This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag +This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + B2IF + Break 2 interrupt flag +This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag +This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0. + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag +Refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag +Refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag +Refer to CC1OF description + 12 + 1 + read-write + + + SBIF + System Break interrupt flag +This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. +This flag must be reset to re-start PWM operation. + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag +Refer to CC1IF description (Note: Channel 5 can only be configured as output) + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag +Refer to CC1IF description (Note: Channel 6 can only be configured as output) + 17 + 1 + read-write + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation +This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/Compare 1 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. +If channel CC1 is configured as output: +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. +If channel CC1 is configured as input: +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation +Refer to CC1G description + 2 + 1 + write-only + + + CC3G + Capture/Compare 3 generation +Refer to CC1G description + 3 + 1 + write-only + + + CC4G + Capture/Compare 4 generation +Refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/Compare control update generation +This bit can be set by software, it is automatically cleared by hardware +Note: This bit acts only on channels having a complementary output. + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated. + 0x1 + + + + + TG + Trigger generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + BG + Break generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + B2G + Break 2 generation +This bit is set by software in order to generate an event, it is automatically cleared by hardware. + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. + 0x1 + + + + + + + TIM1_CCMR1_INPUT + TIM1_CCMR1_INPUT + TIM1 capture/compare mode register 1 + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f<sub>DTS</sub> + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC2F + Input capture 2 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR1_OUTPUT + TIM1_CCMR1_OUTPUT + TIM1 capture/compare mode register 1 + TIM1_CCMR1_INPUT + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output Compare 1 fast enable +This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger. + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode +These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. +Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). +Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. +Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. +Note: The OC1M[3] bit is not contiguous, located in bit 16. + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the output keeps the state (active or inactive) it had before entering the frozen state. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ocref_clr_int signal + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input) + 0x1 + + + + + CC2S + Capture/Compare 2 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output Compare 2 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode +Refer to OC1M[3:0] description. + 12 + 3 + read-write + + + OC2CE + Output Compare 2 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2_INPUT + TIM1_CCMR2_INPUT + TIM1 capture/compare mode register 2 + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC3PSC + Input capture 3 prescaler +Refer to IC1PSC[1:0] description. + 2 + 2 + read-write + + + IC3F + Input capture 3 filter +Refer to IC1F[3:0] description. + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC4PSC + Input capture 4 prescaler +Refer to IC1PSC[1:0] description. + 10 + 2 + read-write + + + IC4F + Input capture 4 filter +Refer to IC1F[3:0] description. + 12 + 4 + read-write + + + + + TIM1_CCMR2_OUTPUT + TIM1_CCMR2_OUTPUT + TIM1 capture/compare mode register 1 + TIM1_CCMR2_INPUT + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC3FE + Output compare 3 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode +Refer to OC1M[3:0] description. + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection +This bit-field defines the direction of the channel (input/output) as well as the used input. +Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC4FE + Output compare 4 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode +Refer to OC3M[3:0] description. + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/Compare 1 output enable +When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table1119 for details. +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity +When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. +CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). +CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). +CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. +CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). +Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity +CC1 channel configured as output: +CC1 channel configured as input: +This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. +Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (channel configured as output). +On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + Capture/Compare 2 output enable +Refer to CC1E description + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity +Refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/Compare 2 complementary output enable +Refer to CC1NE description + 6 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity +Refer to CC1NP description + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable +Refer to CC1E description + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output polarity +Refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/Compare 3 complementary output enable +Refer to CC1NE description + 10 + 1 + read-write + + + CC3NP + Capture/Compare 3 complementary output polarity +Refer to CC1NP description + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable +Refer to CC1E description + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output polarity +Refer to CC1P description + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 complementary output polarity +Refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/Compare 5 output enable +Refer to CC1E description + 16 + 1 + read-write + + + CC5P + Capture/Compare 5 output polarity +Refer to CC1P description + 17 + 1 + read-write + + + CC6E + Capture/Compare 6 output enable +Refer to CC1E description + 20 + 1 + read-write + + + CC6P + Capture/Compare 6 output polarity +Refer to CC1P description + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value +The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). +PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value +ARR is the value to be loaded in the actual auto-reload register. +Refer to the Section122.3.1: Time-base unit on page1497 for more details about ARR update and behavior. +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x30 + 16 + 0x0000 + 0xFFFF + + + REP + Repetition counter value +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. +Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. +It means in PWM mode (REP+1) corresponds to: +the number of PWM periods in edge-aligned mode +the number of half PWM period in center-aligned mode. + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x34 + 16 + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value +If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. +If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x38 + 16 + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value +If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. +If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x3C + 16 + 0x0000 + 0xFFFF + + + CCR3 + Capture/Compare value +If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. +If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x40 + 16 + 0x0000 + 0xFFFF + + + CCR4 + Capture/Compare value +If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. +If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed. + 0 + 16 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + 0 + 8 + read-write + + + LOCK + Lock configuration +These bits offer a write protection against software errors. +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode +This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. + 0x1 + + + + + OSSR + Off-state selection for Run mode +This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable +This bit enables the complete break protection (including all sources connected to bk_acth and BRK sources, as per Figure1152: Break and Break2 circuitry overview). +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) + 0x1 + + + + + MOE + Main output enable +This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. +In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. +See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. OC and OCN outputs are disabled + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter +This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter +This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 20 + 4 + read-write + + + B_0x0 + No filter, BRK2 acts asynchronously + 0x0 + + + B_0x1 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=2 + 0x1 + + + B_0x2 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=4 + 0x2 + + + B_0x3 + f<sub>SAMPLING</sub>=f<sub>CK_INT</sub>, N=8 + 0x3 + + + B_0x4 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=6 + 0x4 + + + B_0x5 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/2, N=8 + 0x5 + + + B_0x6 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=6 + 0x6 + + + B_0x7 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/4, N=8 + 0x7 + + + B_0x8 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=6 + 0x8 + + + B_0x9 + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/8, N=8 + 0x9 + + + B_0xA + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=5 + 0xA + + + B_0xB + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=6 + 0xB + + + B_0xC + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/16, N=8 + 0xC + + + B_0xD + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=5 + 0xD + + + B_0xE + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=6 + 0xE + + + B_0xF + f<sub>SAMPLING</sub>=f<sub>DTS</sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable +Note: The BRK2 must only be used with OSSR = OSSI = 1. +Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 24 + 1 + read-write + + + B_0x0 + Break input BRK2 disabled + 0x0 + + + B_0x1 + Break input BRK2 enabled + 0x1 + + + + + BK2P + Break 2 polarity +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 25 + 1 + read-write + + + B_0x0 + Break input BRK2 is active low + 0x0 + + + B_0x1 + Break input BRK2 is active high + 0x1 + + + + + BKDSRM + Break Disarm +This bit is cleared by hardware when no break source is active. +The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BK2DSRM + Break2 Disarm +Refer to BKDSRM description + 27 + 1 + read-write + + + BKBID + Break Bidirectional +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional +Refer to BKBID description + 29 + 1 + read-write + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x48 + 16 + 0x0000 + 0xFFFF + + + DBA + DMA base address +This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. +Example: +... + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length +This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). +... +Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. +If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: +(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL +In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA +According to the configuration of the DMA Data Size, several cases may occur: +If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. +If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA. + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x11 + 18 transfers + 0x11 + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses +A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 32 + read-write + + + + + TIM1_OR1 + TIM1_OR1 + TIM1 option register 1 + 0x50 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection +This bit selects the ocref_clr input source. +Others: Reserved +Note: COMP3 is available on STM32G0B1xx and STM32G0C1xx salestypes only. + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable +Refer to OC1FE description. + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable +Refer to OC1PE description. + 3 + 1 + read-write + + + OC5M + OC5M[0]: Output compare 5 mode +Refer to OC1M description. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable +Refer to OC1CE description. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable +Refer to OC1FE description. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable +Refer to OC1PE description. + 11 + 1 + read-write + + + OC6M + OC6M[0]: Output compare 6 mode +Refer to OC1M description. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable +Refer to OC1CE description. + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/Compare 5 value +CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. + 0 + 16 + read-write + + + GC5C1 + Group Channel 5 and Channel 1 +Distortion on Channel 1 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC1REFC5 + 0x0 + + + B_0x1 + OC1REFC is the logical AND of OC1REFC and OC5REF + 0x1 + + + + + GC5C2 + Group Channel 5 and Channel 2 +Distortion on Channel 2 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). +Note: it is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC2REFC + 0x0 + + + B_0x1 + OC2REFC is the logical AND of OC2REFC and OC5REF + 0x1 + + + + + GC5C3 + Group Channel 5 and Channel 3 +Distortion on Channel 3 output: +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). +Note: it is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + B_0x0 + No effect of OC5REF on OC3REFC + 0x0 + + + B_0x1 + OC3REFC is the logical AND of OC3REFC and OC5REF + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x5C + 16 + 0x0000 + 0xFFFF + + + CCR6 + Capture/Compare 6 value +CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. +The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. + 0 + 16 + read-write + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x60 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable +This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable +This bit enables the COMP1 for the timers BRK input. COMP1 output is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable +This bit enables the COMP2 for the timers BRK input. COMP2 output is ORed with the other BRK sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity +This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1) + 0x0 + + + B_0x1 + COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1) + 0x1 + + + + + ETRSEL + ETR source selection +These bits select the ETR input source. +Others: Reserved +Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + B_0x2 + COMP2 output + 0x2 + + + B_0x3 + ADC1 AWD1 + 0x3 + + + B_0x4 + ADC1 AWD2 + 0x4 + + + B_0x5 + ADC1 AWD3 + 0x5 + + + B_0x6 + COMP3 output (available on STM32G0B1xx and STM32G0C1xx salestypes only) + 0x6 + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 Alternate function register 2 + 0x64 + 0x20 + 0x00000001 + 0xFFFFFFFF + + + BK2INE + BRK2 BKIN input enable +This bit enables the BKIN2 alternate function input for the timers BRK2 input. BKIN2 input is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 0 + 1 + read-write + + + B_0x0 + BKIN2 input disabled + 0x0 + + + B_0x1 + BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + BRK2 COMP1 enable +This bit enables the COMP1 for the timers BRK2 input. COMP1 output is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BK2CMP2E + BRK2 COMP2 enable +This bit enables the COMP2 for the timers BRK2 input. COMP2 output is ORed with the other BRK2 sources. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BK2INP + BRK2 BKIN2 input polarity +This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 9 + 1 + read-write + + + B_0x0 + BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + BK2CMP1P + BRK2 COMP1 input polarity +This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 10 + 1 + read-write + + + B_0x0 + COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + BK2CMP2P + BRK2 COMP2 input polarity +This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). + 11 + 1 + read-write + + + B_0x0 + COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) + 0x0 + + + B_0x1 + COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) + 0x1 + + + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x68 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input +Others: Reserved + 0 + 4 + read-write + + + B_0x0 + TIM1_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + selects TI2[0] to TI2[15] input +Others: Reserved + 8 + 4 + read-write + + + B_0x0 + TIM1_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + selects TI3[0] to TI3[15] input +Others: Reserved + 16 + 4 + read-write + + + B_0x0 + TIM1_CH3 input + 0x0 + + + + + TI4SEL + selects TI4[0] to TI4[15] input +Others: Reserved + 24 + 4 + read-write + + + B_0x0 + TIM1_CH4 input + 0x0 + + + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40000000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 global interrupt + 15 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section23. + 0x1 + + + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1_ALTERNATE1 + TIM2 capture/compare mode register 1 + TIM2_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2_ALTERNATE1 + TIM2 capture/compare mode register 2 + TIM2_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM2_CNT_ALTERNATE1 + TIM2_CNT_ALTERNATE1 + TIM2 counter + TIM2_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM2_OR1 + TIM2_OR1 + TIM2 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection + + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 + 0x1 + + + B_0x2 + COMP2 + 0x2 + + + B_0x3 + LSE + 0x3 + + + B_0x4 + MCO + 0x4 + + + B_0x5 + MCO2 + 0x5 + + + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM2_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM2_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM2_CH3 input + 0x0 + + + + + + + + + TIM3 + TIM3 address block description + TIM3 + 0x40000400 + + 0x0 + 0x6C + registers + + + TIM3 + TIM3 global interrupt + 16 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO) + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO) + 0x5 + + + B_0x6 + Compare - OC3REFC signal is used as trigger output (TRGO) + 0x6 + + + B_0x7 + Compare - OC4REFC signal is used as trigger output (TRGO) + 0x7 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section23. + 0x1 + + + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. + 0x0 + + + B_0x1 + OCREF_CLR_INT is connected to ETRF + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + B_0x7 + External Trigger input (ETRF) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + ETRP frequency divided by 2 + 0x1 + + + B_0x2 + ETRP frequency divided by 4 + 0x2 + + + B_0x3 + ETRP frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + ETR is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + ETR is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at f less thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_ALTERNATE1 + TIM3_CCMR1_ALTERNATE1 + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + OC1Ref is not affected by the ETRF input + 0x0 + + + B_0x1 + OC1Ref is cleared as soon as a High level is detected on ETRF input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_ALTERNATE1 + TIM3_CCMR2_ALTERNATE1 + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, IC3 is mapped on TI3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, IC3 is mapped on TI4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, IC3 is mapped on TRC. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, IC4 is mapped on TI4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, IC4 is mapped on TI3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, IC4 is mapped on TRC. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 32 + read-write + + + + + TIM3_CNT_ALTERNATE1 + TIM3_CNT_ALTERNATE1 + TIM3 counter + TIM3_CNT + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + 0 + 31 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 32 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Low Capture/Compare 1 value + + 0 + 32 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Low Capture/Compare 2 value + + 0 + 32 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Low Capture/Compare value + + 0 + 32 + read-write + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM3_OR1 + TIM3_OR1 + TIM3 option register 1 + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCREF_CLR + Ocref_clr source selection + + 0 + 2 + read-write + + + B_0x0 + COMP1 output is connected to the OCREF_CLR input + 0x0 + + + B_0x1 + COMP2 output is connected to the OCREF_CLR input + 0x1 + + + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + ETR source selection + + 14 + 4 + read-write + + + B_0x0 + ETR legacy mode + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + B_0x2 + COMP2 output + 0x2 + + + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + TI1[0] to TI1[15] input selection + + 0 + 4 + read-write + + + B_0x0 + TIM3_CH1 input + 0x0 + + + B_0x1 + COMP1 output + 0x1 + + + + + TI2SEL + TI2[0] to TI2[15] input selection + + 8 + 4 + read-write + + + B_0x0 + TIM3_CH2 input + 0x0 + + + B_0x1 + COMP2 output + 0x1 + + + + + TI3SEL + TI3[0] to TI3[15] input selection + + 16 + 4 + read-write + + + B_0x0 + TIM3_CH3 input + 0x0 + + + + + + + + + TIM6 + TIM6 address block description + TIM + 0x40001000 + + 0x0 + 0x30 + registers + + + TIM6_DAC_LPTIM1 + TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) + 17 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable + Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + This bit is set and cleared by software to enable/disable UEV event generation. + Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source + This bit is set and cleared by software to select the UEV event sources. + Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x04 + 16 + 0x0000 + 0xFFFF + + + MMS + Master mode selection + These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: + When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). + Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/Interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 16 + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + This bit is set by hardware on an update event. It is cleared by software. + At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. + When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation + This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). + 0x1 + + + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value + The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). + PSC contains the value to be loaded into the active prescaler register at each update event. + (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Prescaler value + ARR is the value to be loaded into the actual auto-reload register. + Refer to Section123.3.1: Time-base unit on page1596 for more details about ARR update and behavior. + The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + + + TIM7 + TIM7 address block description + TIM + 0x40001400 + + 0x0 + 0x30 + registers + + + TIM7_LPTIM2 + TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) + 18 + + + + TIM7_CR1 + TIM7_CR1 + TIM7 control register 1 + 0x00 + 16 + 0x0000 + 0xFFFF + + + CEN + Counter enable + Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. + CEN is cleared automatically in one-pulse mode, when an update event occurs. + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + This bit is set and cleared by software to enable/disable UEV event generation. + Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + Buffered registers are then loaded with their preload values. + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source + This bit is set and cleared by software to select the UEV event sources. + Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + + + TIM7_CR2 + TIM7_CR2 + TIM7 control register 2 + 0x04 + 16 + 0x0000 + 0xFFFF + + + MMS + Master mode selection + These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: + When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). + Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + + + + + TIM7_DIER + TIM7_DIER + TIM7 DMA/Interrupt enable register + 0x0C + 16 + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM7_SR + TIM7_SR + TIM7 status register + 0x10 + 16 + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + This bit is set by hardware on an update event. It is cleared by software. + At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. + When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register. + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + + + TIM7_EGR + TIM7_EGR + TIM7 event generation register + 0x14 + 16 + 0x0000 + 0xFFFF + + + UG + Update generation + This bit can be set by software, it is automatically cleared by hardware. + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). + 0x1 + + + + + + + TIM7_CNT + TIM7_CNT + TIM7 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + TIM7_PSC + TIM7_PSC + TIM7 prescaler + 0x28 + 16 + 0x0000 + 0xFFFF + + + PSC + Prescaler value + The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). + PSC contains the value to be loaded into the active prescaler register at each update event. + (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode). + 0 + 16 + read-write + + + + + TIM7_ARR + TIM7_ARR + TIM7 auto-reload register + 0x2C + 16 + 0xFFFF + 0xFFFF + + + ARR + Prescaler value + ARR is the value to be loaded into the actual auto-reload register. + Refer to Section123.3.1: Time-base unit on page1596 for more details about ARR update and behavior. + The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + + + TIM15 + TIM15 address block description + TIM15 + 0x40014000 + + 0x0 + 0x6C + registers + + + TIM15_LPTIM3 + TIM15 and LPTIM3 global interrupt (combined with EXTI line 29) + 19 + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt if enabled + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - OC1REFC signal is used as trigger output (TRGO). + 0x4 + + + B_0x5 + Compare - OC2REFC signal is used as trigger output (TRGO). + 0x5 + + + + + TI1S + TI1 selection + 7 + 1 + read-write + + + B_0x0 + The TIMx_CH1 pin is connected to TI1 input + 0x0 + + + B_0x1 + The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) + + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) + + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (OC2 output) + + 10 + 1 + read-write + + + B_0x0 + OC2=0 when MOE=0 + 0x0 + + + B_0x1 + OC2=1 when MOE=0 + 0x1 + + + + + + + TIM15_SMCR + TIM15_SMCR + TIM15 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + 0x7 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (ITR0) + 0x0 + + + B_0x1 + Internal Trigger 1 (ITR1) + 0x1 + + + B_0x2 + Internal Trigger 2 (ITR2) + 0x2 + + + B_0x3 + Internal Trigger 3 (ITR3) + 0x3 + + + B_0x4 + TI1 Edge Detector (TI1F_ED) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (TI1FP1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (TI2FP2) + 0x6 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). + 0x1 + + + + + SMS_1 + SMS[3] + 16 + 1 + read-write + + + TS_1 + TS[4:3] + 20 + 2 + read-write + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred + 0x0 + + + B_0x1 + Trigger interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag + + 10 + 1 + read-write + + + + + TIM15_EGR + TIM15_EGR + TIM15 event generation register + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/Compare 2 generation + + 2 + 1 + write-only + + + COMG + Capture/Compare control update generation + + 5 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM15_CCMR1 + TIM15_CCMR1 + TIM15 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM15_CCMR1_ALTERNATE1 + TIM15_CCMR1_ALTERNATE1 + TIM15 capture/compare mode register 1 + TIM15_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, IC1 is mapped on TI2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, IC1 is mapped on TRC. + 0x3 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, IC2 is mapped on TI2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, IC2 is mapped on TI1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, IC2 is mapped on TRC. + 0x3 + + + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + CC2E + Capture/Compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity + + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity + + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value + + 0 + 16 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value + + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value + + 0 + 16 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register 2 + 0x38 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR2 + Capture/Compare 2 value + + 0 + 16 + read-write + + + + + TIM15_BDTR + TIM15_BDTR + TIM15 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable + + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable + + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity + + 10 + 1 + read-write + + + B_0x0 + COMP1 input is active low + 0x0 + + + B_0x1 + COMP1 input is active high + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity + + 11 + 1 + read-write + + + B_0x0 + COMP2 input is active low + 0x0 + + + B_0x1 + COMP2 input is active high + 0x1 + + + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input + + 0 + 4 + read-write + + + B_0x0 + TIM15_CH1 input + 0x0 + + + B_0x1 + TIM2_IC1 + 0x1 + + + B_0x2 + TIM3_IC1 + 0x2 + + + + + TI2SEL + selects TI2[0] to TI2[15] input + + 8 + 4 + read-write + + + B_0x0 + TIM15_CH2 input + 0x0 + + + B_0x1 + TIM2_IC2 + 0x1 + + + B_0x2 + TIM3_IC2 + 0x2 + + + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40014400 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 global interrupt + 20 + + + + TIM16_CR1 + TIM16_CR1 + TIM16 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + B_0x0 + 0x0 + + + B_0x1 + B_0x1 + 0x1 + + + B_0x2 + B_0x2 + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + + + TIM16_CR2 + TIM16_CR2 + TIM16 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + OIS1 + Output Idle state 1 (OC1 output) + + 8 + 1 + read-write + + + B_0x0 + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0x0 + + + B_0x1 + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (OC1N output) + + 9 + 1 + read-write + + + B_0x0 + OC1N=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + OC1N=1 after a dead-time when MOE=0 + 0x1 + + + + + + + TIM16_DIER + TIM16_DIER + TIM16 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + + + TIM16_SR + TIM16_SR + TIM16 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + + + TIM16_EGR + TIM16_EGR + TIM16 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + COMG + Capture/Compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM16_CCMR1 + TIM16_CCMR1 + TIM16 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input. + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N= + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + + + TIM16_CCMR1_ALTERNATE1 + TIM16_CCMR1_ALTERNATE1 + TIM16 capture/compare mode register 1 + TIM16_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 0x1 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output Compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - OC1REF is forced low. + 0x4 + + + B_0x5 + Force active level - OC1REF is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + + + TIM16_CCER + TIM16_CCER + TIM16 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - OC1N is not active. + 0x0 + + + B_0x1 + On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + OC1N active high + 0x0 + + + B_0x1 + OC1N active low + 0x1 + + + + + + + TIM16_CNT + TIM16_CNT + TIM16 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM16_PSC + TIM16_PSC + TIM16 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM16_ARR + TIM16_ARR + TIM16 auto-reload register + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + ARR + Auto-reload value + + 0 + 16 + read-write + + + + + TIM16_RCR + TIM16_RCR + TIM16 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter value + + 0 + 8 + read-write + + + + + TIM16_CCR1 + TIM16_CCR1 + TIM16 capture/compare register 1 + 0x34 + 16 + read-write + 0x0000 + 0xFFFF + + + CCR1 + Capture/Compare 1 value + + 0 + 16 + read-write + + + + + TIM16_BDTR + TIM16_BDTR + TIM16 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK and CCS clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input BRK is active low + 0x0 + + + B_0x1 + Break input BRK is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, BRK acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break Disarm + + 26 + 1 + read-write + + + B_0x0 + Break input BRK is armed + 0x0 + + + B_0x1 + Break input BRK is disarmed + 0x1 + + + + + BKBID + Break Bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input BRK in input mode + 0x0 + + + B_0x1 + Break input BRK in bidirectional mode + 0x1 + + + + + + + TIM16_DCR + TIM16_DCR + TIM16 DMA control register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + + + TIM16_DMAR + TIM16_DMAR + TIM16 DMA address for full transfer + 0x4C + 16 + read-write + 0x0000 + 0xFFFF + + + DMAB + DMA register for burst accesses + + 0 + 16 + read-write + + + + + TIM16_AF1 + TIM16_AF1 + TIM16 alternate function register 1 + 0x60 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + BRK BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + BKIN input disabled + 0x0 + + + B_0x1 + BKIN input enabled + 0x1 + + + + + BKCMP1E + BRK COMP1 enable + + 1 + 1 + read-write + + + B_0x0 + COMP1 input disabled + 0x0 + + + B_0x1 + COMP1 input enabled + 0x1 + + + + + BKCMP2E + BRK COMP2 enable + + 2 + 1 + read-write + + + B_0x0 + COMP2 input disabled + 0x0 + + + B_0x1 + COMP2 input enabled + 0x1 + + + + + BKINP + BRK BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + BKIN input is active low + 0x0 + + + B_0x1 + BKIN input is active high + 0x1 + + + + + BKCMP1P + BRK COMP1 input polarity + + 10 + 1 + read-write + + + B_0x0 + COMP1 input is active low + 0x0 + + + B_0x1 + COMP1 input is active high + 0x1 + + + + + BKCMP2P + BRK COMP2 input polarity + + 11 + 1 + read-write + + + B_0x0 + COMP2 input is active low + 0x0 + + + B_0x1 + COMP2 input is active high + 0x1 + + + + + + + TIM16_TISEL + TIM16_TISEL + TIM16 input selection register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects TI1[0] to TI1[15] input + + 0 + 4 + read-write + + + B_0x0 + TIM16_CH1 input + 0x0 + + + B_0x1 + LSI + 0x1 + + + B_0x2 + LSE + 0x2 + + + B_0x3 + RTC wakeup + 0x3 + + + B_0x4 + MCO2 + 0x4 + + + + + + + + + TSC + TSC address block description + TSC + 0x40024000 + + 0x0 + 0x50 + registers + + + TSC + TSC global interrupt + 21 + + + + TSC_CR + TSC_CR + TSC control register + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TSCE + Touch sensing controller enable +This bit is set and cleared by software to enable/disable the touch sensing controller. +Note: When the touch sensing controller is disabled, TSC registers settings have no effect. + 0 + 1 + read-write + + + B_0x0 + Touch sensing controller disabled + 0x0 + + + B_0x1 + Touch sensing controller enabled + 0x1 + + + + + START + Start a new acquisition +This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. + 1 + 1 + read-write + + + B_0x0 + Acquisition not started + 0x0 + + + B_0x1 + Start a new acquisition + 0x1 + + + + + AM + Acquisition mode +This bit is set and cleared by software to select the acquisition mode. +Note: This bit must not be modified when an acquisition is ongoing. + 2 + 1 + read-write + + + B_0x0 + Normal acquisition mode (acquisition starts as soon as START bit is set) + 0x0 + + + B_0x1 + Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) + 0x1 + + + + + SYNCPOL + Synchronization pin polarity +This bit is set and cleared by software to select the polarity of the synchronization input pin. + 3 + 1 + read-write + + + B_0x0 + Falling edge only + 0x0 + + + B_0x1 + Rising edge and high level + 0x1 + + + + + IODEF + I/O Default mode +This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). +Note: This bit must not be modified when an acquisition is ongoing. + 4 + 1 + read-write + + + B_0x0 + I/Os are forced to output push-pull low + 0x0 + + + B_0x1 + I/Os are in input floating + 0x1 + + + + + MCV + Max count value +These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. +Note: These bits must not be modified when an acquisition is ongoing. + 5 + 3 + read-write + + + B_0x0 + 255 + 0x0 + + + B_0x1 + 511 + 0x1 + + + B_0x2 + 1023 + 0x2 + + + B_0x3 + 2047 + 0x3 + + + B_0x4 + 4095 + 0x4 + + + B_0x5 + 8191 + 0x5 + + + B_0x6 + 16383 + 0x6 + + + + + PGPSC + Pulse generator prescaler +These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. + 12 + 3 + read-write + + + B_0x0 + f<sub>HCLK</sub> + 0x0 + + + B_0x1 + f<sub>HCLK</sub> /2 + 0x1 + + + B_0x2 + f<sub>HCLK</sub> /4 + 0x2 + + + B_0x3 + f<sub>HCLK</sub> /8 + 0x3 + + + B_0x4 + f<sub>HCLK</sub> /16 + 0x4 + + + B_0x5 + f<sub>HCLK</sub> /32 + 0x5 + + + B_0x6 + f<sub>HCLK</sub> /64 + 0x6 + + + B_0x7 + f<sub>HCLK</sub> /128 + 0x7 + + + + + SSPSC + Spread spectrum prescaler +This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). +Note: This bit must not be modified when an acquisition is ongoing. + 15 + 1 + read-write + + + B_0x0 + f<sub>HCLK</sub> + 0x0 + + + B_0x1 + f<sub>HCLK</sub> /2 + 0x1 + + + + + SSE + Spread spectrum enable +This bit is set and cleared by software to enable/disable the spread spectrum feature. +Note: This bit must not be modified when an acquisition is ongoing. + 16 + 1 + read-write + + + B_0x0 + Spread spectrum disabled + 0x0 + + + B_0x1 + Spread spectrum enabled + 0x1 + + + + + SSD + Spread spectrum deviation +These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. +... +Note: These bits must not be modified when an acquisition is ongoing. + 17 + 7 + read-write + + + B_0x0 + 1x t<sub>SSCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>SSCLK</sub> + 0x1 + + + B_0x7F + 128x t<sub>SSCLK</sub> + 0x7F + + + + + CTPL + Charge transfer pulse low +These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from C<sub>X</sub> to C<sub>S</sub>). +... +Note: These bits must not be modified when an acquisition is ongoing. +Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. + 24 + 4 + read-write + + + B_0x0 + 1x t<sub>PGCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>PGCLK</sub> + 0x1 + + + B_0xF + 16x t<sub>PGCLK</sub> + 0xF + + + + + CTPH + Charge transfer pulse high +These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of C<sub>X</sub>). +... +Note: These bits must not be modified when an acquisition is ongoing. + 28 + 4 + read-write + + + B_0x0 + 1x t<sub>PGCLK</sub> + 0x0 + + + B_0x1 + 2x t<sub>PGCLK</sub> + 0x1 + + + B_0xF + 16x t<sub>PGCLK</sub> + 0xF + + + + + + + TSC_IER + TSC_IER + TSC interrupt enable register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIE + End of acquisition interrupt enable +This bit is set and cleared by software to enable/disable the end of acquisition interrupt. + 0 + 1 + read-write + + + B_0x0 + End of acquisition interrupt disabled + 0x0 + + + B_0x1 + End of acquisition interrupt enabled + 0x1 + + + + + MCEIE + Max count error interrupt enable +This bit is set and cleared by software to enable/disable the max count error interrupt. + 1 + 1 + read-write + + + B_0x0 + Max count error interrupt disabled + 0x0 + + + B_0x1 + Max count error interrupt enabled + 0x1 + + + + + + + TSC_ICR + TSC_ICR + TSC interrupt clear register + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAIC + End of acquisition interrupt clear +This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect. + 0 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding EOAF of the TSC_ISR register + 0x1 + + + + + MCEIC + Max count error interrupt clear +This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect. + 1 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Clears the corresponding MCEF of the TSC_ISR register + 0x1 + + + + + + + TSC_ISR + TSC_ISR + TSC interrupt status register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EOAF + End of acquisition flag +This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register. + 0 + 1 + read-only + + + B_0x0 + Acquisition is ongoing or not started + 0x0 + + + B_0x1 + Acquisition is complete + 0x1 + + + + + MCEF + Max count error flag +This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register. + 1 + 1 + read-only + + + B_0x0 + No max count error (MCE) detected + 0x0 + + + B_0x1 + Max count error (MCE) detected + 0x1 + + + + + + + TSC_IOHCR + TSC_IOHCR + TSC I/O hysteresis control register + 0x10 + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 0 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 1 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 2 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G1_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 3 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 4 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 5 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 6 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G2_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 7 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 8 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 9 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 10 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G3_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 11 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 12 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 13 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 14 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G4_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 15 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 16 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 17 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 18 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G5_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 19 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 20 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 21 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 22 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G6_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 23 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO1 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 24 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO2 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 25 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO3 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 26 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + G7_IO4 + Gx_IOy Schmitt trigger hysteresis mode +These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. +Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). + 27 + 1 + read-write + + + B_0x0 + Gx_IOy Schmitt trigger hysteresis disabled + 0x0 + + + B_0x1 + Gx_IOy Schmitt trigger hysteresis enabled + 0x1 + + + + + + + TSC_IOASCR + TSC_IOASCR + TSC I/O analog switch control register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 0 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 1 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 2 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G1_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 3 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 4 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 5 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 6 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G2_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 7 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 8 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 9 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 10 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G3_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 11 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 12 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 13 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 14 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G4_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 15 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 16 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 17 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 18 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G5_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 19 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 20 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 21 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 22 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G6_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 23 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO1 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 24 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO2 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 25 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO3 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 26 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + G7_IO4 + Gx_IOy analog switch enable +These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. +Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). + 27 + 1 + read-write + + + B_0x0 + Gx_IOy analog switch disabled (opened) + 0x0 + + + B_0x1 + Gx_IOy analog switch enabled (closed) + 0x1 + + + + + + + TSC_IOSCR + TSC_IOSCR + TSC I/O sampling control register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 0 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 1 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 2 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G1_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 3 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 4 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 5 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 6 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G2_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 7 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 8 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 9 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 10 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G3_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 11 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 12 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 13 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 14 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G4_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 15 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 16 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 17 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 18 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G5_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 19 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 20 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 21 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 22 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G6_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 23 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO1 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 24 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO2 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 25 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO3 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 26 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + G7_IO4 + Gx_IOy sampling mode +These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 27 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as sampling capacitor + 0x1 + + + + + + + TSC_IOCCR + TSC_IOCCR + TSC I/O channel control register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 0 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 1 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 2 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G1_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 3 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 4 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 5 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 6 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G2_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 7 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 8 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 9 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 10 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G3_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 11 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 12 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 13 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 14 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G4_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 15 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 16 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 17 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 18 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G5_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 19 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 20 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 21 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 22 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G6_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 23 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO1 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 24 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO2 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 25 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO3 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 26 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + G7_IO4 + Gx_IOy channel mode +These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. +Note: These bits must not be modified when an acquisition is ongoing. +Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. + 27 + 1 + read-write + + + B_0x0 + Gx_IOy unused + 0x0 + + + B_0x1 + Gx_IOy used as channel + 0x1 + + + + + + + TSC_IOGCSR + TSC_IOGCSR + TSC I/O group control status register + 0x30 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + G1E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 0 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G2E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 1 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G3E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 2 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G4E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 3 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G5E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 4 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G6E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 5 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G7E + Analog I/O group x enable +These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. + 6 + 1 + read-write + + + B_0x0 + Acquisition on analog I/O group x disabled + 0x0 + + + B_0x1 + Acquisition on analog I/O group x enabled + 0x1 + + + + + G1S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 16 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G2S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 17 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G3S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 18 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G4S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 19 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G5S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 20 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G6S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 21 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + G7S + Analog I/O group x status +These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. +Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. + 22 + 1 + read-only + + + B_0x0 + Acquisition on analog I/O group x is ongoing or not started + 0x0 + + + B_0x1 + Acquisition on analog I/O group x is complete + 0x1 + + + + + + + TSC_IOG1CR + TSC_IOG1CR + TSC I/O group 1 counter register + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG2CR + TSC_IOG2CR + TSC I/O group 2 counter register + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG3CR + TSC_IOG3CR + TSC I/O group 3 counter register + 0x3C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG4CR + TSC_IOG4CR + TSC I/O group 4 counter register + 0x40 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG5CR + TSC_IOG5CR + TSC I/O group 5 counter register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG6CR + TSC_IOG6CR + TSC I/O group 6 counter register + 0x48 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + TSC_IOG7CR + TSC_IOG7CR + TSC I/O group 7 counter register + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value +These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across C<sub>S</sub> has reached the threshold). + 0 + 14 + read-only + + + + + + + USART1 + USART address block description + USART + 0x40013800 + + 0x0 + 0x30 + registers + + + USART1 + USART1 global interrupt (combined with EXTI line 25) + 27 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + None + 31 + 1 + read-write + + + + + USART_CR1_ALTERNATE + USART_CR1_ALTERNATE + USART control register 1 + USART_CR1 + 0x00 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method +This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in Active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and Active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous Slave mode enable +When the SLVEN bit is set, the Synchronous slave mode is enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the USART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +This bit can only be written when the USART is disabled (UE=0). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in Synchronous mode. +The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase +This bit is used to select the phase of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure1233 and Figure1234) +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +This bit enables the user to select the polarity of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +This bit can only be written when the USART is disabled (UE=0). +Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable +This bit enables the user to enable the CK pin. +This bit can only be written when the USART is disabled (UE=0). +Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. +In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +Note: UE = 1 + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits +These bits are used for programming the stop bits. +This bitfield can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0.5 stop bit. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1.5 stop bits + 0x3 + + + + + LINEN + LIN mode enable +This bit is set and cleared by software. +The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. ((V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable +This bit is set and cleared by software. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode +These bits are set and cleared by software. +This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). +Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable +This bit is set and cleared by software. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node +These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1or UDR = 1 in the USART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable +This bit is set and cleared by software. +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable +This bit is used for enabling Smartcard mode. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the USART is disabled (UE=0). +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the USART is disabled (UE=0) +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable +This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data are written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the USART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode) + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826. + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count +This bitfield specifies the number of retries for transmission and reception in Smartcard mode. +In Transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). +In Reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). +This bitfield must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. +0x1 to 0x7: number of automatic retransmission attempts (before signaling error) +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in Transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + + + WUFIE + Wake-up from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate +BRR[15:4] +BRR[15:4] correspond to USARTDIV[15:4] +BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared. + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value +PSC[7:0] = IrDA Normal and Low-power baud rate +This bitfield is used for programming the prescaler for dividing the USART source clock to achieve the low-power frequency: +The source clock is divided by the value given in the register (8 significant bits): +... +PSC[4:0]: Prescaler value +This bitfield is used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: +... +This bitfield can only be written when the USART is disabled (UE=0). +Note: Bits [7:5] must be kept cleared if Smartcard mode is used. +Note: This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to Section131.4: USART implementation on page1826. + 0 + 8 + read-write + + + B_0x0_SMARTCARD_MODE + Reserved - do not program this value + 0x0 + + + B_0x1_SMARTCARD_MODE + divides the source clock by 2 + 0x1 + + + B_0x2_SMARTCARD_MODE + divides the source clock by 4 + 0x2 + + + B_0x3_SMARTCARD_MODE + divides the source clock by 6 + 0x3 + + + + + GT + Guard time value +This bitfield is used to program the Guard time value in terms of number of baud clock periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value +This bitfield gives the Receiver timeout value in terms of number of bit duration. +In Standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. +Note: This value must only be programmed once per received character. + 0 + 24 + read-write + + + BLEN + Block Length +This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). +This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. +Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request +Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 0 + 1 + write-only + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software must wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This enables to discard the received data without reading them, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section131.5.9: Tolerance of the USART receiver to clock deviation on page1845). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. +RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag behaves as follows: +When TDN = 0, the TC flag is set when the transmission of a frame containing data is complete and when TXE/TXFE is set. +When TDN is equal to the number of data in the TXFIFO, the TC flag is set when TXFIFO is empty and TDN is reached. +When TDN is greater than the number of data in the TXFIFO, TC remains cleared until the TXFIFO is filled again to reach the programmed number of data to be transferred. +When TDN is less than the number of data in the TXFIFO, TC is set when TDN is reached even if the TXFIFO is not empty. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. +An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF must be checked prior to writing in TXFIFO (TXFNF and TXFE is set at the same time). +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if EOBIE1=11 in the USART_CR1 register. +It is cleared by software, writing 1 to EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-only + + + TXFE + TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO Full +This bit is set by hardware when the number of received data corresponds to RXFIFO1size1+11 (RXFIFO full + 1 data in the USART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section131.4: USART implementation on page1826. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. +Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in Reception mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE1=11 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section131.5.9: Tolerance of the USART receiver to clock deviation on page1845). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. The TC flag is set when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is cleared by software by writing 1 to the TCCF in the USART_ICR register or by writing to the USART_TDR register. + 6 + 1 + read-only + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). +An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if EOBIE1=11 in the USART_CR1 register. +It is cleared by software, writing 1 to EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 19 + 1 + read-only + + + B_0x0 + Receiver in Active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag +This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section131.4: USART implementation on page1826. + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to Section131.4: USART implementation on page1826. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register. + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register. + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 8 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 11 + 1 + write-only + + + EOBCF + End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register. +Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826 + 13 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register. + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure1227). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure1227). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The USART input clock can be divided by a prescaler factor: +Remaining combinations: Reserved +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + USART2 + 0x40004400 + + USART2_LPUART2 + USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) + 28 + + + + USART3 + 0x40004800 + + USART3_LPUART1 + USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) + 29 + + + + USART4 + 0x40004C00 + + USART4_LPUART3 + USART4 and LPUART3 global interrupt (combined with EXTI lines 20 and 34) + 30 + + + + USB + USB address block description + USB + 0x40005C00 + + 0x0 + 0x5C + registers + + + USB + USB global interrupt (combined with EXTI line 33) + 8 + + + + USB_CHEP0R + USB_CHEP0R + USB endpoint/channel 0 register + 0x0 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP1R + USB_CHEP1R + USB endpoint/channel 1 register + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP2R + USB_CHEP2R + USB endpoint/channel 2 register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP3R + USB_CHEP3R + USB endpoint/channel 3 register + 0xC + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP4R + USB_CHEP4R + USB endpoint/channel 4 register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP5R + USB_CHEP5R + USB endpoint/channel 5 register + 0x14 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP6R + USB_CHEP6R + USB endpoint/channel 6 register + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP7R + USB_CHEP7R + USB endpoint/channel 7 register + 0x1C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address +Device mode +Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. +Host mode +Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction. + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers +If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). +If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1. + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted +Device mode +This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written. +Host mode +Same as VTRX behavior but for USB OUT and SETUP transactions. + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind +The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table1217 summarizes the different meanings. +DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section134.5.3: Double-buffered endpoints and usage in Device mode. +STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required. + 8 + 1 + read-write + + + UTYPE + USB type of transaction +These bits configure the behavior of this endpoint/channel as described in Table1216: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. +Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. +The usage of isochronous channels/endpoints is explained in Section134.5.5: Isochronous transfers in Device mode + 9 + 2 + read-write + + + SETUP + Setup transaction completed +Device mode +This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. +Host mode +This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated. + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers +Device mode +These bits contain information about the endpoint status, which are listed in Table1215: Reception status encoding on page11025. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX1=11) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. +Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint is defined as isochronous, its status can be only VALID or DISABLED, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. +Host mode +These bits are the host application controls to start, retry, or abort host transactions driven by the channel. +These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: +- DISABLE +DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. +- VALID +A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. +VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. +- NAK +NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE +- STALL +STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate. + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers +If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (01=1DATA0, 11=1DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). +If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section134.5.3: Double-buffered endpoints and usage in Device mode). +If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section134.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. +This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1. + 14 + 1 + write-only + + + VTRX + USB valid transaction received +Device mode +This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. +A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. +This bit is read/write but only 0 can be written, writing 1 has no effect. +Host mode +This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. +- A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. +- A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. +- A transaction ended with ACK handshake sets this bit +If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. +If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. +- A transaction ended with error sets this bit. +Errors can be seen via the bits ERR_RX (host mode only). +This bit is read/write but only 0 can be written, writing 1 has no effect. + 15 + 1 + read-write + + + DEVADDR + Host mode +Device address assigned to the endpoint during the enumeration process. + 16 + 7 + read-write + + + NAK + Host mode +This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device. + 23 + 1 + read-write + + + LS_EP + Low speed endpoint + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction +Host mode +This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated. + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction +Host mode +This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. +Coding of the received error: + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CNTR + USB_CNTR + USB control register + 0x40 + 0x20 + 0x00000003 + 0xFFFFFFFF + + + USBRST + USB Reset +Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. +Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software. + 0 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + USB core is under reset + 0x1 + + + + + PDWN + Power down +This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. + 1 + 1 + read-write + + + B_0x0 + Exit power down + 0x0 + + + B_0x1 + Enter power down mode + 0x1 + + + + + SUSPRDY + Suspend state effective +This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wake-up logic and single ended receiver is kept alive to detect remote wake-up or resume events. +Software must poll this bit to confirm it to be set before any STOP mode entry. +This bit is cleared by hardware simultaneously to the WAKEUP flag being set. + 2 + 1 + read-only + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Suspend state + 0x1 + + + + + SUSPEN + Suspend state enable +Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 31ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. +As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY1=11 acknowledge the suspend request. +This bit is cleared by hardware simultaneous with the WAKEUP flag set. +Software can set this bit when host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. +As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. +This bit is cleared by hardware simultaneous with the WAKEUP flag set. + 3 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + Enter L1/L2 suspend + 0x1 + + + + + L2RES + L2 remote wake-up / resume driver +Device mode +The microcontroller can set this bit to send remote wake-up signaling to the host. It must be activated, according to USB specifications, for no less than 11ms and no more than 151ms after which the host PC is ready to drive the resume sequence up to its end. +Host mode +Software sets this bit to send resume signaling to the device. +Software clears this bit to send end of resume to device and restart SOF generation. +In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send L2 resume signaling to device + 0x1 + + + + + L1RES + L1 remote wake-up / resume driver + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + send 50 micro s remote wake up signaling to host + 0x1 + + + + + L1REQM + LPM L1 state request interrupt mask + 7 + 1 + read-write + + + B_0x0 + LPM L1 state request (L1REQ) interrupt disabled. + 0x0 + + + B_0x1 + L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ESOFM + Expected start of frame interrupt mask + 8 + 1 + read-write + + + B_0x0 + Expected start of frame (ESOF) interrupt disabled. + 0x0 + + + B_0x1 + ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SOFM + Start of frame interrupt mask + 9 + 1 + read-write + + + B_0x0 + SOF interrupt disabled. + 0x0 + + + B_0x1 + SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + RST_DCONM + USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask + 10 + 1 + read-write + + + B_0x0 + RESET interrupt disabled. + 0x0 + + + B_0x1 + RESET interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SUSPM + Suspend mode interrupt mask + 11 + 1 + read-write + + + B_0x0 + Suspend mode request (SUSP) interrupt disabled. + 0x0 + + + B_0x1 + SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + WKUPM + Wake-up interrupt mask + 12 + 1 + read-write + + + B_0x0 + WKUP interrupt disabled. + 0x0 + + + B_0x1 + WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ERRM + Error interrupt mask + 13 + 1 + read-write + + + B_0x0 + ERR interrupt disabled. + 0x0 + + + B_0x1 + ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + PMAOVRM + Packet memory area over / underrun interrupt mask + 14 + 1 + read-write + + + B_0x0 + PMAOVR interrupt disabled. + 0x0 + + + B_0x1 + PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + CTRM + Correct transfer interrupt mask + 15 + 1 + read-write + + + B_0x0 + Correct transfer (CTR) interrupt disabled. + 0x0 + + + B_0x1 + CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + THR512M + 512 byte threshold interrupt mask + 16 + 1 + read-write + + + B_0x0 + 512 byte threshold interrupt disabled + 0x0 + + + B_0x1 + 512 byte threshold interrupt enabled + 0x1 + + + + + DDISCM + Device disconnection mask +Host mode + 17 + 1 + read-write + + + B_0x0 + Device disconnection interrupt disabled + 0x0 + + + B_0x1 + Device disconnection interrupt enabled + 0x1 + + + + + HOST + HOST mode +HOST bit selects betweens host or device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. + 31 + 1 + read-write + + + B_0x0 + USB Device function + 0x0 + + + B_0x1 + USB host function (Reserved, host function is not available in these products, see Section134.3: USB implementation) + 0x1 + + + + + + + USB_ISTR + USB_ISTR + USB interrupt status register + 0x44 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + IDN + Device Endpoint / host channel identification number +These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: two levels are defined, in order of priority: isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only. + 0 + 4 + read-only + + + DIR + Direction of transaction +This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. +If DIR bit1=10, VTTX bit is set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). +If DIR bit1=11, VTRX bit or both VTTX/VTRX are set in the USB_CHEPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. +This information can be used by the application software to access the USB_CHEPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only. + 4 + 1 + read-only + + + L1REQ + LPM L1 state request +Device mode +This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only 0 can be written and writing 1 has no effect. + 7 + 1 + read-write + + + ESOF + Expected start of frame +Device mode +This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 11ms, but if the device does not receive it properly, the suspend timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the suspend timer is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect. + 8 + 1 + read-write + + + SOF + Start of frame +This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 11ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this can be useful for isochronous applications). This bit is read/write but only 0 can be written and writing 1 has no effect. + 9 + 1 + read-write + + + RST_DCON + USB reset request (Device mode) or device connect/disconnect (Host mode) +Device mode +This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. +Host mode +This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22 cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times consecutively from connected state. + 10 + 1 + read-write + + + SUSP + Suspend mode request +Device mode +This bit is set by the hardware when no traffic has been received for 31ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can be written and writing 1 has no effect. + 11 + 1 + read-write + + + WKUP + Wake-up +This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (for example wake-up unit) about the start of the resume process. This bit is read/write but only 0 can be written and writing 1 has no effect. + 12 + 1 + read-write + + + ERR + Error +This flag is set whenever one of the errors listed below has occurred: +NANS: No ANSwer. The timeout for a host response has expired. +CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in the data, was wrong. +BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. +FVIO: Framing format violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). +The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (for example loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only 0 can be written and writing 1 has no effect. + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / underrun +This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host retries the transaction. The PMAOVR interrupt must never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only 0 can be written and writing 1 has no effect. + 14 + 1 + read-write + + + CTR + Completed transfer in host mode +This bit is set by the hardware to indicate that an endpoint/channel has successfully completed a transaction; using DIR and IDN bits software can determine which endpoint/channel requested the interrupt. This bit is read-only. + 15 + 1 + read-only + + + THR512 + 512 byte threshold interrupt +This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel. + 16 + 1 + read-write + + + DDISC + Device connection +Host mode +This bit is set when a device connection is detected. This bit is read/write but only 0 can be written and writing 1 has no effect. + 17 + 1 + read-write + + + DCON_STAT + Device connection status +Host mode: +This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected. + 29 + 1 + read-only + + + B_0x0 + No device connected + 0x0 + + + B_0x1 + FS or LS device connected to the host + 0x1 + + + + + LS_DCON + Low speed device connected +Host mode: +This bit is set by hardware when an LS device connection is detected. Device connection is signaled after LS J-state is sampled for 22 consecutive cycles of the USB clock (481MHz) from the unconnected state. + 30 + 1 + read-only + + + + + USB_FNR + USB_FNR + USB frame number register + 0x48 + 0x20 + 0x00000000 + 0xFFFFF000 + + + FN + Frame number +This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for isochronous transfers. This bit field is updated on the generation of an SOF interrupt. + 0 + 11 + read-only + + + LSOF + Lost SOF +Device mode +These bits are written by the hardware when an ESOF interrupt is generated, counting the number of consecutive SOF packets lost. At the reception of an SOF packet, these bits are cleared. + 11 + 2 + read-only + + + LCK + Locked +Device mode +This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs. + 13 + 1 + read-only + + + RXDM + Receive data - line status +This bit can be used to observe the status of received data minus upstream port data line. It can be used during end-of-suspend routines to help determining the wake-up event. + 14 + 1 + read-only + + + RXDP + Receive data + line status +This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wake-up event. + 15 + 1 + read-only + + + + + USB_DADDR + USB_DADDR + USB Device address + 0x4C + 0x20 + 0x00000000 + 0xFFFFFFFF + + + ADD + Device address +Device mode +These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel address (EA) field in the associated USB_CHEPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. +Host mode +These bits contain the address transmitted with the LPM transaction + 0 + 7 + read-write + + + EF + Enable function +This bit is set by the software to enable the USB Device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at 0 no transactions are handled, irrespective of the settings of USB_CHEPnR registers. + 7 + 1 + read-write + + + + + USB_LPMCSR + USB_LPMCSR + LPM control and status register + 0x54 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + LPMEN + LPM support enable +Device mode +This bit is set by the software to enable the LPM support within the USB Device. If this bit is at 0 no LPM transactions are handled. + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable +Device mode: +The NYET/ACK is returned only on a successful LPM transaction: +No errors in both the EXT token and the LPM token (else ERROR) +A valid bLinkState = 0001B (L1) is received (else STALL) + 1 + 1 + read-write + + + B_0x0 + the valid LPM token is NYET. + 0x0 + + + B_0x1 + the valid LPM token is ACK. + 0x1 + + + + + REMWAKE + bRemoteWake value +Device mode +This bit contains the bRemoteWake value received with last ACKed LPM Token + 3 + 1 + read-only + + + BESL + BESL value +Device mode +These bits contain the BESL value received with last ACKed LPM Token + 4 + 4 + read-only + + + + + USB_BCDR + USB_BCDR + Battery charging detector + 0x58 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + BCDEN + Battery charging detector (BCD) enable +Device mode +This bit is set by the software to enable the BCD support within the USB Device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD must be placed in OFF mode by clearing this bit to 0 in order to allow the normal USB operation. + 0 + 1 + read-write + + + DCDEN + Data contact detection (DCD) mode enable +Device mode +This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) must be selected to work correctly. + 1 + 1 + read-write + + + PDEN + Primary detection (PD) mode enable +Device mode +This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) must be selected to work correctly. + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode enable +Device mode +This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) must be selected to work correctly. + 3 + 1 + read-write + + + DCDET + Data contact detection (DCD) status +Device mode +This bit gives the result of DCD. + 4 + 1 + read-only + + + B_0x0 + data lines contact not detected. + 0x0 + + + B_0x1 + data lines contact detected. + 0x1 + + + + + PDET + Primary detection (PD) status +Device mode +This bit gives the result of PD. + 5 + 1 + read-only + + + B_0x0 + no BCD support detected (connected to SDP or proprietary device). + 0x0 + + + B_0x1 + BCD support detected (connected to ACA, CDP or DCP). + 0x1 + + + + + SDET + Secondary detection (SD) status +Device mode +This bit gives the result of SD. + 6 + 1 + read-only + + + B_0x0 + CDP detected. + 0x0 + + + B_0x1 + DCP detected. + 0x1 + + + + + PS2DET + DM pull-up detection status +Device mode +This bit is active only during PD and gives the result of comparison between DM voltage level and V<sub>LGC</sub> threshold. In normal situation, the DM level must be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. + 7 + 1 + read-only + + + B_0x0 + Normal port detected (connected to SDP, ACA, CDP or DCP). + 0x0 + + + B_0x1 + PS2 port or proprietary charger detected. + 0x1 + + + + + DPPU_DPD + DP pull-up / DPDM pull-down +Device mode +This bit is set by software to enable the embedded pull-up on DP line. Clearing it to 0 can be used to signal disconnect to the host when needed by the user software. +Host mode +This bit is set by software to enable the embedded pull-down on DP and DM lines. + 15 + 1 + read-write + + + + + + + VREFBUF + VREFBUF address block description + VREFBUF + 0x40010030 + + 0x0 + 0x8 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x00 + 0x20 + 0x00000002 + 0xFFFFFFFF + + + ENVR + Voltage reference buffer mode enable +This bit is used to enable the voltage reference buffer mode. + 0 + 1 + read-write + + + B_0x0 + Internal voltage reference mode disable (external voltage reference mode). + 0x0 + + + B_0x1 + Internal voltage reference mode (reference buffer enable or hold mode) enable. + 0x1 + + + + + HIZ + High impedance mode +This bit controls the analog switch to connect or not the V<sub>REF+</sub> pin. +Refer to Table172: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. + 1 + 1 + read-write + + + B_0x0 + V<sub>REF+</sub> pin is internally connected to the voltage reference buffer output. + 0x0 + + + B_0x1 + V<sub>REF+</sub> pin is high impedance. + 0x1 + + + + + VRS + Voltage reference scale +This bit selects the value generated by the voltage reference buffer. + 2 + 1 + read-write + + + B_0x0 + Voltage reference set to V<sub>REF_OUT1</sub> (around 2.0481V). + 0x0 + + + B_0x1 + Voltage reference set to V<sub>REF_OUT2</sub> (around 2.51V). + 0x1 + + + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + B_0x0 + the voltage reference buffer output is not ready. + 0x0 + + + B_0x1 + the voltage reference buffer output reached the requested level. + 0x1 + + + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x04 + 0x20 + 0x00000000 + 0xFFFFFF00 + + + TRIM + None + 0 + 6 + read-write + + + + + + + WWDG + WWDG address block description + WWDG + 0x40002C00 + + 0x0 + 0xC + registers + + + WWDG + Window watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + WWDG control register + 0x000 + 0x20 + 0x0000007F + 0xFFFFFFFF + + + T + 7-bit counter (MSB to LSB) +These bits contain the value of the watchdog counter, decremented every +(4096 x 2<sup>WDGTB[2:0]</sup>) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). + 0 + 7 + read-write + + + WDGA + Activation bit +This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset. + 7 + 1 + read-write + + + B_0x0 + Watchdog disabled + 0x0 + + + B_0x1 + Watchdog enabled + 0x1 + + + + + + + WWDG_CFR + WWDG_CFR + WWDG configuration register + 0x004 + 0x20 + 0x0000007F + 0xFFFFFFFF + + + W + 7-bit window value +These bits contain the window value to be compared with the down-counter. + 0 + 7 + read-write + + + EWI + Early wake-up interrupt enable +Set by software and cleared by hardware after a reset. When set, an interrupt occurs whenever the counter reaches the value 0x40. + 9 + 1 + read-write + + + WDGTB + Timer base +The timebase of the prescaler can be modified as follows: + 11 + 3 + read-write + + + B_0x0 + CK counter clock (PCLK div 4096) div 1 + 0x0 + + + B_0x1 + CK counter clock (PCLK div 4096) div 2 + 0x1 + + + B_0x2 + CK counter clock (PCLK div 4096) div 4 + 0x2 + + + B_0x3 + CK counter clock (PCLK div 4096) div 8 + 0x3 + + + B_0x4 + CK counter clock (PCLK div 4096) div 16 + 0x4 + + + B_0x5 + CK counter clock (PCLK div 4096) div 32 + 0x5 + + + B_0x6 + CK counter clock (PCLK div 4096) div 64 + 0x6 + + + B_0x7 + CK counter clock (PCLK div 4096) div 128 + 0x7 + + + + + + + WWDG_SR + WWDG_SR + WWDG status register + 0x008 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + EWIF + Early wake-up interrupt flag +This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled. + 0 + 1 + read-write + + + + + + + diff --git a/svd/STM32U0xx/STM32U0x.svd b/svd/STM32U0xx/STM32U0x.svd new file mode 100644 index 0000000..eeb08d8 --- /dev/null +++ b/svd/STM32U0xx/STM32U0x.svd @@ -0,0 +1,1583 @@ + + + + ARM Ltd. + ARM + Cortex_M0PLUS + 1.2 + Cortex-M0+ core descriptions, generated from ARM develloper studio + + CM0PLUS + r0p0 + little + true + false + 8 + true + + 8 + 32 + + + Control + System Control registers + 0xE000ED04 + + 0x0 + 0xE0 + registers + + + + ICSR + ICSR + ICSR + 0x0 + 0x20 + read-write + + + NMIPENDSET + NMIPENDSET + 31 + 1 + + + Do_not_activate + 0x0 + + + Activate_NMI_exception + 0x1 + + + + + PENDSVSET + PENDSVSET + 28 + 1 + + + Do_not_set + 0x0 + + + Set_pending + 0x1 + + + + + PENDSVCLR + PENDSVCLR + 27 + 1 + + + Do_not_clear + 0x0 + + + Clear_pending + 0x1 + + + + + PENDSTSET + PENDSTSET + 26 + 1 + + + Do_not_set + 0x0 + + + Set_pending + 0x1 + + + + + PENDSTCLR + PENDSTCLR + 25 + 1 + + + Do_not_clear + 0x0 + + + Clear_pending + 0x1 + + + + + ISRPREEMPT + ISRPREEMPT + 23 + 1 + + + Will_not_service + 0x0 + + + Will_service_pending_exception + 0x1 + + + + + ISRPENDING + ISRPENDING + 22 + 1 + + + Interrupt_not_pending + 0x0 + + + Interrupt_pending + 0x1 + + + + + VECTPENDING + VECTPENDING + 12 + 9 + + + VECTACTIVE + VECTACTIVE + 0 + 9 + + + + + AIRCR + AIRCR + AIRCR + 0x8 + 0x20 + read-write + + + VECTKEY + VECTKEY + 16 + 16 + + + VECTKEYSTAT + UNKNOWN + 16 + 16 + + + ENDIANNESS + ENDIANNESS + 15 + 1 + + + Little_endian + 0x0 + + + Big_endian + 0x1 + + + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + Do_not_request_reset + 0x0 + + + Request_reset + 0x1 + + + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + Do_not_clear + 0x0 + + + Clear_state_information + 0x1 + + + + + + + CCR + CCR + CCR + 0x0 + 0x20 + read-only + + + STKALIGN + STKALIGN + 9 + 1 + + + UNALIGN_TRP + UNALIGN_TRP + 3 + 1 + + + + + SHPR2 + SHPR2 + SHPR2 + 0x18 + 0x20 + read-write + + + PRI_11 + PRI_11 + 30 + 2 + + + + + SHPR3 + SHPR3 + SHPR3 + 0x1C + 0x20 + read-write + + + PRI_15 + PRI_15 + 30 + 2 + + + PRI_14 + PRI_14 + 22 + 2 + + + + + SHCSR + SHCSR + SHCSR + 0x20 + 0x20 + read-write + + + SVCALLPENDED + SVCALLPENDED + 15 + 1 + + + Not_pending + 0x0 + + + Pending + 0x1 + + + + + + + VTOR + VTOR + VTOR + 0x4 + 0x20 + read-write + + + TBLOFF + TBLOFF + 7 + 25 + + + TBLBASE + TBLBASE + 29 + 1 + + + CODE + 0 + + + SRAM + 1 + + + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x24 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Architecture + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 7 + 25 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + + + MPU + Memory Protection Unit registers + 0xE000ED90 + + 0x0 + 0x14 + registers + + + + MPU_TYPE + MPU_TYPE + MPU Type Register + 0x0 + 0x20 + read-only + + + IREGION + IREGION + 16 + 8 + + + DREGION + DREGION + 8 + 8 + + + SEPARATE + SEPARATE + 0 + 1 + + + + + MPU_CTRL + MPU_CTRL + MPU Control Register + 0x4 + 0x20 + read-write + + + PRIVDEFENA + PRIVDEFENA + 2 + 1 + + + Disabled + 0x0 + + + Enabled + 0x1 + + + + + HFNMIENA + HFNMIENA + 1 + 1 + + + Disabled + 0x0 + + + Enabled + 0x1 + + + + + ENABLE + ENABLE + 0 + 1 + + + Disabled + 0x0 + + + Enabled + 0x1 + + + + + + + MPU_RNR + MPU_RNR + MPU Region Number Register + 0x8 + 0x20 + read-write + + + REGION + REGION + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU Region Base Address Register + 0xC + 0x20 + read-write + + + ADDR + ADDR + 8 + 24 + + + VALID + VALID + 4 + 1 + + + REGION + REGION + 0 + 4 + + + + + MPU_RASR + MPU_RASR + MPU Region Attribute and Size Register + 0x10 + 0x20 + read-write + + + XN + XN + 28 + 1 + + + Execution_permitted + 0x0 + + + Execution_not_permitted + 0x1 + + + + + AP + AP + 24 + 3 + + + No_access + 0x0 + + + Privileged_RW + 0x1 + + + Privileged_RW_Unprivileged_RO + 0x2 + + + Full_access + 0x3 + + + Reserved + 0x4 + + + Privileged_RO + 0x5 + + + Privileged_RO_Unprivileged_RO + 0x6 + + + Privileged_RO_Unprivileged_RO + 0x7 + + + + + S + Shareable memory attribute + 18 + 1 + + + C + memory attribute + 17 + 1 + + + B + memory attribute + 16 + 1 + + + SRD + SRD + 8 + 8 + + + SIZE + SIZE + 1 + 5 + + + Reserved + 0x0 + + + Reserved_ + 0x1 + + + Reserved__ + 0x2 + + + Reserved___ + 0x3 + + + Reserved____ + 0x4 + + + Reserved_____ + 0x5 + + + Reserved______ + 0x6 + + + _256B + 0x7 + + + _512B + 0x8 + + + _1KB + 0x9 + + + _2KB + 0xa + + + _4KB + 0xb + + + _8KB + 0xc + + + _16KB + 0xd + + + _32KB + 0xe + + + _64KB + 0xf + + + _128KB + 0x10 + + + _256KB + 0x11 + + + _512KB + 0x12 + + + _1MB + 0x13 + + + _2MB + 0x14 + + + _4MB + 0x15 + + + _8MB + 0x16 + + + _16MB + 0x17 + + + _32MB + 0x18 + + + _64MB + 0x19 + + + _128MB + 0x1a + + + _256MB + 0x1b + + + _512MB + 0x1c + + + _1GB + 0x1d + + + _2GB + 0x1e + + + _4GB + 0x1f + + + + + ENABLE + ENABLE + 0 + 1 + + + Disabled + 0x0 + + + Enabled + 0x1 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0x0 + 0x320 + registers + + + + ISER + ISER + Interrupt Set Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER + ICER + Interrupt Clear Enable Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR + ISPR + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR + ICPR + Interrupt Clear-Pending Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register 0 + 0x300 + 0x20 + read-write + 0x00000000 + + + PRI_0 + priority for interrupt 0 + 0 + 8 + + + PRI_1 + priority for interrupt 1 + 8 + 8 + + + PRI_2 + priority for interrupt 2 + 16 + 8 + + + PRI_3 + priority for interrupt 3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register 1 + 0x304 + 0x20 + read-write + 0x00000000 + + + PRI_4 + priority for interrupt n + 0 + 8 + + + PRI_5 + priority for interrupt n + 8 + 8 + + + PRI_6 + priority for interrupt n + 16 + 8 + + + PRI_7 + priority for interrupt n + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + PRI_8 + priority for interrupt n + 0 + 8 + + + PRI_9 + priority for interrupt n + 8 + 8 + + + PRI_10 + priority for interrupt n + 16 + 8 + + + PRI_11 + priority for interrupt n + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + PRI_12 + priority for interrupt n + 0 + 8 + + + PRI_13 + priority for interrupt n + 8 + 8 + + + PRI_14 + priority for interrupt n + 16 + 8 + + + PRI_15 + priority for interrupt n + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register 4 + 0x310 + 0x20 + read-write + 0x00000000 + + + PRI_16 + priority for interrupt n + 0 + 8 + + + PRI_17 + priority for interrupt n + 8 + 8 + + + PRI_18 + priority for interrupt n + 16 + 8 + + + PRI_19 + priority for interrupt n + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register 5 + 0x314 + 0x20 + read-write + 0x00000000 + + + PRI_20 + priority for interrupt n + 0 + 8 + + + PRI_21 + priority for interrupt n + 8 + 8 + + + PRI_22 + priority for interrupt n + 16 + 8 + + + PRI_23 + priority for interrupt n + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register 6 + 0x318 + 0x20 + read-write + 0x00000000 + + + PRI_24 + priority for interrupt n + 0 + 8 + + + PRI_25 + priority for interrupt n + 8 + 8 + + + PRI_26 + priority for interrupt n + 16 + 8 + + + PRI_27 + priority for interrupt n + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register 7 + 0x31C + 0x20 + read-write + 0x00000000 + + + PRI_28 + priority for interrupt n + 0 + 8 + + + PRI_29 + priority for interrupt n + 8 + 8 + + + PRI_30 + priority for interrupt n + 16 + 8 + + + PRI_31 + priority for interrupt n + 24 + 8 + + + + + + + STK + System Timer registers + 0xE000E010 + + 0x0 + 0x10 + registers + + + + STK_CSR + STK_CSR + SysTick control and status register + 0x0 + 0x20 + read-write + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + Not_counted_to_0 + 0x0 + + + Counted_to_0 + 0x1 + + + + + CLKSOURCE + Clock source selection + 2 + 1 + + + External_clock + 0x0 + + + Processor_clock + 0x1 + + + + + TICKINT + SysTick exception request enable + 1 + 1 + + + Does_not_affect_exception_status + 0x0 + + + Changes_exception_status + 0x1 + + + + + ENABLE + Counter enable + 0 + 1 + + + Counter_disabled + 0x0 + + + Counter_operating + 0x1 + + + + + + + STK_RVR + STK_RVR + SysTick reload value register + 0x4 + 0x20 + read-write + + + RELOAD + RELOAD value + 0 + 24 + + + + + STK_CVR + STK_CVR + SysTick current value register + 0x8 + 0x20 + read-write + + + CURRENT + CURRENT + 0 + 24 + + + + + STK_CALIB + STK_CALIB + SysTick calibration value register + 0xC + 0x20 + read-write + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + Implemented + 0x0 + + + Not_implemented + 0x1 + + + + + SKEW + SKEW flag: Indicates whether the TENMS value is exact + 30 + 1 + + + Exact + 0x0 + + + Inexact + 0x1 + + + + + TENMS + Calibration value + 0 + 24 + + + + + + + diff --git a/svd/STM32WBxx/STM32WB05.svd b/svd/STM32WBxx/STM32WB05.svd new file mode 100644 index 0000000..a11624f --- /dev/null +++ b/svd/STM32WBxx/STM32WB05.svd @@ -0,0 +1,28044 @@ + + + + STM32WB05 + 0.4 + STM32WB05 + + CM0+ + r0p0 + little + true + false + 2 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC + 0x41006000 + + 0x0 + 0x68 + registers + + + ADC + ADC interrupt + 12 + + + + VERSION_ID + VERSION_ID + VERSION_ID register + 0x00 + 0x20 + read-only + 0x30 + 0xFF + + + VERSION_ID + VERSION_ID[7:0]: version of the embedded IP. + 0 + 8 + read-only + + + + + CONF + CONF + CONF register + 0x04 + 0x20 + read-write + 0x20002 + 0xFFFFF + + + CONT + CONT: regular sequence runs continuously when ADC mode is enabled: + +0: enable the single conversion: when the sequence is over, the conversion stops + +1: enable the continuous conversion: when the sequence is over, the sequence starts again + +until the software sets the CTRL.STOP_OP_MODE bit. + 0 + 1 + read-write + + + SEQUENCE + SEQUENCE: enable the sequence mode (active by default): + +0: sequence mode is disabled, only SEQ0 is selected + +1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN + +Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can + +be kept high as redundant with keeping high and setting SEQ_LEN=0000. + 1 + 1 + read-write + + + SEQ_LEN + SEQ_LEN[3:0]: number of conversions in a regular sequence: + +0000: 1 conversion, starting from SEQ0 + +0001: 2 conversions, starting from SEQ0 + +... + +1111: 16 conversions, starting from SEQ0 + 2 + 4 + read-write + + + SMPS_SYNCHRO_ENA + SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the + +SMPS: + +0: SMPS synchronization is disabled for all ADC clock frequencies + +1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) + +Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when + +PWRC_CR5.NOSMPS = 1. + 6 + 1 + read-write + + + SAMPLE_RATE_LSB + SAMPLE_RATE_LSB: Sample Rate LSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. + +When this field is set to a value different than 0, SMPS synchronization is not feasible. + +This value is hidden to the user + 9 + 2 + read-write + + + SAMPLE_RATE + SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): + +F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where + +F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency. + 11 + 2 + read-write + + + DMA_DS_ENA + DMA_DS_EN: enable the DMA mode for the Down Sampler data path: + +0: DMA mode is disabled + +1: DMA mode is enabled + 13 + 1 + read-write + + + OVR_DS_CFG + OVR_DS_CFG: Down Sampler overrun configuration: + +0: the previous data is kept, the new one is lost + +1: the previous data is lost, the new one is kept + 15 + 1 + read-write + + + BIT_INVERT_SN + BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single + +negative input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 17 + 1 + read-write + + + BIT_INVERT_DIFF + BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential + +input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 18 + 1 + read-write + + + ADC_CONT_1V2 + ADC_CONT_1V2: select the input sampling method: + +0: sampling only at conversion start (default) + +1: sampling starts at the end of conversion + 19 + 1 + read-write + + + SAMPLE_RATE_MSB + SAMPLE_RATE_MSB: Sample Rate MSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description + 21 + 3 + read-write + + + + + CTRL + CTRL + CTRL register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + ADC_ON_OFF + ADC_ON_OFF: + +0: power off the ADC + +1: power on the ADC + 0 + 1 + read-write + + + START_CONV + START_CONV (1): generate a start pulse to initiate an ADC conversion: + +0: no effect + +1: start the ADC conversion + +Note: this bit is set by software and cleared by hardware. + 1 + 1 + write-only + + + STOP_OP_MODE + STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full + +mode): + +0: no effect + +1: stop on-going ADC mode + +Note: this bit is set by software and cleared by hardware. + +When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit. + 2 + 1 + write-only + + + TEST_MODE + TEST_MODE: select the functional or the test mode of the ADC: + +0: functional mode (one of the four main functional modes is used) + +1: test mode (for debug, test, calibration) + 4 + 1 + read-write + + + ADC_LDO_ENA + ADC_LDO_ENA: enable the LDO associated to the ADC block: + +0: disable the ADC LDO + +1: enable the ADC LDO + 5 + 1 + read-write + + + + + SWITCH + SWITCH + SWITCH register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + SE_VIN_0 + SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 0 + 2 + read-write + + + SE_VIN_1 + SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 2 + 2 + read-write + + + SE_VIN_2 + SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 4 + 2 + read-write + + + SE_VIN_3 + SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 6 + 2 + read-write + + + SE_VIN_4 + SE_VIN_4[1:0]: input voltage for VINP[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 8 + 2 + read-write + + + SE_VIN_5 + SE_VIN_5[1:0]: input voltage for VINP[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 10 + 2 + read-write + + + SE_VIN_6 + SE_VIN_6[1:0]: input voltage for VINP[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 12 + 2 + read-write + + + SE_VIN_7 + SE_VIN_7[1:0]: input voltage for VINP[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 14 + 2 + read-write + + + + + DS_CONF + DS_CONF + DS_CONF register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DS_RATIO + DS_RATIO[2:0]: program the Down Sampler ratio (N factor) + +000: ratio = 1, no down sampling (default) + +001: ratio = 2 + +010: ratio = 4 + +011: ratio = 8 + +100: ratio = 16 + +101: ratio = 32 + +110: ratio = 64 + +111: ratio = 128 + 0 + 3 + read-write + + + DS_WIDTH + DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) + +000: DS_DATA output on 12-bit (default) + +001: DS_DATA output on 13-bit + +010: DS_DATA output on 14-bit + +011: DS_DATA output on 15-bit + +100: DS_DATA output on 16-bit + +1xx: reserved + 3 + 3 + read-write + + + + + SEQ_1 + SEQ_1 + SEQ_1 register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + SEQ0 + SEQ0[3:0]: channel number code for first conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT - Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ1 + SEQ1[3:0]: channel number code for second conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ2 + SEQ2[3:0]: channel number code for 3rd conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ3 + SEQ3[3:0]: channel number code for 4th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ4 + SEQ4[3:0]: channel number code for 5th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ5 + SEQ5[3:0]: channel number code for 6th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ6 + SEQ6[3:0]: channel number code for 7th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ7 + SEQ7[3:0]: channel number code for 8th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + SEQ_2 + SEQ_2 + SEQ_2 register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + SEQ8 + SEQ8[3:0]: channel number code for 9th conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT - Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ9 + SEQ9[3:0]: channel number code for 10th conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ10 + SEQ10[3:0]: channel number code for 11th conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ11 + SEQ11[3:0]: channel number code for 12th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ12 + SEQ12[3:0]: channel number code for 13th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ13 + SEQ13[3:0]: channel number code for 14th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ14 + SEQ14[3:0]: channel number code for 15th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ15 + SEQ15[3:0]: channel number code for 16th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + COMP_1 + COMP_1 + COMP_1 register + 0x28 + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN1 + GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET1 + OFFSET1[7:0]: first calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_2 + COMP_2 + COMP_2 register + 0x2C + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN2 + GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET2 + OFFSET2[7:0]: second calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_3 + COMP_3 + COMP_3 register + 0x30 + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN3 + GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET3 + OFFSET3[7:0]: third calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_4 + COMP_4 + COMP_4 register + 0x34 + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN4 + GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET4 + OFFSET4[7:0]: fourth calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_SEL + COMP_SEL + COMP_SEL register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + OFFSET_GAIN0 + OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 0 + 2 + read-write + + + OFFSET_GAIN1 + OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 2 + 2 + read-write + + + OFFSET_GAIN2 + OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 4 + 2 + read-write + + + OFFSET_GAIN3 + OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 6 + 2 + read-write + + + OFFSET_GAIN4 + OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 8 + 2 + read-write + + + OFFSET_GAIN5 + OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 10 + 2 + read-write + + + OFFSET_GAIN6 + OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 12 + 2 + read-write + + + OFFSET_GAIN7 + OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 14 + 2 + read-write + + + OFFSET_GAIN8 + OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 16 + 2 + read-write + + + + + WD_TH + WD_TH + WD_TH register + 0x3C + 0x20 + read-write + 0xFFF0000 + 0xFFFFFFF + + + WD_LT + WD_LT[11:0]: analog watchdog low level threshold. + 0 + 12 + read-write + + + WD_HT + WD_HT[11:0]: analog watchdog high level threshold. + 16 + 12 + read-write + + + + + WD_CONF + WD_CONF + WD_CONF register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + AWD_CHX + AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need + +to be guarded by the watchdog. + +Bit0: VINM[0] to ADC negative input + +Bit1: VINM[1] to ADC negative input + +Bit2: VINM[2] to ADC negative input + +Bit3: VINM[3] to ADC negative input + +Bit4: Not used + +Bit5: VBAT to ADC negative input + +Bit6: GND to ADC negative input + +Bit7: VDDA to ADC negative input + +Bit8: VINP[0] to ADC positive input + +Bit9: VINP[1] to ADC positive input + +Bit10: VINP[2] to ADC positive input + +Bit11: VINP[3] to ADC positive input + +Bit12: Not used + +Bit13: TEMP to ADC positive input + +Bit14: GND to ADC positive input + +Bit15: VDDA to ADC positive input + 0 + 16 + read-write + + + + + DS_DATAOUT + DS_DATAOUT + DS_DATAOUT register + 0x44 + 0x20 + read-only + 0x0 + 0xF + + + DS_DATA + DS_DATA[15:0]: contain the converted data at the output of the Down Sampler. + 0 + 16 + read-only + + + + + IRQ_STATUS + IRQ_STATUS + IRQ_STATUS register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + TIMER_CONF + TIMER_CONF + TIMER_CONF register + 0x54 + 0x20 + read-write + 0x28 + 0xFF + + + ADC_LDO_DELAY + ADC_LDO_DELAY[7:0]: define the duration of a waiting time to be inserted between the + +ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a + +conversion. + +The time unit is 4 us. + +Maximum delay is 1.02 ms (255 x 4 us). + +Default value is 40 = 160 us. + 0 + 8 + read-write + + + + + + + CRC + CRC address block description + CRC + 0x48200000 + + 0x0 + 0x400 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + DMA + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + + + GIF1 + GIF1: Channel 1 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 1 +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 1 +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 1 +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TEIF1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 1 +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 2 +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 2 +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 2 +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TEIF2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 2 +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 3 +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 3 +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 3 +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TEIF3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 3 +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 4 +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 4 +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 4 +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TEIF4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 4 +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 5 +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 5 +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 5 +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TEIF5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 5 +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 6 +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 6 +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 6 +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 6 +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 7 +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 7 +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 7 +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 7 +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 8 +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 8 +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 8 +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 8 +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + + + CGIF1 + CGIF1: Channel 1 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + + + DMAMUX + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + GPIOA + GPIOA + 0x48000000 + + 0x0 + 0x2C + registers + + + GPIOA + GPIOA interrupt + 15 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x000000A0 + + + MODE0 + MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE8 + MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT8 + OT8: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000030 + + + OSPEED0 + OSPEED0[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x00550095 + + + PUPD0 + PUPD0: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD8 + PUPD8: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID8 + ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port A output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port A output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port A output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port A output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD8 + OD8: Port A output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port A output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port A output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port A output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + read-write + 0x00000000 + + + BS0 + BS0: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 3 + 1 + write-only + + + BS8 + BS8: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 8 + 1 + write-only + + + BS9 + BS9: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 9 + 1 + write-only + + + BS10 + BS10: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 10 + 1 + write-only + + + BS11 + BS11: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 11 + 1 + write-only + + + BR0 + BR0: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR8 + BR8: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port A lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port A lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port A lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port A lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK8 + LCK8: Port A lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port A lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port A lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port A lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1' + LCKR[15:0] +WR LCKR[16] = 0' + LCKR[15:0] +WR LCKR[16] = 1' + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1' until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR8 + BR8: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55005555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + read-write + 0x00000000 + + + BS0 + BS0: Port B set bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 7 + 1 + write-only + + + BS12 + BS12: Port B set bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit 14 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit 15 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 23 + 1 + write-only + + + BR12 + BR12: Port B reset bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit 14 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit 15 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1' + LCKR[15:0] +WR LCKR[16] = 0' + LCKR[15:0] +WR LCKR[16] = 1' + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1' until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL12 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + read-write + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + read-write + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + read-write + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + read-write + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + read-write + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + read-write + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + read-write + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + read-write + + + BR12 + BR12 Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + read-write + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + read-write + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + read-write + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + read-write + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. +000: divider/4 +001: divider/8 +010: divider/16 +011: divider/32 +100: divider/64 +101: divider/128 +110: divider/256 +111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic 'window' = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + UESM + UESM: LPUART enable in Stop mode +When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. +When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that +the LPUART clock selection is LSE in the RCC. +This bit is set and cleared by software. +-0: LPUART not able to wake up the MCU from Stop mode. +-1: LPUART able to wake up the MCU from Stop mode. When this function is active, the +clock source for the LPUART must be LSE (see RCC chapter) + 1 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + WUS + WUS[1:0]: Wakeup from Stop mode interrupt flag selection +This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). +-00: WUF active on address match (as defined by ADD[7:0] and ADDM7) +-01:Reserved. +-10: WUF active on Start bit detection +-11: WUF active on RXNE. +This bit field can only be written when the LPUART is disabled (UE=0). + 20 + 2 + read-write + + + WUFIE + WUFIE: Wakeup from Stop mode interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register + 22 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0' +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + WUF + WUF: Wakeup from Stop mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the +WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register + 20 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesn't reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesn't reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x200 + registers + + + FLASH + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +- 0x11 : ERASE +- 0x22 : MASSERASE +- 0x33 : WRITE +- 0x44 : MASSWRITE +- 0x55 : MASSREAD +- 0x66 : IFRERASE +- 0x77 : IFRWRITE +- 0x88 : IFRMASSWRITE +- 0x99 : IFRMASSREAD +- 0xAA : SLEEP +- 0xBB : WAKEUP +- 0xCC : BURSTWRITE +- 0xDD : IFRBURSTWRITE +- 0xEE : OTPWRITE +- 0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + LONGACCESS + Additional wait-state for flash read access: +- 0 : no latency added +- 1 : 1 clock cycle latency added + 0 + 1 + read-write + + + REMAP + CPU access routing (it supersedes PREMAP configuration): +- 0 : FLASH memory addressed +- 1 : SRAM0 memory addressed + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +- 0 : burst write allowed +- 1 : burst write forbidden + 2 + 1 + read-write + + + PREMAP + CPU access routing (it can only be set; reset only allowed by POR/PAD reset) +- 0 : IFR memory addressed +- 1 : MAIN flash memory addressed + 3 + 1 + read-write + + + WAIT_STATE + Add latency to flash read opeations: +- 00 : no latency +- 01 : 1 clock cycle latency +- 10 : 2 clock cycles latency +- 11 : 3 clock cycles latency + 4 + 2 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + (1: clear, 0: inactive) CMDDONE_MIS flag + 0 + 1 + read-write + + + CMDSTART_MIS + (1: clear, 0: inactive) CMDSTART_MIS flag + 1 + 1 + read-write + + + CMDBUSYERR_MIS + (1: clear, 0: inactive) CMDBUSYERR_MIS flag + 2 + 1 + read-write + + + ILLCMD_MIS + (1: clear, 0: inactive) ILLCMD_MIS flag + 3 + 1 + read-write + + + READOK_MIS + (1: clear, 0: inactive) READOK_MIS flag + 4 + 1 + read-write + + + FNREADY_MIS + (1: clear, 0: inactive) FNREADY_MIS flag + 5 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + (1: mask, 0: inactive) CMDDONE_MIS mask + 0 + 1 + read-write + + + CMDSTARTM + (1: mask, 0: inactive) CMDSTART_MIS mask + 1 + 1 + read-write + + + CMDBUSYERRM + (1: mask, 0: inactive) CMDBUSYERR_MIS mask + 2 + 1 + read-write + + + ILLCMDM + (1: mask, 0: inactive) ILLCMD_MIS mask + 3 + 1 + read-write + + + READOKM + (1: mask, 0: inactive) READOK_MIS mask + 4 + 1 + read-write + + + FNREADYM + (1: mask, 0: inactive) FNREADY_MIS mask + 5 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + (1: active, 0: inactive) COMMAND sequence ended + 0 + 1 + read-write + + + CMDSTART_RIS + (1: active, 0: inactive) COMMAND sequence started + 1 + 1 + read-write + + + CMDBUSYERR_RIS + (1: active, 0: inactive) COMMAND issued while flash busy + 2 + 1 + read-write + + + ILLCMD_RIS + (1: active, 0: inactive) Illegal command issued + 3 + 1 + read-write + + + READOK_RIS + (1: active, 0: inactive) READ COMMAND completed successfully + 4 + 1 + read-write + + + CMDSLEEPERR_RIS + (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1) + 5 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0006BFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +- 00 : 0x03FFF (64kb) +- 01 : 0x07FFF (128kb) +- 10 : 0x09FFF (160kb) +- 11 : 0x0BFFF (192kb) + 0 + 17 + read-only + + + RAM_SIZE + RAM memory size selection: +- 0 : 16kb +- 1 : 32kb + 17 + 1 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + JTAG_DISABLE + Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE, 1: Flash and JTAG protected) + 20 + 1 + read-only + + + PACKAGE_SIZE + Package selection: +- 0- : CSP +- 10 : 32pins +- 11 : 48pins + 21 + 2 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEGSIZE0 + First segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET0 + First segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE1 + Second segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET1 + Second segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEGSIZE2 + Third segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET2 + Third segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE3 + Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET3 + Fourth segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + + + PKA + PKA + 0x48300000 + + 0x0 + 0x1400 + registers + + + PKA + PKA interrupt + 13 + + + + PKA_CR + PKA_CR + PKA_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + EN + Peripheral enable. +- 0 : Disable PKA. +- 1 : Enable PKA. + 0 + 1 + read-write + + + START + Start the operation +- 0: No operation +- 1: Writing 1' to this bit starts the operation which is selected by MODE[5:0], using the operands and data +already written to the PKA RAM. This bit is always read as 0'. +Nota: START is ignored if PKA is busy. + 1 + 1 + read-write + + + SECLVL + Security enable. +- 0: No side channel countermeasure +- 1: Square and Multiply always / Double and Add always + 2 + 1 + read-write + + + MODE + PKA operation code +- 000000 : Compute Montgomery parameter and modular exponentiation +- 000001 : Compute Montgomery parameter +- 000010 : Compute modular exponentiation only (Montgomery parameter should be loaded) +- 100000 : Compute Montgomery parameter and compute ECC kP operation +- 100010 : Compute the ECC kP primitive only (Montgomery parameter should be loaded) +- 100100 : ECDSA sign +- 100110 : ECDSA Verification +- 101000 : Point Check +- 000111 : RSA CRT exponentiation +- 001000 : Modular inversion +- 001001 : Arithmetic addition +- 001010 : Arithmetic Subtraction +- 001011 : Arithmetic multiplication +- 001100 : Comparison +- 001101 : Modular Reduction +- 001110 : Modular Addition +- 001111 : Modular Subtraction +- 010000 : Montgomery Multiplication + 8 + 6 + read-write + + + PROCENDIE + End of operation interrupt enable +- 0: Interrupt is disabled. +- 1: An interrupt is generated when PROCENDF (PKA_SR[17]) is set. + 17 + 1 + read-write + + + RAMERRIE + RAM error interrupt enable +- 0: Interrupt is disabled. +- 1: An interrupt is generated when RAMERRF (PKA_SR[19]) is set. + 19 + 1 + read-write + + + ADDRERRIE + Address error interrupt enable +- 0: Interrupt is disabled. +- 1: An interrupt is generated when ADDRERRF (PKA_SR[20] is set. + 20 + 1 + read-write + + + + + PKA_SR + PKA_SR + PKA_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + BUSY + PKA operation is in progress +This bit is set to 1' whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. +- 0: No operation is in progress (default) +- 1: An operation is in progress +Nota: if PKA is started with a wrong opcode the IP will be busy for a couple of cycles then it will abort automatically the operation and go back to ready (BUSY bit is set to 0'). + 16 + 1 + read-only + + + PROCENDF + PKA End of Operation flag +- 0: Operation in progress +- 1: PKA operation is completed. This flag is set when the BUSY bit is de-asserted. + 17 + 1 + read-only + + + RAMERRF + PKA RAM error flag +- 0: No PKA RAM access error +- 1: An AHB access to the PKA RAM occured while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress). + 19 + 1 + read-only + + + ADDRERRF + Address error flag +- 0: No Address error +- 1: Address access is out of range (unmapped address) + 20 + 1 + read-only + + + + + PKA_CLRFR + PKA_CLRFR + PKA_CLRFR register + 0x08 + 0x20 + read-write + 0x00000000 + + + PROCENDFC + Clear PKA End of Operation flag +- 0: No action +- 1: Clear the PROCENDF flag + 17 + 1 + read-write + + + RAMERRFC + Clear PKA RAM error flag +- 0: No action +- 1: Clear the RAMERRF flag +Bits 18 Reserved, must be kept at zero + 19 + 1 + read-write + + + ADDRERRFC + Clear Address error flag +- 0: No action +- 1: Clear the ADDRERRF flag + 20 + 1 + read-write + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA0 + registers + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. + 0 + 1 + read-write + + + B_0x0 + Deep Stop mode (default) + 0x0 + + + B_0x1 + Shutdown mode + 0x1 + + + + + ENSDNBOR + ENSDNBOR: Enable BOR supply monitoring during shutdown mode. + 1 + 1 + read-write + + + B_0x1 + the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode + 0x1 + + + B_0x0 + the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode. + 0x0 + + + + + IBIAS_RUN_AUTO + IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. +0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) +1: IBIAS control is automatic (default). + 2 + 1 + read-write + + + IBIAS_RUN_STATE + IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is +disabled. +0: IBIAS control is disabled (default). +1: IBIAS control is enabled. + 3 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU + 4 + 1 + read-write + + + B_0x1 + the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. + 0x1 + + + B_0x0 + the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 0x0 + + + + + ENBORH + ENBORH: enable BORH configuration + 5 + 1 + read-write + + + B_0x1 + BORH is enabled, threshold level depends on SELBOR[1:0] + 0x1 + + + B_0x0 + BORH off (VBOR0): threshold level for above 1.60V voltage operation. + 0x0 + + + + + SELBORH + SELBORH[1:0]: BORH selection of Vbor threshold + 6 + 2 + read-write + + + B_0x3 + BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation. + 0x3 + + + B_0x2 + BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation + 0x2 + + + B_0x1 + BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation + 0x1 + + + B_0x0 + BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation. + 0x0 + + + + + ENBORL + ENBORL: Enable BORL reset supervising during RUN mode. +0: No BORL is monitored during RUN mode. +1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below +1.6V during RUN mode) (default). +Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN. + 8 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +then PVDO=1) + 1 + 3 + read-write + + + B_0x0 + 2.05 V - Lowest level + 0x0 + + + B_0x1 + 2.20 V + 0x1 + + + B_0x2 + 2.36 V + 0x2 + + + B_0x3 + 2.52 V + 0x3 + + + B_0x4 + 2.64 V + 0x4 + + + B_0x5 + 2.81 V + 0x5 + + + B_0x6 + 2.91 V - Highest level + 0x6 + + + B_0x7 + External input analog voltage (compare internally to VBGP; When external input <VBGP + 0x7 + + + + + DBGRET + DBGRET: PA2 and PA3 retention enable after DEEPSTOP +0: PA2, PA3 don't retain their status exiting from DEEPSTOP. (default) +1: PA2, PA3 retain their status exiting from DEEPSTOP. + 4 + 1 + read-write + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode + 5 + 1 + read-write + + + B_0x1 + RAM1 bank is powered during low power mode + 0x1 + + + B_0x0 + RAM1 bank is disabled during low power mode (by default) + 0x0 + + + + + GPIORET + GPIORET: GPIO retention enable. +0: GPIO don't retain their status during DEEPSTOP and exiting from DEEPSTOP (default) +1: GPIO retain their status during DEEPSTOP and exiting from DEEPSTOP. +Note: it's mandatory to ensure this bit is set before entering DEEPSTOP unless DBRG.DEEPSTOP2 bit is set. + 8 + 1 + read-write + + + ENTS + ENTS: Enable Temperature Sensor + 9 + 1 + read-write + + + B_0x1 + Temperature sensor is enabled + 0x1 + + + B_0x0 + Temperature sensor is disabled + 0x0 + + + + + + + CR3 + CR3 + CR3 register + 0x8 + 0x20 + read-write + 0x0000 + + + EWU0 + EWU0 Enable WakeUp line 0 (PB0) +When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit. + 0 + 1 + read-write + + + EWU1 + EWU1 Enable WakeUp line 1 (PB1) +When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit. + 1 + 1 + read-write + + + EWU2 + EWU2 Enable WakeUp line 2 (PB2) +When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit. + 2 + 1 + read-write + + + EWU3 + EWU3 Enable WakeUp line 3 (PB3) +When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit. + 3 + 1 + read-write + + + EWU4 + EWU4 Enable WakeUp line 4 (PB4) +When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit. + 4 + 1 + read-write + + + EWU5 + EWU5 Enable WakeUp line 5 (PB5) +When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit. + 5 + 1 + read-write + + + EWU6 + EWU6 Enable WakeUp line 6 (PB6) +When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit. + 6 + 1 + read-write + + + EWU7 + EWU7 Enable WakeUp line 7 (PB7) +When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit. + 7 + 1 + read-write + + + EWU8 + EWU8 Enable WakeUp line 8 (PA8) +When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit. + 8 + 1 + read-write + + + EWU9 + EWU9 Enable WakeUp line 9 (PA9) +When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit. + 9 + 1 + read-write + + + EWU10 + EWU10 Enable WakeUp line 10 (PA10) +When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit. + 10 + 1 + read-write + + + EWU11 + EWU11 Enable WakeUp line 11 (PA11) +When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit. + 11 + 1 + read-write + + + EWBLE + EWBLE: Enable wakeup on BLE event. +0: Wakeup on BLE line is disabled (default). +1: Wakeup on BLE line is enabled. + 12 + 1 + read-write + + + EWBLEHCPU + EWBLEHCPU: Enable wakeup on BLE Host CPU event. +0: Wakeup on BLE Host CPU line is disabled (default). +1: Wakeup on BLE Host CPU line is enabled. + 13 + 1 + read-write + + + EIWL2 + EIWL2: Enable wakeup on Internal event (LPUART). +0: Wakeup on internal line is disabled (default). +1: Wakeup on internal line is enabled. + 14 + 1 + read-write + + + EIWL + EIWL: Enable wakeup on Internal event (RTC). +0: Wakeup on internal line is disabled (default). +1: Wakeup on internal line is enabled. + 15 + 1 + read-write + + + + + CR4 + CR4 + CR4 register + 0xc + 0x20 + read-write + 0x0 + + + WUP0 + WUP0 Wake-up Line Polarity 0 (PB0) +This bit defines the polarity used for event detection on external wake-up line 0 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP1 + WUP1 Wake-up Line Polarity 1 (PB1) +This bit defines the polarity used for event detection on external wake-up line 1 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP2 + WUP2 Wake-up Line Polarity 2 (PB2) +This bit defines the polarity used for event detection on external wake-up line 2 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP3 + WUP3 Wake-up Line Polarity 3 (PB3) +This bit defines the polarity used for event detection on external wake-up line 3 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP4 + WUP4 Wake-up Line Polarity 4 (PB4) +This bit defines the polarity used for event detection on external wake-up line 4 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP5 + WUP5 Wake-up Line Polarity 5 (PB5) +This bit defines the polarity used for event detection on external wake-up line 5 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP6 + WUP6 Wake-up Line Polarity 6 (PB6) +This bit defines the polarity used for event detection on external wake-up line 6 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP7 + WUP7 Wake-up Line Polarity 7 (PB7) +This bit defines the polarity used for event detection on external wake-up line 7 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP8 + WUP8 Wake-up Line Polarity 8 (PA8) +This bit defines the polarity used for event detection on external wake-up line 8 + 8 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP9 + WUP9 Wake-up Line Polarity 9 (PA9) +This bit defines the polarity used for event detection on external wake-up line 9 + 9 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP10 + WUP10 Wake-up Line Polarity 10 (PA10) +This bit defines the polarity used for event detection on external wake-up line 10 + 10 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP11 + WUP11 Wake-up Line Polarity 11 (PA11) +This bit defines the polarity used for event detection on external wake-up line 11 + 11 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + SR1 + SR1 + SR1 register + 0x10 + 0x20 + read-write + 0x0 + + + WUF0 + WUF0 WakeUp Flag 0 (PB0) +This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF1 + WUF1 WakeUp Flag 1 (PB1) +This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF2 + WUF2 WakeUp Flag 2 (PB2) +This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF3 + WUF3 WakeUp Flag 3 (PB3) +This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF4 + WUF4 WakeUp Flag 4 (PB4) +This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF5 + WUF5 WakeUp Flag 5 (PB5) +This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF6 + WUF6 WakeUp Flag 6 (PB6) +This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF7 + WUF7 WakeUp Flag 7 (PB7) +This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF8 + WUF8 WakeUp Flag 8 (PA8) +This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 8 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF9 + WUF9 WakeUp Flag 9 (PA9) +This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 9 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF10 + WUF10 WakeUp Flag 10 (PA10) +This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 10 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF11 + WUF11 WakeUp Flag 11 (PA11) +This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 11 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WBLEF + WBLEF: BLE wakeup flag. +0: no wakeup from BLE occurred since last clear. +1: a wakeup from BLE occurred since last clear. +Cleared by writing 1 in this bit. + 12 + 1 + read-write + + + WBLEHCPUF + WBLEHCPUF: BLE Host CPU wakeup flag. +0: no wakeup from BLE Host CPU occurred since last clear. +1: a wakeup from BLE Host CPU occurred since last clear. +Cleared by writing 1 in this bit. + 13 + 1 + read-write + + + IWUF2 + IWUF2: Internal wakeup 2 flag (LPUART). +0: no wakeup from LPUART occurred since last clear. +1: a wakeup from LPUART occurred since last clear. +Note: The user must clear the LPUART wakeup flag inside the LPUART IP to clear this bit +(mirror of the LPUART wakeup line on the PWRC block). + 14 + 1 + read-only + + + IWUF + IWUF: Internal wakeup flag (RTC). +0: no wakeup from RTC occurred since last clear. +1: a wakeup from RTC occurred since last clear. +Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of +the RTC wakeup line on the PWRC block). + 15 + 1 + read-only + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0x0306 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. + 2 + 1 + read-only + + + B_0x0 + SMPS regulator is not ready + 0x0 + + + B_0x1 + SMPS regulator is ready. + 0x1 + + + + + IOBOOTVAL2 + Bit3: PB15 input value on VDD33 latched at POR +Bit2: PB14 input value on VDD33 latched at POR +Bit1: PB13 input value on VDD33 latched at POR +Bit0: PB12 input value on VDD33 latched at POR + 4 + 4 + read-only + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. + 8 + 1 + read-only + + + B_0x0 + LP regulator is not ready. + 0x0 + + + B_0x1 + LP regulator is ready. + 0x1 + + + + + REGMS + REGMS: Regulator Main LDO Started +This bit provides the information whether main regulator is ready. + 9 + 1 + read-only + + + B_0x0 + Main regulator is not ready. + 0x0 + + + B_0x1 + Main regulator is ready. + 0x1 + + + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: + 4 + 2 + read-write + + + B_0x0 + BOM1 + 0x0 + + + B_0x1 + BOM2 (default) + 0x1 + + + B_0x2 + BOM3 + 0x2 + + + B_0x3 + n/a + 0x3 + + + + + SMPSFRDY + SMPSFB Force ready check +When this bit is set, the SMPS FSM will consider the SMPS ready . + 7 + 1 + read-write + + + B_0x0 + no effect (by default) + 0x0 + + + B_0x1 + SMPS is considered READY + 0x1 + + + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. + 8 + 1 + read-write + + + B_0x0 + in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. + 0x0 + + + B_0x1 + in Low Power mode, SMPS is disabled, output is floating + 0x1 + + + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. + 9 + 1 + read-write + + + B_0x0 + no effect (by default) + 0x0 + + + B_0x1 + SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 0x1 + + + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. + 10 + 1 + read-write + + + B_0x0 + No effect, SMPS is enabled. + 0x0 + + + B_0x1 + SMPS is disabled; + 0x1 + + + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode + 11 + 1 + read-write + + + B_0x0 + disable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. + 12 + 1 + read-write + + + B_0x0 + SMPS clock detection enabled (default) + 0x0 + + + B_0x1 + SMPS clock detection disabled + 0x1 + + + + + SMPS_PRECH_CUR_SEL + SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current + 13 + 2 + read-write + + + B_0x0 + 2.5mA + 0x0 + + + B_0x1 + 5mA + 0x1 + + + B_0x2 + 10mA + 0x2 + + + B_0x3 + 20mA (default) + 0x3 + + + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0x0F07 + + + PU + PU[x] : Pull Up +Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port A[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRA[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port A[i] + 0x0 + + + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PD + PD[x]: Pull Down +Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port A[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port A[i] + 0x0 + + + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xF0FF + + + PU + PU[x] : Pull Up +Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port B[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRB[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port B[i] + 0x0 + + + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PD + PD[x]: Pull Down +Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port B[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port B[i] + 0x0 + + + + + + + CR6 + CR6 + CR6 register + 0x30 + 0x20 + read-write + 0x0000 + + + EWU12 + EWU12 Enable WakeUp line 12 (PA0) +When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit. + 0 + 1 + read-write + + + EWU13 + EWU13 Enable WakeUp line 13 (PA1) +When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit. + 1 + 1 + read-write + + + EWU14 + EWU14 Enable WakeUp line 14 (PA2) +When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit. + 2 + 1 + read-write + + + EWU15 + EWU15 Enable WakeUp line 15 (PA3) +When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit. + 3 + 1 + read-write + + + EWU16 + EWU16 Enable WakeUp line 16 (PB12) +When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit. + 4 + 1 + read-write + + + EWU17 + EWU17 Enable WakeUp line 17 (PB13) +When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit. + 5 + 1 + read-write + + + EWU18 + EWU18 Enable WakeUp line 18 (PB14) +When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit. + 6 + 1 + read-write + + + EWU19 + EWU19 Enable WakeUp line 19 (PB15) +When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit. + 7 + 1 + read-write + + + + + CR7 + CR7 + CR7 register + 0x34 + 0x20 + read-write + 0x0 + + + WUP12 + WUP12 Wake-up Line Polarity 12 (PA0) +This bit defines the polarity used for event detection on external wake-up line 12 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP13 + WUP13 Wake-up Line Polarity 13 (PA1) +This bit defines the polarity used for event detection on external wake-up line 13 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP14 + WUP14 Wake-up Line Polarity 14 (PA2) +This bit defines the polarity used for event detection on external wake-up line 14 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP15 + WUP15 Wake-up Line Polarity 15 (PA3) +This bit defines the polarity used for event detection on external wake-up line 15 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP16 + WUP16 Wake-up Line Polarity 16 (PB12) +This bit defines the polarity used for event detection on external wake-up line 16 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP17 + WUP17 Wake-up Line Polarity 17 (PB13) +This bit defines the polarity used for event detection on external wake-up line 17 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP18 + WUP18 Wake-up Line Polarity 18 (PB14) +This bit defines the polarity used for event detection on external wake-up line 18 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP19 + WUP19 Wake-up Line Polarity 19 (PB15) +This bit defines the polarity used for event detection on external wake-up line 19 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + SR3 + SR3 + SR3 register + 0x38 + 0x20 + read-write + 0x0 + + + WUF12 + WUF12 WakeUp Flag 12 PA0 +This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF13 + WUF13 WakeUp Flag 13 PA1 +This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF14 + WUF14 WakeUp Flag 14 PA2 +This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF15 + WUF15 WakeUp Flag 15 PA3 +This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF16 + WUF16 WakeUp Flag 16 PB12 +This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF17 + WUF17 WakeUp Flag 17 PB13 +This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF18 + WUF18 WakeUp Flag 18 PB14 +This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF19 + WUF19 WakeUp Flag 19 PB15 +This bit is set when a wakeup is detected on wakeup line 19. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. +0: normal DEEPSTOP will be applied +1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP. + 0 + 1 + read-write + + + DIS_PRECH + DIS_PRECH[2:0]: disable precharge during deepstop (debug) +- 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) +- 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) +- else: No effect (default 0x0) + 13 + 3 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field + 9 + 1 + read-write + + + B_0x0 + System has not been in DEEPSTOP mode + 0x0 + + + B_0x1 + System has been in DEEPSTOP mode + 0x1 + + + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a Radio wake-up event (BLE activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. + 10 + 1 + read-write + + + B_0x0 + RF IP does not require attention + 0x0 + + + B_0x1 + RF IP awake and requesting system attention + 0x1 + + + + + + + + + RNG + RNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + TRNG + TRNG + 28 + + + + RNG_CR + RNG_CR + RNG_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + RNG_DIS + RNG Disable bit. + 2 + 1 + read-write + + + TST_CLK + RNG Test Clock bit. + 3 + 1 + read-write + + + + + RNG_SR + RNG_SR + RNG_SR register + 0x04 + 0x20 + read-write + 0x00000000 + + + RNGRDY + New Random Value Ready. + 0 + 1 + read-only + + + REVCLK + RNGCLK Clock Reveal bit. + 1 + 1 + read-only + + + FAULT + Fault Reveal bit. + 2 + 1 + read-write + + + + + RNG_VAL + RNG_VAL + RNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RANDOM_VALUE + Random Value + 0 + 16 + read-only + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-write + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-write + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-write + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-write + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1' when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0'. + 16 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds don't care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes don't care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours don't care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is don't care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day don't care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescaler's counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescaler's counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1' , the 16-second calibration cycle period is selected.This bit must not be set to 1' if CALW8=1. +Note: CALM[0] is stucked at 0' when CALW16='1'. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1' , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at '00' when CALW8='1'. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. + 15 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescaler's counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are don't care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are don't care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are don't care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are don't care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are don't care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is don't care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKP0R register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKP1R register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x40 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x02028041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. +0: PA0 pin operated in standard mode. +1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. +0: PA1 pin operated in standard mode. +1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. +0: PB6 pin operated in standard mode. +1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. +0: PB7 pin operated in standard mode. +1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 11 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 23 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 3 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 11 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 23 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 3 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 11 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 23 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 3 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 11 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 23 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + BORH_IE + BORH_IE: BORH interrupt enable. +0: BORH interrupt is disabled. +1: BORH interrupt is enabled. + 0 + 1 + read-write + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. +0: PVD interrupt is disabled. +1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. +0: Interrupt on wakeup event seen by the PWRC is disabled. +1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + BORH_ISC + BORH_ISC: BORH interrupt status. +0: no pending interrupt. +1: voltage went under BORH threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. +0: no pending interrupt. +1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. +0: no pending interrupt. +1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + BLERXTX_DTR + BLERXTX_DTR + BLERXTX_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 1 + 1 + read-write + + + + + BLERXTX_IBER + BLERXTX_IBER + BLERXTX_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 1 + 1 + read-write + + + + + BLERXTX_IEVR + BLERXTX_IEVR + BLERXTX_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 1 + 1 + read-write + + + + + BLERXTX_IER + BLERXTX_IER + BLERXTX_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: +0: TX_SEQUENCE interrupt is disabled (default). +1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: +0: RX_SEQUENCE interrupt is disabled (default). +1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + + + BLERXTX_ISCR + BLERXTX_ISCR + BLERXTX_ISCR register + 0x3C + 8 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on TX_SEQUENCE detected. +1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on RX_SEQUENCE detected. +1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + TX_ISEDGE + TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: +0: falling edge on TX_SEQUENCE detected. +1: rising edge on TX_SEQUENCE detected. + 2 + 1 + read-only + + + RX_ISEDGE + RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: +0: falling edge on RX_SEQUENCE detected. +1: rising edge on RX_SEQUENCE detected. + 3 + 1 + read-only + + + + + + + I2C1 + I2C address block description + I2C + 0x41000000 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 interrupt + 3 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match Interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received Interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection Interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer Complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer Complete (TC) +Note: Transfer Complete Reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer Complete interrupt disabled + 0x0 + + + B_0x1 + Transfer Complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration Loss (ARLO) +Note: Bus Error detection (BERR) +Note: Overrun/Underrun (OVR) +Note: Timeout detection (TIMEOUT) +Note: PEC error detection (PECERR) +Note: Alert pin event detection (ALERT) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is also enabled, the digital filter is added to the analog filter. +Note: This filter can only be programmed when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wakeup from Stop mode enable +Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. +Note: WUPEN can be set only when DNF = '0000' + 18 + 1 + read-write + + + B_0x0 + Wakeup from Stop mode disable. + 0x0 + + + B_0x1 + Wakeup from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus host address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 20 + 1 + read-write + + + B_0x0 + Host address disabled. Address 0b0001000x is NACKed. + 0x0 + + + B_0x1 + Host address enabled. Address 0b0001000x is ACKed. + 0x1 + + + + + SMBDEN + SMBus device default address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. Address 0b1100001x is NACKed. + 0x0 + + + B_0x1 + Device default address enabled. Address 0b1100001x is ACKed. + 0x1 + + + + + ALERTEN + SMBus alert enable +Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). + 0x1 + + + + + PECEN + PEC enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] should be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer. + 0x0 + + + B_0x1 + Master requests a read transfer. + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode, + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit generates a START condition once the bus is free. +Note: Writing '0' to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation. + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In Master mode: +Note: Writing '0' to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation. + 0x0 + + + B_0x1 + Stop generation after current byte transfer. + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. +Note: Changing these bits when the START bit is set is not allowed. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit has no effect when RELOAD is set. +Note: This bit has no effect is slave mode when SBC=0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 26 + 1 + read-write + + + B_0x0 + No PEC transfer. + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN=0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN=0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN=0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don't care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don't care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don't care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don't care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don't care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don't care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL+1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH+1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL+1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE=0 +t<sub>TIMEOUT</sub>= (TIMEOUTA+1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE=1 +t<sub>IDLE</sub>= (TIMEOUTA+1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE=0) or high for more than t<sub>IDLE </sub>(TIDLE=1), a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT</sub>= (TIMEOUTB+1) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or t<sub>LOW</sub> detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xA0 + registers + + + RCC + Reset and Clock Controller + 1 + + + PVD + PVD + 2 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator OFF + 0x0 + + + B_0x1 + LSI RC oscillator ON + 0x1 + + + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn + 3 + 1 + read-only + + + B_0x0 + LSI RC oscillator not ready + 0x0 + + + B_0x1 + LSI RC oscillator ready + 0x1 + + + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn + 4 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. + 5 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn + 6 + 1 + read-write + + + B_0x0 + LSE oscillator bypass OFF + 0x0 + + + B_0x1 + LSE oscillator bypass ON + 0x1 + + + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). + 10 + 1 + read-only + + + B_0x0 + internal RC 64 MHz oscillator not ready + 0x0 + + + B_0x1 + internal RC 64 MHz oscillator ready + 0x1 + + + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF2G4 enable. +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + HSE PLL Buffer OFF + 0x0 + + + B_0x1 + HSE PLL Buffer ON + 0x1 + + + + + HSIPLLON + Internal High Speed Clock PLL enable + 13 + 1 + read-write + + + B_0x0 + PLL is OFF + 0x0 + + + B_0x1 + PLL is ON + 0x1 + + + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. + 14 + 1 + read-only + + + B_0x0 + PLL is unlocked + 0x0 + + + B_0x1 + PLL is locked + 0x1 + + + + + FMRAT + Force MR_BLE active transmission status (for debug purpose) + 15 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + active_transmission is force to '1' whatever the HSIPLLRDY status + 0x1 + + + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + SMPSINV + bit to control inversion of the SMPS clock + 0 + 1 + read-write + + + B_0x0 + SMPS clock not inverted (default value) + 0x0 + + + B_0x1 + SMPS clock inverted (for debug) + 0x1 + + + + + HSESEL + Clock source selection request: + 1 + 1 + read-write + + + B_0x0 + HSI clock source is requested (default) + 0x0 + + + B_0x1 + HSE clock source is requested + 0x1 + + + + + STOPHSI + Stop HSI clock source request + 2 + 1 + read-write + + + B_0x0 + HSI is enabled (default) + 0x0 + + + B_0x1 + disable HSI is requested + 0x1 + + + + + HSESEL_STATUS + Clock source selection Status + 3 + 1 + read-only + + + B_0x0 + HSI clock source is requested (default) + 0x0 + + + B_0x1 + HSE clock source is requested + 0x1 + + + + + CLKSYSDIV + CLKSYSDIV: system clock divided factor from HSI_64M. +000: system clock frequency is 64 MHz (not available when HSESEL=1) +001: system clock frequency is 32 MHz +010: system clock frequency is 16 MHz +011: system clock frequency is 8 MHz * +100: system clock frequency is 4 MHz * +101: system clock frequency is 2 MHz * +110: system clock frequency is 1 MHz * +111: not used. +*: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. +Warning: +if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on +HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) +To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. +the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio. + 5 + 3 + read-write + + + CLKSYSDIV_STATUS + CLKSYSDIV_STATUS: system clock frequency status +Set and cleared by hardware to indicate the actual system clock frequency. This register must +be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. +000: system clock frequency is 64 MHz +001: system clock frequency is 32 MHz +010: system clock frequency is 16 MHz +011: system clock frequency is 8 MHz +100: system clock frequency is 4 MHz +101: system clock frequency is 2 MHz +110: system clock frequency is 1 MHz +111: not used. +The actual clock frequency switching can be delayed of up to 128 system clock cycles, +depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied + 8 + 3 + read-only + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz + 12 + 1 + read-write + + + B_0x0 + div 2 when ANADIV=2 or 4 (default ) + 0x0 + + + B_0x1 + div 4 when ANADIV=1 or 2 + 0x1 + + + + + LPUCLKSEL + Selection of LPUART clock: + 13 + 1 + read-write + + + B_0x0 + 16MHz peripheral clock (default) + 0x0 + + + B_0x1 + LSE clock + 0x1 + + + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn + 15 + 2 + read-write + + + B_0x0 + LSILMPU oscillator clock (default) + 0x0 + + + B_0x1 + LSE oscillator clock used as slow clock + 0x1 + + + B_0x2 + LSI oscillator clock used as slow clock + 0x2 + + + B_0x3 + HSI_64M divided by 2048 used as slow clock + 0x3 + + + + + IOBOOSTEN + IO BOOSTER enable +Set and reset by software. + 17 + 1 + read-write + + + B_0x0 + does not enable IO BOOSTER + 0x0 + + + B_0x1 + enable IO BOOSTER + 0x1 + + + + + IOBOOSTCLKEXTEN + IO BOOSTER clock enable as external clock +Set and reset by software. + 18 + 1 + read-write + + + B_0x0 + does not use rcc clock (default) + 0x0 + + + B_0x1 + uses rcc clock + 0x1 + + + + + LCOEN + LCO output enable + 19 + 1 + read-write + + + SPI3I2SCLKSEL + Selection of I2S1 clock: +1x:64MHz peripheral clock + 22 + 2 + read-write + + + B_0x0 + 16MHz peripheral clock (default) + 0x0 + + + B_0x1 + 32MHz peripheral clock + 0x1 + + + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn + 24 + 2 + read-write + + + B_0x0 + LCO output disabled, no clock on LCO + 0x0 + + + B_0x1 + internal 32 KHz (LSI_LPMU) oscillator clock selected + 0x1 + + + B_0x2 + internal 32 KHz (LSI) oscillator clock selected + 0x2 + + + B_0x3 + external 32 KHz (LSE) oscillator clock selected + 0x3 + + + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. + 26 + 3 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + system clock selected + 0x1 + + + B_0x2 + na + 0x2 + + + B_0x3 + internal RC 64 MHz (HSI) oscillator clock selected + 0x3 + + + B_0x4 + external oscillator (HSE) clock selected + 0x4 + + + B_0x5 + internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected + 0x5 + + + B_0x6 + SMPS clock selected + 0x6 + + + B_0x7 + AUX ADC ANA clock selected + 0x7 + + + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +Others: not used + 29 + 3 + read-write + + + B_0x0 + CCO clock is divided by 1 + 0x0 + + + B_0x1 + CCO clock is divided by 2 + 0x1 + + + B_0x2 + CCO clock is divided by 4 + 0x2 + + + B_0x3 + CCO clock is divided by 8 + 0x3 + + + B_0x4 + CCO clock is divided by 16 + 0x4 + + + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. + 5 + 1 + read-write + + + B_0x0 + HSI PLL ready interrupt disabled + 0x0 + + + B_0x1 + HSI PLL ready interrupt enabled + 0x1 + + + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. + 6 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. + 7 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPURSTIE + LPURSTIE: LPUART reset release interrupt enable. + 9 + 1 + read-write + + + B_0x0 + LPUART reset release interrupt is disabled + 0x0 + + + B_0x1 + LPUART reset release interrupt is enabled + 0x1 + + + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. + 0 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the internal RC 32 KHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0x1 + + + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. + 1 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. + 3 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI oscillator + 0x1 + + + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. + 4 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. + 5 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x1 + + + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + LPURSTF + LPUART reset release flag + 9 + 1 + read-write + + + B_0x0 + no LPUART reset release event occurred + 0x0 + + + B_0x1 + LPUART reset release event occurred + 0x1 + + + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done + 0 + 1 + read-write + + + B_0x0 + To cancel an ongiong request - still possible until IRQ assertion + 0x0 + + + B_0x1 + To update the system clock frequency + 0x1 + + + + + CLKSYSDIV_REQ + system clock dividing factor from HSI_64M requested +Note: behavior depends on BLEEN in APB2ENR register + 1 + 3 + read-write + + + B_0x0 + div 1 (sys clock 64M) + 0x0 + + + B_0x1 + div 2 (sys clock 32M) + 0x1 + + + B_0x2 + div 4 (sys clock 16M) + 0x2 + + + B_0x3 + div 8 (sys clock 8M) + 0x3 + + + B_0x4 + div 16 (sys clock 4M) + 0x4 + + + B_0x5 + div 32 (sys clock 2M) + 0x5 + + + B_0x6 + div 64 (sys clock 1M) + 0x6 + + + + + STATUS + Status of clock switch sequence + 4 + 2 + read-only + + + B_0x0 + IDLE no switch requested + 0x0 + + + B_0x1 + ONGOING clock frequency switch is ongoing + 0x1 + + + B_0x2 + DONE clock frequency switch done + 0x2 + + + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. + 6 + 1 + read-write + + + B_0x0 + End of sequence interrupt disabled + 0x0 + + + B_0x1 + End of sequence interrupt enabled + 0x1 + + + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended + 7 + 1 + read-write + + + B_0x0 + No end of sequence event occured + 0x0 + + + B_0x1 + End of sequece event occured + 0x1 + + + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset DMA + 0x0 + + + B_0x1 + resets DMA + 0x1 + + + + + GPIOARST + GPIOA reset +Set and reset by software. + 2 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + GPIOBRST + GPIOB reset +Set and reset by software. + 3 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + CRCRST + CRC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset CRC + 0x0 + + + B_0x1 + resets CRC + 0x1 + + + + + PKARST + PKA reset +Set and reset by software. + 16 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RNGRST + RNG reset +Set and reset by software. + 18 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1: Advanced Timer reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + TIM16RST + TIM16 reset + 1 + 1 + read-write + + + B_0x0 + TIM16 IP is not under reset + 0x0 + + + B_0x1 + TIM16 IP is under reset + 0x1 + + + + + TIM17RST + TIM17 reset + 2 + 1 + read-write + + + B_0x0 + TIM17 IP is not under reset + 0x0 + + + B_0x1 + TIM17 IP is under reset + 0x1 + + + + + SYSCFGRST + SYSTEM CONFIG reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RTCRST + RTC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + WDRST + WATCHDOG reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + AUXADCRST + AUXADC reset for Aux-ADC digital clock +Set and reset by software. + 4 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + LPUARTRST + LPUART reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + USARTRST + USART reset +Set and reset by software. + 10 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + SPI3RST + SPI3 reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + I2C21RST + I2C1 reset +Set and reset by software. + 21 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + BLERST + BLE reset. + 0 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + PKAEN + PKA clock enable +Set and enable by software. + 16 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RNGEN + RNG clock enable +Set and enable by software. + 18 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2: Advanced Timer clock enable +Set and enable by software. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + TIM16EN + TIM16 enable + 1 + 1 + read-write + + + B_0x0 + TIM16 IP is clock gated + 0x0 + + + B_0x1 + TIM16 IP is clocked + 0x1 + + + + + TIM17EN + TIM17 enable + 2 + 1 + read-write + + + B_0x0 + TIM17 IP is clock gated + 0x0 + + + B_0x1 + TIM17 IP is clocked + 0x1 + + + + + SYSCFGEN + SYSTEM CONFIG enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + WDGEN + Watchdog clock enable. +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + ADCDIGEN + AUXADC clock enable for Aux-ADC digital clock +Set and enable by software. + 4 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + ADCANAEN + ADC clock enable for Aux-ADC analog clock +Set and enable by software. + 5 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + LPUARTEN + LPUART clock enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + USART1EN + USART clock enable +Set and enable by software. + 10 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + SPI3EN + SPI3 clock enable +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and enable by software. + 21 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRBLEEN + MR_BLE enable + 0 + 1 + read-write + + + B_0x0 + MR_BLE IP is clock gated + 0x0 + + + B_0x1 + MR_BLE IP is clocked + 0x1 + + + + + CLKBLEDIV + MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1 + 2 + 1 + read-write + + + B_0x0 + 32MHz + 0x0 + + + B_0x1 + 16MHz + 0x1 + + + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags + 23 + 1 + write-only + + + B_0x0 + Nothing done + 0x0 + + + B_0x1 + Reset the value of the reset flags + 0x1 + + + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. + 26 + 1 + read-only + + + B_0x0 + No reset from pad occurred + 0x0 + + + B_0x1 + Reset from pad occurred + 0x1 + + + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. + 27 + 1 + read-only + + + B_0x0 + No POWER reset occurred + 0x0 + + + B_0x1 + POWER reset occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. + 29 + 1 + read-only + + + B_0x0 + No watchdog reset occurred + 0x0 + + + B_0x1 + Watchdog reset occurred + 0x1 + + + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. + 30 + 1 + read-only + + + B_0x0 + No lockup reset occurred + 0x0 + + + B_0x1 + lockup reset occurred + 0x1 + + + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x000000030 + + + SATRG + Sense Amplifier threshold +Set by software. + 3 + 1 + read-write + + + B_0x0 + the bias current is confronted to a reference current with a ratio of 1/2. + 0x0 + + + B_0x1 + the bias current is confronted to a reference current with a ratio of 3/4 + 0x1 + + + + + GMC + High Speed External XO current control +Set by software. + 4 + 3 + read-write + + + B_0x0 + max 0.0 001: max 0.57 mA/V + 0x0 + + + B_0x2 + max 0.78 mA/V + 0x2 + + + B_0x3 + max 1.13 mA/V (Default) + 0x3 + + + B_0x4 + max 0.61 mA/V + 0x4 + + + B_0x5 + max 1.65 mA/V + 0x5 + + + B_0x6 + max 2.12 mA/V + 0x6 + + + B_0x7 + max 2.84 mA/V + 0x7 + + + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + 0x000000000 + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + + + + + SPI3 + SPI address block description + SPI + 0x41007000 + + 0x0 + 0x400 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPIx_CR1 + SPIx_CR1 + SPI control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. +Note: These bits are not used in I<sup>2</sup>S mode. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. +Note: This bit is not used in I<sup>2</sup>S mode. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +Note: This bit is not used in I<sup>2</sup>S mode. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. +Note: This bit is not used in I<sup>2</sup>S mode. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. +Note: This bit is not used in I<sup>2</sup>S mode. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPIx_CR2 + SPIx_CR2 + SPI control register 2 + 0x04 + 16 + read-write + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1 , or FRF = 1 . +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I<sup>2</sup>S mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) +Note: These bits are not used in I<sup>2</sup>S mode. + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPIx_SR + SPIx_SR + SPI status register + 0x08 + 16 + read-write + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CHSIDE + Channel side +Note: This bit is not used in SPI mode. It has no significance in PCM mode. + 2 + 1 + read-only + + + B_0x0 + Channel Left has to be transmitted or has been received + 0x0 + + + B_0x1 + Channel Right has to be transmitted or has been received + 0x1 + + + + + UDR + Underrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. +Note: This bit is not used in SPI mode. + 3 + 1 + read-only + + + B_0x0 + No underrun occurred + 0x0 + + + B_0x1 + Underrun occurred + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPIx_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPIx_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. +Note: This bit is not used in I<sup>2</sup>S mode. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. + 7 + 1 + read-only + + + B_0x0 + SPI (or I2S) not busy + 0x0 + + + B_0x1 + SPI (or I2S) is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I<sup>2</sup>S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPIx_DR + SPIx_DR + SPI data register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPIx_CRCPR + SPIx_CRCPR + SPI CRC polynomial register + 0x10 + 16 + read-write + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPIx_RXCRCR + SPIx_RXCRCR + SPI Rx CRC register + 0x14 + 16 + read-only + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_TXCRCR + SPIx_TXCRCR + SPI Tx CRC register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_I2SCFGR + SPIx_I2SCFGR + SPIx_I2S configuration register + 0x1C + 16 + read-write + 0x0000 + 0xFFFF + + + CHLEN + Channel length (number of bits per audio channel) +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. + 0 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + DATLEN + Data length to be transferred +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 1 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CKPOL + Inactive state clock polarity +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. +Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. + 3 + 1 + read-write + + + B_0x0 + I2S clock inactive state is low level + 0x0 + + + B_0x1 + I2S clock inactive state is high level + 0x1 + + + + + I2SSTD + I2S standard selection +For more details on I<sup>2</sup>S standards, refer to Section 27.7.2 on page 805 +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 4 + 2 + read-write + + + B_0x0 + I<sup>2</sup>S Philips standard + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). +Note: It is not used in SPI mode. + 7 + 1 + read-write + + + B_0x0 + Short frame synchronization + 0x0 + + + B_0x1 + Long frame synchronization + 0x1 + + + + + I2SCFG + I2S configuration mode +Note: These bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 8 + 2 + read-write + + + B_0x0 + Slave - transmit + 0x0 + + + B_0x1 + Slave - receive + 0x1 + + + B_0x2 + Master - transmit + 0x2 + + + B_0x3 + Master - receive + 0x3 + + + + + I2SE + I2S enable +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + B_0x0 + I2S peripheral is disabled + 0x0 + + + B_0x1 + I2S peripheral is enabled + 0x1 + + + + + I2SMOD + I2S mode selection +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S mode is selected + 0x1 + + + + + ASTRTEN + Asynchronous start enable. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. +Note: The appropriate transition is a falling edge on WS signal when I<sup>2</sup>S Philips Standard is used, or a rising edge for other standards. +Note: The appropriate level is a low level on WS signal when I<sup>2</sup>S Philips Standard is used, or a high level for other standards. +Note: Please refer to Section 27.7.3: Start-up description for additional information. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. + 0x0 + + + B_0x1 + The Asynchronous start is enabled. + 0x1 + + + + + + + SPIx_I2SPR + SPIx_I2SPR + SPIx_I2S prescaler register + 0x20 + 16 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. +Refer to Section 27.7.3 on page 812. +Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. +Note: They are not used in SPI mode. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +Refer to Section 27.7.3 on page 812. +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 8 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + Master clock output enable +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 9 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + TIM2 + TIM2 + 0x40002000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS: Master Mode Selection. + +This field is not available in IUM as Timer2 is not connected to ant other timer for master/slave synchronization. + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follow : + +is generated by the trigger input (slave mode controller configured in reset mode) then the signal + +on TRGO is delayed compared to the actual reset. + +start several timers at the same time or to control a window in which a slave timer is enable. The + +Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input + +when configured in gated mode. When the Counter Enable signal is controlled by the trigger + +input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit + +description in GPT_SMCR register). + +can then be used as a prescaler for a slave timer. + +(even if it was already high), as soon as a capture or a compare match occured. (TRGO). + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the GPT_EGR register is used as trigger output (TRGO). If the reset + 0x0 + + + B_0x1 + Enable - the Counter Enable signal cnt_en is used as trigger output (TRGO). It is useful to + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (TRGO). For instance a master timer + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set + 0x3 + + + B_0x4 + Compare - OC1REF signal is used as trigger output (TRGO). + 0x4 + + + B_0x5 + Compare - OC2REF signal is used as trigger output (TRGO). + 0x5 + + + B_0x6 + Compare - OC3REF signal is used as trigger output (TRGO). + 0x6 + + + B_0x7 + Compare - OC4REF signal is used as trigger output (TRGO). + 0x7 + + + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS + TS[2:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +101: Filtered Timer Input 1 (TI1FP1) + +110: Filtered Timer Input 2 (TI2FP2) + +others: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + MSM + MSM: Master/Slave mode + +Not vailable in IUM. Not used in Blue51 as TRGO is not connected to any slave timer + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection - bit 3 + +Refer to SMS description - bits2:0 + 16 + 1 + read-write + + + TS_4_3 + Extended trigger selection. Not used. Not available in IUM + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CC2DE + CC2DE: Capture/Compare 2 DMA request enable + +0: CC2 DMA request disabled + +1: CC2 DMA request enabled + 10 + 1 + read-write + + + CC3DE + CC3DE: Capture/Compare 3 DMA request enable + +0: CC3 DMA request disabled + +1: CC3 DMA request enabled + 11 + 1 + read-write + + + CC4DE + CC4DE: Capture/Compare 4 DMA request enable + +0: CC4 DMA request disabled + +1: CC4 DMA request enabled + 12 + 1 + read-write + + + TDE + TDE: Trigger DMA request Enable. + +Not used in Blue51. Not available in IUM. + +0: Trigger DMA request disabled. + +1: Trigger DMA request enabled. + 14 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as + +TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. . + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIM2_CR1 address) + (DBA + DMA index) x 4 + +where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIM2_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). + 0 + 16 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + 0x0 + 0xF + + + TI1SEL + selects TI1[0] to TI1[15] input + 0 + 4 + read-write + + + TI2SEL + selects TI2[0] to TI2[15] inputt + 8 + 4 + read-write + + + TI3SEL + selects TI3[0] to TI3[15] input + 16 + 4 + read-write + + + TI4SEL + selects TI4[0] to TI4[15] input + 24 + 4 + read-write + + + + + + + TIM16 + TIM16 + 0x40005000 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 interrupt + 26 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x00000000 + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x00000000 + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs. + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. + +0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. + +All other values: Reserved + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the + +comparison changes or when the output compare mode switches from 'frozen' mode + +to 'PWM' mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF - No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKCMP2E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 2 + 1 + read-write + + + AF1_8_3 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 3 + 6 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + BKCMP2P + BKCMP2P: BRK COMP2 input polarity. + +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP2 input is active low. + +1: COMP2 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 11 + 1 + read-write + + + AF1_13_12 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 12 + 2 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + 0x0 + 0xF + + + TI1SEL + selects TI1[0] to TI1[15] input + 0 + 4 + read-write + + + + + + + TIM17 + TIM17 + 0x40006000 + + 0x0 + 0x64 + registers + + + TIM17 + TIM16 interrupt + 27 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs. + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. + +0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. + +All other values: Reserved + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the + +comparison changes or when the output compare mode switches from 'frozen' mode + +to 'PWM' mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF - No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + TI1_RMP + TI1_RMP[1:0]: Timer 17 input 1 connection + +This bit is set and cleared by software. + +00: TIM17 TI1 is connected to GPIO + +01: TIM17 TI1 is connected to LCO + +1x: TIM17 TI1 is connected to MCO + 0 + 2 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x1 + 0xF + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKCMP2E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 2 + 1 + read-write + + + AF1_8_3 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 3 + 6 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + BKCMP2P + BKCMP2P: BRK COMP2 input polarity. + +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP2 input is active low. + +1: COMP2 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 11 + 1 + read-write + + + AF1_13_12 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 12 + 2 + read-write + + + + + + + USART + USART + 0x41004000 + + 0x0 + 0x30 + registers + + + USART + USART interrupt + 8 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + OVER8 + OVER8: Oversampling mode +-0: Oversampling by 16 +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + RTOIE + RTOIE: Receiver timeout interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register + 26 + 1 + read-write + + + EOBIE + EOBIE: End of Block interrupt enable +This bit is set and cleared by software. + + 27 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + + 0x0 + + + B_0x1 + A USART interrupt is generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SLVEN + SLVEN: Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +-0: Slave mode disabled. +-1: Slave mode enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 0 + 1 + read-write + + + DIS_NSS + DIS_NSS +When the DSI_NSS bit is set, the NSS pin input will be ignored. +-0: SPI slave selection depends on NSS input pin. +-1: SPI slave will be always selected and NSS input pin will be ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 3 + 1 + read-write + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + LBDL + LBDL: LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +-0: 10-bit break detection +-1: 11-bit break detection +This bit can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + LBDIE + LBDIE: LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +-0: Interrupt is inhibited +-1: An interrupt is generated whenever LBDF=1 in the USART_ISR register + 6 + 1 + read-write + + + LBCL + LBCL: Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) +has to be output on the SCLK pin in synchronous mode. +-0: The clock pulse of the last data bit is not output to the SCLK pin +-1: The clock pulse of the last data bit is output to the SCLK pin +Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit +format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CPHA + CPHA: Clock phase +This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It +works in conjunction with the CPOL bit to produce the desired clock/data relationship (see +Figure 137 and Figure 138) +-0: The first clock transition is the first data capture edge +-1: The second clock transition is the first data capture edge +This bit can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + CPOL + CPOL: Clock polarity +This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous +mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +-0: Steady low value on SCLK pin outside transmission window +-1: Steady high value on SCLK pin outside transmission window +This bit can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + CLKEN + CLKEN: Clock enable +This bit allows the user to enable the SCLK pin. +-0: SCLK pin disabled +-1: SCLK pin enabled +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced +by hardware to 0'. Please refer to Section 23.4: USART implementation on page 483. +Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps +below must be respected: +- UE = 0 +- SCEN = 1 +- GTPR configuration +- CLKEN= 1 +- UE = 1 + 11 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + LINEN + LINEN: LIN mode enable +This bit is set and cleared by software. +-0: LIN mode disabled +-1: LIN mode enabled +The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit +in the USART_CR1 register, and to detect LIN Sync breaks. +This bit field can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ABREN + ABREN: Auto baud rate enable +This bit is set and cleared by software. +-0: Auto baud rate detection is disabled. +-1: Auto baud rate detection is enabled. + 20 + 1 + read-write + + + ABRMOD + ABRMOD[1:0]: Auto baud rate mode +These bits are set and cleared by software. +-00: Measurement of the start bit is used to detect the baud rate. +-01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> +Frame = Start10xxxxxx) +-10: 0x7F frame detection. +-11: 0x55 frame detection +This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). + 21 + 2 + read-write + + + RTOEN + RTOEN: Receiver timeout enable +This bit is set and cleared by software. +-0: Receiver timeout feature disabled. +-1: Receiver timeout feature enabled. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle +(no reception) for the duration programmed in the RTOR (receiver timeout register). + 23 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + IREN + IREN: IrDA mode enable +This bit is set and cleared by software. +-0: IrDA disabled +-1: IrDA enabled +This bit can only be written when the USART is disabled (UE=0). + 1 + 1 + read-write + + + IRLP + IRLP: IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +-0: Normal mode +-1: Low-power mode +This bit can only be written when the USART is disabled (UE=0). + 2 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + NACK + NACK: Smartcard NACK enable +-0: NACK transmission in case of parity error is disabled +-1: NACK transmission during parity error is enabled +This bit field can only be written when the USART is disabled (UE=0). + 4 + 1 + read-write + + + SCEN + SCEN: Smartcard mode enable +This bit is used for enabling Smartcard mode. +-0: Smartcard Mode disabled +-1: Smartcard Mode enabled +This bit field can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + ONEBIT + ONEBIT: One sample bit method enable +This bit allows the user to select the sample method. When the one sample bit method is +selected the noise detection flag (NF) is disabled. +-0: Three sample bit method +-1: One sample bit method +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + SCARCNT + SCARCNT[2:0]: Smartcard auto-retry count +This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before +generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a +reception error (RXNE/RXFNE and PE bits set). +This bit field must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to +stop retransmission. +-0x0: retransmission disabled - No automatic retransmission in transmit mode. +-0x1 to 0x7: number of automatic retransmission attempts (before signaling error) + 17 + 3 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + TCBGTIE + TCBGTIE: Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register + 24 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[15:4] +BRR[15:4] = USARTDIV[15:4]BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared + 0 + 16 + read-write + + + + + GTPR + GTPR + GTPR register + 0x10 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[7:0]: Prescaler value +In IrDA Low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power Baud Rate +Used for programming the prescaler for dividing the USART source clock to achieve the lowpower +frequency: +The source clock is divided by the value given in the register (8 significant bits): +-00000000: Reserved - do not program this value +-00000001: divides the source clock by 1 +-00000010: divides the source clock by 2 +... +In Smartcard mode: +PSC[4:0]: Prescaler value +Used for programming the prescaler for dividing the USART source clock to provide the +Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor +of the source clock frequency: +-00000: Reserved - do not program this value +-00001: divides the source clock by 2 +-00010: divides the source clock by 4 +-00011: divides the source clock by 6 +... +This bit field can only be written when the USART is disabled (UE=0). + 0 + 8 + read-write + + + GT + GT[7:0]: Guard time value +This bit-field is used to program the Guard time value in terms of number of baud clock +periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time +value. +This bit field can only be written when the USART is disabled (UE=0). + 8 + 8 + read-write + + + + + RTOR + RTOR + RTOR register + 0x14 + 0x20 + read-write + 0x00000000 + + + RTO + RTO[23:0]: Receiver timeout value +This bit-field gives the Receiver timeout value in terms of number of baud clocks. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is +detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard +chapter for more details. In the standard, the CWT/BWT measurement is done starting from +the Start Bit of the last received character. + 0 + 24 + read-write + + + BLEN + BLEN[7:0]: Block Length +This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number +of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO +mode is enabled). +This bit-field can be used also in other modes. In this case, the Block length counter is reset +when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. + 24 + 8 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + ABRRQ + ABRRQ: Auto baud rate request +Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud +rate measurement on the next received data frame. + 0 + 1 + write-only + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0' +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + LBDF + LBDF: LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by +writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +-0: LIN Break not detected +-1: LIN break detected + 8 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + RTOF + RTOF: Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has +lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in +the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +-0: Timeout value not reached +-1: Timeout value reached without any data reception + 11 + 1 + read-only + + + EOBF + EOBF: End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 +Smartcard mode). The detection is done when the number of received bytes (from the start +of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR2 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +-0: End of Block not reached +-1: End of Block (number of characters) reached + 12 + 1 + read-only + + + UDR + UDR: SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock for data transmission appears +while the software has not yet loaded any value into USARTx_DR. +-0: No underrun error +-1: underrun error + 13 + 1 + read-only + + + ABRE + ABRE: Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or +character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register + 14 + 1 + read-only + + + ABRF + ABRF: Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE will also be +set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was +completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to +the ABRRQ in the USART_RQR register. + 15 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + TCBGT + TCBGT: Transmission complete before guard time flagl +This bit indicates when the last data written in the USART_TDR has been transmitted +correctly out of the shift register . +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is +complete and if there is no NACK from the smartcard. An interrupt is generated if +TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the +TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +-0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is +received from the card) +-1: Transmission is complete successfully (before Guard time completion and there is no +NACK from the smart card). + 25 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesn't reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesn't reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFECF: TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register + 5 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + TCBGTCF + TCBGTCF: Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LBDCF: LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. + 8 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + RTOCF + RTOCF: Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. + 11 + 1 + write-only + + + EOBCF + EOBCF: End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register + 12 + 1 + write-only + + + UDRCF + UDRCF:SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register + 13 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + BLUE_REG + BLUE_REG_BLOCK + 0x60000000 + + 0x0 + 0x1000 + registers + + + RADIO_TXRX + RADIO Tx/Rx interrupt + 18 + + + + INTERRUPT1REG + INTERRUPT1REG + INTERRUPT1REG register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error. + 4 + 1 + read-write + + + RXOVERFLOWERROR + Receive Overflow error. + 5 + 1 + read-write + + + SEQDONE + Sequencer end of task. + 7 + 1 + read-write + + + TXERROR_0 + Transmission error 0: transmit block missing data error. + 8 + 1 + read-write + + + TXERROR_1 + Transmission error 1: a TX skip happened during an on-going transmission. + 9 + 1 + read-write + + + TXERROR_2 + Transmission error 2: channel index is greater than 39. + 10 + 1 + read-write + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state. + 11 + 1 + read-write + + + TXERROR_4 + Transmission error 4: a CTE issue occurred. + 12 + 1 + read-write + + + ENCERROR + Encryption error on reception. + 13 + 1 + read-write + + + ALLTABLEREADYERROR + All RAM Table not ready on time. + 14 + 1 + read-write + + + TXDATAREADYERROR + Transmit data pack not ready error + + 15 + 1 + read-write + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-write + + + RCVLENGTHERROR + Receive length error. + 18 + 1 + read-write + + + SEMATIMEOUTERROR + Semaphore timeout error + + 19 + 1 + read-write + + + TXRXSKIP + Transmission/Reception skip. + 21 + 1 + read-write + + + ACTIVE2ERROR + Active2 Radio state error. + 22 + 1 + read-write + + + CONFIGERROR + Data pointer configuration error. + 23 + 1 + read-write + + + TXOK + Previous transmitted packet received OK by the peer device. + 24 + 1 + read-write + + + DONE + Receive/Transmit done. + 25 + 1 + read-write + + + RCVTIMEOUT + Receive timeout (no preamble found). + 26 + 1 + read-write + + + RCVNOMD + Received low MD bit. + 27 + 1 + read-write + + + RCVCMD + Received command + + 28 + 1 + read-write + + + TIMECAPTURETRIG + A time has been captured in TIMERCAPTUREREG. + 29 + 1 + read-write + + + RCVCRCERR + Receive data fail + + 30 + 1 + read-write + + + RCVOK + Receive data OK. + 31 + 1 + read-write + + + + + INTERRUPT2REG + INTERRUPT2REG + INTERRUPT2REG register + 0x8 + 0x20 + read-write + 0x00000000 + + + AESMANENCINT + AES manual encryption. + 0 + 1 + read-write + + + AESLEPRIVINT + AES LE privacy engine. + 1 + 1 + read-write + + + + + TIMEOUTDESTREG + TIMEOUTDESTREG + TIMEOUTDESTREG register + 0xc + 0x20 + read-write + 0x00000000 + + + DESTINATION + Timeout timer Destination + + 0 + 2 + read-write + + + + + TIMEOUTREG + TIMEOUTREG + TIMEOUTREG register + 0x10 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timer1 or Timer2 Timeout value (depending on Destination register) + + 0 + 32 + read-write + + + + + TIMERCAPTUREREG + TIMERCAPTUREREG + TIMERCAPTUREREG register + 0x14 + 0x20 + read-only + 0x00000000 + + + TIMERCAPTURE + Interpolated absolute time capture register + + 0 + 32 + read-only + + + + + CMDREG + CMDREG + CMDREG register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXRXSKIP + Transmission/Reception skip command. + 0 + 1 + write-only + + + CLEARSEMAREQ + Semaphore Clear command. + 3 + 1 + write-only + + + + + STATUSREG + STATUSREG + STATUSREG register + 0x1c + 0x20 + read-only + 0x00000000 + + + AESONFLYBUSY + AES on the fligh encryption busy status + 0 + 1 + read-only + + + NOTSUPPORTED_FUNCTION + indicates the SW requests an unsupported feature. + 3 + 1 + read-only + + + ADDPOINTERROR + Address Pointer Error status + + 4 + 1 + read-only + + + RXOVERFLOWERROR + AHB arbiter is full and there is no more storage capability available in RX datapath + 5 + 1 + read-only + + + PREVTRANSMIT + Previous event was a Transmission (1) or Reception (0) status + 6 + 1 + read-only + + + SEQDONE + Sequencer end of task status. + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 status: Transmit block missing data error. + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 status + + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 status. + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach. + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 status + + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive status + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready status + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready status. + 15 + 1 + read-only + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error status + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error status + + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip status. + 21 + 1 + read-only + + + ACTIVE2ERROR + Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step. + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error status + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK by the peer device status. + 24 + 1 + read-only + + + DONE + Receive/Transmit done status. + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout status (no access address found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit status (valid only on Data Physical Channel PDU reception) + + 27 + 1 + read-only + + + RCVCMD + Received command status (valid only on Data Physical Channel PDU reception). + 28 + 1 + read-only + + + TIMECAPTURETRIG + indicates a time has been captured in TIMERCAPTUREREG when set. + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail (CRC error or invalid CI field) status. + 30 + 1 + read-only + + + RCVOK + Receive data OK status + 31 + 1 + read-only + + + + + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG register + 0x20 + 0x20 + read-only + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error enable interruption + 4 + 1 + read-only + + + RXOVERFLOWERROR + Rx Overflow Error enable interruption + 5 + 1 + read-only + + + SEQDONE + Sequencer end of task enable interruption + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 enable interruption + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 enable interruption + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 enable interruption + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3 enable interruption + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 enable interruption + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive enable interruption + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready enable interruption + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready enable interruption + 15 + 1 + read-only + + + NOACTIVELERROR + active bit error enable interruption + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error enable interruption + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error enable interruption + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip enable interruption + 21 + 1 + read-only + + + ACTIVE2ERROR + Active2 Radio state error enable interruption + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error enable interruption + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK enable interruption + 24 + 1 + read-only + + + DONE + Receive/Transmit done interruption + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout enable interruption (no preamble found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit embedded in the PDU data packet header was zero enable interruption + 27 + 1 + read-only + + + RCVCMD + Received command enable interruption + 28 + 1 + read-only + + + TIMECAPTURETRIG + TimerCaptureReg time capture enable interruption + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail enable interruption + 30 + 1 + read-only + + + RCVOK + Receive data OK enable interruption + 31 + 1 + read-only + + + + + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG register + 0x24 + 0x20 + read-only + 0x00000000 + + + INTERRUPT1LATENCY + relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence. + 0 + 8 + read-only + + + + + MANAESKEY0REG + MANAESKEY0REG + MANAESKEY0REG register + 0x28 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_31_0 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY1REG + MANAESKEY1REG + MANAESKEY1REG register + 0x2c + 0x20 + read-write + 0x00000000 + + + MANAESKEY_63_32 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY2REG + MANAESKEY2REG + MANAESKEY2REG register + 0x30 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_95_64 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY3REG + MANAESKEY3REG + MANAESKEY3REG register + 0x34 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_127_96 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG register + 0x38 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG register + 0x3c + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG register + 0x40 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG register + 0x44 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG register + 0x48 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG register + 0x4c + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG register + 0x50 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG register + 0x54 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCMDREG + MANAESCMDREG + MANAESCMDREG register + 0x58 + 0x20 + read-write + 0x00000000 + + + START + AES Manual encryption Start command. + 0 + 1 + write-only + + + INTENA + AES Manual encryption interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + + + MANAESSTATREG + MANAESSTATREG + MANAESSTATREG register + 0x5c + 0x20 + read-only + 0x00000000 + + + BUSY + AES manual encryption busy status + 0 + 1 + read-only + + + + + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG register + 0x60 + 0x20 + read-write + 0x00000000 + + + POINTER + AES Le privacy pointer + 0 + 24 + read-write + + + + + AESLEPRIVHASHREG + AESLEPRIVHASHREG + AESLEPRIVHASHREG register + 0x64 + 0x20 + read-write + 0x00000000 + + + HASH + AES Le privacy Reference Hash + 0 + 24 + read-write + + + + + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG register + 0x68 + 0x20 + read-write + 0x00000000 + + + PRAND + AES Le privacy Prand + 0 + 24 + read-write + + + + + AESLEPRIVCMDREG + AESLEPRIVCMDREG + AESLEPRIVCMDREG register + 0x6c + 0x20 + read-write + 0x00000000 + + + START + AES Le privacy Start command. + 0 + 1 + write-only + + + INTENA + AES Le privacy interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + NBKEYS + AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list. + 2 + 8 + read-write + + + + + AESLEPRIVSTATREG + AESLEPRIVSTATREG + AESLEPRIVSTATREG register + 0x70 + 0x20 + read-only + 0x00000000 + + + BUSY + AES Le privacy busy status + 0 + 1 + read-only + + + KEYFND + AES Le privacy key finding status + 1 + 1 + read-only + + + KEYFNDINDEX + AES Le privacy index of the key found in the resolution key list. + 2 + 8 + read-only + + + + + STATUS2REG + STATUS2REG + STATUS2REG register + 0x7c + 0x20 + read-only + 0x00000000 + + + IQSAMPLESREADY + indicates if IQ samples have been received on the last reception. + 0 + 1 + read-only + + + IQSAMPLESNUMBER + indicate the number of IQ samples stored in the RAM buffer addressed by StatMach. + 1 + 7 + read-only + + + IQSAMPLESMISSINGERROR + IQ sample internal buffer overflow error flag. + 29 + 1 + read-only + + + ANTENNASWITCHINGPATTERNACCESSERROR + timing error flag related to Antenna Pattern not read on-time. + 30 + 1 + read-only + + + ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR + AHB access error flag. + 31 + 1 + read-only + + + + + + + GLOBALSTATMACH_REG + GLOBALSTATMACH_REG_BLOCK + 0x200000C0 + + 0x0 + 0x1C + registers + + + + WORD0 + WORD0 + WORD0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + RadioConfigPtr + Radio Configuration address Pointer. + 0 + 32 + read-write + + + + + WORD1 + WORD1 + WORD1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + CurStMachNum + current connection machine number. + 0 + 7 + read-write + + + Active + Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence. + 7 + 1 + read-write + + + WakeupInitDelay + Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM. + 8 + 8 + read-write + + + Timer12InitDelayCal + Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 16 + 8 + read-write + + + Timer2InitDelayNoCal + Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 24 + 8 + read-write + + + + + WORD2 + WORD2 + WORD2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + TransmitCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block. + 0 + 8 + read-write + + + TransmitNoCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse to the transmit block. + 8 + 8 + read-write + + + ReceiveCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block. + 16 + 8 + read-write + + + ReceiveNoCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse to the receive block. + 24 + 8 + read-write + + + + + WORD3 + WORD3 + WORD3 register + 0xc + 0x20 + read-write + 0x00000000 + + + ConfigEndDuration + Duration for the Sequencer to execute the final configuration. + 0 + 8 + read-write + + + TxdataReadyCheck + Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table. + 8 + 8 + read-write + + + TxdelayStart + Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator. + 16 + 8 + read-write + + + TxdelayEnd + Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer. + 24 + 6 + read-write + + + TimeCaptureSel + - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event). + 30 + 1 + read-write + + + TimeCapture + - 0: No capture is requested to monitor the Bluetooth LE sequence. + 31 + 1 + read-write + + + + + WORD4 + WORD4 + WORD4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + TxReadyTimeout + Transmission ready timeout. + 0 + 8 + read-write + + + RcvTimeout + Receive window timeout. + 8 + 20 + read-write + + + + + WORD5 + WORD5 + WORD5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + AutoTxRxskipEn + Automatic transfer (TX or RX) skip enable. + 0 + 1 + read-write + + + ChkFlagAutoClearEna + Active bit Auto Clear Enable. + 2 + 1 + read-write + + + IntAddPointError + Address pointer error interrupt enable. + 20 + 1 + read-write + + + IntAllTableReadyError + All table ready error interrupt enable. + 21 + 1 + read-write + + + IntTxDataReadyError + Transmission data payload ready error interrupt enable. + 22 + 1 + read-write + + + IntNoActiveLError + Active bit low value reading interrupt enable. + 23 + 1 + read-write + + + IntRcvLengthError + Too long received payload length interrupt enable. + 25 + 1 + read-write + + + IntSemaTimeoutError + Semaphore timeout error interrupt enable. + 26 + 1 + read-write + + + IntSeqDone + Sequencer end of task interrupt enable. + 28 + 1 + read-write + + + intTxRxSkip + Transmission or reception skip interrupt enable. + 29 + 1 + read-write + + + IntActive2Err + not in ACTIVE2 information from Radio FSM received on time interrupt enable. + 30 + 1 + read-write + + + IntConfigError + Configuration error interrupt enable. + 31 + 1 + read-write + + + + + WORD6 + WORD6 + WORD6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + DefaultAntennaID + Default Antenna ID corresponding to the number of the antenna used to receive/transmit: + + 0 + 7 + + + + + + + RADIO_CONTROL_REG + RADIO_CONTROL_REG_BLOCK + 0x60001000 + + 0x0 + 0x400 + registers + + + + RADIO_CONTROL_ID + RADIO_CONTROL_ID + RADIO_CONTROL_ID register + 0x0 + 0x20 + read-only + 0x00003000 + + + REVISION + Incremented for metal fix version + 4 + 4 + read-only + + + VERSION + Cut Number + 8 + 4 + read-only + + + PRODUCT + incremented on major features add-on like new Bluetooth LE SIG version support + + 12 + 4 + read-only + + + + + CLK32COUNT_REG + CLK32COUNT_REG + CLK32COUNT_REG register + 0x4 + 0x20 + read-write + 0x00000017 + + + SLOW_COUNT + program the window length (in slow clock period) for slow clock measurement. + 0 + 9 + read-write + + + + + CLK32PERIOD_REG + CLK32PERIOD_REG + CLK32PERIOD_REG register + 0x8 + 0x20 + read-only + 0x00000000 + + + SLOW_PERIOD + indicates slow clock period information. + 0 + 19 + read-only + + + + + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG register + 0xc + 0x20 + read-only + 0x00000000 + + + SLOW_FREQUENCY + value equal to (2^39/ SLOW_PERIOD). + 0 + 27 + read-only + + + + + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ + slow clock measurement end of calculation interrupt status + + 0 + 1 + read-write + + + RADIO_FSM_IRQ + Radio FSM interrupt status (aka RfFsm_event_irq). + 8 + 6 + read-write + + + + + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ_MASK + mask slow clock measurement interrupt + + 0 + 1 + read-write + + + RADIO_FSM_IRQ_MASK + mask for each RfFsm_event (Radio FSM) interrupt. + 8 + 6 + read-write + + + + + + + RADIO_REG_REG + RADIO_REG_REG_BLOCK + 0x60001500 + + 0x0 + 0x300 + registers + + + RADIO_ERROR + RADIO Error interrupt + 20 + + + + AA0_DIG_USR + AA0_DIG_USR + AA0_DIG_USR register + 0x0 + 0x20 + read-write + 0x000000D6 + + + AA_7_0 + Least significant byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA1_DIG_USR + AA1_DIG_USR + AA1_DIG_USR register + 0x4 + 0x20 + read-write + 0x000000BE + + + AA_15_8 + Next byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + AA2_DIG_USR + AA2_DIG_USR + AA2_DIG_USR register + 0x8 + 0x20 + read-write + 0x00000089 + + + AA_23_16 + Next byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA3_DIG_USR + AA3_DIG_USR + AA3_DIG_USR register + 0xc + 0x20 + read-write + 0x0000008E + + + AA_31_24 + Most significant byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR register + 0x10 + 0x20 + read-write + 0x00000026 + + + CHANNEL_NUM + Index for internal lock up table in which the synthesizer setup is contained. + 1 + 7 + read-write + + + + + RADIO_FSM_USR + RADIO_FSM_USR + RADIO_FSM_USR register + 0x14 + 0x20 + read-write + 0x00000004 + + + EN_CALIB_CBP + CBP calibration enable bit. + 1 + 1 + read-write + + + EN_CALIB_SYNTH + SYNTH calibration enable bit. + 2 + 1 + read-write + + + PA_POWER + PA Power coefficient. + 3 + 5 + read-write + + + + + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RXTXPHY + RXTXPHY selection. + 0 + 3 + read-write + + + + + AFC1_DIG_ENG + AFC1_DIG_ENG + AFC1_DIG_ENG register + 0x48 + 0x20 + read-write + 0x00000044 + + + AFC_DELAY_AFTER + Set the decay factor of the AFC loop after Access Address detection + 0 + 4 + read-write + + + AFC_DELAY_BEFORE + Set the decay factor of the AFC loop before Access Address detection + 4 + 4 + read-write + + + + + CR0_DIG_ENG + CR0_DIG_ENG + CR0_DIG_ENG register + 0x54 + 0x20 + read-write + 0x00000044 + + + CR_GAIN_AFTER + Set the gain of the clock recovery loop before Access Address detection to the value + + 0 + 4 + read-write + + + CR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value + + 4 + 4 + read-write + + + + + CR0_LR + CR0_LR + CR0_LR register + 0x68 + 0x20 + read-write + 0x00000066 + + + CR_LR_GAIN_AFTER + Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use + 0 + 4 + read-write + + + CR_LR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use + 4 + 4 + read-write + + + + + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG register + 0x6c + 0x20 + read-write + 0x00000000 + + + VIT_EN + Viterbi enable + + 0 + 1 + read-write + + + SPARE + spare + 2 + 6 + read-write + + + + + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG register + 0x84 + 0x20 + read-write + 0x00000050 + + + LR_PD_THR + preamble detect threshold value + 0 + 8 + read-write + + + + + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG register + 0x88 + 0x20 + read-write + 0x0000001B + + + LR_RSSI_THR + RSSI or peak threshold value + 0 + 8 + read-write + + + + + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG register + 0x8c + 0x20 + read-write + 0x00000038 + + + LR_AAC_THR + address coded correlation threshold + 0 + 8 + read-write + + + + + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG register + 0xa8 + 0x20 + read-write + 0x00000000 + + + SYNTHCAL_DEBUG_BUS_SEL + for Debug purpose + + 0 + 4 + read-write + + + SYNTH_IF_FREQ_CAL + Define the frequency applied on the PLL during calibration phase + + 6 + 2 + read-write + + + + + DTB5_DIG_ENG + DTB5_DIG_ENG + DTB5_DIG_ENG register + 0xf0 + 0x20 + read-write + 0x00000000 + + + RXTX_START_SEL + enable the possibility to control some signals by the other register bits instead of system design: + + 0 + 1 + read-write + + + TX_ACTIVE + Force TX_ACTIVE signal + 1 + 1 + read-write + + + RX_ACTIVE + Force RX_ACTIVE signal + 2 + 1 + read-write + + + INITIALIZE + Force INITIALIZE signal (emulate a token request of the IP_BLE) + 3 + 1 + read-write + + + PORT_SELECTED_EN + enable port selection + 4 + 1 + read-write + + + PORT_SELECTED_0 + force port_selected[0] signal + 5 + 1 + read-write + + + + + RXADC_ANA_USR + RXADC_ANA_USR + RXADC_ANA_USR register + 0x148 + 0x20 + read-write + 0x0000001B + + + RFD_RXADC_DELAYTRIM_I + ADC loop delay control bits for I channel to apply when SW overload is enabled + 0 + 3 + read-write + + + RFD_RXADC_DELAYTRIM_Q + ADC loop delay control bits for Q channel to apply when SW overload is enabled + 3 + 3 + read-write + + + RXADC_DELAYTRIM_I_TST_SEL + Enable the SW overload on RXADX delay trimming + + 6 + 1 + read-write + + + RXADC_DELAYTRIM_Q_TST_SEL + Enable the SW overload on RXADX delay trimming + + 7 + 1 + read-write + + + + + LDO_ANA_ENG + LDO_ANA_ENG + LDO_ANA_ENG register + 0x154 + 0x20 + read-write + 0x00000000 + + + RFD_RF_REG_BYPASS + RF_REG Bypass mode: + + 0 + 1 + read-write + + + + + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG register + 0x174 + 0x20 + read-write + 0x00000088 + + + RFD_CBIAS_IBIAS_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 0 + 4 + read-write + + + RFD_CBIAS_IPTAT_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 4 + 4 + read-write + + + + + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG register + 0x178 + 0x20 + read-write + 0x00000000 + + + CBIAS0_TRIM_TST_SEL + When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings + 7 + 1 + read-write + + + + + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT register + 0x180 + 0x20 + read-only + 0x00000000 + + + VCO_CALAMP_OUT_6_0 + VCO CALAMP value + 0 + 7 + read-only + + + + + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT register + 0x184 + 0x20 + read-only + 0x00000001 + + + VCO_CALAMP_OUT_10_7 + VCO CALAMP value + 0 + 4 + read-only + + + + + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT register + 0x188 + 0x20 + read-only + 0x00000040 + + + VCO_CALFREQ_OUT + VCO CALFREQ value + 0 + 7 + read-only + + + + + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT register + 0x18c + 0x20 + read-only + 0x00000000 + + + SYNTHCAL_DEBUG_BUS + Calibration debug bus. + 0 + 8 + read-only + + + + + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT register + 0x190 + 0x20 + read-only + 0x00000018 + + + MOD_REF_DAC_WORD_OUT + Calibration word + 0 + 6 + read-only + + + + + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT register + 0x194 + 0x20 + read-only + 0x00000007 + + + CBP_CALIB_WORD + CBP Calibration word + 0 + 4 + read-only + + + + + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT register + 0x198 + 0x20 + read-only + 0x00000000 + + + STATUS + RF FSM state: + + 0 + 5 + read-only + + + SYNTH_CAL_ERROR + PLL calibration error + 7 + 1 + read-only + + + + + RSSI0_DIG_OUT + RSSI0_DIG_OUT + RSSI0_DIG_OUT register + 0x1a4 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_7_0 + Measure of the received signal strength. + 0 + 8 + read-only + + + + + RSSI1_DIG_OUT + RSSI1_DIG_OUT + RSSI1_DIG_OUT register + 0x1a8 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_15_8 + Measure of the received signal strength + 0 + 8 + read-only + + + + + AGC_DIG_OUT + AGC_DIG_OUT + AGC_DIG_OUT register + 0x1ac + 0x20 + read-only + 0x00000000 + + + AGC_ATT_OUT + AGC attenuation value + 0 + 4 + read-only + + + + + DEMOD_DIG_OUT + DEMOD_DIG_OUT + DEMOD_DIG_OUT register + 0x1b0 + 0x20 + read-only + 0x00000000 + + + CI_FIELD + CI field + 0 + 2 + read-only + + + AAC_FOUND + aac_found + 2 + 1 + read-only + + + PD_FOUND + pd_found + 3 + 1 + read-only + + + RX_END + rx_end + 4 + 1 + read-only + + + + + AGC2_ANA_TST + AGC2_ANA_TST + AGC2_ANA_TST register + 0x1bc + 0x20 + read-write + 0x00000000 + + + AGC2_ANA_TST_SEL + Selection: + + 0 + 1 + read-write + + + AGC_ANTENNAE_USR_TRIM + the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1) + 1 + 3 + read-write + + + + + AGC0_DIG_ENG + AGC0_DIG_ENG + AGC0_DIG_ENG register + 0x1c0 + 0x20 + read-write + 0x0000004A + + + AGC_THR_HIGH + High AGC threshold + 0 + 6 + read-write + + + AGC_ENABLE + Enable AGC + 6 + 1 + read-write + + + + + AGC1_DIG_ENG + AGC1_DIG_ENG + AGC1_DIG_ENG register + 0x1c4 + 0x20 + read-write + 0x00000084 + + + AGC_THR_LOW_6 + Low threshold for 6dB steps + 0 + 6 + read-write + + + AGC_AUTOLOCK + AGC locks when level is steady between high threshold and lock threshold + 6 + 1 + read-write + + + AGC_LOCK_SYNC + AGC locks when Access Address is detected (recommended) + 7 + 1 + read-write + + + + + AGC10_DIG_ENG + AGC10_DIG_ENG + AGC10_DIG_ENG register + 0x1e8 + 0x20 + read-write + 0x00000000 + + + ATT_IF_0 + Attenuation at IF Level for the AGC step 0: + + 0 + 3 + read-write + + + ATT_LNA_0 + Attenuation at LNA Level for the AGC step 0: + + 3 + 1 + read-write + + + ATT_ANT_0 + Attenuation at Antenna Level for the AGC step 0: + + 4 + 2 + read-write + + + + + AGC11_DIG_ENG + AGC11_DIG_ENG + AGC11_DIG_ENG register + 0x1ec + 0x20 + read-write + 0x00000010 + + + ATT_IF_1 + Attenuation at IF Level for the AGC step 1 + 0 + 3 + read-write + + + ATT_LNA_1 + Attenuation at LNA Level for the AGC step 1 + 3 + 1 + read-write + + + ATT_ANT_1 + Attenuation at Antenna Level for the AGC step 1 + 4 + 2 + read-write + + + + + AGC12_DIG_ENG + AGC12_DIG_ENG + AGC12_DIG_ENG register + 0x1f0 + 0x20 + read-write + 0x000000020 + + + ATT_IF_2 + Attenuation at IF Level for the AGC step 2 + 0 + 3 + read-write + + + ATT_LNA_2 + Attenuation at LNA Level for the AGC step 2 + 3 + 1 + read-write + + + ATT_ANT_2 + Attenuation at Antenna Level for the AGC step 2 + 4 + 2 + read-write + + + + + AGC13_DIG_ENG + AGC13_DIG_ENG + AGC13_DIG_ENG register + 0x1f4 + 0x20 + read-write + 0x00000030 + + + ATT_IF_3 + Attenuation at IF Level for the AGC step 3 + 0 + 3 + read-write + + + ATT_LNA_3 + Attenuation at LNA Level for the AGC step 3 + 3 + 1 + read-write + + + ATT_ANT_3 + Attenuation at Antenna Level for the AGC step 3 + 4 + 2 + read-write + + + + + AGC14_DIG_ENG + AGC14_DIG_ENG + AGC14_DIG_ENG register + 0x1f8 + 0x20 + read-write + 0x00000038 + + + ATT_IF_4 + Attenuation at IF Level for the AGC step 4 + 0 + 3 + read-write + + + ATT_LNA_4 + Attenuation at LNA Level for the AGC step 4 + 3 + 1 + read-write + + + ATT_ANT_4 + Attenuation at Antenna Level for the AGC step 4 + 4 + 2 + read-write + + + + + AGC15_DIG_ENG + AGC15_DIG_ENG + AGC15_DIG_ENG register + 0x1fc + 0x20 + read-write + 0x00000039 + + + ATT_IF_5 + Attenuation at IF Level for the AGC step 5 + 0 + 3 + read-write + + + ATT_LNA_5 + Attenuation at LNA Level for the AGC step 5 + 3 + 1 + read-write + + + ATT_ANT_5 + Attenuation at Antenna Level for the AGC step 5 + 4 + 2 + read-write + + + + + AGC16_DIG_ENG + AGC16_DIG_ENG + AGC16_DIG_ENG register + 0x200 + 0x20 + read-write + 0x0000003A + + + ATT_IF_6 + Attenuation at IF Level for the AGC step 6 + 0 + 3 + read-write + + + ATT_LNA_6 + Attenuation at LNA Level for the AGC step 6 + 3 + 1 + read-write + + + ATT_ANT_6 + Attenuation at Antenna Level for the AGC step 6 + 4 + 2 + read-write + + + + + AGC17_DIG_ENG + AGC17_DIG_ENG + AGC17_DIG_ENG register + 0x204 + 0x20 + read-write + 0x0000003B + + + ATT_IF_7 + Attenuation at IF Level for the AGC step 7 + 0 + 3 + read-write + + + ATT_LNA_7 + Attenuation at LNA Level for the AGC step 7 + 3 + 1 + read-write + + + ATT_ANT_7 + Attenuation at Antenna Level for the AGC step 7 + 4 + 2 + read-write + + + + + AGC18_DIG_ENG + AGC18_DIG_ENG + AGC18_DIG_ENG register + 0x208 + 0x20 + read-write + 0x0000003C + + + ATT_IF_8 + Attenuation at IF Level for the AGC step 8 + 0 + 3 + read-write + + + ATT_LNA_8 + Attenuation at LNA Level for the AGC step 8 + 3 + 1 + read-write + + + ATT_ANT_8 + Attenuation at Antenna Level for the AGC step 8 + 4 + 2 + read-write + + + + + AGC19_DIG_ENG + AGC19_DIG_ENG + AGC19_DIG_ENG register + 0x20c + 0x20 + read-write + 0x0000003D + + + ATT_IF_9 + Attenuation at IF Level for the AGC step 9 + 0 + 3 + read-write + + + ATT_LNA_9 + Attenuation at LNA Level for the AGC step 9 + 3 + 1 + read-write + + + ATT_ANT_9 + Attenuation at Antenna Level for the AGC step 9 + 4 + 2 + read-write + + + + + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT register + 0x224 + 0x20 + read-only + 0x0000001B + + + HW_RXADC_DELAYTRIM_I + control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR). + 0 + 3 + read-only + + + HW_RXADC_DELAYTRIM_Q + control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR). + 3 + 3 + read-only + + + + + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT register + 0x228 + 0x20 + read-only + 0x00000088 + + + HW_CBIAS_IBIAS_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 0 + 4 + read-only + + + HW_CBIAS_IPTAT_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 4 + 4 + read-only + + + + + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT register + 0x230 + 0x20 + read-only + 0x00000006 + + + HW_AGC_ANTENNAE_TRIM + AGC trim value (provided by the HW trimming, automatically loaded on POR). + 1 + 3 + read-only + + + + + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST register + 0x23c + 0x20 + read-write + 0x00000000 + + + EXTCFG_SAMPLING_TIME + Defines the sampling time, when extended configuration is enabled: + + 0 + 2 + read-write + + + EXTCFG_TRIG_SELECTION + Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled: + + 2 + 2 + read-write + + + + + ANTSW0_DIG_USR + ANTSW0_DIG_USR + ANTSW0_DIG_USR register + 0x240 + 0x20 + read-write + 0x0000001C + + + RX_TIME_TO_SAMPLE + specifies the exact timing of the first I/Q sampling in the reference period. + 0 + 7 + read-write + + + + + ANTSW1_DIG_USR + ANTSW1_DIG_USR + ANTSW1_DIG_USR register + 0x244 + 0x20 + read-write + 0x0000000B + + + RX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching at receiver level (in AoA). + 0 + 6 + read-write + + + + + ANTSW2_DIG_USR + ANTSW2_DIG_USR + ANTSW2_DIG_USR register + 0x248 + 0x20 + read-write + 0x00000029 + + + TX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD). + 0 + 7 + read-write + + + + + ANTSW3_DIG_USR + ANTSW3_DIG_USR + ANTSW3_DIG_USR register + 0x24c + 0x20 + read-write + 0x00000023 + + + TX_TIME_TO_SWITCH_2M + specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD). + 0 + 7 + read-write + + + + + + + RRM_REG + RRM_REG_BLOCK + 0x60001400 + + 0x0 + 0x100 + registers + + + + UDRA_CTRL0 + UDRA_CTRL0 + UDRA_CTRL0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + RELOAD_RDCFGPTR + reload the radio configuration pointer from RAM. + 0 + 1 + read-write + + + + + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + UDRA interrupt enable (reload radio config pointer) + 0 + 1 + read-write + + + CMD_START + UDRA interrupt enable (command start) + 1 + 1 + read-write + + + CMD_END + UDRA interrupt enable (command end) + 2 + 1 + read-write + + + + + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + On read, returns the UDRA reload radio configuration pointer interrupt status. + 0 + 1 + read-write + + + CMD_STARD + On read, returns the UDRA command start interrupt status. + 1 + 1 + read-write + + + CMD_END + On read, returns the UDRA command end interrupt status + + 2 + 1 + read-write + + + + + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR register + 0x1c + 0x20 + read-only + 0x00000000 + + + RADIO_CONFIG_ADDRESS + UDRA radio configuration address. + 0 + 32 + read-only + + + + + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE register + 0x20 + 0x20 + read-write + 0x00000000 + + + LOCK + semaphore locked (= one port granted) interrupt enable + 0 + 1 + read-write + + + UNLOCK + semaphore unlocked (=no port selected) interrupt enable + 1 + 1 + read-write + + + + + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS register + 0x24 + 0x20 + read-write + 0x00000000 + + + LOCK + On read, returns the semaphore locked interrupt status. + 0 + 1 + read-write + + + UNLOCK + On read, returns the semaphore unlocked interrupt status. + 1 + 1 + read-write + + + + + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE register + 0x28 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE Port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE Port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + IP_BLE Port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + IP_BLE Port command end interrup enable + 4 + 1 + read-write + + + + + BLE_IRQ_STATUS + BLE_IRQ_STATUS + BLE_IRQ_STATUS register + 0x2c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE hardware port granted interrupt status: + + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE hardware port released interrupt status. + 1 + 1 + read-write + + + CMD_START + IP_BLE hardware port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + IP_BLE hardware port command end interrupt status. + 4 + 1 + read-write + + + + + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS register + 0x60 + 0x20 + read-write + 0x00000000 + + + COMMAND + command number + 0 + 3 + read-write + + + COMMAND_REQ + CPU Virtual port command request: + + 3 + 1 + read-write + + + + + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS register + 0x64 + 0x20 + read-write + 0x00000000 + + + TAKE_PRIO + semaphore priority: priority value (between 0 and 7) of the take request. + 0 + 3 + read-write + + + TAKE_REQ + semaphore token request: + + 3 + 1 + read-write + + + + + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE register + 0x68 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + CPU virtual port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + CPU virtual port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + CPU virtual port command end interrup enable + 4 + 1 + read-write + + + + + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS register + 0x6c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port granted interrupt status. + 0 + 1 + read-write + + + PORT_RELEASE + virtual port released interrupt status. + 1 + 1 + read-write + + + PORT_PREEMPT + CPU virtual port preemption (at semaphore level) interrupt status. + 2 + 1 + read-write + + + CMD_START + CPU virtual port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + CPU virtual port command end interrupt status. + 4 + 1 + read-write + + + + + + + WAKEUP_REG + WAKEUP_REG_BLOCK + 0x60001800 + + 0x0 + 0x400 + registers + + + RADIO_CPU_WKUP + RADIO CPU Wakeup interrupt + 23 + + + RADIO_TXRX_WKUP + RADIO Wakeup interrupt + 24 + + + + WAKEUP_OFFSET + WAKEUP_OFFSET + WAKEUP_OFFSET register + 0x8 + 0x20 + read-write + 0x00000000 + + + WAKEUP_OFFSET + delay of anticipation of the Soc device to settle power and clock + + 0 + 8 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0x10 + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + absolute time + + 0 + 32 + read-only + + + + + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH register + 0x14 + 0x20 + read-only + 0x00000000 + + + LENGTH + minimum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH register + 0x18 + 0x20 + read-only + 0x00000000 + + + LENGTH_FRACT + additional information/precision on slow clock frequency. + 0 + 4 + read-only + + + LENGTH_INT + average period length computed by Time Interpolator. + 4 + 10 + read-only + + + AVERAGE_COUNT + Number of slow clock cycles. + 24 + 8 + read-only + + + + + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH register + 0x1c + 0x20 + read-only + 0x00000000 + + + LENGTH + maximum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + STATISTICS_RESTART + STATISTICS_RESTART + STATISTICS_RESTART register + 0x20 + 0x20 + read-write + 0x00000000 + + + CLR_MIN_MAX + Write '1' to clear the minimum and maximum registers. + 0 + 1 + read-write + + + CLR_AVR + Write '1' to clear the AVERAGE_PERIOD_LENGTH register value. + 1 + 1 + read-write + + + + + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME register + 0x24 + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for the IP_BLE. + 0 + 32 + read-write + + + + + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE register + 0x28 + 0x20 + read-write + 0x00000007 + + + SLEEP_EN + IP_BLE sleeping mode enable: + + 29 + 1 + read-write + + + BLE_WAKEUP_EN + IP_BLE wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + IP_BLE sleeping control: + + 31 + 1 + read-write + + + + + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME register + 0x2c + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for CPU. + 4 + 28 + read-write + + + + + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE register + 0x30 + 0x20 + read-write + 0x80000007 + + + CPU_WAKEUP_EN + CPU wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + CPU sleeping control: + + 31 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE register + 0x40 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + IP_BLE wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS register + 0x44 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the IP_BLE wakeup interrupt status. + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE register + 0x48 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + CPU wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS register + 0x4c + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the CPU wakeup interrupt status. + 0 + 1 + read-write + + + + + + + diff --git a/svd/STM32WBxx/STM32WB06.svd b/svd/STM32WBxx/STM32WB06.svd new file mode 100644 index 0000000..e29c68a --- /dev/null +++ b/svd/STM32WBxx/STM32WB06.svd @@ -0,0 +1,32837 @@ + + + + STM32WB06 + 0.3 + STM32WB06 + + CM0+ + r0p0 + little + true + false + 2 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x41006000 + + 0x0 + 0x400 + registers + + + ADC + ADC interrupt + 12 + + + + VERSION_ID + VERSION_ID + VERSION_ID register + 0x00 + 0x20 + read-only + 0x00000020 + + + VERSION_ID + version of the embedded IP. + 0 + 8 + + + + + CONF + CONF + ADC configuration register + 0x04 + 0x20 + read-write + 0x00020002 + + + VBIAS_PRECH_FORCE + possibility to keep the VBIAS_PRECH enabled to deactivate the filter + 20 + 1 + + + ADC_CONT_1V2 + select the input sampling method + 19 + 1 + + + BIT_INVERT_DIFF + invert bit to bit the ADC data output when a + differential + + 18 + 1 + + + BIT_INVERT_SN + invert bit to bit the ADC data output when a single + + 17 + 1 + + + OVR_DF_CFG + decimation overrun configuration + 16 + 1 + + + OVR_DS_CFG + Down Sampler overrun configuration + 15 + 1 + + + DMA_DF_ENA + enable DMA mode for Decimation Filter data path + 14 + 1 + + + DMA_DS_ENA + enable DMA mode for Down Sampler data path + 13 + 1 + + + SAMPLE_RATE + conversion rate of ADC + 11 + 2 + + + OP_MODE + ADC mode selection (= data path selection) + 7 + 2 + + + SMPS_SYNCHRO_ENA + synchronize the ADC start conversion with a pulse + generated by the + + 6 + 1 + + + SEQ_LEN + number of conversions in a regular sequence + 2 + 4 + + + SEQUENCE + enable the sequence mode (active by default) + 1 + 1 + + + CONT + regular sequence runs continuously when ADC mode is enabled + 0 + 1 + + + + + CTRL + CTRL + ADC control register + 0x08 + 0x20 + read-write + 0x00000000 + + + ADC_LDO_ENA + enable the LDO associated to the ADC block + 5 + 1 + + + TEST_MODE + select the functional or the test mode of the ADC + 4 + 1 + + + DIG_AUD_MODE + enable the digital audio mode (the data path uses + the decimation filter) + 3 + 1 + + + STOP_OP_MOD + stop the on-going OP_MODE (ADC mode, Analog audio mode, Full + 2 + 1 + + + START_CON + generate a start pulse to initiate an ADC conversion + 1 + 1 + + + ADC_ON_OFF + ADC_ON_OFF: + +– 0: power off the ADC + +– 1: power on the ADC + 0 + 1 + + + + + OCM_CTRL + OCM_CTRL + Occasionnal mode control register + 0x0C + 0x20 + read-write + 0x00000000 + + + OCM_ENA + start occasional conversion in analog audio and full + modes + 1 + 1 + + + OCM_SRC + select the occasional conversion source + 0 + 1 + + + + + PGA_CONF + PGA_CONF + PGA configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + PGA_BIAS + set the microphone bias voltage + 4 + 3 + + + PGA_GAIN + from 6 to 30 dB + 0 + 4 + + + + + SWITCH + SWITCH + ADC switch control for Input Selection + 0x14 + 0x20 + read-write + 0x00000000 + + + SE_VIN_7 + input voltage for VINP[3] + 14 + 2 + + + SE_VIN_6 + input voltage for VINP[2] + 12 + 2 + + + SE_VIN_5 + input voltage for VINP[1] + 10 + 2 + + + SE_VIN_4 + input voltage for VINP[0] + 8 + 2 + + + SE_VIN_3 + input voltage for VINM[3] / VINP[3]-VINM[3] + 6 + 2 + + + SE_VIN_2 + input voltage for VINM[2] / VINP[2]-VINM[2] + 4 + 2 + + + SE_VIN_1 + input voltage for VINM[1] / VINP[1]-VINM[1] + 2 + 2 + + + SE_VIN_0 + input voltage for VINM[0] / VINP[0]-VINM[0] + 0 + 2 + + + + + DF_CONF + DF_CONF + Decimation filter configuration register + 0x18 + 0x20 + read-write + 0x00003015 + + + DF_HALF_D_EN + half dynamic enable. + 17 + 1 + + + DF_HPF_EN + high pass filter enable. + 16 + 1 + + + DF_MICROL_RN + left/right channel selection on digital microphone + 15 + 1 + + + PDM_RATE + select the PDM clock rate. + 11 + 4 + + + DF_O_S2U + select signed/unsigned format for data output + 10 + 1 + + + DF_I_U2S + select signed/unsigned format for input + 9 + 1 + + + DF_ITP1P2 + 1.2 fractional interpolator enable + 8 + 1 + + + DF_CIC_DHF + CIC filter decimator half factor + 7 + 1 + + + DF_CIC_DEC_FACTOR + 0 + 7 + + + + + DS_CONF + DS_CONF + Downsampler configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + DS_WIDTH + program the Down Sampler width of data output (DSDTATA) + 3 + 3 + + + DS_RATIO + program the Down Sampler ratio (N factor) + 0 + 3 + + + + + SEQ_1 + SEQ_1 + ADC regular sequence configuration register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + SEQ7 + channel number code for 8th conversion of the sequence. + 28 + 4 + + + SEQ6 + channel number code for 7th conversion of the sequence. + 24 + 4 + + + SEQ5 + channel number code for 6th conversion of the sequence. + 20 + 4 + + + SEQ4 + channel number code for 5th conversion of the sequence. + 16 + 4 + + + SEQ3 + channel number code for 4th conversion of the sequence. + 12 + 4 + + + SEQ2 + channel number code for 3rd conversion of the sequence. + 8 + 4 + + + SEQ1 + channel number code for second conversion of the sequence. + 4 + 4 + + + SEQ0 + channel number code for first conversion of the sequence + 0 + 4 + + + + + SEQ_2 + SEQ_2 + ADC regular sequence configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + SEQ15 + channel number code for 16th conversion of the sequence. + 28 + 4 + + + SEQ14 + channel number code for 15th conversion of the sequence. + 24 + 4 + + + SEQ13 + channel number code for 14th conversion of the sequence. + 20 + 4 + + + SEQ12 + channel number code for 13th conversion of the sequence. + 16 + 4 + + + SEQ11 + channel number code for 12th conversion of the sequence. + 12 + 4 + + + SEQ10 + channel number code for 11th conversion of the sequence. + 8 + 4 + + + SEQ9 + channel number code for 10th conversion of the sequence. + 4 + 4 + + + SEQ8 + channel number code for 9th conversion of the sequence + 0 + 4 + + + + + COMP_1 + COMP_1 + ADC Gain and offset correction values register 1 + 0x28 + 0x20 + read-write + 0x00000555 + + + OFFSET1 + first calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN1 + first calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_2 + COMP_2 + ADC Gain and offset correction values register 2 + + 0x2C + 0x20 + read-write + 0x00000555 + + + OFFSET2 + second calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN2 + second calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_3 + COMP_3 + ADC Gain and offset correction values register 3 + + 0x30 + 0x20 + read-write + 0x00000555 + + + OFFSET3 + third calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN3 + third calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_4 + COMP_4 + ADC Gain and offset correction values register 4 + + 0x34 + 0x20 + read-write + 0x00000555 + + + OFFSET4 + fourth calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN4 + fourth calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_SEL + COMP_SEL + ADC Gain and Offset selection values register + 0x38 + 0x20 + read-write + 0x00000000 + + + GAIN_OFFSET8 + gain / offset used in ADC differential mode with Vinput range = 3.6V + 16 + 2 + + + GAIN_OFFSET7 + gain / offset used in ADC single positive mode with Vinput range = 3.6V + 14 + 2 + + + GAIN_OFFSET6 + gain / offset used in ADC single negative mode with Vinput range = 3.6V + 12 + 2 + + + GAIN_OFFSET5 + gain / offset used in ADC differential mode with Vinput range = 2.4V + 10 + 2 + + + GAIN_OFFSET4 + gain / offset used in ADC single positive mode with Vinput range = 2.4V + 8 + 2 + + + GAIN_OFFSET3 + gain / offset used in ADC single negative mode with Vinput range = 2.4V + 6 + 2 + + + GAIN_OFFSET2 + gain / offset used in ADC differential mode with Vinput range = 1.2V + 4 + 2 + + + GAIN_OFFSET1 + gain / offset used in ADC single positive mode with Vinput range = 1.2V + 2 + 2 + + + GAIN_OFFSET0 + gain / offset used in ADC single negative mode with Vinput range = 1.2V + 0 + 2 + + + + + WD_TH + WD_TH + High/low limits for event monitoring a channel register + 0x3C + 0x20 + read-write + 0x0FFF0000 + + + WD_HT + analog watchdog high level threshold. + 16 + 12 + + + WD_LT + analog watchdog low level threshold. + 0 + 12 + + + + + WD_CONF + WD_CONF + Channel selection for event monitoring register + 0x40 + 0x20 + read-write + 0x00000000 + + + AWD_CHX + analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog. + 0 + 16 + + + + + DS_DATAOUT + DS_DATAOUT + Downsampler Data output register + 0x44 + 0x20 + read-only + 0x00000000 + + + DS_DATA + contain the converted data at the output of the Down Sampler + 0 + 16 + + + + + DF_DATAOUT + DF_DATAOUT + Decimation filter Data output register + 0x48 + 0x20 + read-only + 0x00000000 + + + DF_DATA + contain the converted data at the output of the + decimation filter. + + 0 + 16 + + + + + IRQ_STATUS + IRQ_STATUS + Interrupt Status register + 0x4C + 0x20 + read-write + 0x00000000 + + + DF_OVRFL_IRQ + set to indicate the decimation filter is saturated. + 7 + 1 + + + OVR_DF_IRQ + set to indicate a decimation filter overrun (a data is lost) + 6 + 1 + + + OVR_DS_IRQ + set to indicate a Down Sampler overrun (at least one data is lost) + 5 + 1 + + + AWD_IRQ + set when an analog watchdog event occurs + 4 + 1 + + + EOS_IRQ + set when a sequence of conversion is completed + 3 + 1 + + + EODF_IRQ + set when the decimation filter conversion is completed + 2 + 1 + + + EODS_IRQ + set when the Down Sampler conversion is completed. + 1 + 1 + + + EOC_IRQ + (Used in test mode only): set when the ADC conversion is completed. + 0 + 1 + + + + + IRQ_ENABLE + IRQ_ENABLE + Enable/disable Interrupts + 0x50 + 0x20 + read-write + 0x00000000 + + + DF_OVRFL_IRQ_ENA + decimation filter saturation interrupt enable + 7 + 1 + + + OVR_DF_IRQ_ENA + decimation filter overrun interrupt enable + 6 + 1 + + + OVR_DS_IRQ_ENA + Down Sampler overrun interrupt enable + 5 + 1 + + + AWD_IRQ_ENA + analog watchdog interrupt enable + 4 + 1 + + + EOS_IRQ_ENA + End of regular sequence interrupt enable + 3 + 1 + + + EODF_IRQ_ENA + End of conversion interrupt enable for the decimation filter output + 2 + 1 + + + EODS_IRQ_ENA + End of conversion interrupt enable for the Down Sampler output + 1 + 1 + + + EOC_IRQ_ENA + (Used in test mode only): End of ADC conversion interrupt enable + 0 + 1 + + + + + TIMER_CONF + TIMER_CONF + Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it + 0x54 + 0x20 + read-write + 0x00009628 + + + PRECH_DELAY_SEL + Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer + 16 + 1 + + + VBIAS_PRECH_DELAY + define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration + 8 + 8 + + + ADC_LDO_DELAY + define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion. + 0 + 8 + + + + + + + CRC + CRC address block description + CRC + 0x48200000 + + 0x0 + 0x400 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + DMA + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + + + GIF1 + GIF1: Channel 1 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 1 +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 1 +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 1 +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TEIF1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 1 +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 2 +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 2 +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 2 +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TEIF2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 2 +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 3 +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 3 +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 3 +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TEIF3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 3 +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 4 +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 4 +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 4 +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TEIF4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 4 +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 5 +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 5 +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 5 +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TEIF5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 5 +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 6 +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 6 +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 6 +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 6 +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 7 +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 7 +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 7 +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 7 +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 8 +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 8 +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 8 +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 8 +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + + + CGIF1 + CGIF1: Channel 1 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + + + DMAMUX + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + GPIOA + GPIOA address block description + GPIOA + 0x48000000 + + 0x0 + 0x400 + registers + + + GPIOA + GPIOA interrupt + 15 + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODER0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEEDR0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPDR0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + IDR0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + IDR1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + IDR2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + IDR3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + IDR4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + IDR5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + IDR6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + IDR7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + IDR8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + IDR9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + IDR10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + IDR11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + IDR12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + IDR13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + IDR14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + IDR15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ODR0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + ODR1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + ODR2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + ODR3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + ODR4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + ODR5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + ODR6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + ODR7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + ODR8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + ODR9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + ODR10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + ODR11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + ODR12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + ODR13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + ODR14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + ODR15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = '1' + LCKR[15:0] +WR LCKR[16] = '0' + LCKR[15:0] +WR LCKR[16] = '1' + LCKR[15:0] +RD LCKR +RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns '1' until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFR0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFR8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + I2C1 + I2C address block description + I2C + 0x41000000 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 interrupt + 3 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match Interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received Interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection Interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer Complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer Complete (TC) +Note: Transfer Complete Reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer Complete interrupt disabled + 0x0 + + + B_0x1 + Transfer Complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration Loss (ARLO) +Note: Bus Error detection (BERR) +Note: Overrun/Underrun (OVR) +Note: Timeout detection (TIMEOUT) +Note: PEC error detection (PECERR) +Note: Alert pin event detection (ALERT) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is also enabled, the digital filter is added to the analog filter. +Note: This filter can only be programmed when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wakeup from Stop mode enable +Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. +Note: WUPEN can be set only when DNF = '0000' + 18 + 1 + read-write + + + B_0x0 + Wakeup from Stop mode disable. + 0x0 + + + B_0x1 + Wakeup from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus host address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 20 + 1 + read-write + + + B_0x0 + Host address disabled. Address 0b0001000x is NACKed. + 0x0 + + + B_0x1 + Host address enabled. Address 0b0001000x is ACKed. + 0x1 + + + + + SMBDEN + SMBus device default address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. Address 0b1100001x is NACKed. + 0x0 + + + B_0x1 + Device default address enabled. Address 0b1100001x is ACKed. + 0x1 + + + + + ALERTEN + SMBus alert enable +Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). + 0x1 + + + + + PECEN + PEC enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] should be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer. + 0x0 + + + B_0x1 + Master requests a read transfer. + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode, + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit generates a START condition once the bus is free. +Note: Writing '0' to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation. + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In Master mode: +Note: Writing '0' to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation. + 0x0 + + + B_0x1 + Stop generation after current byte transfer. + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. +Note: Changing these bits when the START bit is set is not allowed. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit has no effect when RELOAD is set. +Note: This bit has no effect is slave mode when SBC=0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 26 + 1 + read-write + + + B_0x0 + No PEC transfer. + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN=0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN=0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN=0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don't care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don't care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don't care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don't care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don't care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don't care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL+1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH+1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL+1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale i2c_ker_ck in order to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings on page2521) and for SCL high and low level counters (refer to I2C master initialization on page2536). +t<sub>PRESC </sub>= (PRESC+1) x t<sub>I2CCLK</sub> + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE=0 +t<sub>TIMEOUT</sub>= (TIMEOUTA+1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE=1 +t<sub>IDLE</sub>= (TIMEOUTA+1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE=0) or high for more than t<sub>IDLE </sub>(TIDLE=1), a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT</sub>= (TIMEOUTB+1) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or t<sub>LOW</sub> detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xA0 + registers + + + RCC + Reset and Clock Controller + 1 + + + BATTERY + PVD + 2 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator OFF + 0x0 + + + B_0x1 + LSI RC oscillator ON + 0x1 + + + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn + 3 + 1 + read-only + + + B_0x0 + LSI RC oscillator not ready + 0x0 + + + B_0x1 + LSI RC oscillator ready + 0x1 + + + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn + 4 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. + 5 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn + 6 + 1 + read-write + + + B_0x0 + LSE oscillator bypass OFF + 0x0 + + + B_0x1 + LSE oscillator bypass ON + 0x1 + + + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). + 10 + 1 + read-only + + + B_0x0 + internal RC 64 MHz oscillator not ready + 0x0 + + + B_0x1 + internal RC 64 MHz oscillator ready + 0x1 + + + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF2G4 enable. +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + HSE PLL Buffer OFF + 0x0 + + + B_0x1 + HSE PLL Buffer ON + 0x1 + + + + + HSIPLLON + Internal High Speed Clock PLL enable + 13 + 1 + read-write + + + B_0x0 + PLL is OFF + 0x0 + + + B_0x1 + PLL is ON + 0x1 + + + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. + 14 + 1 + read-only + + + B_0x0 + PLL is unlocked + 0x0 + + + B_0x1 + PLL is locked + 0x1 + + + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + SMPSINV + bit to control inversion of the SMPS clock + 0 + 1 + read-write + + + B_0x0 + SMPS clock not inverted (default value) + 0x0 + + + B_0x1 + SMPS clock inverted (for debug) + 0x1 + + + + + HSESEL + Clock source selection request: + 1 + 1 + read-write + + + B_0x0 + HSI clock source is requested (default) + 0x0 + + + B_0x1 + HSE clock source is requested + 0x1 + + + + + STOPHSI + Stop HSI clock source request + 2 + 1 + read-write + + + B_0x0 + HSI is enabled (default) + 0x0 + + + B_0x1 + disable HSI is requested + 0x1 + + + + + CLKSYSDIV + CLKSYSDIV: system clock divided factor from HSI_64M. + 5 + 3 + read-write + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz + 12 + 1 + read-write + + + B_0x0 + div 2 when ANADIV=2 or 4 (default ) + 0x0 + + + B_0x1 + div 4 when ANADIV=1 or 2 + 0x1 + + + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn + 15 + 2 + read-write + + + B_0x0 + LSILMPU oscillator clock (default) + 0x0 + + + B_0x1 + LSE oscillator clock used as slow clock + 0x1 + + + B_0x2 + LSI oscillator clock used as slow clock + 0x2 + + + B_0x3 + HSI_64M divided by 2048 used as slow clock + 0x3 + + + + + IOBOOSTEN + IO BOOSTER enable +Set and reset by software. + 17 + 1 + read-write + + + B_0x0 + does not enable IO BOOSTER + 0x0 + + + B_0x1 + enable IO BOOSTER + 0x1 + + + + + SPI3I2SCLKSEL + Selection of I2S1 clock: +1x:64MHz peripheral clock + 22 + 1 + read-write + + + B_0x0 + 16MHz peripheral clock (default) + 0x0 + + + B_0x1 + 32MHz peripheral clock + 0x1 + + + + + SPI2I2SCLKSEL + Selection of I2S clock: +1x:64MHz peripheral clock + 23 + 1 + read-write + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn + 24 + 2 + read-write + + + B_0x0 + LCO output disabled, no clock on LCO + 0x0 + + + B_0x1 + internal 32 KHz (LSI_LPMU) oscillator clock selected + 0x1 + + + B_0x2 + internal 32 KHz (LSI) oscillator clock selected + 0x2 + + + B_0x3 + external 32 KHz (LSE) oscillator clock selected + 0x3 + + + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. + 26 + 3 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + system clock selected + 0x1 + + + B_0x2 + na + 0x2 + + + B_0x3 + internal RC 64 MHz (HSI) oscillator clock selected + 0x3 + + + B_0x4 + external oscillator (HSE) clock selected + 0x4 + + + B_0x5 + internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected + 0x5 + + + B_0x6 + SMPS clock selected + 0x6 + + + B_0x7 + AUX ADC ANA clock selected + 0x7 + + + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +Others: not used + 29 + 3 + read-write + + + B_0x0 + CCO clock is divided by 1 + 0x0 + + + B_0x1 + CCO clock is divided by 2 + 0x1 + + + B_0x2 + CCO clock is divided by 4 + 0x2 + + + B_0x3 + CCO clock is divided by 8 + 0x3 + + + B_0x4 + CCO clock is divided by 16 + 0x4 + + + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. + 5 + 1 + read-write + + + B_0x0 + HSI PLL ready interrupt disabled + 0x0 + + + B_0x1 + HSI PLL ready interrupt enabled + 0x1 + + + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. + 6 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. + 7 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. + 0 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the internal RC 32 KHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0x1 + + + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. + 1 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. + 3 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI oscillator + 0x1 + + + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. + 4 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. + 5 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x1 + + + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done + 0 + 1 + read-write + + + B_0x0 + To cancel an ongiong request - still possible until IRQ assertion + 0x0 + + + B_0x1 + To update the system clock frequency + 0x1 + + + + + CLKSYSDIV_REQ + system clock dividing factor from HSI_64M requested +Note: behavior depends on BLEEN in APB2ENR register + 1 + 3 + read-write + + + B_0x0 + div 1 (sys clock 64M) + 0x0 + + + B_0x1 + div 2 (sys clock 32M) + 0x1 + + + B_0x2 + div 4 (sys clock 16M) + 0x2 + + + B_0x3 + div 8 (sys clock 8M) + 0x3 + + + B_0x4 + div 16 (sys clock 4M) + 0x4 + + + B_0x5 + div 32 (sys clock 2M) + 0x5 + + + B_0x6 + div 64 (sys clock 1M) + 0x6 + + + + + STATUS + Status of clock switch sequence + 4 + 2 + read-only + + + B_0x0 + IDLE no switch requested + 0x0 + + + B_0x1 + ONGOING clock frequency switch is ongoing + 0x1 + + + B_0x2 + DONE clock frequency switch done + 0x2 + + + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. + 6 + 1 + read-write + + + B_0x0 + End of sequence interrupt disabled + 0x0 + + + B_0x1 + End of sequence interrupt enabled + 0x1 + + + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended + 7 + 1 + read-write + + + B_0x0 + No end of sequence event occured + 0x0 + + + B_0x1 + End of sequece event occured + 0x1 + + + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset DMA + 0x0 + + + B_0x1 + resets DMA + 0x1 + + + + + GPIOARST + GPIOA reset +Set and reset by software. + 2 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + GPIOBRST + GPIOB reset +Set and reset by software. + 3 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + CRCRST + CRC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset CRC + 0x0 + + + B_0x1 + resets CRC + 0x1 + + + + + PKARST + PKA reset +Set and reset by software. + 16 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RNGRST + RNG reset +Set and reset by software. + 18 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1: Advanced Timer reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + SYSCFGRST + SYSTEM CONFIG reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RTCRST + RTC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + WDGRST + WATCHDOG reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + SPI1RST + SPI1 reset + 0 + 1 + read-write + + + ADCRST + ADC reset. + 4 + 1 + read-write + + + LPUARTRST + LPUART reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + USARTRST + USART reset +Set and reset by software. + 10 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + SPI2RST + SPI2 reset. + 12 + 1 + read-write + + + SPI3RST + SPI3 reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + I2C1RST + I2C1 reset +Set and reset by software. + 21 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + I2C2RST + 2C2 reset. + 23 + 1 + read-write + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + MRBLERST + MR_BLE (Bluetooth radio) reset. + 0 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + PKAEN + PKA clock enable +Set and enable by software. + 16 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RNGEN + RNG clock enable +Set and enable by software. + 18 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 enable + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + SYSCFGEN + SYSTEM CONFIG enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + WDGEN + Watchdog clock enable. +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + SPI1EN + SPI1 enable. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + ADCDIGEN + ADC clock enable for digital part of the ADC block. + 4 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + ADCANAEN + ADC clock enable for the analog part of the ADC block. + 5 + 1 + read-write + + + LPUARTEN + LPUART clock enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + USART1EN + USART clock enable +Set and enable by software. + 10 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + SPI2EN + SPI2 enable + 12 + 1 + read-write + + + SPI3EN + SPI3 clock enable +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and enable by software. + 21 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + I2C2EN + I2C2 enable. + 23 + 1 + read-write + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRBLEEN + MR_BLE enable + 0 + 1 + read-write + + + B_0x0 + MR_BLE IP is clock gated + 0x0 + + + B_0x1 + MR_BLE IP is clocked + 0x1 + + + + + CLKBLEDIV + MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1 + 2 + 1 + read-write + + + B_0x0 + 32MHz + 0x0 + + + B_0x1 + 16MHz + 0x1 + + + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags + 23 + 1 + write-only + + + B_0x0 + Nothing done + 0x0 + + + B_0x1 + Reset the value of the reset flags + 0x1 + + + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. + 26 + 1 + read-only + + + B_0x0 + No reset from pad occurred + 0x0 + + + B_0x1 + Reset from pad occurred + 0x1 + + + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. + 27 + 1 + read-only + + + B_0x0 + No POWER reset occurred + 0x0 + + + B_0x1 + POWER reset occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. + 29 + 1 + read-only + + + B_0x0 + No watchdog reset occurred + 0x0 + + + B_0x1 + Watchdog reset occurred + 0x1 + + + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. + 30 + 1 + read-only + + + B_0x0 + No lockup reset occurred + 0x0 + + + B_0x1 + lockup reset occurred + 0x1 + + + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x000000030 + + + SATRG + Sense Amplifier threshold +Set by software. + 3 + 1 + read-write + + + B_0x0 + the bias current is confronted to a reference current with a ratio of half. + 0x0 + + + B_0x1 + the bias current is confronted to a reference current with a ratio of 3/4 + 0x1 + + + + + GMC + High Speed External XO current control +Set by software. + 4 + 3 + read-write + + + B_0x0 + max 0.0 001: max 0.57 mA/V + 0x0 + + + B_0x2 + max 0.78 mA/V + 0x2 + + + B_0x3 + max 1.13 mA/V (Default) + 0x3 + + + B_0x4 + max 0.61 mA/V + 0x4 + + + B_0x5 + max 1.65 mA/V + 0x5 + + + B_0x6 + max 2.12 mA/V + 0x6 + + + B_0x7 + max 2.84 mA/V + 0x7 + + + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + + + + + SPI3 + SPI address block description + SPI + 0x41007000 + + 0x0 + 0x400 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPIx_CR1 + SPIx_CR1 + SPI control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. +Note: These bits are not used in I<sup>2</sup>S mode. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. +Note: This bit is not used in I<sup>2</sup>S mode. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +Note: This bit is not used in I<sup>2</sup>S mode. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. +Note: This bit is not used in I<sup>2</sup>S mode. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. +Note: This bit is not used in I<sup>2</sup>S mode. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPIx_CR2 + SPIx_CR2 + SPI control register 2 + 0x04 + 16 + read-write + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1 , or FRF = 1 . +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I<sup>2</sup>S mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) +Note: These bits are not used in I<sup>2</sup>S mode. + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPIx_SR + SPIx_SR + SPI status register + 0x08 + 16 + read-write + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CHSIDE + Channel side +Note: This bit is not used in SPI mode. It has no significance in PCM mode. + 2 + 1 + read-only + + + B_0x0 + Channel Left has to be transmitted or has been received + 0x0 + + + B_0x1 + Channel Right has to be transmitted or has been received + 0x1 + + + + + UDR + Underrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. +Note: This bit is not used in SPI mode. + 3 + 1 + read-only + + + B_0x0 + No underrun occurred + 0x0 + + + B_0x1 + Underrun occurred + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPIx_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPIx_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. +Note: This bit is not used in I<sup>2</sup>S mode. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. + 7 + 1 + read-only + + + B_0x0 + SPI (or I2S) not busy + 0x0 + + + B_0x1 + SPI (or I2S) is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I<sup>2</sup>S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPIx_DR + SPIx_DR + SPI data register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPIx_CRCPR + SPIx_CRCPR + SPI CRC polynomial register + 0x10 + 16 + read-write + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPIx_RXCRCR + SPIx_RXCRCR + SPI Rx CRC register + 0x14 + 16 + read-only + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_TXCRCR + SPIx_TXCRCR + SPI Tx CRC register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_I2SCFGR + SPIx_I2SCFGR + SPIx_I2S configuration register + 0x1C + 16 + read-write + 0x0000 + 0xFFFF + + + CHLEN + Channel length (number of bits per audio channel) +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. + 0 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + DATLEN + Data length to be transferred +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 1 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CKPOL + Inactive state clock polarity +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. +Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. + 3 + 1 + read-write + + + B_0x0 + I2S clock inactive state is low level + 0x0 + + + B_0x1 + I2S clock inactive state is high level + 0x1 + + + + + I2SSTD + I2S standard selection +For more details on I<sup>2</sup>S standards, refer to Section 27.7.2 on page 805 +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 4 + 2 + read-write + + + B_0x0 + I<sup>2</sup>S Philips standard + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). +Note: It is not used in SPI mode. + 7 + 1 + read-write + + + B_0x0 + Short frame synchronization + 0x0 + + + B_0x1 + Long frame synchronization + 0x1 + + + + + I2SCFG + I2S configuration mode +Note: These bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 8 + 2 + read-write + + + B_0x0 + Slave - transmit + 0x0 + + + B_0x1 + Slave - receive + 0x1 + + + B_0x2 + Master - transmit + 0x2 + + + B_0x3 + Master - receive + 0x3 + + + + + I2SE + I2S enable +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + B_0x0 + I2S peripheral is disabled + 0x0 + + + B_0x1 + I2S peripheral is enabled + 0x1 + + + + + I2SMOD + I2S mode selection +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S mode is selected + 0x1 + + + + + ASTRTEN + Asynchronous start enable. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. +Note: The appropriate transition is a falling edge on WS signal when I<sup>2</sup>S Philips Standard is used, or a rising edge for other standards. +Note: The appropriate level is a low level on WS signal when I<sup>2</sup>S Philips Standard is used, or a high level for other standards. +Note: Please refer to Section 27.7.3: Start-up description for additional information. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. + 0x0 + + + B_0x1 + The Asynchronous start is enabled. + 0x1 + + + + + + + SPIx_I2SPR + SPIx_I2SPR + SPIx_I2S prescaler register + 0x20 + 16 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. +Refer to Section 27.7.3 on page 812. +Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. +Note: They are not used in SPI mode. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +Refer to Section 27.7.3 on page 812. +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 8 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + Master clock output enable +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 9 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + USART + USART address block description + USART + 0x41004000 + + 0x0 + 0x400 + registers + + + USART + USART interrupt + 8 + + + TIM17 + TIM16 interrupt + 27 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit +M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit +M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when RXFF=1 in the USART_ISR register + 0x1 + + + + + + + USART_CR1_ALTERNATE1 + USART_CR1_ALTERNATE1 + USART control register 1 + USART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit +M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit +M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the USART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +This bit can only be written when the USART is disabled (UE=0). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. +The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase +This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure589 and Figure590) +This bit can only be written when the USART is disabled (UE=0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +This bit can only be written when the USART is disabled (UE=0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable +This bit enables the user to enable the CK pin. +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. +In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +Note: UE = 1 + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits +These bits are used for programming the stop bits. +This bitfield can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0.5 stop bit. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1.5 stop bits + 0x3 + + + + + LINEN + LIN mode enable +This bit is set and cleared by software. +The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted (V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted (V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable +This bit is set and cleared by software. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode +These bits are set and cleared by software. +This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). +Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable +This bit is set and cleared by software. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node +These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE=0) or when the USART is disabled (UE=0). + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1 or UDR = 1 in the USART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable +This bit is set and cleared by software. +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half duplex mode is not selected + 0x0 + + + B_0x1 + Half duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable +This bit is used for enabling Smartcard mode. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 5 + 1 + read-write + + + B_0x0 + Smartcard Mode disabled + 0x0 + + + B_0x1 + Smartcard Mode enabled + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the USART is disabled (UE=0). +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the USART is disabled (UE=0) +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable +This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the USART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode). + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587. + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count +This bitfield specifies the number of retries for transmission and reception in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). +This bitfield must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. +0x1 to 0x7: number of automatic retransmission attempts (before signaling error) +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmit mode. + 0x0 + + + + + WUS + Wakeup from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 2 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + WUF active on start bit detection + 0x2 + + + B_0x3 + WUF active on RXNE/RXFNE. + 0x3 + + + + + WUFIE + Wakeup from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate +BRR[15:4] +BRR[15:4] = USARTDIV[15:4] +BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared. + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value +In IrDA low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power baud rate +PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): +In Smartcard mode: +PSC[4:0]=Prescaler value +PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: +... +... +This bitfield can only be written when the USART is disabled (UE=0). +Note: Bits [7:5] must be kept cleared if Smartcard mode is used. +Note: This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA modes are not supported. Refer to Section 53.4: USART implementation on page 2587. + 0 + 8 + read-write + + + B_0x0 + Reserved - do not program this value + 0x0 + + + B_0x1 + Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode) + 0x1 + + + B_0x2 + Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode) + 0x2 + + + B_0x3 + Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode) + 0x3 + + + B_0x1F + Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode) + 0x1F + + + B_0x20 + Divides the source clock by 32 (IrDA mode) + 0x20 + + + B_0xFF + Divides the source clock by 255 (IrDA mode) + 0xFF + + + + + GT + Guard time value +This bitfield is used to program the Guard time value in terms of number of baud clock periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value +This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. +Note: This value must only be programmed once per received character. + 0 + 24 + read-write + + + BLEN + Block Length +This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0: 0 information characters + LEC +BLEN = 1: 0 information characters + CRC +BLEN = 255: 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). +This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. +Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request +Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 0 + 1 + write-only + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This enables to discard the received data without reading them, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +When FIFO mode is disabled, writing '1' to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + read-only + 0x008000C0 + 0xF0FFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE=1 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section53.5.8: Tolerance of the USART receiver to clock deviation on page2604). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. +RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. +It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set. + 6 + 1 + read-only + + + B_0x0 + Transmission is not complete + 0x0 + + + B_0x1 + Transmission is complete + 0x1 + + + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. +An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR1 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character Match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + Break character transmitted + 0x0 + + + B_0x1 + Break character requested by setting SBKRQ bit in USART_RQR register + 0x1 + + + + + RWU + Receiver wakeup from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wakeup from low-power mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 22 + 1 + read-only + + + TXFE + TXFIFO empty +This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO full +This bit is set by hardware when the number of received data corresponds to RXFIFOsize+1 (RXFIFO full + 1 data in the USART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 53.4: USART implementation on page 2587. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. +Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE1 + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE=1 in the USART_CR3 register. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section53.5.8: Tolerance of the USART receiver to clock deviation on page2604). + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXNEIE=1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. +It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately. + 6 + 1 + read-only + + + B_0x0 + Transmission is not complete + 0x0 + + + B_0x1 + Transmission is complete + 0x1 + + + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). +An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR1 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character Match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + Break character transmitted + 0x0 + + + B_0x1 + Break character requested by setting SBKRQ bit in USART_RQR register + 0x1 + + + + + RWU + Receiver wakeup from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wakeup from low-power mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 53.4: USART implementation on page 2587. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register. + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register. + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 11 + 1 + write-only + + + EOBCF + End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register. +Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587 + 13 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register. + 17 + 1 + write-only + + + WUCF + Wakeup from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure583). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure583). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The USART input clock can be divided by a prescaler factor: +Remaining combinations: Reserved +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + BLUE + BLUE + 0x60000000 + + 0x0 + 0x1000 + registers + + + BLE_TX_RX_IRQn + BLE Tx/Rx interrupt + 18 + + + + INTERRUPT1REG + INTERRUPT1REG + INTERRUPT1REG register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error. + 4 + 1 + read-write + + + RXOVERFLOWERROR + Receive Overflow error. + 5 + 1 + read-write + + + SEQDONE + Sequencer end of task. + 7 + 1 + read-write + + + TXERROR_0 + Transmission error 0: transmit block missing data error. + 8 + 1 + read-write + + + TXERROR_1 + Transmission error 1: a TX skip happened during an on-going transmission. + 9 + 1 + read-write + + + TXERROR_2 + Transmission error 2: channel index is greater than 39. + 10 + 1 + read-write + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state. + 11 + 1 + read-write + + + TXERROR_4 + Transmission error 4: a CTE issue occurred. + 12 + 1 + read-write + + + ENCERROR + Encryption error on reception. + 13 + 1 + read-write + + + ALLTABLEREADYERROR + All RAM Table not ready on time. + 14 + 1 + read-write + + + TXDATAREADYERROR + Transmit data pack not ready error + + 15 + 1 + read-write + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-write + + + RCVLENGTHERROR + Receive length error. + 18 + 1 + read-write + + + SEMATIMEOUTERROR + Semaphore timeout error + + 19 + 1 + read-write + + + TXRXSKIP + Transmission/Reception skip. + 21 + 1 + read-write + + + ACTIVE2ERROR + Active2 Radio state error. + 22 + 1 + read-write + + + CONFIGERROR + Data pointer configuration error. + 23 + 1 + read-write + + + TXOK + Previous transmitted packet received OK by the peer device. + 24 + 1 + read-write + + + DONE + Receive/Transmit done. + 25 + 1 + read-write + + + RCVTIMEOUT + Receive timeout (no preamble found). + 26 + 1 + read-write + + + RCVNOMD + Received low MD bit. + 27 + 1 + read-write + + + RCVCMD + Received command + + 28 + 1 + read-write + + + TIMECAPTURETRIG + A time has been captured in TIMERCAPTUREREG. + 29 + 1 + read-write + + + RCVCRCERR + Receive data fail + + 30 + 1 + read-write + + + RCVOK + Receive data OK. + 31 + 1 + read-write + + + + + INTERRUPT2REG + INTERRUPT2REG + INTERRUPT2REG register + 0x8 + 0x20 + read-write + 0x00000000 + + + AESMANENCINT + AES manual encryption. + 0 + 1 + read-write + + + AESLEPRIVINT + AES LE privacy engine. + 1 + 1 + read-write + + + + + TIMEOUTDESTREG + TIMEOUTDESTREG + TIMEOUTDESTREG register + 0xc + 0x20 + read-write + 0x00000000 + + + DESTINATION + Timeout timer Destination + + 0 + 2 + read-write + + + + + TIMEOUTREG + TIMEOUTREG + TIMEOUTREG register + 0x10 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timer1 or Timer2 Timeout value (depending on Destination register) + + 0 + 32 + read-write + + + + + TIMERCAPTUREREG + TIMERCAPTUREREG + TIMERCAPTUREREG register + 0x14 + 0x20 + read-only + 0x00000000 + + + TIMERCAPTURE + Interpolated absolute time capture register + + 0 + 32 + read-only + + + + + CMDREG + CMDREG + CMDREG register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXRXSKIP + Transmission/Reception skip command. + 0 + 1 + write-only + + + CLEARSEMAREQ + Semaphore Clear command. + 3 + 1 + write-only + + + + + STATUSREG + STATUSREG + STATUSREG register + 0x1c + 0x20 + read-only + 0x00000000 + + + AESONFLYBUSY + AES on the fligh encryption busy status + 0 + 1 + read-only + + + NOTSUPPORTED_FUNCTION + indicates the SW requests an unsupported feature. + 3 + 1 + read-only + + + ADDPOINTERROR + Address Pointer Error status + + 4 + 1 + read-only + + + RXOVERFLOWERROR + AHB arbiter is full and there is no more storage capability available in RX datapath + 5 + 1 + read-only + + + PREVTRANSMIT + Previous event was a Transmission (1) or Reception (0) status + 6 + 1 + read-only + + + SEQDONE + Sequencer end of task status. + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 status: Transmit block missing data error. + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 status + + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 status. + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach. + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 status + + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive status + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready status + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready status. + 15 + 1 + read-only + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error status + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error status + + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip status. + 21 + 1 + read-only + + + ACTIVE2ERROR + Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step. + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error status + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK by the peer device status. + 24 + 1 + read-only + + + DONE + Receive/Transmit done status. + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout status (no access address found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit status (valid only on Data Physical Channel PDU reception) + + 27 + 1 + read-only + + + RCVCMD + Received command status (valid only on Data Physical Channel PDU reception). + 28 + 1 + read-only + + + TIMECAPTURETRIG + indicates a time has been captured in TIMERCAPTUREREG when set. + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail (CRC error or invalid CI field) status. + 30 + 1 + read-only + + + RCVOK + Receive data OK status + 31 + 1 + read-only + + + + + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG register + 0x20 + 0x20 + read-only + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error enable interruption + 4 + 1 + read-only + + + RXOVERFLOWERROR + Rx Overflow Error enable interruption + 5 + 1 + read-only + + + SEQDONE + Sequencer end of task enable interruption + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 enable interruption + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 enable interruption + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 enable interruption + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3 enable interruption + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 enable interruption + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive enable interruption + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready enable interruption + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready enable interruption + 15 + 1 + read-only + + + NOACTIVELERROR + active bit error enable interruption + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error enable interruption + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error enable interruption + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip enable interruption + 21 + 1 + read-only + + + ACTIVE2ERROR + Active2 Radio state error enable interruption + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error enable interruption + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK enable interruption + 24 + 1 + read-only + + + DONE + Receive/Transmit done interruption + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout enable interruption (no preamble found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit embedded in the PDU data packet header was zero enable interruption + 27 + 1 + read-only + + + RCVCMD + Received command enable interruption + 28 + 1 + read-only + + + TIMECAPTURETRIG + TimerCaptureReg time capture enable interruption + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail enable interruption + 30 + 1 + read-only + + + RCVOK + Receive data OK enable interruption + 31 + 1 + read-only + + + + + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG register + 0x24 + 0x20 + read-only + 0x00000000 + + + INTERRUPT1LATENCY + relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence. + 0 + 8 + read-only + + + + + MANAESKEY0REG + MANAESKEY0REG + MANAESKEY0REG register + 0x28 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_31_0 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY1REG + MANAESKEY1REG + MANAESKEY1REG register + 0x2c + 0x20 + read-write + 0x00000000 + + + MANAESKEY_63_32 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY2REG + MANAESKEY2REG + MANAESKEY2REG register + 0x30 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_95_64 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY3REG + MANAESKEY3REG + MANAESKEY3REG register + 0x34 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_127_96 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG register + 0x38 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG register + 0x3c + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG register + 0x40 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG register + 0x44 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG register + 0x48 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG register + 0x4c + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG register + 0x50 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG register + 0x54 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCMDREG + MANAESCMDREG + MANAESCMDREG register + 0x58 + 0x20 + read-write + 0x00000000 + + + START + AES Manual encryption Start command. + 0 + 1 + write-only + + + INTENA + AES Manual encryption interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + + + MANAESSTATREG + MANAESSTATREG + MANAESSTATREG register + 0x5c + 0x20 + read-only + 0x00000000 + + + BUSY + AES manual encryption busy status + 0 + 1 + read-only + + + + + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG register + 0x60 + 0x20 + read-write + 0x00000000 + + + POINTER + AES Le privacy pointer + 0 + 24 + read-write + + + + + AESLEPRIVHASHREG + AESLEPRIVHASHREG + AESLEPRIVHASHREG register + 0x64 + 0x20 + read-write + 0x00000000 + + + HASH + AES Le privacy Reference Hash + 0 + 24 + read-write + + + + + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG register + 0x68 + 0x20 + read-write + 0x00000000 + + + PRAND + AES Le privacy Prand + 0 + 24 + read-write + + + + + AESLEPRIVCMDREG + AESLEPRIVCMDREG + AESLEPRIVCMDREG register + 0x6c + 0x20 + read-write + 0x00000000 + + + START + AES Le privacy Start command. + 0 + 1 + write-only + + + INTENA + AES Le privacy interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + NBKEYS + AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list. + 2 + 8 + read-write + + + + + AESLEPRIVSTATREG + AESLEPRIVSTATREG + AESLEPRIVSTATREG register + 0x70 + 0x20 + read-only + 0x00000000 + + + BUSY + AES Le privacy busy status + 0 + 1 + read-only + + + KEYFND + AES Le privacy key finding status + 1 + 1 + read-only + + + KEYFNDINDEX + AES Le privacy index of the key found in the resolution key list. + 2 + 8 + read-only + + + + + DEBUGCMDREG + DEBUGCMDREG + DebugCmd register + 0x74 + 32 + read-write + 0x00000000 + + + CLEARDEBUGINT + CLEARDEBUGINT + 0 + 1 + + + SEQDEBUGMODE + SEQDEBUGMODE + 1 + 1 + + + SEQDEBUGBUSSEL + SEQDEBUGBUSSEL + 2 + 4 + + + AESDEBUGMODE + AESDEBUGMODE + 16 + 4 + + + + + DEBUGSTATUSREG + DEBUGSTATUSREG + DebugStatus register + 0x78 + 32 + read-only + 0x00000000 + + + DEBUGSTATUSREG + DEBUGSTATUSREG + 0 + 7 + + + AESDBG_0 + AESDBG_0 + 16 + 1 + + + AESDBG_1 + AESDBG_1 + 17 + 1 + + + AESDBG_2 + AESDBG_2 + 18 + 1 + + + AESDBG_3 + AESDBG_3 + 19 + 1 + + + + + + + GLOBALSTATMACH + GLOBALSTATMACH + 0x200000C0 + + 0x0 + 0x1C + registers + + + + WORD0 + WORD0 + WORD0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + RadioConfigPtr + Radio Configuration address Pointer. + 0 + 32 + read-write + + + + + WORD1 + WORD1 + WORD1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + CurStMachNum + current connection machine number. + 0 + 7 + read-write + + + Active + Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence. + 7 + 1 + read-write + + + WakeupInitDelay + Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM. + 8 + 8 + read-write + + + Timer12InitDelayCal + Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 16 + 8 + read-write + + + Timer2InitDelayNoCal + Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 24 + 8 + read-write + + + + + WORD2 + WORD2 + WORD2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + TransmitCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block. + 0 + 8 + read-write + + + TransmitNoCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse to the transmit block. + 8 + 8 + read-write + + + ReceiveCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block. + 16 + 8 + read-write + + + ReceiveNoCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse to the receive block. + 24 + 8 + read-write + + + + + WORD3 + WORD3 + WORD3 register + 0xc + 0x20 + read-write + 0x00000000 + + + ConfigEndDuration + Duration for the Sequencer to execute the final configuration. + 0 + 8 + read-write + + + TxdataReadyCheck + Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table. + 8 + 8 + read-write + + + TxdelayStart + Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator. + 16 + 8 + read-write + + + TxdelayEnd + Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer. + 24 + 6 + read-write + + + TimeCaptureSel + - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event). + 30 + 1 + read-write + + + TimeCapture + - 0: No capture is requested to monitor the Bluetooth LE sequence. + 31 + 1 + read-write + + + + + WORD4 + WORD4 + WORD4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + TxReadyTimeout + Transmission ready timeout. + 0 + 8 + read-write + + + RcvTimeout + Receive window timeout. + 8 + 20 + read-write + + + + + WORD5 + WORD5 + WORD5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + AutoTxRxskipEn + Automatic transfer (TX or RX) skip enable. + 0 + 1 + read-write + + + ChkFlagAutoClearEna + Active bit Auto Clear Enable. + 2 + 1 + read-write + + + IntAddPointError + Address pointer error interrupt enable. + 20 + 1 + read-write + + + IntAllTableReadyError + All table ready error interrupt enable. + 21 + 1 + read-write + + + IntTxDataReadyError + Transmission data payload ready error interrupt enable. + 22 + 1 + read-write + + + IntNoActiveLError + Active bit low value reading interrupt enable. + 23 + 1 + read-write + + + IntRcvLengthError + Too long received payload length interrupt enable. + 25 + 1 + read-write + + + IntSemaTimeoutError + Semaphore timeout error interrupt enable. + 26 + 1 + read-write + + + IntSeqDone + Sequencer end of task interrupt enable. + 28 + 1 + read-write + + + intTxRxSkip + Transmission or reception skip interrupt enable. + 29 + 1 + read-write + + + IntActive2Err + not in ACTIVE2 information from Radio FSM received on time interrupt enable. + 30 + 1 + read-write + + + IntConfigError + Configuration error interrupt enable. + 31 + 1 + read-write + + + + + WORD6 + WORD6 + WORD6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + DefaultAntennaID + Default Antenna ID corresponding to the number of the antenna used to receive/transmit: + + 0 + 7 + + + + + + + RADIO_CONTROL + RADIO_CONTROL + 0x60001000 + + 0x0 + 0x400 + registers + + + + RADIO_CONTROL_ID + RADIO_CONTROL_ID + RADIO_CONTROL_ID register + 0x0 + 0x20 + read-only + 0x00003000 + + + REVISION + Incremented for metal fix version + 4 + 4 + read-only + + + VERSION + Cut Number + 8 + 4 + read-only + + + PRODUCT + incremented on major features add-on like new Bluetooth LE SIG version support + + 12 + 4 + read-only + + + + + CLK32COUNT_REG + CLK32COUNT_REG + CLK32COUNT_REG register + 0x4 + 0x20 + read-write + 0x00000017 + + + SLOW_COUNT + program the window length (in slow clock period) for slow clock measurement. + 0 + 9 + read-write + + + + + CLK32PERIOD_REG + CLK32PERIOD_REG + CLK32PERIOD_REG register + 0x8 + 0x20 + read-only + 0x00000000 + + + SLOW_PERIOD + indicates slow clock period information. + 0 + 19 + read-only + + + + + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG register + 0xc + 0x20 + read-only + 0x00000000 + + + SLOW_FREQUENCY + value equal to (2^39/ SLOW_PERIOD). + 0 + 27 + read-only + + + + + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ + slow clock measurement end of calculation interrupt status + + 0 + 1 + read-write + + + RADIO_FSM_IRQ + Radio FSM interrupt status (aka RfFsm_event_irq). + 8 + 6 + read-write + + + + + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ_MASK + mask slow clock measurement interrupt + + 0 + 1 + read-write + + + RADIO_FSM_IRQ_MASK + mask for each RfFsm_event (Radio FSM) interrupt. + 8 + 6 + read-write + + + + + + + RADIO + RADIO + 0x60001500 + + 0x0 + 0x300 + registers + + + RADIO_ERROR + RADIO Error interrupt + 20 + + + RADIO_CPU_WKUP + RADIO CPU Wakeup interrupt + 23 + + + RADIO_TXRX_WKUP + RADIO Wakeup interrupt + 24 + + + RADIO_TXRX_SEQ + RADIO RX/TX sequence interrupt + 25 + + + + AA0_DIG_USR + AA0_DIG_USR + AA0_DIG_USR register + 0x0 + 0x20 + read-write + 0x000000D6 + + + AA_7_0 + Least significant byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA1_DIG_USR + AA1_DIG_USR + AA1_DIG_USR register + 0x4 + 0x20 + read-write + 0x000000BE + + + AA_15_8 + Next byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + AA2_DIG_USR + AA2_DIG_USR + AA2_DIG_USR register + 0x8 + 0x20 + read-write + 0x00000089 + + + AA_23_16 + Next byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA3_DIG_USR + AA3_DIG_USR + AA3_DIG_USR register + 0xc + 0x20 + read-write + 0x0000008E + + + AA_31_24 + Most significant byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR register + 0x10 + 0x20 + read-write + 0x00000026 + + + CHANNEL_NUM + Index for internal lock up table in which the synthesizer setup is contained. + 1 + 7 + read-write + + + + + RADIO_FSM_USR + RADIO_FSM_USR + RADIO_FSM_USR register + 0x14 + 0x20 + read-write + 0x00000004 + + + EN_CALIB_CBP + CBP calibration enable bit. + 1 + 1 + read-write + + + EN_CALIB_SYNTH + SYNTH calibration enable bit. + 2 + 1 + read-write + + + PA_POWER + PA Power coefficient. + 3 + 5 + read-write + + + + + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RXTXPHY + RXTXPHY selection. + 0 + 3 + read-write + + + + + AFC1_DIG_ENG + AFC1_DIG_ENG + AFC1_DIG_ENG register + 0x48 + 0x20 + read-write + 0x00000044 + + + AFC_DELAY_AFTER + Set the decay factor of the AFC loop after Access Address detection + 0 + 4 + read-write + + + AFC_DELAY_BEFORE + Set the decay factor of the AFC loop before Access Address detection + 4 + 4 + read-write + + + + + CR0_DIG_ENG + CR0_DIG_ENG + CR0_DIG_ENG register + 0x54 + 0x20 + read-write + 0x00000044 + + + CR_GAIN_AFTER + Set the gain of the clock recovery loop before Access Address detection to the value + + 0 + 4 + read-write + + + CR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value + + 4 + 4 + read-write + + + + + CR0_LR + CR0_LR + CR0_LR register + 0x68 + 0x20 + read-write + 0x00000066 + + + CR_LR_GAIN_AFTER + Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use + 0 + 4 + read-write + + + CR_LR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use + 4 + 4 + read-write + + + + + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG register + 0x6c + 0x20 + read-write + 0x00000000 + + + VIT_EN + Viterbi enable + + 0 + 1 + read-write + + + SPARE + spare + 2 + 6 + read-write + + + + + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG register + 0x84 + 0x20 + read-write + 0x00000050 + + + LR_PD_THR + preamble detect threshold value + 0 + 8 + read-write + + + + + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG register + 0x88 + 0x20 + read-write + 0x0000001B + + + LR_RSSI_THR + RSSI or peak threshold value + 0 + 8 + read-write + + + + + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG register + 0x8c + 0x20 + read-write + 0x00000038 + + + LR_AAC_THR + address coded correlation threshold + 0 + 8 + read-write + + + + + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG register + 0xa8 + 0x20 + read-write + 0x00000000 + + + SYNTHCAL_DEBUG_BUS_SEL + for Debug purpose + + 0 + 4 + read-write + + + SYNTH_IF_FREQ_CAL + Define the frequency applied on the PLL during calibration phase + + 6 + 2 + read-write + + + + + DTB5_DIG_ENG + DTB5_DIG_ENG + DTB5_DIG_ENG register + 0xf0 + 0x20 + read-write + 0x00000000 + + + RXTX_START_SEL + enable the possibility to control some signals by the other register bits instead of system design: + + 0 + 1 + read-write + + + TX_ACTIVE + Force TX_ACTIVE signal + 1 + 1 + read-write + + + RX_ACTIVE + Force RX_ACTIVE signal + 2 + 1 + read-write + + + INITIALIZE + Force INITIALIZE signal (emulate a token request of the IP_BLE) + 3 + 1 + read-write + + + PORT_SELECTED_EN + enable port selection + 4 + 1 + read-write + + + PORT_SELECTED_0 + force port_selected[0] signal + 5 + 1 + read-write + + + + + RXADC_ANA_USR + RXADC_ANA_USR + RXADC_ANA_USR register + 0x148 + 0x20 + read-write + 0x0000001B + + + RFD_RXADC_DELAYTRIM_I + ADC loop delay control bits for I channel to apply when SW overload is enabled + 0 + 3 + read-write + + + RFD_RXADC_DELAYTRIM_Q + ADC loop delay control bits for Q channel to apply when SW overload is enabled + 3 + 3 + read-write + + + RXADC_DELAYTRIM_I_TST_SEL + Enable the SW overload on RXADX delay trimming + + 6 + 1 + read-write + + + RXADC_DELAYTRIM_Q_TST_SEL + Enable the SW overload on RXADX delay trimming + + 7 + 1 + read-write + + + + + LDO_ANA_ENG + LDO_ANA_ENG + LDO_ANA_ENG register + 0x154 + 0x20 + read-write + 0x00000000 + + + RFD_RF_REG_BYPASS + RF_REG Bypass mode: + + 0 + 1 + read-write + + + + + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG register + 0x174 + 0x20 + read-write + 0x00000088 + + + RFD_CBIAS_IBIAS_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 0 + 4 + read-write + + + RFD_CBIAS_IPTAT_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 4 + 4 + read-write + + + + + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG register + 0x178 + 0x20 + read-write + 0x00000000 + + + CBIAS0_TRIM_TST_SEL + When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings + 7 + 1 + read-write + + + + + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT register + 0x180 + 0x20 + read-only + 0x00000000 + + + VCO_CALAMP_OUT_6_0 + VCO CALAMP value + 0 + 7 + read-only + + + + + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT register + 0x184 + 0x20 + read-only + 0x00000001 + + + VCO_CALAMP_OUT_10_7 + VCO CALAMP value + 0 + 4 + read-only + + + + + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT register + 0x188 + 0x20 + read-only + 0x00000040 + + + VCO_CALFREQ_OUT + VCO CALFREQ value + 0 + 7 + read-only + + + + + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT register + 0x18c + 0x20 + read-only + 0x00000000 + + + SYNTHCAL_DEBUG_BUS + Calibration debug bus. + 0 + 8 + read-only + + + + + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT register + 0x190 + 0x20 + read-only + 0x00000018 + + + MOD_REF_DAC_WORD_OUT + Calibration word + 0 + 6 + read-only + + + + + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT register + 0x194 + 0x20 + read-only + 0x00000007 + + + CBP_CALIB_WORD + CBP Calibration word + 0 + 4 + read-only + + + + + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT register + 0x198 + 0x20 + read-only + 0x00000000 + + + STATUS + RF FSM state: + + 0 + 5 + read-only + + + SYNTH_CAL_ERROR + PLL calibration error + 7 + 1 + read-only + + + + + RSSI0_DIG_OUT + RSSI0_DIG_OUT + RSSI0_DIG_OUT register + 0x1a4 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_7_0 + Measure of the received signal strength. + 0 + 8 + read-only + + + + + RSSI1_DIG_OUT + RSSI1_DIG_OUT + RSSI1_DIG_OUT register + 0x1a8 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_15_8 + Measure of the received signal strength + 0 + 8 + read-only + + + + + AGC_DIG_OUT + AGC_DIG_OUT + AGC_DIG_OUT register + 0x1ac + 0x20 + read-only + 0x00000000 + + + AGC_ATT_OUT + AGC attenuation value + 0 + 4 + read-only + + + + + DEMOD_DIG_OUT + DEMOD_DIG_OUT + DEMOD_DIG_OUT register + 0x1b0 + 0x20 + read-only + 0x00000000 + + + CI_FIELD + CI field + 0 + 2 + read-only + + + AAC_FOUND + aac_found + 2 + 1 + read-only + + + PD_FOUND + pd_found + 3 + 1 + read-only + + + RX_END + rx_end + 4 + 1 + read-only + + + + + AGC2_ANA_TST + AGC2_ANA_TST + AGC2_ANA_TST register + 0x1bc + 0x20 + read-write + 0x00000000 + + + AGC2_ANA_TST_SEL + Selection: + + 0 + 1 + read-write + + + AGC_ANTENNAE_USR_TRIM + the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1) + 1 + 3 + read-write + + + + + AGC0_DIG_ENG + AGC0_DIG_ENG + AGC0_DIG_ENG register + 0x1c0 + 0x20 + read-write + 0x0000004A + + + AGC_THR_HIGH + High AGC threshold + 0 + 6 + read-write + + + AGC_ENABLE + Enable AGC + 6 + 1 + read-write + + + + + AGC1_DIG_ENG + AGC1_DIG_ENG + AGC1_DIG_ENG register + 0x1c4 + 0x20 + read-write + 0x00000084 + + + AGC_THR_LOW_6 + Low threshold for 6dB steps + 0 + 6 + read-write + + + AGC_AUTOLOCK + AGC locks when level is steady between high threshold and lock threshold + 6 + 1 + read-write + + + AGC_LOCK_SYNC + AGC locks when Access Address is detected (recommended) + 7 + 1 + read-write + + + + + AGC10_DIG_ENG + AGC10_DIG_ENG + AGC10_DIG_ENG register + 0x1e8 + 0x20 + read-write + 0x00000000 + + + ATT_IF_0 + Attenuation at IF Level for the AGC step 0: + + 0 + 3 + read-write + + + ATT_LNA_0 + Attenuation at LNA Level for the AGC step 0: + + 3 + 1 + read-write + + + ATT_ANT_0 + Attenuation at Antenna Level for the AGC step 0: + + 4 + 2 + read-write + + + + + AGC11_DIG_ENG + AGC11_DIG_ENG + AGC11_DIG_ENG register + 0x1ec + 0x20 + read-write + 0x00000010 + + + ATT_IF_1 + Attenuation at IF Level for the AGC step 1 + 0 + 3 + read-write + + + ATT_LNA_1 + Attenuation at LNA Level for the AGC step 1 + 3 + 1 + read-write + + + ATT_ANT_1 + Attenuation at Antenna Level for the AGC step 1 + 4 + 2 + read-write + + + + + AGC12_DIG_ENG + AGC12_DIG_ENG + AGC12_DIG_ENG register + 0x1f0 + 0x20 + read-write + 0x000000020 + + + ATT_IF_2 + Attenuation at IF Level for the AGC step 2 + 0 + 3 + read-write + + + ATT_LNA_2 + Attenuation at LNA Level for the AGC step 2 + 3 + 1 + read-write + + + ATT_ANT_2 + Attenuation at Antenna Level for the AGC step 2 + 4 + 2 + read-write + + + + + AGC13_DIG_ENG + AGC13_DIG_ENG + AGC13_DIG_ENG register + 0x1f4 + 0x20 + read-write + 0x00000030 + + + ATT_IF_3 + Attenuation at IF Level for the AGC step 3 + 0 + 3 + read-write + + + ATT_LNA_3 + Attenuation at LNA Level for the AGC step 3 + 3 + 1 + read-write + + + ATT_ANT_3 + Attenuation at Antenna Level for the AGC step 3 + 4 + 2 + read-write + + + + + AGC14_DIG_ENG + AGC14_DIG_ENG + AGC14_DIG_ENG register + 0x1f8 + 0x20 + read-write + 0x00000038 + + + ATT_IF_4 + Attenuation at IF Level for the AGC step 4 + 0 + 3 + read-write + + + ATT_LNA_4 + Attenuation at LNA Level for the AGC step 4 + 3 + 1 + read-write + + + ATT_ANT_4 + Attenuation at Antenna Level for the AGC step 4 + 4 + 2 + read-write + + + + + AGC15_DIG_ENG + AGC15_DIG_ENG + AGC15_DIG_ENG register + 0x1fc + 0x20 + read-write + 0x00000039 + + + ATT_IF_5 + Attenuation at IF Level for the AGC step 5 + 0 + 3 + read-write + + + ATT_LNA_5 + Attenuation at LNA Level for the AGC step 5 + 3 + 1 + read-write + + + ATT_ANT_5 + Attenuation at Antenna Level for the AGC step 5 + 4 + 2 + read-write + + + + + AGC16_DIG_ENG + AGC16_DIG_ENG + AGC16_DIG_ENG register + 0x200 + 0x20 + read-write + 0x0000003A + + + ATT_IF_6 + Attenuation at IF Level for the AGC step 6 + 0 + 3 + read-write + + + ATT_LNA_6 + Attenuation at LNA Level for the AGC step 6 + 3 + 1 + read-write + + + ATT_ANT_6 + Attenuation at Antenna Level for the AGC step 6 + 4 + 2 + read-write + + + + + AGC17_DIG_ENG + AGC17_DIG_ENG + AGC17_DIG_ENG register + 0x204 + 0x20 + read-write + 0x0000003B + + + ATT_IF_7 + Attenuation at IF Level for the AGC step 7 + 0 + 3 + read-write + + + ATT_LNA_7 + Attenuation at LNA Level for the AGC step 7 + 3 + 1 + read-write + + + ATT_ANT_7 + Attenuation at Antenna Level for the AGC step 7 + 4 + 2 + read-write + + + + + AGC18_DIG_ENG + AGC18_DIG_ENG + AGC18_DIG_ENG register + 0x208 + 0x20 + read-write + 0x0000003C + + + ATT_IF_8 + Attenuation at IF Level for the AGC step 8 + 0 + 3 + read-write + + + ATT_LNA_8 + Attenuation at LNA Level for the AGC step 8 + 3 + 1 + read-write + + + ATT_ANT_8 + Attenuation at Antenna Level for the AGC step 8 + 4 + 2 + read-write + + + + + AGC19_DIG_ENG + AGC19_DIG_ENG + AGC19_DIG_ENG register + 0x20c + 0x20 + read-write + 0x0000003D + + + ATT_IF_9 + Attenuation at IF Level for the AGC step 9 + 0 + 3 + read-write + + + ATT_LNA_9 + Attenuation at LNA Level for the AGC step 9 + 3 + 1 + read-write + + + ATT_ANT_9 + Attenuation at Antenna Level for the AGC step 9 + 4 + 2 + read-write + + + + + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT register + 0x224 + 0x20 + read-only + 0x0000001B + + + HW_RXADC_DELAYTRIM_I + control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR). + 0 + 3 + read-only + + + HW_RXADC_DELAYTRIM_Q + control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR). + 3 + 3 + read-only + + + + + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT register + 0x228 + 0x20 + read-only + 0x00000088 + + + HW_CBIAS_IBIAS_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 0 + 4 + read-only + + + HW_CBIAS_IPTAT_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 4 + 4 + read-only + + + + + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT register + 0x230 + 0x20 + read-only + 0x00000006 + + + HW_AGC_ANTENNAE_TRIM + AGC trim value (provided by the HW trimming, automatically loaded on POR). + 1 + 3 + read-only + + + + + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST register + 0x23c + 0x20 + read-write + 0x00000000 + + + EXTCFG_SAMPLING_TIME + Defines the sampling time, when extended configuration is enabled: + + 0 + 2 + read-write + + + EXTCFG_TRIG_SELECTION + Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled: + + 2 + 2 + read-write + + + + + ANTSW0_DIG_USR + ANTSW0_DIG_USR + ANTSW0_DIG_USR register + 0x240 + 0x20 + read-write + 0x0000001C + + + RX_TIME_TO_SAMPLE + specifies the exact timing of the first I/Q sampling in the reference period. + 0 + 7 + read-write + + + + + ANTSW1_DIG_USR + ANTSW1_DIG_USR + ANTSW1_DIG_USR register + 0x244 + 0x20 + read-write + 0x0000000B + + + RX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching at receiver level (in AoA). + 0 + 6 + read-write + + + + + ANTSW2_DIG_USR + ANTSW2_DIG_USR + ANTSW2_DIG_USR register + 0x248 + 0x20 + read-write + 0x00000029 + + + TX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD). + 0 + 7 + read-write + + + + + ANTSW3_DIG_USR + ANTSW3_DIG_USR + ANTSW3_DIG_USR register + 0x24c + 0x20 + read-write + 0x00000023 + + + TX_TIME_TO_SWITCH_2M + specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD). + 0 + 7 + read-write + + + + + + + RRM + RRM + 0x60001400 + + 0x0 + 0x100 + registers + + + + UDRA_CTRL0 + UDRA_CTRL0 + UDRA_CTRL0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + RELOAD_RDCFGPTR + reload the radio configuration pointer from RAM. + 0 + 1 + read-write + + + + + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + UDRA interrupt enable (reload radio config pointer) + 0 + 1 + read-write + + + CMD_START + UDRA interrupt enable (command start) + 1 + 1 + read-write + + + CMD_END + UDRA interrupt enable (command end) + 2 + 1 + read-write + + + + + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + On read, returns the UDRA reload radio configuration pointer interrupt status. + 0 + 1 + read-write + + + CMD_STARD + On read, returns the UDRA command start interrupt status. + 1 + 1 + read-write + + + CMD_END + On read, returns the UDRA command end interrupt status + + 2 + 1 + read-write + + + + + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR register + 0x1c + 0x20 + read-only + 0x00000000 + + + RADIO_CONFIG_ADDRESS + UDRA radio configuration address. + 0 + 32 + read-only + + + + + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE register + 0x20 + 0x20 + read-write + 0x00000000 + + + LOCK + semaphore locked (= one port granted) interrupt enable + 0 + 1 + read-write + + + UNLOCK + semaphore unlocked (=no port selected) interrupt enable + 1 + 1 + read-write + + + + + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS register + 0x24 + 0x20 + read-write + 0x00000000 + + + LOCK + On read, returns the semaphore locked interrupt status. + 0 + 1 + read-write + + + UNLOCK + On read, returns the semaphore unlocked interrupt status. + 1 + 1 + read-write + + + + + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE register + 0x28 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE Port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE Port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + IP_BLE Port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + IP_BLE Port command end interrup enable + 4 + 1 + read-write + + + + + BLE_IRQ_STATUS + BLE_IRQ_STATUS + BLE_IRQ_STATUS register + 0x2c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE hardware port granted interrupt status: + + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE hardware port released interrupt status. + 1 + 1 + read-write + + + CMD_START + IP_BLE hardware port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + IP_BLE hardware port command end interrupt status. + 4 + 1 + read-write + + + + + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS register + 0x60 + 0x20 + read-write + 0x00000000 + + + COMMAND + command number + 0 + 3 + read-write + + + COMMAND_REQ + CPU Virtual port command request: + + 3 + 1 + read-write + + + + + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS register + 0x64 + 0x20 + read-write + 0x00000000 + + + TAKE_PRIO + semaphore priority: priority value (between 0 and 7) of the take request. + 0 + 3 + read-write + + + TAKE_REQ + semaphore token request: + + 3 + 1 + read-write + + + + + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE register + 0x68 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + CPU virtual port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + CPU virtual port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + CPU virtual port command end interrup enable + 4 + 1 + read-write + + + + + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS register + 0x6c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port granted interrupt status. + 0 + 1 + read-write + + + PORT_RELEASE + virtual port released interrupt status. + 1 + 1 + read-write + + + PORT_PREEMPT + CPU virtual port preemption (at semaphore level) interrupt status. + 2 + 1 + read-write + + + CMD_START + CPU virtual port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + CPU virtual port command end interrupt status. + 4 + 1 + read-write + + + + + + + WAKEUP + WAKEUP + 0x60001800 + + 0x0 + 0x400 + registers + + + + WAKEUP_OFFSET + WAKEUP_OFFSET + WAKEUP_OFFSET register + 0x8 + 0x20 + read-write + 0x00000000 + + + WAKEUP_OFFSET + delay of anticipation of the Soc device to settle power and clock + + 0 + 8 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0x10 + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + absolute time + + 0 + 32 + read-only + + + + + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH register + 0x14 + 0x20 + read-only + 0x00000000 + + + LENGTH + minimum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH register + 0x18 + 0x20 + read-only + 0x00000000 + + + LENGTH_FRACT + additional information/precision on slow clock frequency. + 0 + 4 + read-only + + + LENGTH_INT + average period length computed by Time Interpolator. + 4 + 10 + read-only + + + AVERAGE_COUNT + Number of slow clock cycles. + 24 + 8 + read-only + + + + + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH register + 0x1c + 0x20 + read-only + 0x00000000 + + + LENGTH + maximum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + STATISTICS_RESTART + STATISTICS_RESTART + STATISTICS_RESTART register + 0x20 + 0x20 + read-write + 0x00000000 + + + CLR_MIN_MAX + Write '1' to clear the minimum and maximum registers. + 0 + 1 + read-write + + + CLR_AVR + Write '1' to clear the AVERAGE_PERIOD_LENGTH register value. + 1 + 1 + read-write + + + + + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME register + 0x24 + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for the IP_BLE. + 0 + 32 + read-write + + + + + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE register + 0x28 + 0x20 + read-write + 0x00000007 + + + SLEEP_EN + IP_BLE sleeping mode enable: + + 29 + 1 + read-write + + + BLE_WAKEUP_EN + IP_BLE wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + IP_BLE sleeping control: + + 31 + 1 + read-write + + + + + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME register + 0x2c + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for CPU. + 4 + 28 + read-write + + + + + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE register + 0x30 + 0x20 + read-write + 0x80000007 + + + CPU_WAKEUP_EN + CPU wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + CPU sleeping control: + + 31 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE register + 0x40 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + IP_BLE wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS register + 0x44 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the IP_BLE wakeup interrupt status. + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE register + 0x48 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + CPU wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS register + 0x4c + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the CPU wakeup interrupt status. + 0 + 1 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x2000 + registers + + + FLASH + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +- 0x11 : ERASE +- 0x22 : MASSERASE +- 0x33 : WRITE +- 0x44 : MASSWRITE +- 0x55 : MASSREAD +- 0x66 : IFRERASE +- 0x77 : IFRWRITE +- 0x88 : IFRMASSWRITE +- 0x99 : IFRMASSREAD +- 0xAA : SLEEP +- 0xBB : WAKEUP +- 0xCC : BURSTWRITE +- 0xDD : IFRBURSTWRITE +- 0xEE : OTPWRITE +- 0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + REMAP + Bit to redirect boot area on SRAM0. + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +- 0 : burst write allowed +- 1 : burst write forbidden + 2 + 1 + read-write + + + WAIT_STATES + Number of wait states to be inserted on Flash read (AHB accesses) + 4 + 2 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + Command done masked interrupt status. + 0 + 1 + read-write + + + CMDSTART_MIS + Command started masked interrupt status. + 1 + 1 + read-write + + + CMDERR_MIS + Command error masked interrupt status. + 2 + 1 + read-write + + + ILLCMD_MIS + Illegal command masked interrupt status + 3 + 1 + read-write + + + READOK_MIS + Mass read OK masked interrupt status. + 4 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + Command done mask + 0 + 1 + read-write + + + CMDSTARTM + Command started mask. + 1 + 1 + read-write + + + CMDERRM + Command error mask. + 2 + 1 + read-write + + + ILLCMDM + Illegal command mask. + 3 + 1 + read-write + + + READOKM + Mass read OK mask. + 4 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + Command done raw/unmasked interrupt status. This it is set once the requested command +execution is completed. Cleared by writing 1. + 0 + 1 + read-write + + + CMDSTART_RIS + Command started raw/unmasked interrupt status. This bit is set once the requested command +execution has started. + 1 + 1 + read-write + + + CMDERR_RIS + Command error raw/unmasked interrupt status + 2 + 1 + read-write + + + ILLCMD_RIS + Illegal command raw/unmasked interrupt status. + 3 + 1 + read-write + + + READOK_RIS + Mass read OK raw/unmasked interrupt status + 4 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0000FFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +- 00 : 0x0BFFF (192kb) +- 01 : 0x0FFFF (256kb) +- 10 : 0x17FFF (384kb) +- 11 : 0x1FFFF (512kb) + 0 + 16 + read-only + + + RAM_SIZE + RAM memory size selection: +- 00 : 32kb +- 01 : 32kb +- 10 : 48kb +- 11 : 64kb + 17 + 2 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + SWD_DISABLE + Flash+SWD protection: +0: No SWD protection (refer to FLASH_SECURE) +1: Flash and SWD protected + + 20 + 1 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEG0 + First segment definition. + 0 + 16 + read-write + + + SEG1 + Second segment definition. See SEG0 description for details on SEG1[31:16] content + 16 + 16 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEG2 + Third segment definition. See PAGEPROT0 SEG0 description for details on SEG2[15:0] content + 0 + 16 + read-write + + + SEG3 + Fourth segment definition. See PAGEPROT0 SEG0 description for details on SEG3[15:0] content. + 16 + 16 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + + + RNG + RNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + + RNG_CR + RNG_CR + RNG_CR register + 0x00 + 0x20 + read-write + 0x0000FF00 + + + RNG_DIS + This bit enables or disables the random number generator. +0: RNG is enabled (default) +1: RNG is disabled. The internal free-running oscillators are put in power-down +mode and the RNG clock is stopped at the input of the block. + 1 + 1 + read-write + + + B_0x0 + The RNG core is enabled + + 0x0 + + + B_0x1 + The RNG core is disabled + 0x1 + + + + + TST_CLK + Reset reveal clock error flags when writing a '1' without resetting the whole TRNG. +When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. + 3 + 1 + read-write + + + B_0x0 + no reset + + 0x0 + + + B_0x1 + reset revclk flag + + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + RNGRDY + New random value ready + 0 + 1 + read-only + + + B_0x0 + Normal operation. + + 0x0 + + + B_0x1 + RNG is disabled. + 0x1 + + + + + REVCLK + RNGCLK clock reveal bit. + 1 + 1 + read-only + + + B_0x0 + At least one oscillator is ON + 0x0 + + + B_0x1 + All oscillators are down + + 0x1 + + + + + FAULT + Fault reveal bit. + 2 + 1 + read-only + + + B_0x0 + Internal clock for RNG clock is present. + + 0x0 + + + B_0x1 + Internal RNG clock is not present. + 0x1 + + + + + + + RNG_VAL + RNG_VAL + RNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RND_VAL + Random value + 0 + 16 + read-only + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA0 + registers + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. + 0 + 1 + read-write + + + B_0x0 + Deep Stop mode (default) + 0x0 + + + B_0x1 + Shutdown mode + 0x1 + + + + + ENSDNBOR + Enable BOR reset supervising during SHUTDOWN mode. + 1 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU + 4 + 1 + read-write + + + B_0x1 + the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. + 0x1 + + + B_0x0 + the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 0x0 + + + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +then PVDO=1) + 1 + 3 + read-write + + + B_0x0 + 2.05 V - Lowest level + 0x0 + + + B_0x1 + 2.20 V + 0x1 + + + B_0x2 + 2.36 V + 0x2 + + + B_0x3 + 2.52 V + 0x3 + + + B_0x4 + 2.64 V + 0x4 + + + B_0x5 + 2.81 V + 0x5 + + + B_0x6 + 2.91 V - Highest level + 0x6 + + + B_0x7 + External input analog voltage (compare internally to VBGP; When external input <VBGP + 0x7 + + + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode + 5 + 1 + read-write + + + B_0x1 + RAM1 bank is powered during low power mode + 0x1 + + + B_0x0 + RAM1 bank is disabled during low power mode (by default) + 0x0 + + + + + RAMRET2 + Enables the RAM2 bank retention in DEEPSTOP mode. + 6 + 1 + read-write + + + RAMRET3 + Enables the RAM3 bank retention in DEEPSTOP mode. + 7 + 1 + read-write + + + B_0x1 + Temperature sensor is enabled + 0x1 + + + B_0x0 + Temperature sensor is disabled + 0x0 + + + + + ENTS + Enable the temperature sensor. + 9 + 1 + read-write + + + LSILPMUFEN + LSI LPMU force enable. + 10 + 1 + read-write + + + + + CR3 + CR3 + CR3 register + 0x8 + 0x20 + read-write + 0x0000 + + + EWU0 + EWU0 Enable WakeUp line 0 (PB0) +When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit. + 0 + 1 + read-write + + + EWU1 + EWU1 Enable WakeUp line 1 (PB1) +When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit. + 1 + 1 + read-write + + + EWU2 + EWU2 Enable WakeUp line 2 (PB2) +When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit. + 2 + 1 + read-write + + + EWU3 + EWU3 Enable WakeUp line 3 (PB3) +When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit. + 3 + 1 + read-write + + + EWU4 + EWU4 Enable WakeUp line 4 (PB4) +When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit. + 4 + 1 + read-write + + + EWU5 + EWU5 Enable WakeUp line 5 (PB5) +When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit. + 5 + 1 + read-write + + + EWU6 + EWU6 Enable WakeUp line 6 (PB6) +When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit. + 6 + 1 + read-write + + + EWU7 + EWU7 Enable WakeUp line 7 (PB7) +When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit. + 7 + 1 + read-write + + + EWU8 + EWU8 Enable WakeUp line 8 (PA8) +When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit. + 8 + 1 + read-write + + + EWU9 + EWU9 Enable WakeUp line 9 (PA9) +When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit. + 9 + 1 + read-write + + + EWU10 + EWU10 Enable WakeUp line 10 (PA10) +When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit. + 10 + 1 + read-write + + + EWU11 + EWU11 Enable WakeUp line 11 (PA11) +When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit. + 11 + 1 + read-write + + + EWBLE + EWBLE: Enable wakeup on BLE event. +0: Wakeup on BLE line is disabled (default). +1: Wakeup on BLE line is enabled. + 12 + 1 + read-write + + + EWBLEHCPU + EWBLEHCPU: Enable wakeup on BLE Host CPU event. +0: Wakeup on BLE Host CPU line is disabled (default). +1: Wakeup on BLE Host CPU line is enabled. + 13 + 1 + read-write + + + EIWL + EIWL: Enable wakeup on Internal event (RTC). +0: Wakeup on internal line is disabled (default). +1: Wakeup on internal line is enabled. + 15 + 1 + read-write + + + + + CR4 + CR4 + CR4 register + 0xc + 0x20 + read-write + 0x0 + + + WUP0 + WUP0 Wake-up Line Polarity 0 (PB0) +This bit defines the polarity used for event detection on external wake-up line 0 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP1 + WUP1 Wake-up Line Polarity 1 (PB1) +This bit defines the polarity used for event detection on external wake-up line 1 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP2 + WUP2 Wake-up Line Polarity 2 (PB2) +This bit defines the polarity used for event detection on external wake-up line 2 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP3 + WUP3 Wake-up Line Polarity 3 (PB3) +This bit defines the polarity used for event detection on external wake-up line 3 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP4 + WUP4 Wake-up Line Polarity 4 (PB4) +This bit defines the polarity used for event detection on external wake-up line 4 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP5 + WUP5 Wake-up Line Polarity 5 (PB5) +This bit defines the polarity used for event detection on external wake-up line 5 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP6 + WUP6 Wake-up Line Polarity 6 (PB6) +This bit defines the polarity used for event detection on external wake-up line 6 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP7 + WUP7 Wake-up Line Polarity 7 (PB7) +This bit defines the polarity used for event detection on external wake-up line 7 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP8 + WUP8 Wake-up Line Polarity 8 (PA8) +This bit defines the polarity used for event detection on external wake-up line 8 + 8 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP9 + WUP9 Wake-up Line Polarity 9 (PA9) +This bit defines the polarity used for event detection on external wake-up line 9 + 9 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP10 + WUP10 Wake-up Line Polarity 10 (PA10) +This bit defines the polarity used for event detection on external wake-up line 10 + 10 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP11 + WUP11 Wake-up Line Polarity 11 (PA11) +This bit defines the polarity used for event detection on external wake-up line 11 + 11 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + SR1 + SR1 + SR1 register + 0x10 + 0x20 + read-write + 0x0 + + + WUF0 + WUF0 WakeUp Flag 0 (PB0) +This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF1 + WUF1 WakeUp Flag 1 (PB1) +This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF2 + WUF2 WakeUp Flag 2 (PB2) +This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF3 + WUF3 WakeUp Flag 3 (PB3) +This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF4 + WUF4 WakeUp Flag 4 (PB4) +This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF5 + WUF5 WakeUp Flag 5 (PB5) +This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF6 + WUF6 WakeUp Flag 6 (PB6) +This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF7 + WUF7 WakeUp Flag 7 (PB7) +This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF8 + WUF8 WakeUp Flag 8 (PA8) +This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 8 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF9 + WUF9 WakeUp Flag 9 (PA9) +This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 9 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF10 + WUF10 WakeUp Flag 10 (PA10) +This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 10 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF11 + WUF11 WakeUp Flag 11 (PA11) +This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 11 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WBLEF + WBLEF: BLE wakeup flag. +0: no wakeup from BLE occurred since last clear. +1: a wakeup from BLE occurred since last clear. +Cleared by writing 1 in this bit. + 12 + 1 + read-write + + + WBLEHCPUF + WBLEHCPUF: BLE Host CPU wakeup flag. +0: no wakeup from BLE Host CPU occurred since last clear. +1: a wakeup from BLE Host CPU occurred since last clear. +Cleared by writing 1 in this bit. + 13 + 1 + read-write + + + IWUF + IWUF: Internal wakeup flag (RTC). +0: no wakeup from RTC occurred since last clear. +1: a wakeup from RTC occurred since last clear. +Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of +the RTC wakeup line on the PWRC block). + 15 + 1 + read-only + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0x0306 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. + 2 + 1 + read-only + + + B_0x0 + SMPS regulator is not ready + 0x0 + + + B_0x1 + SMPS regulator is ready. + 0x1 + + + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. + 8 + 1 + read-only + + + B_0x0 + LP regulator is not ready. + 0x0 + + + B_0x1 + LP regulator is ready. + 0x1 + + + + + REGMS + REGMS: Regulator Main LDO Started +This bit provides the information whether main regulator is ready. + 9 + 1 + read-only + + + B_0x0 + Main regulator is not ready. + 0x0 + + + B_0x1 + Main regulator is ready. + 0x1 + + + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: + 4 + 2 + read-write + + + B_0x0 + BOM1 + 0x0 + + + B_0x1 + BOM2 (default) + 0x1 + + + B_0x2 + BOM3 + 0x2 + + + B_0x3 + n/a + 0x3 + + + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. + 8 + 1 + read-write + + + B_0x0 + in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. + 0x0 + + + B_0x1 + in Low Power mode, SMPS is disabled, output is floating + 0x1 + + + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. + 9 + 1 + read-write + + + B_0x0 + no effect (by default) + 0x0 + + + B_0x1 + SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 0x1 + + + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. + 10 + 1 + read-write + + + B_0x0 + No effect, SMPS is enabled. + 0x0 + + + B_0x1 + SMPS is disabled; + 0x1 + + + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode + 11 + 1 + read-write + + + B_0x0 + disable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. + 12 + 1 + read-write + + + B_0x0 + SMPS clock detection enabled (default) + 0x0 + + + B_0x1 + SMPS clock detection disabled + 0x1 + + + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0x0F07 + + + PUA + PUA[x] : Pull Up +Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port A[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRA[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port A[i] + 0x0 + + + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PDA + PDA[x]: Pull Down +Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port A[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port A[i] + 0x0 + + + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xF0FF + + + PUB + PUB[x] : Pull Up +Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port B[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRB[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port B[i] + 0x0 + + + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PDB + PDB[x]: Pull Down +Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port B[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port B[i] + 0x0 + + + + + + + CR6 + CR6 + CR6 register + 0x30 + 0x20 + read-write + 0x0000 + + + EWU12 + EWU12 Enable WakeUp line 12 (PA0) +When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit. + 0 + 1 + read-write + + + EWU13 + EWU13 Enable WakeUp line 13 (PA1) +When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit. + 1 + 1 + read-write + + + EWU14 + EWU14 Enable WakeUp line 14 (PA2) +When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit. + 2 + 1 + read-write + + + EWU15 + EWU15 Enable WakeUp line 15 (PA3) +When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit. + 3 + 1 + read-write + + + EWU16 + EWU16 Enable WakeUp line 16 (PB12) +When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit. + 4 + 1 + read-write + + + EWU17 + EWU17 Enable WakeUp line 17 (PB13) +When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit. + 5 + 1 + read-write + + + EWU18 + EWU18 Enable WakeUp line 18 (PB14) +When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit. + 6 + 1 + read-write + + + EWU19 + EWU19 Enable WakeUp line 19 (PB15) +When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit. + 7 + 1 + read-write + + + EWU20 + Enable wakeup on PB8 I/O event. + 8 + 1 + read-write + + + EWU21 + Enable wakeup on PB9 I/O event. + 9 + 1 + read-write + + + EWU22 + Enable wakeup on PB10 I/O event. + 10 + 1 + read-write + + + EWU23 + Enable wakeup on PB11 I/O event. + 11 + 1 + read-write + + + EWU24 + Enable wakeup on PA12 I/O event. + 12 + 1 + read-write + + + EWU25 + Enable wakeup on PA13 I/O event. + 13 + 1 + read-write + + + EWU26 + Enable wakeup on PA14 I/O event. + 14 + 1 + read-write + + + EWU27 + Enable wakeup on PA15 I/O event. + 15 + 1 + read-write + + + + + CR7 + CR7 + CR7 register + 0x34 + 0x20 + read-write + 0x0 + + + WUP12 + WUP12 Wake-up Line Polarity 12 (PA0) +This bit defines the polarity used for event detection on external wake-up line 12 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP13 + WUP13 Wake-up Line Polarity 13 (PA1) +This bit defines the polarity used for event detection on external wake-up line 13 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP14 + WUP14 Wake-up Line Polarity 14 (PA2) +This bit defines the polarity used for event detection on external wake-up line 14 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP15 + WUP15 Wake-up Line Polarity 15 (PA3) +This bit defines the polarity used for event detection on external wake-up line 15 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP16 + WUP16 Wake-up Line Polarity 16 (PB12) +This bit defines the polarity used for event detection on external wake-up line 16 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP17 + WUP17 Wake-up Line Polarity 17 (PB13) +This bit defines the polarity used for event detection on external wake-up line 17 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP18 + WUP18 Wake-up Line Polarity 18 (PB14) +This bit defines the polarity used for event detection on external wake-up line 18 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP19 + WUP19 Wake-up Line Polarity 19 (PB15) +This bit defines the polarity used for event detection on external wake-up line 19 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP20 + Wake-up polarity for PB8 IO event. + 8 + 1 + read-write + + + WUP21 + Wake-up polarity for PB9 IO event. + 9 + 1 + read-write + + + WUP22 + Wake-up polarity for PB10 IO event. + 10 + 1 + read-write + + + WUP23 + Wake-up polarity for PB11 IO event. + 11 + 1 + read-write + + + WUP24 + Wake-up polarity for PB12 IO event. + 12 + 1 + read-write + + + WUP25 + Wake-up polarity for PB13 IO event. + 13 + 1 + read-write + + + WUP26 + Wake-up polarity for PB14 IO event. + 14 + 1 + read-write + + + WUP27 + Wake-up polarity for PB15 IO event. + 15 + 1 + read-write + + + + + SR3 + SR3 + SR3 register + 0x38 + 0x20 + read-write + 0x0 + + + WUF12 + WUF12 WakeUp Flag 12 PA0 +This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF13 + WUF13 WakeUp Flag 13 PA1 +This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF14 + WUF14 WakeUp Flag 14 PA2 +This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF15 + WUF15 WakeUp Flag 15 PA3 +This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF16 + WUF16 WakeUp Flag 16 PB12 +This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF17 + WUF17 WakeUp Flag 17 PB13 +This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF18 + WUF18 WakeUp Flag 18 PB14 +This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF19 + PA7 I/O wake-up flag. + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF20 + PB8 I/O wake-up flag. + 8 + 1 + read-write + + + WUF21 + PB9 I/O wake-up flag. + 9 + 1 + read-write + + + WUF22 + PB10 I/O wake-up flag. + 10 + 1 + read-write + + + WUF23 + PB11 I/O wake-up flag. + 11 + 1 + read-write + + + WUF24 + PB12 I/O wake-up flag. + 12 + 1 + read-write + + + WUF25 + PB13 I/O wake-up flag. + 13 + 1 + read-write + + + WUF26 + PB14 I/O wake-up flag. + 14 + 1 + read-write + + + WUF27 + PB15 I/O wake-up flag. + 15 + 1 + read-write + + + + + IOxCFG + IOxCFG + IOxCFG register + 0x40 + 0x20 + read-write + 0x0 + + + IOCFG0 + Drive configuration for PA8. + 0 + 2 + read-write + + + IOCFG1 + Drive configuration for PA9. + 2 + 2 + read-write + + + IOCFG2 + Drive configuration for PA10. + 4 + 2 + read-write + + + IOCFG3 + Drive configuration for PA11. + 6 + 2 + read-write + + + IOCFG4 + Drive configuration for PA4. + 8 + 2 + read-write + + + IOCFG5 + Drive configuration for PA5. + 10 + 2 + read-write + + + IOCFG6 + Drive configuration for PA6. + 12 + 2 + read-write + + + IOCFG7 + Drive configuration for PA7. + 14 + 2 + read-write + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. +0: normal DEEPSTOP will be applied +1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP. + 0 + 1 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field + 9 + 1 + read-write + + + B_0x0 + System has not been in DEEPSTOP mode + 0x0 + + + B_0x1 + System has been in DEEPSTOP mode + 0x1 + + + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a Radio wake-up event (BLE activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. + 10 + 1 + read-write + + + B_0x0 + RF IP does not require attention + 0x0 + + + B_0x1 + RF IP awake and requesting system attention + 0x1 + + + + + + + + + PKA + PKA + 0x48300000 + + 0x0 + 0x1400 + registers + + + PKA + PKA interrupt + 13 + + + + PKA_CSR + PKA_CSR + PKA_CSR register + 0x00 + 0x20 + read-write + 0x00000000 + + + GO + PKA start processing command. +Writing 0 has no effect +Writing 1 starts the encryption engine + 0 + 1 + read-write + + + READY + PKA readiness status. +0: The PKA is still computing +1: The PKA is ready to start a new calculation + 1 + 1 + read-only + + + SFT_RST + PKA software reset. +Writing 0 clears the bit and releases the PKA block reset. +Writing 1 resets the PKA block. The PKA RAM content is not changed. + 7 + 1 + read-write + + + + + PKA_ISR + PKA_ISR + PKA_ISR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PROC_END + PKA process ending interrupt. When read: +0: No new event detected +1: The PKA process is ended (This bit is set to 1 when the PKA_CSR.READY bit +rises.) +When written: +To clear the pending interrupt, the user must write this bit to 1 and clear it just after by writing +0. If the write 0 does not occur, the interrupt is generated on next event towards the CPU +if enabled in PKA_IER but the flag is seen at 0 when the interrupt handler reads it in this +register (as clear action is still active). + 0 + 1 + read-write + + + RAM_ERR + RAM read / write access error interrupt. + 2 + 1 + read-write + + + ADD_ERR + AHB Address error interrupt. + 3 + 1 + read-write + + + + + PKA_IEN + PKA_IEN + PKA_IEN register + 0x08 + 0x20 + read-write + 0x00000000 + + + READY_EN + READY interrupt enable. + 0 + 1 + read-write + + + RAMERR_EN + RAM access error interrupt enable. + 2 + 1 + read-write + + + ADDERR_EN + AHB Address error interrupt enable. + 3 + 1 + read-write + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55005555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +00: No pullup, pulldown +01: Pullup +10: Pulldown +11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pullup or pulldown +00: No pullup, pulldown +01: Pullup +10: Pulldown +11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + read-write + 0x00000000 + + + BS0 + BS0: Port B set bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 7 + 1 + write-only + + + BS12 + BS12: Port B set bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit 14 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit 15 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 23 + 1 + write-only + + + BR12 + BR12: Port B reset bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit 14 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit 15 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + read-write + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + read-write + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + read-write + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + read-write + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + read-write + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + read-write + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + read-write + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + read-write + + + BR12 + BR12 Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + read-write + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + read-write + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + read-write + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be 1011 i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + SPI2 + SPI2 + 0x41003000 + + 0x0 + 0x24 + registers + + + SPI2 + SPI2 interrupt + 6 + + + + SPI2_CR1 + SPI2_CR1 + SPI2_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI2_CR2 + SPI2_CR2 + SPI2_CR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI2_SR + SPI2_SR + SPI2_SR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI2_DR + SPI2_DR + SPI2_DR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI2_CRCPR + SPI2_CRCPR + SPI2_CRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI2_RXCRCR + SPI2_RXCRCR + SPI2_RXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI2_TXCRCR + SPI2_TXCRCR + SPI2_TXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 16 + read-only + + + + + SPI2_I2SCFGR + SPI2_I2SCFGR + SPI2_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +- 0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. +- 1: The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + + + SPI2_I2SPR + SPI2_I2SPR + SPI2_I2SPR register + 0x20 + 0x20 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + SPI1 + SPI1 + 0x41002000 + + 0x0 + 0x24 + registers + + + SPI1 + SPI1 interrupt + 5 + + + + SPI1_CR1 + SPI1_CR1 + SPI1_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI1_CR2 + SPI1_CR2 + SPI1_CR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI1_SR + SPI1_SR + SPI1_SR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI1_DR + SPI1_DR + SPI1_DR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI1_CRCPR + SPI1_CRCPR + SPI1_CRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI1_RXCRCR + SPI1_RXCRCR + SPI1_RXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI1_TXCRCR + SPI1_TXCRCR + SPI1_TXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 16 + read-only + + + + + SPI1_I2SCFGR + SPI1_I2SCFGR + SPI1_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +- 0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. +- 1: The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + + + SPI1_I2SPR + SPI1_I2SPR + SPI1_I2SPR register + 0x20 + 0x20 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + I2C2 + I2C2 + 0x41001000 + + 0x0 + 0x2C + registers + + + I2C2 + I2C2 interrupt + 4 + + + + I2C2_CR1 + I2C2_CR1 + I2C2_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable +- 0: Peripheral disable +- 1: Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable +- 0: Transmit (TXIS) interrupt disabled +- 1: Transmit (TXIS) interrupt enabled + 1 + 1 + read-write + + + RXIE + RX Interrupt enable +- 0: Receive (RXNE) interrupt disabled +- 1: Receive (RXNE) interrupt enabled + 2 + 1 + read-write + + + ADDRIE + Address match Interrupt enable (slave only) +- 0: Address match (ADDR) interrupts disabled +- 1: Address match (ADDR) interrupts enabled + 3 + 1 + read-write + + + NACKIE + Not acknowledge received Interrupt enable +- 0: Not acknowledge (NACKF) received interrupts disabled +- 1: Not acknowledge (NACKF) received interrupts enabled + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt enable +- 0: Stop detection (STOPF) interrupt disabled +- 1: Stop detection (STOPF) interrupt enabled + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt enable +- 0: Transfer Complete interrupt disabled +- 1: Transfer Complete interrupt enabled + 6 + 1 + read-write + + + ERRIE + Error interrupts enable +- 0: Error detection interrupts disabled +- 1: Error detection interrupts enabled +Note: Any of these errors generate an interrupt: +Arbitration Loss (ARLO) +Bus Error detection (BERR) +Overrun/Underrun (OVR) +Timeout detection (TIMEOUT) +PEC error detection (PECERR) +Alert pin event detection (ALERT) + 7 + 1 + read-write + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter +will filter spikes with a length of up to DNF[3:0] * tI2CCLK +- 0000: Digital filter disabled +- 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK +- 1111: digital filter enabled and filtering capability up to15 tI2CCLK + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF +- 0: Analog noise filter enabled +- 1: Analog noise filter disabled + 12 + 1 + read-write + + + TXDMAEN + DMA transmission requests enable +- 0: DMA mode disabled for transmission +- 1: DMA mode enabled for transmission + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests enable +- 0: DMA mode disabled for reception +- 1: DMA mode enabled for reception + 15 + 1 + read-only + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. +- 0: Slave byte control disabled +- 1: Slave byte control enabled + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +- 0: Clock stretching enabled +- 1: Clock stretching disabled +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + GCEN + General call enable +- 0: General call disabled. Address 0b00000000 is NACKed. +- 1: General call enabled. Address 0b00000000 is ACKed. + 19 + 1 + read-write + + + SMBHEN + SMBus Host address enable +- 0: Host address disabled. Address 0b0001000x is NACKed. +- 1: Host address enabled. Address 0b0001000x is ACKed. + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address enable +- 0: Device default address disabled. Address 0b1100001x is NACKed. +- 1: Device default address enabled. Address 0b1100001x is ACKed. + 21 + 1 + read-write + + + ALERTEN + SMBus alert enable +Device mode (SMBHEN=0): +- 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. +- 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. +Host mode (SMBHEN=1): +- 0: SMBus Alert pin (SMBA) not supported. +- 1: SMBus Alert pin (SMBA) supported. + 22 + 1 + read-write + + + PECEN + PEC enable +- 0: PEC calculation disabled +- 1: PEC calculation enabled + 23 + 1 + read-write + + + + + I2C2_CR2 + I2C2_CR2 + I2C2_CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SADD + Slave address + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +- 0: Master requests a write transfer. +- 1: Master requests a read transfer. + 10 + 1 + read-write + + + ADD10 + Ten-bit addressing mode (master mode) +- 0: The master operates in 7-bit addressing mode, +- 1: The master operates in 10-bit addressing mode + 11 + 1 + read-write + + + HEAD10R + Ten bit (10-bit) address header only read direction (master receiver mode) +- 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. +- 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 12 + 1 + read-write + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. +- 0: No Start generation. +- 1: Restart/Start generation: + If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. + Otherwise setting this bit will generate a START condition once the bus is free. + 13 + 1 + read-write + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. +In Master Mode: +- 0: No Stop generation. +- 1: Stop generation after current byte transfer. + 14 + 1 + read-write + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP +condition or an Address matched is received, or when PE=0. +- 0: an ACK is sent after current received byte. +- 1: a NACK is sent after current received byte. + 15 + 1 + read-write + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is dont care in +slave mode with SBC=0. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. +- 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). +- 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). +TCR flag is set when NBYTES data are transferred, stretching SCL low. + 24 + 1 + read-write + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +- 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. +- 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are +transferred. + 25 + 1 + read-write + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a +STOP condition or an Address matched is received, also when PE=0. +- 0: No PEC transfer. +- 1: PEC transmission/reception is requested + 26 + 1 + read-write + + + + + I2C2_OAR1 + I2C2_OAR1 + I2C2_OAR1 register + 0x08 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + read-write + + + OA1MODE + Own Address 1 10-bit mode +- 0: Own address 1 is a 7-bit address. +- 1: Own address 1 is a 10-bit address. + 10 + 1 + read-write + + + OA1EN + Own Address 1 enable +- 0: Own address 1 disabled. The received slave address OA1 is NACKed. +- 1: Own address 1 enabled. The received slave address OA1 is ACKed. + 15 + 1 + read-write + + + + + I2C2_OAR2 + I2C2_OAR2 + I2C2_OAR2 register + 0x0C + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address +bits 7:1 of address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own Address 2 masks +- 000: No mask +- 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. +- 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. +- 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. +- 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. +- 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. +- 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. +- 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 8 + 3 + read-write + + + OA2EN + Own Address 2 enable +- 0: Own address 2 disabled. The received slave address OA2 is NACKed. +- 1: Own address 2 enabled. The received slave address OA2 is ACKed. + 15 + 1 + read-write + + + + + I2C2_TIMING + I2C2_TIMING + I2C2_TIMING register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +tSCLL = (SCLL+1) x tPRESC +Note: SCLL is also used to generate tBUF and tSU:STA timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +tSCLH = (SCLH+1) x tPRESC +Note: SCLH is also used to generate tSU:STO and tHD:STA timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in +transmission mode. +tSDADEL= SDADEL x tPRESC +Note: SDADEL is used to generate tHD:DAT timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in +transmission mode. +tSCLDEL = (SCLDEL+1) x tPRESC +Note: tSCLDEL is used to generate tSU:DAT timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data +setup and hold counters and for SCL high and low level +counters +tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + read-write + + + + + I2C2_TIMEOUT + I2C2_TIMEOUT + I2C2_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A +This field is used to configure: + The SCL low timeout condition tTIMEOUT when TIDLE=0 +tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK + The bus idle condition (both SCL and SDA high) when TIDLE=1 +tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +- 0: TIMEOUTA is used to detect SCL low timeout +- 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + TIMEOUTEN + Clock timeout enable +- 0: SCL timeout detection is disabled +- 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or +high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). + 15 + 1 + read-write + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected +In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected +tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable +- 0: Extended clock timeout detection is disabled +- 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more +than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 31 + 1 + read-write + + + + + I2C2_ISR + I2C2_ISR + I2C2_ISR register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). +Note: This bit is cleared by hardware when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: + either as a master, provided that the STOP condition is generated by the peripheral. + or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE=0. +This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR=1). +- 0: Write transfer, slave enters receiver mode. +- 1: Read transfer, slave enters transmitter mode. + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C2_ICR + I2C2_ICR + I2C2_ICR register + 0x1C + 0x20 + read-write + 0x00000000 + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears +the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the ACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + Stop detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration Lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C2_PECR + I2C2_PECR + I2C2_PECR register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE=0. + 0 + 8 + read-only + + + + + I2C2_RXDR + I2C2_RXDR + I2C2_RXDR register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + Eight bit (8-bit) receive data +Data byte received from the I2C bus. + 0 + 8 + read-only + + + + + I2C2_TXDR + I2C2_TXDR + I2C2_TXDR register + 0x28 + 0x20 + read-write + + + TXDATA + Eight bits (8-bit) transmit data +Data byte to be transmitted to the I2C bus. +Note: These bits can be written only when TXE=1. + 0 + 8 + read-write + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. + 0: AM or 24-hour format + 1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-only + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-only + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-only + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-only + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. + 16 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds dont care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes dont care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours dont care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is dont care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day dont care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescalers counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. +Note: CALM[0] is stucked at 0 when CALW16=1. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1 , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at 00 when CALW8=1. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. + 15 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescalers counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKP0R register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKP1R register + 0x54 + 0x20 + read-write + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. + 000: divider/4 + 001: divider/8 + 010: divider/16 + 011: divider/32 + 100: divider/64 + 101: divider/128 + 110: divider/256 + 111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic window = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + TIM1 + TIM1 + 0x40002000 + + 0x0 + 0x68 + registers + + + TIM1 + TIM1 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIFREMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + Capture/compare preloaded control. + 0 + 1 + read-write + + + CCUS + Capture/compare control update selection. + 2 + 1 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + OIS1 + Output idle state 1 (OC1 output). + 8 + 1 + read-write + + + OIS1N + Output idle state 1 (OC1N output). + 9 + 1 + read-write + + + OIS2 + Output idle state 2 (OC2 output). Refer to OIS1 bit. + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (OC2N output). Refer to OIS1N bit. + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (OC3 output). Refer to OIS1 bit. + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (OC3N output). Refer to OIS1N bit. + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (OC4 output). +Refer to OIS1 bit. + 14 + 1 + read-write + + + OIS5 + Output idle state 5 (OC5 output). Refer to OIS1 bit. + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (OC6 output). Refer to OIS1 bit. + 18 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS + TS[2:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +101: Filtered Timer Input 1 (TI1FP1) + +110: Filtered Timer Input 2 (TI2FP2) + +others: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection - bit 3 + +Refer to SMS description - bits2:0 + 16 + 1 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + BIE + Break interrupt enable. + 7 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag. + 5 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + BIF + Break interrupt flag. + 7 + 1 + read-write + + + B2IF + Break 2 interrupt flag. + 8 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + CC5IF + Compare 5 interrupt flag. + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag. + 17 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/compare control update generation. + 5 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + BG + Break generation. + 7 + 1 + write-only + + + B2G + Break 2 generation. + 8 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as + +TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. . + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NE + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable. Refer to CC1NE description. + 6 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable. Refer to CC1NE description. + 10 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable. Refer to CC1NE description. + 14 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable. Refer to CC1E description. + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity. Refer to CC1P description. + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable. Refer to CC1E description. + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity. Refer to CC1P description. + 21 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIFCPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 16 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + Deadtime generator setup. + 0 + 8 + read-write + + + LOCK + Lock configuration. + 8 + 2 + read-write + + + OSSI + Off-state selection for Idle mode. + 10 + 1 + read-write + + + OSSR + Off-state selection for Run mode. + 11 + 1 + read-write + + + BKE + Break enable. + 12 + 1 + read-write + + + BKP + Break polarity. + 13 + 1 + read-write + + + AOE + Automatic output enable. + 14 + 1 + read-write + + + MOE + Main output enable. + 15 + 1 + read-write + + + BKF + Break filter. + 16 + 4 + read-write + + + BK2F + Break 2 filter. + 20 + 4 + read-write + + + BK2E + Break 2 enable. + 24 + 1 + read-write + + + BK2P + Break 2 polarity. + 25 + 1 + read-write + + + + + CCMR3 + CCMR3 + CCMR3 register + 0x54 + 0x20 + read-write + 0x0 + 0xF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable. + 3 + 1 + read-write + + + OC5M_2_0 + Output compare 5 mode. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable. + 11 + 1 + read-write + + + OC6M_2_0 + Output compare 6 mode. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable. + 15 + 1 + read-write + + + OC5M_3 + Output compare 5 mode - bit 3. + 16 + 1 + read-write + + + OC6M_3 + Output compare 6 mode - bit 3. + 24 + 1 + read-write + + + + + CCMR3_in + CCMR3_in + CCMR3 + 0x54 + 0x20 + read-write + 0x0 + 0xF + + + IC5PSC + IC5PSC: Input capture 1 prescaler + 2 + 2 + read-write + + + IC5F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + 4 + 4 + read-write + + + IC6PSC + IC6PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC6F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCR5 + CCR5 + CCR5 register + 0x58 + 0x20 + read-write + 0x0 + 0xF + + + CCR5 + Capture/compare 5 value + 0 + 16 + read-write + + + GC5C1 + Group channel 5 and channel 1 distortion on channel 1 output: +0: No effect of OC5REF on OC1REFC5 +1: OC1REFC is the logical AND of OC1REFC and OC5REF +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload +feature is selected in TIMxCCMR1). +Note: It is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + GC5C2 + Group channel 5 and channel 2 distortion on channel 2 output: +0: No effect of OC5REF on OC2REFC +1: OC2REFC is the logical AND of OC2REFC and OC5REF +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload +feature is selected in TIMxCCMR1). +Note: It is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + GC5C3 + Group channel 5 and channel 3 distortion on channel 3 output: +0: No effect of OC5REF on OC3REFC +1: OC3REFC is the logical AND of OC3REFC and OC5REF +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload +feature is selected in TIMxCCMR2). +Note: It is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + + + CCR6 + CCR6 + CCR6 register + 0x5C + 0x20 + read-write + 0x0 + 0xF + + + CCR6 + Capture/compare 6 value + 0 + 16 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x0001 + 0xF + + + BKINE + BRK BKIN input enable + 0 + 1 + read-write + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + read-write + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + read-write + + + BKINP + BRK BKIN input polarity + 9 + 1 + read-write + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + read-write + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + read-write + + + + + AF2 + AF2 + AF2 register + 0x64 + 0x20 + read-write + 0x0001 + 0xF + + + BK2INE + BRK2 BKIN input enable. + 0 + 1 + read-write + + + BK2CMP1E + BRK2 COMP1 enable. + 1 + 1 + read-write + + + BK2CMP2E + BRK2 COMP2 enable. + 2 + 1 + read-write + + + BK2INP + BRK2 BKIN2 input polarity + 9 + 1 + read-write + + + BK2CMP1P + BRK2 COMP1 input polarity. + 10 + 1 + read-write + + + BK2CMP2P + BRK2 COMP2 input polarity. + 11 + 1 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x40 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x0201E041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. + 0: PA0 pin operated in standard mode. + 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. + 0: PA1 pin operated in standard mode. + 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. + 0: PB6 pin operated in standard mode. + 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. + 0: PB7 pin operated in standard mode. + 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA4_DT + PA4_DT:Interrupt Detection Type for port A I/Os. + 4 + 1 + read-write + + + PA5_DT + PA5_DT:Interrupt Detection Type for port A I/Os. + 5 + 1 + read-write + + + PA6_DT + PA6_DT:Interrupt Detection Type for port A I/Os. + 6 + 1 + read-write + + + PA7_DT + PA7_DT:Interrupt Detection Type for port A I/Os. + 7 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 11 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 23 + 1 + read-write + + + PB8_DT + PB8_DT:Interrupt Detection Type for port B I/Os. + 24 + 1 + read-write + + + PB9_DT + PB9_DT:Interrupt Detection Type for port B I/Os. + 25 + 1 + read-write + + + PB10_DT + PB10_DT:Interrupt Detection Type for port B I/Os. + 26 + 1 + read-write + + + PB11_DT + PB11_DT:Interrupt Detection Type for port B I/Os. + 27 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 3 + 1 + read-write + + + PA4_IBE + PA4_IBE: Interrupt edge selection for Port A I/Os. + 4 + 1 + read-write + + + PA5_IBE + PA5_IBE: Interrupt edge selection for Port A I/Os. + 5 + 1 + read-write + + + PA6_IBE + PA6_IBE: Interrupt edge selection for Port A I/Os. + 6 + 1 + read-write + + + PA7_IBE + PA7_IBE: Interrupt edge selection for Port A I/Os. + 7 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 11 + 1 + read-write + + + PA12_IBE + PA12_IBE: Interrupt edge selection for Port A I/Os. + 12 + 1 + read-write + + + PA13_IBE + PA13_IBE: Interrupt edge selection for Port A I/Os. + 13 + 1 + read-write + + + PA14_IBE + PA14_IBE: Interrupt edge selection for Port A I/Os. + 14 + 1 + read-write + + + PA15_IBE + PA15_IBE: Interrupt edge selection for Port A I/Os. + 15 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. + 23 + 1 + read-write + + + PB8_IBE + PB8_IBE: Interrupt edge selection for port B I/Os. + 24 + 1 + read-write + + + PB9_IBE + PB9_IBE: Interrupt edge selection for port B I/Os. + 25 + 1 + read-write + + + PB10_IBE + PB10_IBE: Interrupt edge selection for port B I/Os. + 26 + 1 + read-write + + + PB11_IBE + PB11_IBE: Interrupt edge selection for port B I/Os. + 27 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 3 + 1 + read-write + + + PA4_IEV + PA4_IEV : Interrupt polarity event for Port A I/Os. + 4 + 1 + read-write + + + PA5_IEV + PA5_IEV : Interrupt polarity event for Port A I/Os. + 5 + 1 + read-write + + + PA6_IEV + PA6_IEV : Interrupt polarity event for Port A I/Os. + 6 + 1 + read-write + + + PA7_IEV + PA7_IEV : Interrupt polarity event for Port A I/Os. + 7 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 11 + 1 + read-write + + + PA12_IEV + PA12_IEV : Interrupt polarity event for Port A I/Os. + 12 + 1 + read-write + + + PA13_IEV + PA13_IEV : Interrupt polarity event for Port A I/Os. + 13 + 1 + read-write + + + PA14_IEV + PA14_IEV : Interrupt polarity event for Port A I/Os. + 14 + 1 + read-write + + + PA15_IEV + PA15_IEV : Interrupt polarity event for Port A I/Os. + 15 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 23 + 1 + read-write + + + PB8_IEV + PB8_IEV : Interrupt polarity event for Port B I/Os. + 24 + 1 + read-write + + + PB9_IEV + PB9_IEV : Interrupt polarity event for Port B I/Os. + 25 + 1 + read-write + + + PB10_IEV + PB10_IEV : Interrupt polarity event for Port B I/Os. + 26 + 1 + read-write + + + PB11_IEV + PB11_IEV : Interrupt polarity event for Port B I/Os. + 27 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 3 + 1 + read-write + + + PA4_IE + PA4_IE: Interrupt enable for port A I/Os. + 4 + 1 + read-write + + + PA5_IE + PA5_IE: Interrupt enable for port A I/Os. + 5 + 1 + read-write + + + PA6_IE + PA6_IE: Interrupt enable for port A I/Os. + 6 + 1 + read-write + + + PA7_IE + PA7_IE: Interrupt enable for port A I/Os. + 7 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 11 + 1 + read-write + + + PA12_IE + PA12_IE: Interrupt enable for port A I/Os. + 12 + 1 + read-write + + + PA13_IE + PA13_IE: Interrupt enable for port A I/Os. + 13 + 1 + read-write + + + PA14_IE + PA14_IE: Interrupt enable for port A I/Os. + 14 + 1 + read-write + + + PA15_IE + PA15_IE: Interrupt enable for port A I/Os. + 15 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 23 + 1 + read-write + + + PB8_IE + PB8_IE: Interrupt enable for port B I/Os. + 24 + 1 + read-write + + + PB9_IE + PB9_IE: Interrupt enable for port B I/Os. + 25 + 1 + read-write + + + PB10_IE + PB10_IE: Interrupt enable for port B I/Os. + 26 + 1 + read-write + + + PB11_IE + PB11_IE: Interrupt enable for port B I/Os. + 27 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA4_ISC + PA4_ISC: Interrupt status (before mask) for port a I/Os.. + 4 + 1 + read-write + + + PA5_ISC + PA5_ISC: Interrupt status (before mask) for port a I/Os.. + 5 + 1 + read-write + + + PA6_ISC + PA6_ISC: Interrupt status (before mask) for port a I/Os.. + 6 + 1 + read-write + + + PA7_ISC + PA7_ISC: Interrupt status (before mask) for port a I/Os.. + 7 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PA12_ISC + PA12_ISC: Interrupt status (before mask) for port a I/Os. + 12 + 1 + read-write + + + PA13_ISC + PA13_ISC: Interrupt status (before mask) for port a I/Os. + 13 + 1 + read-write + + + PA14_ISC + PA14_ISC: Interrupt status (before mask) for port a I/Os. + 14 + 1 + read-write + + + PA15_ISC + PA15_ISC: Interrupt status (before mask) for port a I/Os. + 15 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB8_ISC + PB8_ISC: Interrupt status (before mask) for port B I/Os.. + 24 + 1 + read-write + + + PB9_ISC + PB9_ISC: Interrupt status (before mask) for port B I/Os.. + 25 + 1 + read-write + + + PB10_ISC + PB10_ISC: Interrupt status (before mask) for port B I/Os.. + 26 + 1 + read-write + + + PB11_ISC + PB11_ISC: Interrupt status (before mask) for port B I/Os.. + 27 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. + 0: PVD interrupt is disabled. + 1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. + 0: Interrupt on wakeup event seen by the PWRC is disabled. + 1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. + 0: no pending interrupt. + 1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. + 0: no pending interrupt. + 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + BLERXTX_DTR + BLERXTX_DTR + BLERXTX_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: + 0: detection on edge (default). + 1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: + 0: detection on edge (default). + 1: detection on level + 1 + 1 + read-write + + + + + BLERXTX_IBER + BLERXTX_IBER + BLERXTX_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: + 0: detection on single edge (default). + 1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: + 0: detection on single edge (default). + 1: detection on both edges + 1 + 1 + read-write + + + + + BLERXTX_IEVR + BLERXTX_IEVR + BLERXTX_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: + 0: detection on falling edge / low level (default). + 1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: + 0: detection on falling edge / low level (default). + 1: detection on rising edge / high level + 1 + 1 + read-write + + + + + BLERXTX_IER + BLERXTX_IER + BLERXTX_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: + 0: TX_SEQUENCE interrupt is disabled (default). + 1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: + 0: RX_SEQUENCE interrupt is disabled (default). + 1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + + + BLERXTX_ISCR + BLERXTX_ISCR + BLERXTX_ISCR register + 0x3C + 8 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): + 0: no activity on TX_SEQUENCE detected. + 1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): + 0: no activity on RX_SEQUENCE detected. + 1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + + + + + diff --git a/svd/STM32WBxx/STM32WB07.svd b/svd/STM32WBxx/STM32WB07.svd new file mode 100644 index 0000000..0b42a84 --- /dev/null +++ b/svd/STM32WBxx/STM32WB07.svd @@ -0,0 +1,32832 @@ + + + + STM32WB07 + 0.4 + STM32WB07 + + CM0+ + r0p0 + little + true + false + 2 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x41006000 + + 0x0 + 0x400 + registers + + + ADC + ADC interrupt + 12 + + + + VERSION_ID + VERSION_ID + VERSION_ID register + 0x00 + 0x20 + read-only + 0x00000020 + + + VERSION_ID + version of the embedded IP. + 0 + 8 + + + + + CONF + CONF + ADC configuration register + 0x04 + 0x20 + read-write + 0x00020002 + + + VBIAS_PRECH_FORCE + possibility to keep the VBIAS_PRECH enabled to deactivate the filter + 20 + 1 + + + ADC_CONT_1V2 + select the input sampling method + 19 + 1 + + + BIT_INVERT_DIFF + invert bit to bit the ADC data output when a + differential + + 18 + 1 + + + BIT_INVERT_SN + invert bit to bit the ADC data output when a single + + 17 + 1 + + + OVR_DF_CFG + decimation overrun configuration + 16 + 1 + + + OVR_DS_CFG + Down Sampler overrun configuration + 15 + 1 + + + DMA_DF_ENA + enable DMA mode for Decimation Filter data path + 14 + 1 + + + DMA_DS_ENA + enable DMA mode for Down Sampler data path + 13 + 1 + + + SAMPLE_RATE + conversion rate of ADC + 11 + 2 + + + OP_MODE + ADC mode selection (= data path selection) + 7 + 2 + + + SMPS_SYNCHRO_ENA + synchronize the ADC start conversion with a pulse + generated by the + + 6 + 1 + + + SEQ_LEN + number of conversions in a regular sequence + 2 + 4 + + + SEQUENCE + enable the sequence mode (active by default) + 1 + 1 + + + CONT + regular sequence runs continuously when ADC mode is enabled + 0 + 1 + + + + + CTRL + CTRL + ADC control register + 0x08 + 0x20 + read-write + 0x00000000 + + + ADC_LDO_ENA + enable the LDO associated to the ADC block + 5 + 1 + + + TEST_MODE + select the functional or the test mode of the ADC + 4 + 1 + + + DIG_AUD_MODE + enable the digital audio mode (the data path uses + the decimation filter) + 3 + 1 + + + STOP_OP_MOD + stop the on-going OP_MODE (ADC mode, Analog audio mode, Full + 2 + 1 + + + START_CON + generate a start pulse to initiate an ADC conversion + 1 + 1 + + + ADC_ON_OFF + ADC_ON_OFF: + +– 0: power off the ADC + +– 1: power on the ADC + 0 + 1 + + + + + OCM_CTRL + OCM_CTRL + Occasionnal mode control register + 0x0C + 0x20 + read-write + 0x00000000 + + + OCM_ENA + start occasional conversion in analog audio and full + modes + 1 + 1 + + + OCM_SRC + select the occasional conversion source + 0 + 1 + + + + + PGA_CONF + PGA_CONF + PGA configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + PGA_BIAS + set the microphone bias voltage + 4 + 3 + + + PGA_GAIN + from 6 to 30 dB + 0 + 4 + + + + + SWITCH + SWITCH + ADC switch control for Input Selection + 0x14 + 0x20 + read-write + 0x00000000 + + + SE_VIN_7 + input voltage for VINP[3] + 14 + 2 + + + SE_VIN_6 + input voltage for VINP[2] + 12 + 2 + + + SE_VIN_5 + input voltage for VINP[1] + 10 + 2 + + + SE_VIN_4 + input voltage for VINP[0] + 8 + 2 + + + SE_VIN_3 + input voltage for VINM[3] / VINP[3]-VINM[3] + 6 + 2 + + + SE_VIN_2 + input voltage for VINM[2] / VINP[2]-VINM[2] + 4 + 2 + + + SE_VIN_1 + input voltage for VINM[1] / VINP[1]-VINM[1] + 2 + 2 + + + SE_VIN_0 + input voltage for VINM[0] / VINP[0]-VINM[0] + 0 + 2 + + + + + DF_CONF + DF_CONF + Decimation filter configuration register + 0x18 + 0x20 + read-write + 0x00003015 + + + DF_HALF_D_EN + half dynamic enable. + 17 + 1 + + + DF_HPF_EN + high pass filter enable. + 16 + 1 + + + DF_MICROL_RN + left/right channel selection on digital microphone + 15 + 1 + + + PDM_RATE + select the PDM clock rate. + 11 + 4 + + + DF_O_S2U + select signed/unsigned format for data output + 10 + 1 + + + DF_I_U2S + select signed/unsigned format for input + 9 + 1 + + + DF_ITP1P2 + 1.2 fractional interpolator enable + 8 + 1 + + + DF_CIC_DHF + CIC filter decimator half factor + 7 + 1 + + + DF_CIC_DEC_FACTOR + 0 + 7 + + + + + DS_CONF + DS_CONF + Downsampler configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + DS_WIDTH + program the Down Sampler width of data output (DSDTATA) + 3 + 3 + + + DS_RATIO + program the Down Sampler ratio (N factor) + 0 + 3 + + + + + SEQ_1 + SEQ_1 + ADC regular sequence configuration register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + SEQ7 + channel number code for 8th conversion of the sequence. + 28 + 4 + + + SEQ6 + channel number code for 7th conversion of the sequence. + 24 + 4 + + + SEQ5 + channel number code for 6th conversion of the sequence. + 20 + 4 + + + SEQ4 + channel number code for 5th conversion of the sequence. + 16 + 4 + + + SEQ3 + channel number code for 4th conversion of the sequence. + 12 + 4 + + + SEQ2 + channel number code for 3rd conversion of the sequence. + 8 + 4 + + + SEQ1 + channel number code for second conversion of the sequence. + 4 + 4 + + + SEQ0 + channel number code for first conversion of the sequence + 0 + 4 + + + + + SEQ_2 + SEQ_2 + ADC regular sequence configuration register 2 + 0x24 + 0x20 + read-write + 0x00000000 + + + SEQ15 + channel number code for 16th conversion of the sequence. + 28 + 4 + + + SEQ14 + channel number code for 15th conversion of the sequence. + 24 + 4 + + + SEQ13 + channel number code for 14th conversion of the sequence. + 20 + 4 + + + SEQ12 + channel number code for 13th conversion of the sequence. + 16 + 4 + + + SEQ11 + channel number code for 12th conversion of the sequence. + 12 + 4 + + + SEQ10 + channel number code for 11th conversion of the sequence. + 8 + 4 + + + SEQ9 + channel number code for 10th conversion of the sequence. + 4 + 4 + + + SEQ8 + channel number code for 9th conversion of the sequence + 0 + 4 + + + + + COMP_1 + COMP_1 + ADC Gain and offset correction values register 1 + 0x28 + 0x20 + read-write + 0x00000555 + + + OFFSET1 + first calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN1 + first calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_2 + COMP_2 + ADC Gain and offset correction values register 2 + + 0x2C + 0x20 + read-write + 0x00000555 + + + OFFSET2 + second calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN2 + second calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_3 + COMP_3 + ADC Gain and offset correction values register 3 + + 0x30 + 0x20 + read-write + 0x00000555 + + + OFFSET3 + third calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN3 + third calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_4 + COMP_4 + ADC Gain and offset correction values register 4 + + 0x34 + 0x20 + read-write + 0x00000555 + + + OFFSET4 + fourth calibration point: signed offset compensation[6:0] + 12 + 7 + + + GAIN4 + fourth calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + + + + + COMP_SEL + COMP_SEL + ADC Gain and Offset selection values register + 0x38 + 0x20 + read-write + 0x00000000 + + + GAIN_OFFSET8 + gain / offset used in ADC differential mode with Vinput range = 3.6V + 16 + 2 + + + GAIN_OFFSET7 + gain / offset used in ADC single positive mode with Vinput range = 3.6V + 14 + 2 + + + GAIN_OFFSET6 + gain / offset used in ADC single negative mode with Vinput range = 3.6V + 12 + 2 + + + GAIN_OFFSET5 + gain / offset used in ADC differential mode with Vinput range = 2.4V + 10 + 2 + + + GAIN_OFFSET4 + gain / offset used in ADC single positive mode with Vinput range = 2.4V + 8 + 2 + + + GAIN_OFFSET3 + gain / offset used in ADC single negative mode with Vinput range = 2.4V + 6 + 2 + + + GAIN_OFFSET2 + gain / offset used in ADC differential mode with Vinput range = 1.2V + 4 + 2 + + + GAIN_OFFSET1 + gain / offset used in ADC single positive mode with Vinput range = 1.2V + 2 + 2 + + + GAIN_OFFSET0 + gain / offset used in ADC single negative mode with Vinput range = 1.2V + 0 + 2 + + + + + WD_TH + WD_TH + High/low limits for event monitoring a channel register + 0x3C + 0x20 + read-write + 0x0FFF0000 + + + WD_HT + analog watchdog high level threshold. + 16 + 12 + + + WD_LT + analog watchdog low level threshold. + 0 + 12 + + + + + WD_CONF + WD_CONF + Channel selection for event monitoring register + 0x40 + 0x20 + read-write + 0x00000000 + + + AWD_CHX + analog watchdog channel selection to define which input channel(s) need to be guarded by the watchdog. + 0 + 16 + + + + + DS_DATAOUT + DS_DATAOUT + Downsampler Data output register + 0x44 + 0x20 + read-only + 0x00000000 + + + DS_DATA + contain the converted data at the output of the Down Sampler + 0 + 16 + + + + + DF_DATAOUT + DF_DATAOUT + Decimation filter Data output register + 0x48 + 0x20 + read-only + 0x00000000 + + + DF_DATA + contain the converted data at the output of the + decimation filter. + + 0 + 16 + + + + + IRQ_STATUS + IRQ_STATUS + Interrupt Status register + 0x4C + 0x20 + read-write + 0x00000000 + + + DF_OVRFL_IRQ + set to indicate the decimation filter is saturated. + 7 + 1 + + + OVR_DF_IRQ + set to indicate a decimation filter overrun (a data is lost) + 6 + 1 + + + OVR_DS_IRQ + set to indicate a Down Sampler overrun (at least one data is lost) + 5 + 1 + + + AWD_IRQ + set when an analog watchdog event occurs + 4 + 1 + + + EOS_IRQ + set when a sequence of conversion is completed + 3 + 1 + + + EODF_IRQ + set when the decimation filter conversion is completed + 2 + 1 + + + EODS_IRQ + set when the Down Sampler conversion is completed. + 1 + 1 + + + EOC_IRQ + (Used in test mode only): set when the ADC conversion is completed. + 0 + 1 + + + + + IRQ_ENABLE + IRQ_ENABLE + Enable/disable Interrupts + 0x50 + 0x20 + read-write + 0x00000000 + + + DF_OVRFL_IRQ_ENA + decimation filter saturation interrupt enable + 7 + 1 + + + OVR_DF_IRQ_ENA + decimation filter overrun interrupt enable + 6 + 1 + + + OVR_DS_IRQ_ENA + Down Sampler overrun interrupt enable + 5 + 1 + + + AWD_IRQ_ENA + analog watchdog interrupt enable + 4 + 1 + + + EOS_IRQ_ENA + End of regular sequence interrupt enable + 3 + 1 + + + EODF_IRQ_ENA + End of conversion interrupt enable for the decimation filter output + 2 + 1 + + + EODS_IRQ_ENA + End of conversion interrupt enable for the Down Sampler output + 1 + 1 + + + EOC_IRQ_ENA + (Used in test mode only): End of ADC conversion interrupt enable + 0 + 1 + + + + + TIMER_CONF + TIMER_CONF + Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it + 0x54 + 0x20 + read-write + 0x00009628 + + + PRECH_DELAY_SEL + Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer + 16 + 1 + + + VBIAS_PRECH_DELAY + define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration + 8 + 8 + + + ADC_LDO_DELAY + define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion. + 0 + 8 + + + + + + + CRC + CRC address block description + CRC + 0x48200000 + + 0x0 + 0x400 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + DMA + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + + + GIF1 + GIF1: Channel 1 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 1 +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 1 +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 1 +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TEIF1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 1 +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 2 +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 2 +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 2 +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TEIF2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 2 +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 3 +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 3 +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 3 +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TEIF3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 3 +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 4 +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 4 +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 4 +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TEIF4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 4 +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 5 +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 5 +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 5 +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TEIF5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 5 +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 6 +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 6 +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 6 +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 6 +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 7 +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 7 +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 7 +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 7 +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 8 +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 8 +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 8 +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 8 +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + + + CGIF1 + CGIF1: Channel 1 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + + + DMAMUX + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + GPIOA + GPIOA address block description + GPIOA + 0x48000000 + + 0x0 + 0x400 + registers + + + GPIOA + GPIOA interrupt + 15 + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MODER0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + MODER15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O mode. + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output type. + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEEDR0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + OSPEEDR15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O output speed. +Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V<sub>DD</sub> range and external load. + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPDR0 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR1 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR2 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR3 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR4 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR5 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR6 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR7 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR8 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR9 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR10 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR11 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR12 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR13 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR14 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPDR15 + Port x configuration I/O pin y +These bits are written by software to configure the I/O pull-up or pull-down + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + IDR0 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 0 + 1 + read-only + + + IDR1 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 1 + 1 + read-only + + + IDR2 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 2 + 1 + read-only + + + IDR3 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 3 + 1 + read-only + + + IDR4 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 4 + 1 + read-only + + + IDR5 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 5 + 1 + read-only + + + IDR6 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 6 + 1 + read-only + + + IDR7 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 7 + 1 + read-only + + + IDR8 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 8 + 1 + read-only + + + IDR9 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 9 + 1 + read-only + + + IDR10 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 10 + 1 + read-only + + + IDR11 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 11 + 1 + read-only + + + IDR12 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 12 + 1 + read-only + + + IDR13 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 13 + 1 + read-only + + + IDR14 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 14 + 1 + read-only + + + IDR15 + Port x input data I/O pin y +These bits are read-only. They contain the input value of the corresponding I/O port. + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ODR0 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 0 + 1 + read-write + + + ODR1 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 1 + 1 + read-write + + + ODR2 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 2 + 1 + read-write + + + ODR3 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 3 + 1 + read-write + + + ODR4 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 4 + 1 + read-write + + + ODR5 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 5 + 1 + read-write + + + ODR6 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 6 + 1 + read-write + + + ODR7 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 7 + 1 + read-write + + + ODR8 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 8 + 1 + read-write + + + ODR9 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 9 + 1 + read-write + + + ODR10 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 10 + 1 + read-write + + + ODR11 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 11 + 1 + read-write + + + ODR12 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 12 + 1 + read-write + + + ODR13 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 13 + 1 + read-write + + + ODR14 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 14 + 1 + read-write + + + ODR15 + Port output data I/O pin y +These bits can be read and written by software. +Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A..F). + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS1 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS2 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS3 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS4 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS5 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS6 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS7 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS8 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS9 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS10 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS11 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS12 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS13 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS14 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BS15 + Port x set I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Sets the corresponding ODRx bit + 0x1 + + + + + BR0 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR1 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR2 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR3 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR4 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR5 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR6 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR7 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR8 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR9 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR10 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR11 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR12 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR13 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR14 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + BR15 + Port x reset I/O pin y +These bits are write-only. A read to these bits returns the value 0x0000. +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODRx bit + 0x0 + + + B_0x1 + Resets the corresponding ODRx bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y +These bits are read/write but can only be written when the LCKK bit is '0. + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +LOCK key write sequence: +WR LCKR[16] = '1' + LCKR[15:0] +WR LCKR[16] = '0' + LCKR[15:0] +WR LCKR[16] = '1' + LCKR[15:0] +RD LCKR +RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Note: Any error in the lock sequence aborts the lock. +Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns '1' until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFR0 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR1 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR2 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR3 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR4 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR5 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR6 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR7 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFR8 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR9 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR10 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR11 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR12 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR13 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR14 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFR15 + Alternate function selection for port x I/O pin y +These bits are written by software to configure alternate function I/Os. + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR1 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR2 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR3 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR4 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR5 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR6 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR7 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR8 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR9 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR10 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR11 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR12 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR13 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR14 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + BR15 + Port x reset IO pin y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODx bit + 0x0 + + + B_0x1 + Reset the corresponding ODx bit + 0x1 + + + + + + + + + I2C1 + I2C address block description + I2C + 0x41000000 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 interrupt + 3 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match Interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received Interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection Interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer Complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer Complete (TC) +Note: Transfer Complete Reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer Complete interrupt disabled + 0x0 + + + B_0x1 + Transfer Complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration Loss (ARLO) +Note: Bus Error detection (BERR) +Note: Overrun/Underrun (OVR) +Note: Timeout detection (TIMEOUT) +Note: PEC error detection (PECERR) +Note: Alert pin event detection (ALERT) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is also enabled, the digital filter is added to the analog filter. +Note: This filter can only be programmed when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wakeup from Stop mode enable +Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. +Note: WUPEN can be set only when DNF = '0000' + 18 + 1 + read-write + + + B_0x0 + Wakeup from Stop mode disable. + 0x0 + + + B_0x1 + Wakeup from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus host address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 20 + 1 + read-write + + + B_0x0 + Host address disabled. Address 0b0001000x is NACKed. + 0x0 + + + B_0x1 + Host address enabled. Address 0b0001000x is ACKed. + 0x1 + + + + + SMBDEN + SMBus device default address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. Address 0b1100001x is NACKed. + 0x0 + + + B_0x1 + Device default address enabled. Address 0b1100001x is ACKed. + 0x1 + + + + + ALERTEN + SMBus alert enable +Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). + 0x1 + + + + + PECEN + PEC enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] should be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer. + 0x0 + + + B_0x1 + Master requests a read transfer. + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode, + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit generates a START condition once the bus is free. +Note: Writing '0' to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation. + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In Master mode: +Note: Writing '0' to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation. + 0x0 + + + B_0x1 + Stop generation after current byte transfer. + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. +Note: Changing these bits when the START bit is set is not allowed. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit has no effect when RELOAD is set. +Note: This bit has no effect is slave mode when SBC=0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 26 + 1 + read-write + + + B_0x0 + No PEC transfer. + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN=0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN=0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN=0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don't care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don't care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don't care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don't care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don't care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don't care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL+1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH+1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL+1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale i2c_ker_ck in order to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings on page2521) and for SCL high and low level counters (refer to I2C master initialization on page2536). +t<sub>PRESC </sub>= (PRESC+1) x t<sub>I2CCLK</sub> + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE=0 +t<sub>TIMEOUT</sub>= (TIMEOUTA+1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE=1 +t<sub>IDLE</sub>= (TIMEOUTA+1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE=0) or high for more than t<sub>IDLE </sub>(TIDLE=1), a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT</sub>= (TIMEOUTB+1) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or t<sub>LOW</sub> detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xA0 + registers + + + RCC + Reset and Clock Controller + 1 + + + BATTERY + PVD + 2 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator OFF + 0x0 + + + B_0x1 + LSI RC oscillator ON + 0x1 + + + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn + 3 + 1 + read-only + + + B_0x0 + LSI RC oscillator not ready + 0x0 + + + B_0x1 + LSI RC oscillator ready + 0x1 + + + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn + 4 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. + 5 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn + 6 + 1 + read-write + + + B_0x0 + LSE oscillator bypass OFF + 0x0 + + + B_0x1 + LSE oscillator bypass ON + 0x1 + + + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). + 10 + 1 + read-only + + + B_0x0 + internal RC 64 MHz oscillator not ready + 0x0 + + + B_0x1 + internal RC 64 MHz oscillator ready + 0x1 + + + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF2G4 enable. +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + HSE PLL Buffer OFF + 0x0 + + + B_0x1 + HSE PLL Buffer ON + 0x1 + + + + + HSIPLLON + Internal High Speed Clock PLL enable + 13 + 1 + read-write + + + B_0x0 + PLL is OFF + 0x0 + + + B_0x1 + PLL is ON + 0x1 + + + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. + 14 + 1 + read-only + + + B_0x0 + PLL is unlocked + 0x0 + + + B_0x1 + PLL is locked + 0x1 + + + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + SMPSINV + bit to control inversion of the SMPS clock + 0 + 1 + read-write + + + B_0x0 + SMPS clock not inverted (default value) + 0x0 + + + B_0x1 + SMPS clock inverted (for debug) + 0x1 + + + + + HSESEL + Clock source selection request: + 1 + 1 + read-write + + + B_0x0 + HSI clock source is requested (default) + 0x0 + + + B_0x1 + HSE clock source is requested + 0x1 + + + + + STOPHSI + Stop HSI clock source request + 2 + 1 + read-write + + + B_0x0 + HSI is enabled (default) + 0x0 + + + B_0x1 + disable HSI is requested + 0x1 + + + + + CLKSYSDIV + CLKSYSDIV: system clock divided factor from HSI_64M. + 5 + 3 + read-write + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz + 12 + 1 + read-write + + + B_0x0 + div 2 when ANADIV=2 or 4 (default ) + 0x0 + + + B_0x1 + div 4 when ANADIV=1 or 2 + 0x1 + + + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn + 15 + 2 + read-write + + + B_0x0 + LSILMPU oscillator clock (default) + 0x0 + + + B_0x1 + LSE oscillator clock used as slow clock + 0x1 + + + B_0x2 + LSI oscillator clock used as slow clock + 0x2 + + + B_0x3 + HSI_64M divided by 2048 used as slow clock + 0x3 + + + + + IOBOOSTEN + IO BOOSTER enable +Set and reset by software. + 17 + 1 + read-write + + + B_0x0 + does not enable IO BOOSTER + 0x0 + + + B_0x1 + enable IO BOOSTER + 0x1 + + + + + SPI3I2SCLKSEL + Selection of I2S1 clock: +1x:64MHz peripheral clock + 22 + 1 + read-write + + + B_0x0 + 16MHz peripheral clock (default) + 0x0 + + + B_0x1 + 32MHz peripheral clock + 0x1 + + + + + SPI2I2SCLKSEL + Selection of I2S clock: +1x:64MHz peripheral clock + 23 + 1 + read-write + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn + 24 + 2 + read-write + + + B_0x0 + LCO output disabled, no clock on LCO + 0x0 + + + B_0x1 + internal 32 KHz (LSI_LPMU) oscillator clock selected + 0x1 + + + B_0x2 + internal 32 KHz (LSI) oscillator clock selected + 0x2 + + + B_0x3 + external 32 KHz (LSE) oscillator clock selected + 0x3 + + + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. + 26 + 3 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + system clock selected + 0x1 + + + B_0x2 + na + 0x2 + + + B_0x3 + internal RC 64 MHz (HSI) oscillator clock selected + 0x3 + + + B_0x4 + external oscillator (HSE) clock selected + 0x4 + + + B_0x5 + internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected + 0x5 + + + B_0x6 + SMPS clock selected + 0x6 + + + B_0x7 + AUX ADC ANA clock selected + 0x7 + + + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +Others: not used + 29 + 3 + read-write + + + B_0x0 + CCO clock is divided by 1 + 0x0 + + + B_0x1 + CCO clock is divided by 2 + 0x1 + + + B_0x2 + CCO clock is divided by 4 + 0x2 + + + B_0x3 + CCO clock is divided by 8 + 0x3 + + + B_0x4 + CCO clock is divided by 16 + 0x4 + + + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. + 5 + 1 + read-write + + + B_0x0 + HSI PLL ready interrupt disabled + 0x0 + + + B_0x1 + HSI PLL ready interrupt enabled + 0x1 + + + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. + 6 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. + 7 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. + 0 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the internal RC 32 KHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0x1 + + + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. + 1 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. + 3 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI oscillator + 0x1 + + + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. + 4 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. + 5 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x1 + + + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done + 0 + 1 + read-write + + + B_0x0 + To cancel an ongiong request - still possible until IRQ assertion + 0x0 + + + B_0x1 + To update the system clock frequency + 0x1 + + + + + CLKSYSDIV_REQ + system clock dividing factor from HSI_64M requested +Note: behavior depends on BLEEN in APB2ENR register + 1 + 3 + read-write + + + B_0x0 + div 1 (sys clock 64M) + 0x0 + + + B_0x1 + div 2 (sys clock 32M) + 0x1 + + + B_0x2 + div 4 (sys clock 16M) + 0x2 + + + B_0x3 + div 8 (sys clock 8M) + 0x3 + + + B_0x4 + div 16 (sys clock 4M) + 0x4 + + + B_0x5 + div 32 (sys clock 2M) + 0x5 + + + B_0x6 + div 64 (sys clock 1M) + 0x6 + + + + + STATUS + Status of clock switch sequence + 4 + 2 + read-only + + + B_0x0 + IDLE no switch requested + 0x0 + + + B_0x1 + ONGOING clock frequency switch is ongoing + 0x1 + + + B_0x2 + DONE clock frequency switch done + 0x2 + + + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. + 6 + 1 + read-write + + + B_0x0 + End of sequence interrupt disabled + 0x0 + + + B_0x1 + End of sequence interrupt enabled + 0x1 + + + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended + 7 + 1 + read-write + + + B_0x0 + No end of sequence event occured + 0x0 + + + B_0x1 + End of sequece event occured + 0x1 + + + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset DMA + 0x0 + + + B_0x1 + resets DMA + 0x1 + + + + + GPIOARST + GPIOA reset +Set and reset by software. + 2 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + GPIOBRST + GPIOB reset +Set and reset by software. + 3 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + CRCRST + CRC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset CRC + 0x0 + + + B_0x1 + resets CRC + 0x1 + + + + + PKARST + PKA reset +Set and reset by software. + 16 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RNGRST + RNG reset +Set and reset by software. + 18 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1: Advanced Timer reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + SYSCFGRST + SYSTEM CONFIG reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RTCRST + RTC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + WDGRST + WATCHDOG reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + SPI1RST + SPI1 reset + 0 + 1 + read-write + + + ADCRST + ADC reset. + 4 + 1 + read-write + + + LPUARTRST + LPUART reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + USARTRST + USART reset +Set and reset by software. + 10 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + SPI2RST + SPI2 reset. + 12 + 1 + read-write + + + SPI3RST + SPI3 reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + I2C1RST + I2C1 reset +Set and reset by software. + 21 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + I2C2RST + 2C2 reset. + 23 + 1 + read-write + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + MRBLERST + MR_BLE (Bluetooth radio) reset. + 0 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + PKAEN + PKA clock enable +Set and enable by software. + 16 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RNGEN + RNG clock enable +Set and enable by software. + 18 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 enable + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + SYSCFGEN + SYSTEM CONFIG enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + WDGEN + Watchdog clock enable. +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + SPI1EN + SPI1 enable. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + ADCDIGEN + ADC clock enable for digital part of the ADC block. + 4 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + ADCANAEN + ADC clock enable for the analog part of the ADC block. + 5 + 1 + read-write + + + LPUARTEN + LPUART clock enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + USART1EN + USART clock enable +Set and enable by software. + 10 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + SPI2EN + SPI2 enable + 12 + 1 + read-write + + + SPI3EN + SPI3 clock enable +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and enable by software. + 21 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + I2C2EN + I2C2 enable. + 23 + 1 + read-write + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRBLEEN + MR_BLE enable + 0 + 1 + read-write + + + B_0x0 + MR_BLE IP is clock gated + 0x0 + + + B_0x1 + MR_BLE IP is clocked + 0x1 + + + + + CLKBLEDIV + MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1 + 2 + 1 + read-write + + + B_0x0 + 32MHz + 0x0 + + + B_0x1 + 16MHz + 0x1 + + + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags + 23 + 1 + write-only + + + B_0x0 + Nothing done + 0x0 + + + B_0x1 + Reset the value of the reset flags + 0x1 + + + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. + 26 + 1 + read-only + + + B_0x0 + No reset from pad occurred + 0x0 + + + B_0x1 + Reset from pad occurred + 0x1 + + + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. + 27 + 1 + read-only + + + B_0x0 + No POWER reset occurred + 0x0 + + + B_0x1 + POWER reset occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. + 29 + 1 + read-only + + + B_0x0 + No watchdog reset occurred + 0x0 + + + B_0x1 + Watchdog reset occurred + 0x1 + + + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. + 30 + 1 + read-only + + + B_0x0 + No lockup reset occurred + 0x0 + + + B_0x1 + lockup reset occurred + 0x1 + + + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x000000030 + + + SATRG + Sense Amplifier threshold +Set by software. + 3 + 1 + read-write + + + B_0x0 + the bias current is confronted to a reference current with a ratio of half. + 0x0 + + + B_0x1 + the bias current is confronted to a reference current with a ratio of 3/4 + 0x1 + + + + + GMC + High Speed External XO current control +Set by software. + 4 + 3 + read-write + + + B_0x0 + max 0.0 001: max 0.57 mA/V + 0x0 + + + B_0x2 + max 0.78 mA/V + 0x2 + + + B_0x3 + max 1.13 mA/V (Default) + 0x3 + + + B_0x4 + max 0.61 mA/V + 0x4 + + + B_0x5 + max 1.65 mA/V + 0x5 + + + B_0x6 + max 2.12 mA/V + 0x6 + + + B_0x7 + max 2.84 mA/V + 0x7 + + + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + + + + + SPI3 + SPI address block description + SPI + 0x41007000 + + 0x0 + 0x400 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPIx_CR1 + SPIx_CR1 + SPI control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. +Note: These bits are not used in I<sup>2</sup>S mode. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. +Note: This bit is not used in I<sup>2</sup>S mode. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +Note: This bit is not used in I<sup>2</sup>S mode. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. +Note: This bit is not used in I<sup>2</sup>S mode. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. +Note: This bit is not used in I<sup>2</sup>S mode. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPIx_CR2 + SPIx_CR2 + SPI control register 2 + 0x04 + 16 + read-write + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1 , or FRF = 1 . +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I<sup>2</sup>S mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) +Note: These bits are not used in I<sup>2</sup>S mode. + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPIx_SR + SPIx_SR + SPI status register + 0x08 + 16 + read-write + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CHSIDE + Channel side +Note: This bit is not used in SPI mode. It has no significance in PCM mode. + 2 + 1 + read-only + + + B_0x0 + Channel Left has to be transmitted or has been received + 0x0 + + + B_0x1 + Channel Right has to be transmitted or has been received + 0x1 + + + + + UDR + Underrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. +Note: This bit is not used in SPI mode. + 3 + 1 + read-only + + + B_0x0 + No underrun occurred + 0x0 + + + B_0x1 + Underrun occurred + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPIx_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPIx_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. +Note: This bit is not used in I<sup>2</sup>S mode. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. + 7 + 1 + read-only + + + B_0x0 + SPI (or I2S) not busy + 0x0 + + + B_0x1 + SPI (or I2S) is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I<sup>2</sup>S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPIx_DR + SPIx_DR + SPI data register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPIx_CRCPR + SPIx_CRCPR + SPI CRC polynomial register + 0x10 + 16 + read-write + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPIx_RXCRCR + SPIx_RXCRCR + SPI Rx CRC register + 0x14 + 16 + read-only + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_TXCRCR + SPIx_TXCRCR + SPI Tx CRC register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_I2SCFGR + SPIx_I2SCFGR + SPIx_I2S configuration register + 0x1C + 16 + read-write + 0x0000 + 0xFFFF + + + CHLEN + Channel length (number of bits per audio channel) +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. + 0 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + DATLEN + Data length to be transferred +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 1 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CKPOL + Inactive state clock polarity +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. +Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. + 3 + 1 + read-write + + + B_0x0 + I2S clock inactive state is low level + 0x0 + + + B_0x1 + I2S clock inactive state is high level + 0x1 + + + + + I2SSTD + I2S standard selection +For more details on I<sup>2</sup>S standards, refer to Section 27.7.2 on page 805 +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 4 + 2 + read-write + + + B_0x0 + I<sup>2</sup>S Philips standard + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). +Note: It is not used in SPI mode. + 7 + 1 + read-write + + + B_0x0 + Short frame synchronization + 0x0 + + + B_0x1 + Long frame synchronization + 0x1 + + + + + I2SCFG + I2S configuration mode +Note: These bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 8 + 2 + read-write + + + B_0x0 + Slave - transmit + 0x0 + + + B_0x1 + Slave - receive + 0x1 + + + B_0x2 + Master - transmit + 0x2 + + + B_0x3 + Master - receive + 0x3 + + + + + I2SE + I2S enable +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + B_0x0 + I2S peripheral is disabled + 0x0 + + + B_0x1 + I2S peripheral is enabled + 0x1 + + + + + I2SMOD + I2S mode selection +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S mode is selected + 0x1 + + + + + ASTRTEN + Asynchronous start enable. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. +Note: The appropriate transition is a falling edge on WS signal when I<sup>2</sup>S Philips Standard is used, or a rising edge for other standards. +Note: The appropriate level is a low level on WS signal when I<sup>2</sup>S Philips Standard is used, or a high level for other standards. +Note: Please refer to Section 27.7.3: Start-up description for additional information. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. + 0x0 + + + B_0x1 + The Asynchronous start is enabled. + 0x1 + + + + + + + SPIx_I2SPR + SPIx_I2SPR + SPIx_I2S prescaler register + 0x20 + 16 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. +Refer to Section 27.7.3 on page 812. +Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. +Note: They are not used in SPI mode. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +Refer to Section 27.7.3 on page 812. +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 8 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + Master clock output enable +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 9 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + USART + USART address block description + USART + 0x41004000 + + 0x0 + 0x400 + registers + + + USART + USART interrupt + 8 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit +M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit +M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable +This bit is set and cleared by software. + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable +This bit is set and cleared by software. + 31 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when RXFF=1 in the USART_ISR register + 0x1 + + + + + + + USART_CR1_ALTERNATE1 + USART_CR1_ALTERNATE1 + USART control register 1 + USART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. +Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. +Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. +Note: In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value. + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode +When this bit is cleared, the USART cannot wake up the MCU from low-power mode. +When this bit is set, the USART can wake up the MCU from low-power mode. +This bit is set and cleared by software. +Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable +This bit enables the receiver. It is set and cleared by software. + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. +Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts. + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable +This bit is set and cleared by software. + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE=1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty +This bit is set and cleared by software. + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable +This bit is set and cleared by software. + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty +This bit is set and cleared by software. + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable +This bit is set and cleared by software. + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. +This bitfield can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). +This bitfield can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length +This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + Mute mode enable +This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between Mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable +This bit is set and cleared by software. + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode +This bit can only be written when the USART is disabled (UE=0). +Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared. + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587. + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of Block interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length +This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. +M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit +M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit +M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0). +Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported. + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). +Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes. + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +This bit can only be written when the USART is disabled (UE=0) +Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +This bit can only be written when the USART is disabled (UE=0). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. +The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase +This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure589 and Figure590) +This bit can only be written when the USART is disabled (UE=0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +This bit can only be written when the USART is disabled (UE=0). +Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable +This bit enables the user to enable the CK pin. +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. +In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +Note: UE = 1 + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits +These bits are used for programming the stop bits. +This bitfield can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0.5 stop bit. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1.5 stop bits + 0x3 + + + + + LINEN + LIN mode enable +This bit is set and cleared by software. +The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. + 0x1 + + + + + RXINV + RX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the RX line. +This bitfield can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted (V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + TXINV + TX pin active level inversion +This bit is set and cleared by software. +This enables the use of an external inverter on the TX line. +This bitfield can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (V<sub>DD</sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted (V<sub>DD</sub> =0/mark, Gnd=1/idle). + 0x1 + + + + + DATAINV + Binary data inversion +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. + 0x1 + + + + + MSBFIRST + Most significant bit first +This bit is set and cleared by software. +This bitfield can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable +This bit is set and cleared by software. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode +These bits are set and cleared by software. +This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). +Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable +This bit is set and cleared by software. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node +These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: +In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. +In low-power mode: they are used for wake up from low-power mode on character match. +When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. +In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. +These bits can only be written when the reception is disabled (RE=0) or when the USART is disabled (UE=0). + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1 or UDR = 1 in the USART_ISR register). + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable +This bit is set and cleared by software. +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +This bit can only be written when the USART is disabled (UE=0). +Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection +Selection of Single-wire Half-duplex mode +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + B_0x0 + Half duplex mode is not selected + 0x0 + + + B_0x1 + Half duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable +This bit is used for enabling Smartcard mode. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 5 + 1 + read-write + + + B_0x0 + Smartcard Mode disabled + 0x0 + + + B_0x1 + Smartcard Mode enabled + 0x1 + + + + + DMAR + DMA enable receiver +This bit is set/reset by software + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter +This bit is set/reset by software + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable +This bit can only be written when the USART is disabled (UE=0). +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. + 0x1 + + + + + CTSE + CTS enable +This bit can only be written when the USART is disabled (UE=0) +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. + 0x1 + + + + + CTSIE + CTS interrupt enable +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable +This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable +This bit is used to disable the receive overrun detection. +the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). +Note: This control bit enables checking the communication flow w/o reading the data + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. If new data is received while the RXNE flag is still set + 0x1 + + + + + DDRE + DMA Disable on Reception Error +This bit can only be written when the USART is disabled (UE=0). +Note: The reception errors are: parity error, framing error or noise error. + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode). + 0x0 + + + B_0x1 + DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag. + 0x1 + + + + + DEM + Driver enable mode +This bit enables the user to activate the external transceiver control, through the DE signal. +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section53.4: USART implementation on page2587. + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. The DE signal is output on the RTS pin. + 0x1 + + + + + DEP + Driver enable polarity selection +This bit can only be written when the USART is disabled (UE=0). +Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count +This bitfield specifies the number of retries for transmission and reception in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). +This bitfield must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. +0x1 to 0x7: number of automatic retransmission attempts (before signaling error) +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmit mode. + 0x0 + + + + + WUS + Wakeup from low-power mode interrupt flag selection +This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). +This bitfield can only be written when the USART is disabled (UE=0). +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 2 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + B_0x1 + Reserved. + 0x1 + + + B_0x2 + WUF active on start bit detection + 0x2 + + + B_0x3 + WUF active on RXNE/RXFNE. + 0x3 + + + + + WUFIE + Wakeup from low-power mode interrupt enable +This bit is set and cleared by software. +Note: WUFIE must be set before entering in low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable +This bit is set and cleared by software. + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration +Remaining combinations: Reserved + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable +This bit is set and cleared by software. + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration +Remaining combinations: Reserved + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate +BRR[15:4] +BRR[15:4] = USARTDIV[15:4] +BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared. + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value +In IrDA low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power baud rate +PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): +In Smartcard mode: +PSC[4:0]=Prescaler value +PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: +... +... +This bitfield can only be written when the USART is disabled (UE=0). +Note: Bits [7:5] must be kept cleared if Smartcard mode is used. +Note: This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA modes are not supported. Refer to Section 53.4: USART implementation on page 2587. + 0 + 8 + read-write + + + B_0x0 + Reserved - do not program this value + 0x0 + + + B_0x1 + Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode) + 0x1 + + + B_0x2 + Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode) + 0x2 + + + B_0x3 + Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode) + 0x3 + + + B_0x1F + Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode) + 0x1F + + + B_0x20 + Divides the source clock by 32 (IrDA mode) + 0x20 + + + B_0xFF + Divides the source clock by 255 (IrDA mode) + 0xFF + + + + + GT + Guard time value +This bitfield is used to program the Guard time value in terms of number of baud clock periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. +This bitfield can only be written when the USART is disabled (UE=0). +Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value +This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. +Note: This value must only be programmed once per received character. + 0 + 24 + read-write + + + BLEN + Block Length +This bitfield gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0: 0 information characters + LEC +BLEN = 1: 0 information characters + CRC +BLEN = 255: 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO mode is enabled). +This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. +Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request +Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 0 + 1 + write-only + + + SBKRQ + Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. +Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. + 1 + 1 + write-only + + + MMRQ + Mute mode request +Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This enables to discard the received data without reading them, and avoid an overrun condition. + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request +When FIFO mode is disabled, writing '1' to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. +Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register. + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + read-only + 0x008000C0 + 0xF0FFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +Note: This error is associated with the character in the USART_RDR. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE=1 in the USART_CR3 register. +Note: This error is associated with the character in the USART_RDR. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section53.5.8: Tolerance of the USART receiver to clock deviation on page2604). +Note: This error is associated with the character in the USART_RDR. + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty +RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. +RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXFNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. +It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set. + 6 + 1 + read-only + + + B_0x0 + Transmission is not complete + 0x0 + + + B_0x1 + Transmission is complete + 0x1 + + + + + TXFNF + TXFIFO not full +TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. +An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). +Note: This bit is used during single buffer transmission. + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR1 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character Match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + Break character transmitted + 0x0 + + + B_0x1 + Break character requested by setting SBKRQ bit in USART_RQR register + 0x1 + + + + + RWU + Receiver wakeup from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wakeup from low-power mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 22 + 1 + read-only + + + TXFE + TXFIFO empty +This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO full +This bit is set by hardware when the number of received data corresponds to RXFIFOsize+1 (RXFIFO full + 1 data in the USART_RDR register. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 53.4: USART implementation on page 2587. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag +This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. +Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data. + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE1 + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xFFFFFFFF + + + PE + Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE=1 in the USART_CR3 register. + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. +Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. +Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section53.5.8: Tolerance of the USART receiver to clock deviation on page2604). + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USART_RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. +An interrupt is generated if RXNEIE=1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the USART_CR3 register. +Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. +Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register. + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. +Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). +Note: If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty +RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. +An interrupt is generated if RXNEIE=1 in the USART_CR1 register. + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete +This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. +It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately. + 6 + 1 + read-only + + + B_0x0 + Transmission is not complete + 0x0 + + + B_0x1 + Transmission is complete + 0x1 + + + + + TXE + Transmit data register empty +TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of transmission failure). +An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register not full + 0x1 + + + + + LBDF + LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag +This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. +Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value. + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. +Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value. + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR1 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 12 + 1 + read-only + + + B_0x0 + End of Block not reached + 0x0 + + + B_0x1 + End of Block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. +Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 14 + 1 + read-only + + + ABRF + Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. +Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value. + 15 + 1 + read-only + + + BUSY + Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception on going + 0x1 + + + + + CMF + Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character Match detected + 0x1 + + + + + SBKF + Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. + 18 + 1 + read-only + + + B_0x0 + Break character transmitted + 0x0 + + + B_0x1 + Break character requested by setting SBKRQ bit in USART_RQR register + 0x1 + + + + + RWU + Receiver wakeup from Mute mode +This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in Mute mode + 0x1 + + + + + WUF + Wakeup from low-power mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. +An interrupt is generated if WUFIE=1 in the USART_CR3 register. +Note: When UESM is cleared, WUF flag is also cleared. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. +It can be used to verify that the USART is ready for reception before entering low-power mode. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section53.4: USART implementation on page2587. + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag +This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. +This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to Section 53.4: USART implementation on page 2587. + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card) + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register. + 1 + 1 + write-only + + + NECF + Noise detected clear flag +Writing 1 to this bit clears the NE flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register. + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register. + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. +Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 8 + 1 + write-only + + + CTSCF + CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. +Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. +Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 11 + 1 + write-only + + + EOBCF + End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register. +Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register. +Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587 + 13 + 1 + write-only + + + CMCF + Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register. + 17 + 1 + write-only + + + WUCF + Wakeup from low-power mode clear flag +Writing 1 to this bit clears the WUF flag in the USART_ISR register. +Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section53.4: USART implementation on page2587. + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure583). +When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value +Contains the data character to be transmitted. +The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure583). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler +The USART input clock can be divided by a prescaler factor: +Remaining combinations: Reserved +Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256. + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + BLUE + BLUE + 0x60000000 + + 0x0 + 0x1000 + registers + + + BLE_TX_RX_IRQn + BLE Tx/Rx interrupt + 18 + + + + INTERRUPT1REG + INTERRUPT1REG + INTERRUPT1REG register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error. + 4 + 1 + read-write + + + RXOVERFLOWERROR + Receive Overflow error. + 5 + 1 + read-write + + + SEQDONE + Sequencer end of task. + 7 + 1 + read-write + + + TXERROR_0 + Transmission error 0: transmit block missing data error. + 8 + 1 + read-write + + + TXERROR_1 + Transmission error 1: a TX skip happened during an on-going transmission. + 9 + 1 + read-write + + + TXERROR_2 + Transmission error 2: channel index is greater than 39. + 10 + 1 + read-write + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state. + 11 + 1 + read-write + + + TXERROR_4 + Transmission error 4: a CTE issue occurred. + 12 + 1 + read-write + + + ENCERROR + Encryption error on reception. + 13 + 1 + read-write + + + ALLTABLEREADYERROR + All RAM Table not ready on time. + 14 + 1 + read-write + + + TXDATAREADYERROR + Transmit data pack not ready error + + 15 + 1 + read-write + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-write + + + RCVLENGTHERROR + Receive length error. + 18 + 1 + read-write + + + SEMATIMEOUTERROR + Semaphore timeout error + + 19 + 1 + read-write + + + TXRXSKIP + Transmission/Reception skip. + 21 + 1 + read-write + + + ACTIVE2ERROR + Active2 Radio state error. + 22 + 1 + read-write + + + CONFIGERROR + Data pointer configuration error. + 23 + 1 + read-write + + + TXOK + Previous transmitted packet received OK by the peer device. + 24 + 1 + read-write + + + DONE + Receive/Transmit done. + 25 + 1 + read-write + + + RCVTIMEOUT + Receive timeout (no preamble found). + 26 + 1 + read-write + + + RCVNOMD + Received low MD bit. + 27 + 1 + read-write + + + RCVCMD + Received command + + 28 + 1 + read-write + + + TIMECAPTURETRIG + A time has been captured in TIMERCAPTUREREG. + 29 + 1 + read-write + + + RCVCRCERR + Receive data fail + + 30 + 1 + read-write + + + RCVOK + Receive data OK. + 31 + 1 + read-write + + + + + INTERRUPT2REG + INTERRUPT2REG + INTERRUPT2REG register + 0x8 + 0x20 + read-write + 0x00000000 + + + AESMANENCINT + AES manual encryption. + 0 + 1 + read-write + + + AESLEPRIVINT + AES LE privacy engine. + 1 + 1 + read-write + + + + + TIMEOUTDESTREG + TIMEOUTDESTREG + TIMEOUTDESTREG register + 0xc + 0x20 + read-write + 0x00000000 + + + DESTINATION + Timeout timer Destination + + 0 + 2 + read-write + + + + + TIMEOUTREG + TIMEOUTREG + TIMEOUTREG register + 0x10 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timer1 or Timer2 Timeout value (depending on Destination register) + + 0 + 32 + read-write + + + + + TIMERCAPTUREREG + TIMERCAPTUREREG + TIMERCAPTUREREG register + 0x14 + 0x20 + read-only + 0x00000000 + + + TIMERCAPTURE + Interpolated absolute time capture register + + 0 + 32 + read-only + + + + + CMDREG + CMDREG + CMDREG register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXRXSKIP + Transmission/Reception skip command. + 0 + 1 + write-only + + + CLEARSEMAREQ + Semaphore Clear command. + 3 + 1 + write-only + + + + + STATUSREG + STATUSREG + STATUSREG register + 0x1c + 0x20 + read-only + 0x00000000 + + + AESONFLYBUSY + AES on the fligh encryption busy status + 0 + 1 + read-only + + + NOTSUPPORTED_FUNCTION + indicates the SW requests an unsupported feature. + 3 + 1 + read-only + + + ADDPOINTERROR + Address Pointer Error status + + 4 + 1 + read-only + + + RXOVERFLOWERROR + AHB arbiter is full and there is no more storage capability available in RX datapath + 5 + 1 + read-only + + + PREVTRANSMIT + Previous event was a Transmission (1) or Reception (0) status + 6 + 1 + read-only + + + SEQDONE + Sequencer end of task status. + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 status: Transmit block missing data error. + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 status + + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 status. + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach. + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 status + + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive status + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready status + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready status. + 15 + 1 + read-only + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error status + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error status + + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip status. + 21 + 1 + read-only + + + ACTIVE2ERROR + Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step. + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error status + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK by the peer device status. + 24 + 1 + read-only + + + DONE + Receive/Transmit done status. + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout status (no access address found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit status (valid only on Data Physical Channel PDU reception) + + 27 + 1 + read-only + + + RCVCMD + Received command status (valid only on Data Physical Channel PDU reception). + 28 + 1 + read-only + + + TIMECAPTURETRIG + indicates a time has been captured in TIMERCAPTUREREG when set. + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail (CRC error or invalid CI field) status. + 30 + 1 + read-only + + + RCVOK + Receive data OK status + 31 + 1 + read-only + + + + + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG register + 0x20 + 0x20 + read-only + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error enable interruption + 4 + 1 + read-only + + + RXOVERFLOWERROR + Rx Overflow Error enable interruption + 5 + 1 + read-only + + + SEQDONE + Sequencer end of task enable interruption + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 enable interruption + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 enable interruption + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 enable interruption + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3 enable interruption + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 enable interruption + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive enable interruption + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready enable interruption + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready enable interruption + 15 + 1 + read-only + + + NOACTIVELERROR + active bit error enable interruption + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error enable interruption + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error enable interruption + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip enable interruption + 21 + 1 + read-only + + + ACTIVE2ERROR + Active2 Radio state error enable interruption + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error enable interruption + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK enable interruption + 24 + 1 + read-only + + + DONE + Receive/Transmit done interruption + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout enable interruption (no preamble found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit embedded in the PDU data packet header was zero enable interruption + 27 + 1 + read-only + + + RCVCMD + Received command enable interruption + 28 + 1 + read-only + + + TIMECAPTURETRIG + TimerCaptureReg time capture enable interruption + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail enable interruption + 30 + 1 + read-only + + + RCVOK + Receive data OK enable interruption + 31 + 1 + read-only + + + + + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG register + 0x24 + 0x20 + read-only + 0x00000000 + + + INTERRUPT1LATENCY + relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence. + 0 + 8 + read-only + + + + + MANAESKEY0REG + MANAESKEY0REG + MANAESKEY0REG register + 0x28 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_31_0 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY1REG + MANAESKEY1REG + MANAESKEY1REG register + 0x2c + 0x20 + read-write + 0x00000000 + + + MANAESKEY_63_32 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY2REG + MANAESKEY2REG + MANAESKEY2REG register + 0x30 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_95_64 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY3REG + MANAESKEY3REG + MANAESKEY3REG register + 0x34 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_127_96 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG register + 0x38 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG register + 0x3c + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG register + 0x40 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG register + 0x44 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG register + 0x48 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG register + 0x4c + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG register + 0x50 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG register + 0x54 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCMDREG + MANAESCMDREG + MANAESCMDREG register + 0x58 + 0x20 + read-write + 0x00000000 + + + START + AES Manual encryption Start command. + 0 + 1 + write-only + + + INTENA + AES Manual encryption interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + + + MANAESSTATREG + MANAESSTATREG + MANAESSTATREG register + 0x5c + 0x20 + read-only + 0x00000000 + + + BUSY + AES manual encryption busy status + 0 + 1 + read-only + + + + + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG register + 0x60 + 0x20 + read-write + 0x00000000 + + + POINTER + AES Le privacy pointer + 0 + 24 + read-write + + + + + AESLEPRIVHASHREG + AESLEPRIVHASHREG + AESLEPRIVHASHREG register + 0x64 + 0x20 + read-write + 0x00000000 + + + HASH + AES Le privacy Reference Hash + 0 + 24 + read-write + + + + + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG register + 0x68 + 0x20 + read-write + 0x00000000 + + + PRAND + AES Le privacy Prand + 0 + 24 + read-write + + + + + AESLEPRIVCMDREG + AESLEPRIVCMDREG + AESLEPRIVCMDREG register + 0x6c + 0x20 + read-write + 0x00000000 + + + START + AES Le privacy Start command. + 0 + 1 + write-only + + + INTENA + AES Le privacy interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + NBKEYS + AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list. + 2 + 8 + read-write + + + + + AESLEPRIVSTATREG + AESLEPRIVSTATREG + AESLEPRIVSTATREG register + 0x70 + 0x20 + read-only + 0x00000000 + + + BUSY + AES Le privacy busy status + 0 + 1 + read-only + + + KEYFND + AES Le privacy key finding status + 1 + 1 + read-only + + + KEYFNDINDEX + AES Le privacy index of the key found in the resolution key list. + 2 + 8 + read-only + + + + + DEBUGCMDREG + DEBUGCMDREG + DebugCmd register + 0x74 + 32 + read-write + 0x00000000 + + + CLEARDEBUGINT + CLEARDEBUGINT + 0 + 1 + + + SEQDEBUGMODE + SEQDEBUGMODE + 1 + 1 + + + SEQDEBUGBUSSEL + SEQDEBUGBUSSEL + 2 + 4 + + + AESDEBUGMODE + AESDEBUGMODE + 16 + 4 + + + + + DEBUGSTATUSREG + DEBUGSTATUSREG + DebugStatus register + 0x78 + 32 + read-only + 0x00000000 + + + DEBUGSTATUSREG + DEBUGSTATUSREG + 0 + 7 + + + AESDBG_0 + AESDBG_0 + 16 + 1 + + + AESDBG_1 + AESDBG_1 + 17 + 1 + + + AESDBG_2 + AESDBG_2 + 18 + 1 + + + AESDBG_3 + AESDBG_3 + 19 + 1 + + + + + + + GLOBALSTATMACH + GLOBALSTATMACH + 0x200000C0 + + 0x0 + 0x1C + registers + + + + WORD0 + WORD0 + WORD0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + RadioConfigPtr + Radio Configuration address Pointer. + 0 + 32 + read-write + + + + + WORD1 + WORD1 + WORD1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + CurStMachNum + current connection machine number. + 0 + 7 + read-write + + + Active + Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence. + 7 + 1 + read-write + + + WakeupInitDelay + Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM. + 8 + 8 + read-write + + + Timer12InitDelayCal + Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 16 + 8 + read-write + + + Timer2InitDelayNoCal + Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 24 + 8 + read-write + + + + + WORD2 + WORD2 + WORD2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + TransmitCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block. + 0 + 8 + read-write + + + TransmitNoCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse to the transmit block. + 8 + 8 + read-write + + + ReceiveCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block. + 16 + 8 + read-write + + + ReceiveNoCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse to the receive block. + 24 + 8 + read-write + + + + + WORD3 + WORD3 + WORD3 register + 0xc + 0x20 + read-write + 0x00000000 + + + ConfigEndDuration + Duration for the Sequencer to execute the final configuration. + 0 + 8 + read-write + + + TxdataReadyCheck + Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table. + 8 + 8 + read-write + + + TxdelayStart + Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator. + 16 + 8 + read-write + + + TxdelayEnd + Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer. + 24 + 6 + read-write + + + TimeCaptureSel + - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event). + 30 + 1 + read-write + + + TimeCapture + - 0: No capture is requested to monitor the Bluetooth LE sequence. + 31 + 1 + read-write + + + + + WORD4 + WORD4 + WORD4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + TxReadyTimeout + Transmission ready timeout. + 0 + 8 + read-write + + + RcvTimeout + Receive window timeout. + 8 + 20 + read-write + + + + + WORD5 + WORD5 + WORD5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + AutoTxRxskipEn + Automatic transfer (TX or RX) skip enable. + 0 + 1 + read-write + + + ChkFlagAutoClearEna + Active bit Auto Clear Enable. + 2 + 1 + read-write + + + IntAddPointError + Address pointer error interrupt enable. + 20 + 1 + read-write + + + IntAllTableReadyError + All table ready error interrupt enable. + 21 + 1 + read-write + + + IntTxDataReadyError + Transmission data payload ready error interrupt enable. + 22 + 1 + read-write + + + IntNoActiveLError + Active bit low value reading interrupt enable. + 23 + 1 + read-write + + + IntRcvLengthError + Too long received payload length interrupt enable. + 25 + 1 + read-write + + + IntSemaTimeoutError + Semaphore timeout error interrupt enable. + 26 + 1 + read-write + + + IntSeqDone + Sequencer end of task interrupt enable. + 28 + 1 + read-write + + + intTxRxSkip + Transmission or reception skip interrupt enable. + 29 + 1 + read-write + + + IntActive2Err + not in ACTIVE2 information from Radio FSM received on time interrupt enable. + 30 + 1 + read-write + + + IntConfigError + Configuration error interrupt enable. + 31 + 1 + read-write + + + + + WORD6 + WORD6 + WORD6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + DefaultAntennaID + Default Antenna ID corresponding to the number of the antenna used to receive/transmit: + + 0 + 7 + + + + + + + RADIO_CONTROL + RADIO_CONTROL + 0x60001000 + + 0x0 + 0x400 + registers + + + + RADIO_CONTROL_ID + RADIO_CONTROL_ID + RADIO_CONTROL_ID register + 0x0 + 0x20 + read-only + 0x00003000 + + + REVISION + Incremented for metal fix version + 4 + 4 + read-only + + + VERSION + Cut Number + 8 + 4 + read-only + + + PRODUCT + incremented on major features add-on like new Bluetooth LE SIG version support + + 12 + 4 + read-only + + + + + CLK32COUNT_REG + CLK32COUNT_REG + CLK32COUNT_REG register + 0x4 + 0x20 + read-write + 0x00000017 + + + SLOW_COUNT + program the window length (in slow clock period) for slow clock measurement. + 0 + 9 + read-write + + + + + CLK32PERIOD_REG + CLK32PERIOD_REG + CLK32PERIOD_REG register + 0x8 + 0x20 + read-only + 0x00000000 + + + SLOW_PERIOD + indicates slow clock period information. + 0 + 19 + read-only + + + + + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG register + 0xc + 0x20 + read-only + 0x00000000 + + + SLOW_FREQUENCY + value equal to (2^39/ SLOW_PERIOD). + 0 + 27 + read-only + + + + + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ + slow clock measurement end of calculation interrupt status + + 0 + 1 + read-write + + + RADIO_FSM_IRQ + Radio FSM interrupt status (aka RfFsm_event_irq). + 8 + 6 + read-write + + + + + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ_MASK + mask slow clock measurement interrupt + + 0 + 1 + read-write + + + RADIO_FSM_IRQ_MASK + mask for each RfFsm_event (Radio FSM) interrupt. + 8 + 6 + read-write + + + + + + + RADIO + RADIO + 0x60001500 + + 0x0 + 0x300 + registers + + + RADIO_ERROR + RADIO Error interrupt + 20 + + + RADIO_CPU_WKUP + RADIO CPU Wakeup interrupt + 23 + + + RADIO_TXRX_WKUP + RADIO Wakeup interrupt + 24 + + + RADIO_TXRX_SEQ + RADIO RX/TX sequence interrupt + 25 + + + + AA0_DIG_USR + AA0_DIG_USR + AA0_DIG_USR register + 0x0 + 0x20 + read-write + 0x000000D6 + + + AA_7_0 + Least significant byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA1_DIG_USR + AA1_DIG_USR + AA1_DIG_USR register + 0x4 + 0x20 + read-write + 0x000000BE + + + AA_15_8 + Next byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + AA2_DIG_USR + AA2_DIG_USR + AA2_DIG_USR register + 0x8 + 0x20 + read-write + 0x00000089 + + + AA_23_16 + Next byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA3_DIG_USR + AA3_DIG_USR + AA3_DIG_USR register + 0xc + 0x20 + read-write + 0x0000008E + + + AA_31_24 + Most significant byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR register + 0x10 + 0x20 + read-write + 0x00000026 + + + CHANNEL_NUM + Index for internal lock up table in which the synthesizer setup is contained. + 1 + 7 + read-write + + + + + RADIO_FSM_USR + RADIO_FSM_USR + RADIO_FSM_USR register + 0x14 + 0x20 + read-write + 0x00000004 + + + EN_CALIB_CBP + CBP calibration enable bit. + 1 + 1 + read-write + + + EN_CALIB_SYNTH + SYNTH calibration enable bit. + 2 + 1 + read-write + + + PA_POWER + PA Power coefficient. + 3 + 5 + read-write + + + + + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RXTXPHY + RXTXPHY selection. + 0 + 3 + read-write + + + + + AFC1_DIG_ENG + AFC1_DIG_ENG + AFC1_DIG_ENG register + 0x48 + 0x20 + read-write + 0x00000044 + + + AFC_DELAY_AFTER + Set the decay factor of the AFC loop after Access Address detection + 0 + 4 + read-write + + + AFC_DELAY_BEFORE + Set the decay factor of the AFC loop before Access Address detection + 4 + 4 + read-write + + + + + CR0_DIG_ENG + CR0_DIG_ENG + CR0_DIG_ENG register + 0x54 + 0x20 + read-write + 0x00000044 + + + CR_GAIN_AFTER + Set the gain of the clock recovery loop before Access Address detection to the value + + 0 + 4 + read-write + + + CR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value + + 4 + 4 + read-write + + + + + CR0_LR + CR0_LR + CR0_LR register + 0x68 + 0x20 + read-write + 0x00000066 + + + CR_LR_GAIN_AFTER + Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use + 0 + 4 + read-write + + + CR_LR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use + 4 + 4 + read-write + + + + + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG register + 0x6c + 0x20 + read-write + 0x00000000 + + + VIT_EN + Viterbi enable + + 0 + 1 + read-write + + + SPARE + spare + 2 + 6 + read-write + + + + + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG register + 0x84 + 0x20 + read-write + 0x00000050 + + + LR_PD_THR + preamble detect threshold value + 0 + 8 + read-write + + + + + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG register + 0x88 + 0x20 + read-write + 0x0000001B + + + LR_RSSI_THR + RSSI or peak threshold value + 0 + 8 + read-write + + + + + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG register + 0x8c + 0x20 + read-write + 0x00000038 + + + LR_AAC_THR + address coded correlation threshold + 0 + 8 + read-write + + + + + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG register + 0xa8 + 0x20 + read-write + 0x00000000 + + + SYNTHCAL_DEBUG_BUS_SEL + for Debug purpose + + 0 + 4 + read-write + + + SYNTH_IF_FREQ_CAL + Define the frequency applied on the PLL during calibration phase + + 6 + 2 + read-write + + + + + DTB5_DIG_ENG + DTB5_DIG_ENG + DTB5_DIG_ENG register + 0xf0 + 0x20 + read-write + 0x00000000 + + + RXTX_START_SEL + enable the possibility to control some signals by the other register bits instead of system design: + + 0 + 1 + read-write + + + TX_ACTIVE + Force TX_ACTIVE signal + 1 + 1 + read-write + + + RX_ACTIVE + Force RX_ACTIVE signal + 2 + 1 + read-write + + + INITIALIZE + Force INITIALIZE signal (emulate a token request of the IP_BLE) + 3 + 1 + read-write + + + PORT_SELECTED_EN + enable port selection + 4 + 1 + read-write + + + PORT_SELECTED_0 + force port_selected[0] signal + 5 + 1 + read-write + + + + + RXADC_ANA_USR + RXADC_ANA_USR + RXADC_ANA_USR register + 0x148 + 0x20 + read-write + 0x0000001B + + + RFD_RXADC_DELAYTRIM_I + ADC loop delay control bits for I channel to apply when SW overload is enabled + 0 + 3 + read-write + + + RFD_RXADC_DELAYTRIM_Q + ADC loop delay control bits for Q channel to apply when SW overload is enabled + 3 + 3 + read-write + + + RXADC_DELAYTRIM_I_TST_SEL + Enable the SW overload on RXADX delay trimming + + 6 + 1 + read-write + + + RXADC_DELAYTRIM_Q_TST_SEL + Enable the SW overload on RXADX delay trimming + + 7 + 1 + read-write + + + + + LDO_ANA_ENG + LDO_ANA_ENG + LDO_ANA_ENG register + 0x154 + 0x20 + read-write + 0x00000000 + + + RFD_RF_REG_BYPASS + RF_REG Bypass mode: + + 0 + 1 + read-write + + + + + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG register + 0x174 + 0x20 + read-write + 0x00000088 + + + RFD_CBIAS_IBIAS_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 0 + 4 + read-write + + + RFD_CBIAS_IPTAT_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 4 + 4 + read-write + + + + + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG register + 0x178 + 0x20 + read-write + 0x00000000 + + + CBIAS0_TRIM_TST_SEL + When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings + 7 + 1 + read-write + + + + + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT register + 0x180 + 0x20 + read-only + 0x00000000 + + + VCO_CALAMP_OUT_6_0 + VCO CALAMP value + 0 + 7 + read-only + + + + + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT register + 0x184 + 0x20 + read-only + 0x00000001 + + + VCO_CALAMP_OUT_10_7 + VCO CALAMP value + 0 + 4 + read-only + + + + + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT register + 0x188 + 0x20 + read-only + 0x00000040 + + + VCO_CALFREQ_OUT + VCO CALFREQ value + 0 + 7 + read-only + + + + + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT register + 0x18c + 0x20 + read-only + 0x00000000 + + + SYNTHCAL_DEBUG_BUS + Calibration debug bus. + 0 + 8 + read-only + + + + + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT register + 0x190 + 0x20 + read-only + 0x00000018 + + + MOD_REF_DAC_WORD_OUT + Calibration word + 0 + 6 + read-only + + + + + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT register + 0x194 + 0x20 + read-only + 0x00000007 + + + CBP_CALIB_WORD + CBP Calibration word + 0 + 4 + read-only + + + + + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT register + 0x198 + 0x20 + read-only + 0x00000000 + + + STATUS + RF FSM state: + + 0 + 5 + read-only + + + SYNTH_CAL_ERROR + PLL calibration error + 7 + 1 + read-only + + + + + RSSI0_DIG_OUT + RSSI0_DIG_OUT + RSSI0_DIG_OUT register + 0x1a4 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_7_0 + Measure of the received signal strength. + 0 + 8 + read-only + + + + + RSSI1_DIG_OUT + RSSI1_DIG_OUT + RSSI1_DIG_OUT register + 0x1a8 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_15_8 + Measure of the received signal strength + 0 + 8 + read-only + + + + + AGC_DIG_OUT + AGC_DIG_OUT + AGC_DIG_OUT register + 0x1ac + 0x20 + read-only + 0x00000000 + + + AGC_ATT_OUT + AGC attenuation value + 0 + 4 + read-only + + + + + DEMOD_DIG_OUT + DEMOD_DIG_OUT + DEMOD_DIG_OUT register + 0x1b0 + 0x20 + read-only + 0x00000000 + + + CI_FIELD + CI field + 0 + 2 + read-only + + + AAC_FOUND + aac_found + 2 + 1 + read-only + + + PD_FOUND + pd_found + 3 + 1 + read-only + + + RX_END + rx_end + 4 + 1 + read-only + + + + + AGC2_ANA_TST + AGC2_ANA_TST + AGC2_ANA_TST register + 0x1bc + 0x20 + read-write + 0x00000000 + + + AGC2_ANA_TST_SEL + Selection: + + 0 + 1 + read-write + + + AGC_ANTENNAE_USR_TRIM + the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1) + 1 + 3 + read-write + + + + + AGC0_DIG_ENG + AGC0_DIG_ENG + AGC0_DIG_ENG register + 0x1c0 + 0x20 + read-write + 0x0000004A + + + AGC_THR_HIGH + High AGC threshold + 0 + 6 + read-write + + + AGC_ENABLE + Enable AGC + 6 + 1 + read-write + + + + + AGC1_DIG_ENG + AGC1_DIG_ENG + AGC1_DIG_ENG register + 0x1c4 + 0x20 + read-write + 0x00000084 + + + AGC_THR_LOW_6 + Low threshold for 6dB steps + 0 + 6 + read-write + + + AGC_AUTOLOCK + AGC locks when level is steady between high threshold and lock threshold + 6 + 1 + read-write + + + AGC_LOCK_SYNC + AGC locks when Access Address is detected (recommended) + 7 + 1 + read-write + + + + + AGC10_DIG_ENG + AGC10_DIG_ENG + AGC10_DIG_ENG register + 0x1e8 + 0x20 + read-write + 0x00000000 + + + ATT_IF_0 + Attenuation at IF Level for the AGC step 0: + + 0 + 3 + read-write + + + ATT_LNA_0 + Attenuation at LNA Level for the AGC step 0: + + 3 + 1 + read-write + + + ATT_ANT_0 + Attenuation at Antenna Level for the AGC step 0: + + 4 + 2 + read-write + + + + + AGC11_DIG_ENG + AGC11_DIG_ENG + AGC11_DIG_ENG register + 0x1ec + 0x20 + read-write + 0x00000010 + + + ATT_IF_1 + Attenuation at IF Level for the AGC step 1 + 0 + 3 + read-write + + + ATT_LNA_1 + Attenuation at LNA Level for the AGC step 1 + 3 + 1 + read-write + + + ATT_ANT_1 + Attenuation at Antenna Level for the AGC step 1 + 4 + 2 + read-write + + + + + AGC12_DIG_ENG + AGC12_DIG_ENG + AGC12_DIG_ENG register + 0x1f0 + 0x20 + read-write + 0x000000020 + + + ATT_IF_2 + Attenuation at IF Level for the AGC step 2 + 0 + 3 + read-write + + + ATT_LNA_2 + Attenuation at LNA Level for the AGC step 2 + 3 + 1 + read-write + + + ATT_ANT_2 + Attenuation at Antenna Level for the AGC step 2 + 4 + 2 + read-write + + + + + AGC13_DIG_ENG + AGC13_DIG_ENG + AGC13_DIG_ENG register + 0x1f4 + 0x20 + read-write + 0x00000030 + + + ATT_IF_3 + Attenuation at IF Level for the AGC step 3 + 0 + 3 + read-write + + + ATT_LNA_3 + Attenuation at LNA Level for the AGC step 3 + 3 + 1 + read-write + + + ATT_ANT_3 + Attenuation at Antenna Level for the AGC step 3 + 4 + 2 + read-write + + + + + AGC14_DIG_ENG + AGC14_DIG_ENG + AGC14_DIG_ENG register + 0x1f8 + 0x20 + read-write + 0x00000038 + + + ATT_IF_4 + Attenuation at IF Level for the AGC step 4 + 0 + 3 + read-write + + + ATT_LNA_4 + Attenuation at LNA Level for the AGC step 4 + 3 + 1 + read-write + + + ATT_ANT_4 + Attenuation at Antenna Level for the AGC step 4 + 4 + 2 + read-write + + + + + AGC15_DIG_ENG + AGC15_DIG_ENG + AGC15_DIG_ENG register + 0x1fc + 0x20 + read-write + 0x00000039 + + + ATT_IF_5 + Attenuation at IF Level for the AGC step 5 + 0 + 3 + read-write + + + ATT_LNA_5 + Attenuation at LNA Level for the AGC step 5 + 3 + 1 + read-write + + + ATT_ANT_5 + Attenuation at Antenna Level for the AGC step 5 + 4 + 2 + read-write + + + + + AGC16_DIG_ENG + AGC16_DIG_ENG + AGC16_DIG_ENG register + 0x200 + 0x20 + read-write + 0x0000003A + + + ATT_IF_6 + Attenuation at IF Level for the AGC step 6 + 0 + 3 + read-write + + + ATT_LNA_6 + Attenuation at LNA Level for the AGC step 6 + 3 + 1 + read-write + + + ATT_ANT_6 + Attenuation at Antenna Level for the AGC step 6 + 4 + 2 + read-write + + + + + AGC17_DIG_ENG + AGC17_DIG_ENG + AGC17_DIG_ENG register + 0x204 + 0x20 + read-write + 0x0000003B + + + ATT_IF_7 + Attenuation at IF Level for the AGC step 7 + 0 + 3 + read-write + + + ATT_LNA_7 + Attenuation at LNA Level for the AGC step 7 + 3 + 1 + read-write + + + ATT_ANT_7 + Attenuation at Antenna Level for the AGC step 7 + 4 + 2 + read-write + + + + + AGC18_DIG_ENG + AGC18_DIG_ENG + AGC18_DIG_ENG register + 0x208 + 0x20 + read-write + 0x0000003C + + + ATT_IF_8 + Attenuation at IF Level for the AGC step 8 + 0 + 3 + read-write + + + ATT_LNA_8 + Attenuation at LNA Level for the AGC step 8 + 3 + 1 + read-write + + + ATT_ANT_8 + Attenuation at Antenna Level for the AGC step 8 + 4 + 2 + read-write + + + + + AGC19_DIG_ENG + AGC19_DIG_ENG + AGC19_DIG_ENG register + 0x20c + 0x20 + read-write + 0x0000003D + + + ATT_IF_9 + Attenuation at IF Level for the AGC step 9 + 0 + 3 + read-write + + + ATT_LNA_9 + Attenuation at LNA Level for the AGC step 9 + 3 + 1 + read-write + + + ATT_ANT_9 + Attenuation at Antenna Level for the AGC step 9 + 4 + 2 + read-write + + + + + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT register + 0x224 + 0x20 + read-only + 0x0000001B + + + HW_RXADC_DELAYTRIM_I + control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR). + 0 + 3 + read-only + + + HW_RXADC_DELAYTRIM_Q + control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR). + 3 + 3 + read-only + + + + + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT register + 0x228 + 0x20 + read-only + 0x00000088 + + + HW_CBIAS_IBIAS_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 0 + 4 + read-only + + + HW_CBIAS_IPTAT_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 4 + 4 + read-only + + + + + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT register + 0x230 + 0x20 + read-only + 0x00000006 + + + HW_AGC_ANTENNAE_TRIM + AGC trim value (provided by the HW trimming, automatically loaded on POR). + 1 + 3 + read-only + + + + + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST register + 0x23c + 0x20 + read-write + 0x00000000 + + + EXTCFG_SAMPLING_TIME + Defines the sampling time, when extended configuration is enabled: + + 0 + 2 + read-write + + + EXTCFG_TRIG_SELECTION + Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled: + + 2 + 2 + read-write + + + + + ANTSW0_DIG_USR + ANTSW0_DIG_USR + ANTSW0_DIG_USR register + 0x240 + 0x20 + read-write + 0x0000001C + + + RX_TIME_TO_SAMPLE + specifies the exact timing of the first I/Q sampling in the reference period. + 0 + 7 + read-write + + + + + ANTSW1_DIG_USR + ANTSW1_DIG_USR + ANTSW1_DIG_USR register + 0x244 + 0x20 + read-write + 0x0000000B + + + RX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching at receiver level (in AoA). + 0 + 6 + read-write + + + + + ANTSW2_DIG_USR + ANTSW2_DIG_USR + ANTSW2_DIG_USR register + 0x248 + 0x20 + read-write + 0x00000029 + + + TX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD). + 0 + 7 + read-write + + + + + ANTSW3_DIG_USR + ANTSW3_DIG_USR + ANTSW3_DIG_USR register + 0x24c + 0x20 + read-write + 0x00000023 + + + TX_TIME_TO_SWITCH_2M + specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD). + 0 + 7 + read-write + + + + + + + RRM + RRM + 0x60001400 + + 0x0 + 0x100 + registers + + + + UDRA_CTRL0 + UDRA_CTRL0 + UDRA_CTRL0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + RELOAD_RDCFGPTR + reload the radio configuration pointer from RAM. + 0 + 1 + read-write + + + + + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + UDRA interrupt enable (reload radio config pointer) + 0 + 1 + read-write + + + CMD_START + UDRA interrupt enable (command start) + 1 + 1 + read-write + + + CMD_END + UDRA interrupt enable (command end) + 2 + 1 + read-write + + + + + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + On read, returns the UDRA reload radio configuration pointer interrupt status. + 0 + 1 + read-write + + + CMD_STARD + On read, returns the UDRA command start interrupt status. + 1 + 1 + read-write + + + CMD_END + On read, returns the UDRA command end interrupt status + + 2 + 1 + read-write + + + + + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR register + 0x1c + 0x20 + read-only + 0x00000000 + + + RADIO_CONFIG_ADDRESS + UDRA radio configuration address. + 0 + 32 + read-only + + + + + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE register + 0x20 + 0x20 + read-write + 0x00000000 + + + LOCK + semaphore locked (= one port granted) interrupt enable + 0 + 1 + read-write + + + UNLOCK + semaphore unlocked (=no port selected) interrupt enable + 1 + 1 + read-write + + + + + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS register + 0x24 + 0x20 + read-write + 0x00000000 + + + LOCK + On read, returns the semaphore locked interrupt status. + 0 + 1 + read-write + + + UNLOCK + On read, returns the semaphore unlocked interrupt status. + 1 + 1 + read-write + + + + + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE register + 0x28 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE Port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE Port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + IP_BLE Port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + IP_BLE Port command end interrup enable + 4 + 1 + read-write + + + + + BLE_IRQ_STATUS + BLE_IRQ_STATUS + BLE_IRQ_STATUS register + 0x2c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE hardware port granted interrupt status: + + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE hardware port released interrupt status. + 1 + 1 + read-write + + + CMD_START + IP_BLE hardware port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + IP_BLE hardware port command end interrupt status. + 4 + 1 + read-write + + + + + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS register + 0x60 + 0x20 + read-write + 0x00000000 + + + COMMAND + command number + 0 + 3 + read-write + + + COMMAND_REQ + CPU Virtual port command request: + + 3 + 1 + read-write + + + + + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS register + 0x64 + 0x20 + read-write + 0x00000000 + + + TAKE_PRIO + semaphore priority: priority value (between 0 and 7) of the take request. + 0 + 3 + read-write + + + TAKE_REQ + semaphore token request: + + 3 + 1 + read-write + + + + + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE register + 0x68 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + CPU virtual port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + CPU virtual port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + CPU virtual port command end interrup enable + 4 + 1 + read-write + + + + + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS register + 0x6c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port granted interrupt status. + 0 + 1 + read-write + + + PORT_RELEASE + virtual port released interrupt status. + 1 + 1 + read-write + + + PORT_PREEMPT + CPU virtual port preemption (at semaphore level) interrupt status. + 2 + 1 + read-write + + + CMD_START + CPU virtual port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + CPU virtual port command end interrupt status. + 4 + 1 + read-write + + + + + + + WAKEUP + WAKEUP + 0x60001800 + + 0x0 + 0x400 + registers + + + + WAKEUP_OFFSET + WAKEUP_OFFSET + WAKEUP_OFFSET register + 0x8 + 0x20 + read-write + 0x00000000 + + + WAKEUP_OFFSET + delay of anticipation of the Soc device to settle power and clock + + 0 + 8 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0x10 + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + absolute time + + 0 + 32 + read-only + + + + + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH register + 0x14 + 0x20 + read-only + 0x00000000 + + + LENGTH + minimum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH register + 0x18 + 0x20 + read-only + 0x00000000 + + + LENGTH_FRACT + additional information/precision on slow clock frequency. + 0 + 4 + read-only + + + LENGTH_INT + average period length computed by Time Interpolator. + 4 + 10 + read-only + + + AVERAGE_COUNT + Number of slow clock cycles. + 24 + 8 + read-only + + + + + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH register + 0x1c + 0x20 + read-only + 0x00000000 + + + LENGTH + maximum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + STATISTICS_RESTART + STATISTICS_RESTART + STATISTICS_RESTART register + 0x20 + 0x20 + read-write + 0x00000000 + + + CLR_MIN_MAX + Write '1' to clear the minimum and maximum registers. + 0 + 1 + read-write + + + CLR_AVR + Write '1' to clear the AVERAGE_PERIOD_LENGTH register value. + 1 + 1 + read-write + + + + + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME register + 0x24 + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for the IP_BLE. + 0 + 32 + read-write + + + + + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE register + 0x28 + 0x20 + read-write + 0x00000007 + + + SLEEP_EN + IP_BLE sleeping mode enable: + + 29 + 1 + read-write + + + BLE_WAKEUP_EN + IP_BLE wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + IP_BLE sleeping control: + + 31 + 1 + read-write + + + + + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME register + 0x2c + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for CPU. + 4 + 28 + read-write + + + + + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE register + 0x30 + 0x20 + read-write + 0x80000007 + + + CPU_WAKEUP_EN + CPU wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + CPU sleeping control: + + 31 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE register + 0x40 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + IP_BLE wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS register + 0x44 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the IP_BLE wakeup interrupt status. + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE register + 0x48 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + CPU wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS register + 0x4c + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the CPU wakeup interrupt status. + 0 + 1 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x2000 + registers + + + FLASH + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +- 0x11 : ERASE +- 0x22 : MASSERASE +- 0x33 : WRITE +- 0x44 : MASSWRITE +- 0x55 : MASSREAD +- 0x66 : IFRERASE +- 0x77 : IFRWRITE +- 0x88 : IFRMASSWRITE +- 0x99 : IFRMASSREAD +- 0xAA : SLEEP +- 0xBB : WAKEUP +- 0xCC : BURSTWRITE +- 0xDD : IFRBURSTWRITE +- 0xEE : OTPWRITE +- 0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + REMAP + Bit to redirect boot area on SRAM0. + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +- 0 : burst write allowed +- 1 : burst write forbidden + 2 + 1 + read-write + + + WAIT_STATES + Number of wait states to be inserted on Flash read (AHB accesses) + 4 + 2 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + Command done masked interrupt status. + 0 + 1 + read-write + + + CMDSTART_MIS + Command started masked interrupt status. + 1 + 1 + read-write + + + CMDERR_MIS + Command error masked interrupt status. + 2 + 1 + read-write + + + ILLCMD_MIS + Illegal command masked interrupt status + 3 + 1 + read-write + + + READOK_MIS + Mass read OK masked interrupt status. + 4 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + Command done mask + 0 + 1 + read-write + + + CMDSTARTM + Command started mask. + 1 + 1 + read-write + + + CMDERRM + Command error mask. + 2 + 1 + read-write + + + ILLCMDM + Illegal command mask. + 3 + 1 + read-write + + + READOKM + Mass read OK mask. + 4 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + Command done raw/unmasked interrupt status. This it is set once the requested command +execution is completed. Cleared by writing 1. + 0 + 1 + read-write + + + CMDSTART_RIS + Command started raw/unmasked interrupt status. This bit is set once the requested command +execution has started. + 1 + 1 + read-write + + + CMDERR_RIS + Command error raw/unmasked interrupt status + 2 + 1 + read-write + + + ILLCMD_RIS + Illegal command raw/unmasked interrupt status. + 3 + 1 + read-write + + + READOK_RIS + Mass read OK raw/unmasked interrupt status + 4 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0000FFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +- 00 : 0x0BFFF (192kb) +- 01 : 0x0FFFF (256kb) +- 10 : 0x17FFF (384kb) +- 11 : 0x1FFFF (512kb) + 0 + 16 + read-only + + + RAM_SIZE + RAM memory size selection: +- 00 : 32kb +- 01 : 32kb +- 10 : 48kb +- 11 : 64kb + 17 + 2 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + SWD_DISABLE + Flash+SWD protection: +0: No SWD protection (refer to FLASH_SECURE) +1: Flash and SWD protected + + 20 + 1 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEG0 + First segment definition. + 0 + 16 + read-write + + + SEG1 + Second segment definition. See SEG0 description for details on SEG1[31:16] content + 16 + 16 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEG2 + Third segment definition. See PAGEPROT0 SEG0 description for details on SEG2[15:0] content + 0 + 16 + read-write + + + SEG3 + Fourth segment definition. See PAGEPROT0 SEG0 description for details on SEG3[15:0] content. + 16 + 16 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + + + RNG + RNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + + RNG_CR + RNG_CR + RNG_CR register + 0x00 + 0x20 + read-write + 0x0000FF00 + + + RNG_DIS + This bit enables or disables the random number generator. +0: RNG is enabled (default) +1: RNG is disabled. The internal free-running oscillators are put in power-down +mode and the RNG clock is stopped at the input of the block. + 1 + 1 + read-write + + + B_0x0 + The RNG core is enabled + + 0x0 + + + B_0x1 + The RNG core is disabled + 0x1 + + + + + TST_CLK + Reset reveal clock error flags when writing a '1' without resetting the whole TRNG. +When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. + 3 + 1 + read-write + + + B_0x0 + no reset + + 0x0 + + + B_0x1 + reset revclk flag + + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + RNGRDY + New random value ready + 0 + 1 + read-only + + + B_0x0 + Normal operation. + + 0x0 + + + B_0x1 + RNG is disabled. + 0x1 + + + + + REVCLK + RNGCLK clock reveal bit. + 1 + 1 + read-only + + + B_0x0 + At least one oscillator is ON + 0x0 + + + B_0x1 + All oscillators are down + + 0x1 + + + + + FAULT + Fault reveal bit. + 2 + 1 + read-only + + + B_0x0 + Internal clock for RNG clock is present. + + 0x0 + + + B_0x1 + Internal RNG clock is not present. + 0x1 + + + + + + + RNG_VAL + RNG_VAL + RNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RND_VAL + Random value + 0 + 16 + read-only + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA0 + registers + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. + 0 + 1 + read-write + + + B_0x0 + Deep Stop mode (default) + 0x0 + + + B_0x1 + Shutdown mode + 0x1 + + + + + ENSDNBOR + Enable BOR reset supervising during SHUTDOWN mode. + 1 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU + 4 + 1 + read-write + + + B_0x1 + the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. + 0x1 + + + B_0x0 + the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 0x0 + + + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +then PVDO=1) + 1 + 3 + read-write + + + B_0x0 + 2.05 V - Lowest level + 0x0 + + + B_0x1 + 2.20 V + 0x1 + + + B_0x2 + 2.36 V + 0x2 + + + B_0x3 + 2.52 V + 0x3 + + + B_0x4 + 2.64 V + 0x4 + + + B_0x5 + 2.81 V + 0x5 + + + B_0x6 + 2.91 V - Highest level + 0x6 + + + B_0x7 + External input analog voltage (compare internally to VBGP; When external input <VBGP + 0x7 + + + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode + 5 + 1 + read-write + + + B_0x1 + RAM1 bank is powered during low power mode + 0x1 + + + B_0x0 + RAM1 bank is disabled during low power mode (by default) + 0x0 + + + + + RAMRET2 + Enables the RAM2 bank retention in DEEPSTOP mode. + 6 + 1 + read-write + + + RAMRET3 + Enables the RAM3 bank retention in DEEPSTOP mode. + 7 + 1 + read-write + + + B_0x1 + Temperature sensor is enabled + 0x1 + + + B_0x0 + Temperature sensor is disabled + 0x0 + + + + + ENTS + Enable the temperature sensor. + 9 + 1 + read-write + + + LSILPMUFEN + LSI LPMU force enable. + 10 + 1 + read-write + + + + + CR3 + CR3 + CR3 register + 0x8 + 0x20 + read-write + 0x0000 + + + EWU0 + EWU0 Enable WakeUp line 0 (PB0) +When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit. + 0 + 1 + read-write + + + EWU1 + EWU1 Enable WakeUp line 1 (PB1) +When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit. + 1 + 1 + read-write + + + EWU2 + EWU2 Enable WakeUp line 2 (PB2) +When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit. + 2 + 1 + read-write + + + EWU3 + EWU3 Enable WakeUp line 3 (PB3) +When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit. + 3 + 1 + read-write + + + EWU4 + EWU4 Enable WakeUp line 4 (PB4) +When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit. + 4 + 1 + read-write + + + EWU5 + EWU5 Enable WakeUp line 5 (PB5) +When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit. + 5 + 1 + read-write + + + EWU6 + EWU6 Enable WakeUp line 6 (PB6) +When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit. + 6 + 1 + read-write + + + EWU7 + EWU7 Enable WakeUp line 7 (PB7) +When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit. + 7 + 1 + read-write + + + EWU8 + EWU8 Enable WakeUp line 8 (PA8) +When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit. + 8 + 1 + read-write + + + EWU9 + EWU9 Enable WakeUp line 9 (PA9) +When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit. + 9 + 1 + read-write + + + EWU10 + EWU10 Enable WakeUp line 10 (PA10) +When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit. + 10 + 1 + read-write + + + EWU11 + EWU11 Enable WakeUp line 11 (PA11) +When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit. + 11 + 1 + read-write + + + EWBLE + EWBLE: Enable wakeup on BLE event. +0: Wakeup on BLE line is disabled (default). +1: Wakeup on BLE line is enabled. + 12 + 1 + read-write + + + EWBLEHCPU + EWBLEHCPU: Enable wakeup on BLE Host CPU event. +0: Wakeup on BLE Host CPU line is disabled (default). +1: Wakeup on BLE Host CPU line is enabled. + 13 + 1 + read-write + + + EIWL + EIWL: Enable wakeup on Internal event (RTC). +0: Wakeup on internal line is disabled (default). +1: Wakeup on internal line is enabled. + 15 + 1 + read-write + + + + + CR4 + CR4 + CR4 register + 0xc + 0x20 + read-write + 0x0 + + + WUP0 + WUP0 Wake-up Line Polarity 0 (PB0) +This bit defines the polarity used for event detection on external wake-up line 0 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP1 + WUP1 Wake-up Line Polarity 1 (PB1) +This bit defines the polarity used for event detection on external wake-up line 1 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP2 + WUP2 Wake-up Line Polarity 2 (PB2) +This bit defines the polarity used for event detection on external wake-up line 2 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP3 + WUP3 Wake-up Line Polarity 3 (PB3) +This bit defines the polarity used for event detection on external wake-up line 3 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP4 + WUP4 Wake-up Line Polarity 4 (PB4) +This bit defines the polarity used for event detection on external wake-up line 4 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP5 + WUP5 Wake-up Line Polarity 5 (PB5) +This bit defines the polarity used for event detection on external wake-up line 5 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP6 + WUP6 Wake-up Line Polarity 6 (PB6) +This bit defines the polarity used for event detection on external wake-up line 6 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP7 + WUP7 Wake-up Line Polarity 7 (PB7) +This bit defines the polarity used for event detection on external wake-up line 7 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP8 + WUP8 Wake-up Line Polarity 8 (PA8) +This bit defines the polarity used for event detection on external wake-up line 8 + 8 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP9 + WUP9 Wake-up Line Polarity 9 (PA9) +This bit defines the polarity used for event detection on external wake-up line 9 + 9 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP10 + WUP10 Wake-up Line Polarity 10 (PA10) +This bit defines the polarity used for event detection on external wake-up line 10 + 10 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP11 + WUP11 Wake-up Line Polarity 11 (PA11) +This bit defines the polarity used for event detection on external wake-up line 11 + 11 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + SR1 + SR1 + SR1 register + 0x10 + 0x20 + read-write + 0x0 + + + WUF0 + WUF0 WakeUp Flag 0 (PB0) +This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF1 + WUF1 WakeUp Flag 1 (PB1) +This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF2 + WUF2 WakeUp Flag 2 (PB2) +This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF3 + WUF3 WakeUp Flag 3 (PB3) +This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF4 + WUF4 WakeUp Flag 4 (PB4) +This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF5 + WUF5 WakeUp Flag 5 (PB5) +This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF6 + WUF6 WakeUp Flag 6 (PB6) +This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF7 + WUF7 WakeUp Flag 7 (PB7) +This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF8 + WUF8 WakeUp Flag 8 (PA8) +This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 8 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF9 + WUF9 WakeUp Flag 9 (PA9) +This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 9 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF10 + WUF10 WakeUp Flag 10 (PA10) +This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 10 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF11 + WUF11 WakeUp Flag 11 (PA11) +This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 11 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WBLEF + WBLEF: BLE wakeup flag. +0: no wakeup from BLE occurred since last clear. +1: a wakeup from BLE occurred since last clear. +Cleared by writing 1 in this bit. + 12 + 1 + read-write + + + WBLEHCPUF + WBLEHCPUF: BLE Host CPU wakeup flag. +0: no wakeup from BLE Host CPU occurred since last clear. +1: a wakeup from BLE Host CPU occurred since last clear. +Cleared by writing 1 in this bit. + 13 + 1 + read-write + + + IWUF + IWUF: Internal wakeup flag (RTC). +0: no wakeup from RTC occurred since last clear. +1: a wakeup from RTC occurred since last clear. +Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of +the RTC wakeup line on the PWRC block). + 15 + 1 + read-only + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0x0306 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. + 2 + 1 + read-only + + + B_0x0 + SMPS regulator is not ready + 0x0 + + + B_0x1 + SMPS regulator is ready. + 0x1 + + + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. + 8 + 1 + read-only + + + B_0x0 + LP regulator is not ready. + 0x0 + + + B_0x1 + LP regulator is ready. + 0x1 + + + + + REGMS + REGMS: Regulator Main LDO Started +This bit provides the information whether main regulator is ready. + 9 + 1 + read-only + + + B_0x0 + Main regulator is not ready. + 0x0 + + + B_0x1 + Main regulator is ready. + 0x1 + + + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: + 4 + 2 + read-write + + + B_0x0 + BOM1 + 0x0 + + + B_0x1 + BOM2 (default) + 0x1 + + + B_0x2 + BOM3 + 0x2 + + + B_0x3 + n/a + 0x3 + + + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. + 8 + 1 + read-write + + + B_0x0 + in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. + 0x0 + + + B_0x1 + in Low Power mode, SMPS is disabled, output is floating + 0x1 + + + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. + 9 + 1 + read-write + + + B_0x0 + no effect (by default) + 0x0 + + + B_0x1 + SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 0x1 + + + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. + 10 + 1 + read-write + + + B_0x0 + No effect, SMPS is enabled. + 0x0 + + + B_0x1 + SMPS is disabled; + 0x1 + + + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode + 11 + 1 + read-write + + + B_0x0 + disable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. + 12 + 1 + read-write + + + B_0x0 + SMPS clock detection enabled (default) + 0x0 + + + B_0x1 + SMPS clock detection disabled + 0x1 + + + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0x0F07 + + + PUA + PUA[x] : Pull Up +Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port A[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRA[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port A[i] + 0x0 + + + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PDA + PDA[x]: Pull Down +Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port A[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port A[i] + 0x0 + + + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xF0FF + + + PUB + PUB[x] : Pull Up +Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port B[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRB[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port B[i] + 0x0 + + + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PDB + PDB[x]: Pull Down +Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port B[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port B[i] + 0x0 + + + + + + + CR6 + CR6 + CR6 register + 0x30 + 0x20 + read-write + 0x0000 + + + EWU12 + EWU12 Enable WakeUp line 12 (PA0) +When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit. + 0 + 1 + read-write + + + EWU13 + EWU13 Enable WakeUp line 13 (PA1) +When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit. + 1 + 1 + read-write + + + EWU14 + EWU14 Enable WakeUp line 14 (PA2) +When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit. + 2 + 1 + read-write + + + EWU15 + EWU15 Enable WakeUp line 15 (PA3) +When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit. + 3 + 1 + read-write + + + EWU16 + EWU16 Enable WakeUp line 16 (PB12) +When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit. + 4 + 1 + read-write + + + EWU17 + EWU17 Enable WakeUp line 17 (PB13) +When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit. + 5 + 1 + read-write + + + EWU18 + EWU18 Enable WakeUp line 18 (PB14) +When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit. + 6 + 1 + read-write + + + EWU19 + EWU19 Enable WakeUp line 19 (PB15) +When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit. + 7 + 1 + read-write + + + EWU20 + Enable wakeup on PB8 I/O event. + 8 + 1 + read-write + + + EWU21 + Enable wakeup on PB9 I/O event. + 9 + 1 + read-write + + + EWU22 + Enable wakeup on PB10 I/O event. + 10 + 1 + read-write + + + EWU23 + Enable wakeup on PB11 I/O event. + 11 + 1 + read-write + + + EWU24 + Enable wakeup on PA12 I/O event. + 12 + 1 + read-write + + + EWU25 + Enable wakeup on PA13 I/O event. + 13 + 1 + read-write + + + EWU26 + Enable wakeup on PA14 I/O event. + 14 + 1 + read-write + + + EWU27 + Enable wakeup on PA15 I/O event. + 15 + 1 + read-write + + + + + CR7 + CR7 + CR7 register + 0x34 + 0x20 + read-write + 0x0 + + + WUP12 + WUP12 Wake-up Line Polarity 12 (PA0) +This bit defines the polarity used for event detection on external wake-up line 12 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP13 + WUP13 Wake-up Line Polarity 13 (PA1) +This bit defines the polarity used for event detection on external wake-up line 13 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP14 + WUP14 Wake-up Line Polarity 14 (PA2) +This bit defines the polarity used for event detection on external wake-up line 14 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP15 + WUP15 Wake-up Line Polarity 15 (PA3) +This bit defines the polarity used for event detection on external wake-up line 15 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP16 + WUP16 Wake-up Line Polarity 16 (PB12) +This bit defines the polarity used for event detection on external wake-up line 16 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP17 + WUP17 Wake-up Line Polarity 17 (PB13) +This bit defines the polarity used for event detection on external wake-up line 17 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP18 + WUP18 Wake-up Line Polarity 18 (PB14) +This bit defines the polarity used for event detection on external wake-up line 18 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP19 + WUP19 Wake-up Line Polarity 19 (PB15) +This bit defines the polarity used for event detection on external wake-up line 19 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP20 + Wake-up polarity for PB8 IO event. + 8 + 1 + read-write + + + WUP21 + Wake-up polarity for PB9 IO event. + 9 + 1 + read-write + + + WUP22 + Wake-up polarity for PB10 IO event. + 10 + 1 + read-write + + + WUP23 + Wake-up polarity for PB11 IO event. + 11 + 1 + read-write + + + WUP24 + Wake-up polarity for PB12 IO event. + 12 + 1 + read-write + + + WUP25 + Wake-up polarity for PB13 IO event. + 13 + 1 + read-write + + + WUP26 + Wake-up polarity for PB14 IO event. + 14 + 1 + read-write + + + WUP27 + Wake-up polarity for PB15 IO event. + 15 + 1 + read-write + + + + + SR3 + SR3 + SR3 register + 0x38 + 0x20 + read-write + 0x0 + + + WUF12 + WUF12 WakeUp Flag 12 PA0 +This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF13 + WUF13 WakeUp Flag 13 PA1 +This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF14 + WUF14 WakeUp Flag 14 PA2 +This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF15 + WUF15 WakeUp Flag 15 PA3 +This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF16 + WUF16 WakeUp Flag 16 PB12 +This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF17 + WUF17 WakeUp Flag 17 PB13 +This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF18 + WUF18 WakeUp Flag 18 PB14 +This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF19 + PA7 I/O wake-up flag. + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF20 + PB8 I/O wake-up flag. + 8 + 1 + read-write + + + WUF21 + PB9 I/O wake-up flag. + 9 + 1 + read-write + + + WUF22 + PB10 I/O wake-up flag. + 10 + 1 + read-write + + + WUF23 + PB11 I/O wake-up flag. + 11 + 1 + read-write + + + WUF24 + PB12 I/O wake-up flag. + 12 + 1 + read-write + + + WUF25 + PB13 I/O wake-up flag. + 13 + 1 + read-write + + + WUF26 + PB14 I/O wake-up flag. + 14 + 1 + read-write + + + WUF27 + PB15 I/O wake-up flag. + 15 + 1 + read-write + + + + + IOxCFG + IOxCFG + IOxCFG register + 0x40 + 0x20 + read-write + 0x0 + + + IOCFG0 + Drive configuration for PA8. + 0 + 2 + read-write + + + IOCFG1 + Drive configuration for PA9. + 2 + 2 + read-write + + + IOCFG2 + Drive configuration for PA10. + 4 + 2 + read-write + + + IOCFG3 + Drive configuration for PA11. + 6 + 2 + read-write + + + IOCFG4 + Drive configuration for PA4. + 8 + 2 + read-write + + + IOCFG5 + Drive configuration for PA5. + 10 + 2 + read-write + + + IOCFG6 + Drive configuration for PA6. + 12 + 2 + read-write + + + IOCFG7 + Drive configuration for PA7. + 14 + 2 + read-write + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. +0: normal DEEPSTOP will be applied +1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP. + 0 + 1 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field + 9 + 1 + read-write + + + B_0x0 + System has not been in DEEPSTOP mode + 0x0 + + + B_0x1 + System has been in DEEPSTOP mode + 0x1 + + + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a Radio wake-up event (BLE activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. + 10 + 1 + read-write + + + B_0x0 + RF IP does not require attention + 0x0 + + + B_0x1 + RF IP awake and requesting system attention + 0x1 + + + + + + + + + PKA + PKA + 0x48300000 + + 0x0 + 0x1400 + registers + + + PKA + PKA interrupt + 13 + + + + PKA_CSR + PKA_CSR + PKA_CSR register + 0x00 + 0x20 + read-write + 0x00000000 + + + GO + PKA start processing command. +Writing 0 has no effect +Writing 1 starts the encryption engine + 0 + 1 + read-write + + + READY + PKA readiness status. +0: The PKA is still computing +1: The PKA is ready to start a new calculation + 1 + 1 + read-only + + + SFT_RST + PKA software reset. +Writing 0 clears the bit and releases the PKA block reset. +Writing 1 resets the PKA block. The PKA RAM content is not changed. + 7 + 1 + read-write + + + + + PKA_ISR + PKA_ISR + PKA_ISR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PROC_END + PKA process ending interrupt. When read: +0: No new event detected +1: The PKA process is ended (This bit is set to 1 when the PKA_CSR.READY bit +rises.) +When written: +To clear the pending interrupt, the user must write this bit to 1 and clear it just after by writing +0. If the write 0 does not occur, the interrupt is generated on next event towards the CPU +if enabled in PKA_IER but the flag is seen at 0 when the interrupt handler reads it in this +register (as clear action is still active). + 0 + 1 + read-write + + + RAM_ERR + RAM read / write access error interrupt. + 2 + 1 + read-write + + + ADD_ERR + AHB Address error interrupt. + 3 + 1 + read-write + + + + + PKA_IEN + PKA_IEN + PKA_IEN register + 0x08 + 0x20 + read-write + 0x00000000 + + + READY_EN + READY interrupt enable. + 0 + 1 + read-write + + + RAMERR_EN + RAM access error interrupt enable. + 2 + 1 + read-write + + + ADDERR_EN + AHB Address error interrupt enable. + 3 + 1 + read-write + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55005555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +00: No pullup, pulldown +01: Pullup +10: Pulldown +11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pullup or pulldown +00: No pullup, pulldown +01: Pullup +10: Pulldown +11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + read-write + 0x00000000 + + + BS0 + BS0: Port B set bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 7 + 1 + write-only + + + BS12 + BS12: Port B set bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit 14 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit 15 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 23 + 1 + write-only + + + BR12 + BR12: Port B reset bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit 14 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit 15 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + read-write + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + read-write + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + read-write + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + read-write + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + read-write + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + read-write + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + read-write + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + read-write + + + BR12 + BR12 Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + read-write + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + read-write + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + read-write + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be 1011 i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + SPI2 + SPI2 + 0x41003000 + + 0x0 + 0x24 + registers + + + SPI2 + SPI2 interrupt + 6 + + + + SPI2_CR1 + SPI2_CR1 + SPI2_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI2_CR2 + SPI2_CR2 + SPI2_CR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI2_SR + SPI2_SR + SPI2_SR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI2_DR + SPI2_DR + SPI2_DR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI2_CRCPR + SPI2_CRCPR + SPI2_CRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI2_RXCRCR + SPI2_RXCRCR + SPI2_RXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI2_TXCRCR + SPI2_TXCRCR + SPI2_TXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 16 + read-only + + + + + SPI2_I2SCFGR + SPI2_I2SCFGR + SPI2_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +- 0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. +- 1: The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + + + SPI2_I2SPR + SPI2_I2SPR + SPI2_I2SPR register + 0x20 + 0x20 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + SPI1 + SPI1 + 0x41002000 + + 0x0 + 0x24 + registers + + + SPI1 + SPI1 interrupt + 5 + + + + SPI1_CR1 + SPI1_CR1 + SPI1_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI1_CR2 + SPI1_CR2 + SPI1_CR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI1_SR + SPI1_SR + SPI1_SR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI1_DR + SPI1_DR + SPI1_DR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI1_CRCPR + SPI1_CRCPR + SPI1_CRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI1_RXCRCR + SPI1_RXCRCR + SPI1_RXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI1_TXCRCR + SPI1_TXCRCR + SPI1_TXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 16 + read-only + + + + + SPI1_I2SCFGR + SPI1_I2SCFGR + SPI1_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +- 0: The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. +- 1: The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + + + SPI1_I2SPR + SPI1_I2SPR + SPI1_I2SPR register + 0x20 + 0x20 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + I2C2 + I2C2 + 0x41001000 + + 0x0 + 0x2C + registers + + + I2C2 + I2C2 interrupt + 4 + + + + I2C2_CR1 + I2C2_CR1 + I2C2_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable +- 0: Peripheral disable +- 1: Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable +- 0: Transmit (TXIS) interrupt disabled +- 1: Transmit (TXIS) interrupt enabled + 1 + 1 + read-write + + + RXIE + RX Interrupt enable +- 0: Receive (RXNE) interrupt disabled +- 1: Receive (RXNE) interrupt enabled + 2 + 1 + read-write + + + ADDRIE + Address match Interrupt enable (slave only) +- 0: Address match (ADDR) interrupts disabled +- 1: Address match (ADDR) interrupts enabled + 3 + 1 + read-write + + + NACKIE + Not acknowledge received Interrupt enable +- 0: Not acknowledge (NACKF) received interrupts disabled +- 1: Not acknowledge (NACKF) received interrupts enabled + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt enable +- 0: Stop detection (STOPF) interrupt disabled +- 1: Stop detection (STOPF) interrupt enabled + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt enable +- 0: Transfer Complete interrupt disabled +- 1: Transfer Complete interrupt enabled + 6 + 1 + read-write + + + ERRIE + Error interrupts enable +- 0: Error detection interrupts disabled +- 1: Error detection interrupts enabled +Note: Any of these errors generate an interrupt: +Arbitration Loss (ARLO) +Bus Error detection (BERR) +Overrun/Underrun (OVR) +Timeout detection (TIMEOUT) +PEC error detection (PECERR) +Alert pin event detection (ALERT) + 7 + 1 + read-write + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter +will filter spikes with a length of up to DNF[3:0] * tI2CCLK +- 0000: Digital filter disabled +- 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK +- 1111: digital filter enabled and filtering capability up to15 tI2CCLK + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF +- 0: Analog noise filter enabled +- 1: Analog noise filter disabled + 12 + 1 + read-write + + + TXDMAEN + DMA transmission requests enable +- 0: DMA mode disabled for transmission +- 1: DMA mode enabled for transmission + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests enable +- 0: DMA mode disabled for reception +- 1: DMA mode enabled for reception + 15 + 1 + read-only + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. +- 0: Slave byte control disabled +- 1: Slave byte control enabled + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +- 0: Clock stretching enabled +- 1: Clock stretching disabled +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + GCEN + General call enable +- 0: General call disabled. Address 0b00000000 is NACKed. +- 1: General call enabled. Address 0b00000000 is ACKed. + 19 + 1 + read-write + + + SMBHEN + SMBus Host address enable +- 0: Host address disabled. Address 0b0001000x is NACKed. +- 1: Host address enabled. Address 0b0001000x is ACKed. + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address enable +- 0: Device default address disabled. Address 0b1100001x is NACKed. +- 1: Device default address enabled. Address 0b1100001x is ACKed. + 21 + 1 + read-write + + + ALERTEN + SMBus alert enable +Device mode (SMBHEN=0): +- 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. +- 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. +Host mode (SMBHEN=1): +- 0: SMBus Alert pin (SMBA) not supported. +- 1: SMBus Alert pin (SMBA) supported. + 22 + 1 + read-write + + + PECEN + PEC enable +- 0: PEC calculation disabled +- 1: PEC calculation enabled + 23 + 1 + read-write + + + + + I2C2_CR2 + I2C2_CR2 + I2C2_CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SADD + Slave address + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +- 0: Master requests a write transfer. +- 1: Master requests a read transfer. + 10 + 1 + read-write + + + ADD10 + Ten-bit addressing mode (master mode) +- 0: The master operates in 7-bit addressing mode, +- 1: The master operates in 10-bit addressing mode + 11 + 1 + read-write + + + HEAD10R + Ten bit (10-bit) address header only read direction (master receiver mode) +- 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. +- 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 12 + 1 + read-write + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. +- 0: No Start generation. +- 1: Restart/Start generation: + If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. + Otherwise setting this bit will generate a START condition once the bus is free. + 13 + 1 + read-write + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. +In Master Mode: +- 0: No Stop generation. +- 1: Stop generation after current byte transfer. + 14 + 1 + read-write + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP +condition or an Address matched is received, or when PE=0. +- 0: an ACK is sent after current received byte. +- 1: a NACK is sent after current received byte. + 15 + 1 + read-write + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is dont care in +slave mode with SBC=0. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. +- 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). +- 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). +TCR flag is set when NBYTES data are transferred, stretching SCL low. + 24 + 1 + read-write + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +- 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. +- 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are +transferred. + 25 + 1 + read-write + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a +STOP condition or an Address matched is received, also when PE=0. +- 0: No PEC transfer. +- 1: PEC transmission/reception is requested + 26 + 1 + read-write + + + + + I2C2_OAR1 + I2C2_OAR1 + I2C2_OAR1 register + 0x08 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + read-write + + + OA1MODE + Own Address 1 10-bit mode +- 0: Own address 1 is a 7-bit address. +- 1: Own address 1 is a 10-bit address. + 10 + 1 + read-write + + + OA1EN + Own Address 1 enable +- 0: Own address 1 disabled. The received slave address OA1 is NACKed. +- 1: Own address 1 enabled. The received slave address OA1 is ACKed. + 15 + 1 + read-write + + + + + I2C2_OAR2 + I2C2_OAR2 + I2C2_OAR2 register + 0x0C + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address +bits 7:1 of address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own Address 2 masks +- 000: No mask +- 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. +- 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. +- 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. +- 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. +- 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. +- 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. +- 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 8 + 3 + read-write + + + OA2EN + Own Address 2 enable +- 0: Own address 2 disabled. The received slave address OA2 is NACKed. +- 1: Own address 2 enabled. The received slave address OA2 is ACKed. + 15 + 1 + read-write + + + + + I2C2_TIMING + I2C2_TIMING + I2C2_TIMING register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +tSCLL = (SCLL+1) x tPRESC +Note: SCLL is also used to generate tBUF and tSU:STA timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +tSCLH = (SCLH+1) x tPRESC +Note: SCLH is also used to generate tSU:STO and tHD:STA timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in +transmission mode. +tSDADEL= SDADEL x tPRESC +Note: SDADEL is used to generate tHD:DAT timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in +transmission mode. +tSCLDEL = (SCLDEL+1) x tPRESC +Note: tSCLDEL is used to generate tSU:DAT timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data +setup and hold counters and for SCL high and low level +counters +tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + read-write + + + + + I2C2_TIMEOUT + I2C2_TIMEOUT + I2C2_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A +This field is used to configure: + The SCL low timeout condition tTIMEOUT when TIDLE=0 +tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK + The bus idle condition (both SCL and SDA high) when TIDLE=1 +tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +- 0: TIMEOUTA is used to detect SCL low timeout +- 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + TIMEOUTEN + Clock timeout enable +- 0: SCL timeout detection is disabled +- 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or +high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). + 15 + 1 + read-write + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected +In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected +tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable +- 0: Extended clock timeout detection is disabled +- 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more +than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 31 + 1 + read-write + + + + + I2C2_ISR + I2C2_ISR + I2C2_ISR register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). +Note: This bit is cleared by hardware when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: + either as a master, provided that the STOP condition is generated by the peripheral. + or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE=0. +This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR=1). +- 0: Write transfer, slave enters receiver mode. +- 1: Read transfer, slave enters transmitter mode. + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C2_ICR + I2C2_ICR + I2C2_ICR register + 0x1C + 0x20 + read-write + 0x00000000 + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears +the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the ACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + Stop detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration Lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C2_PECR + I2C2_PECR + I2C2_PECR register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE=0. + 0 + 8 + read-only + + + + + I2C2_RXDR + I2C2_RXDR + I2C2_RXDR register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + Eight bit (8-bit) receive data +Data byte received from the I2C bus. + 0 + 8 + read-only + + + + + I2C2_TXDR + I2C2_TXDR + I2C2_TXDR register + 0x28 + 0x20 + read-write + + + TXDATA + Eight bits (8-bit) transmit data +Data byte to be transmitted to the I2C bus. +Note: These bits can be written only when TXE=1. + 0 + 8 + read-write + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. + 0: AM or 24-hour format + 1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-only + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-only + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-only + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-only + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. + 16 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds dont care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes dont care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours dont care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is dont care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day dont care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescalers counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. +Note: CALM[0] is stucked at 0 when CALW16=1. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1 , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at 00 when CALW8=1. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. + 15 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescalers counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKP0R register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKP1R register + 0x54 + 0x20 + read-write + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. + 000: divider/4 + 001: divider/8 + 010: divider/16 + 011: divider/32 + 100: divider/64 + 101: divider/128 + 110: divider/256 + 111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic window = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + TIM1 + TIM1 + 0x40002000 + + 0x0 + 0x68 + registers + + + TIM1 + TIM1 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIFREMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + Capture/compare preloaded control. + 0 + 1 + read-write + + + CCUS + Capture/compare control update selection. + 2 + 1 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + OIS1 + Output idle state 1 (OC1 output). + 8 + 1 + read-write + + + OIS1N + Output idle state 1 (OC1N output). + 9 + 1 + read-write + + + OIS2 + Output idle state 2 (OC2 output). Refer to OIS1 bit. + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (OC2N output). Refer to OIS1N bit. + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (OC3 output). Refer to OIS1 bit. + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (OC3N output). Refer to OIS1N bit. + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (OC4 output). +Refer to OIS1 bit. + 14 + 1 + read-write + + + OIS5 + Output idle state 5 (OC5 output). Refer to OIS1 bit. + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (OC6 output). Refer to OIS1 bit. + 18 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS + TS[2:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +101: Filtered Timer Input 1 (TI1FP1) + +110: Filtered Timer Input 2 (TI2FP2) + +others: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection - bit 3 + +Refer to SMS description - bits2:0 + 16 + 1 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + BIE + Break interrupt enable. + 7 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + COMIF + COM interrupt flag. + 5 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + BIF + Break interrupt flag. + 7 + 1 + read-write + + + B2IF + Break 2 interrupt flag. + 8 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + CC5IF + Compare 5 interrupt flag. + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag. + 17 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + COMG + Capture/compare control update generation. + 5 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + BG + Break generation. + 7 + 1 + write-only + + + B2G + Break 2 generation. + 8 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as + +TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. . + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NE + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable. Refer to CC1NE description. + 6 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable. Refer to CC1NE description. + 10 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable. Refer to CC1NE description. + 14 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable. Refer to CC1E description. + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity. Refer to CC1P description. + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable. Refer to CC1E description. + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity. Refer to CC1P description. + 21 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIFCPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 16 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + Deadtime generator setup. + 0 + 8 + read-write + + + LOCK + Lock configuration. + 8 + 2 + read-write + + + OSSI + Off-state selection for Idle mode. + 10 + 1 + read-write + + + OSSR + Off-state selection for Run mode. + 11 + 1 + read-write + + + BKE + Break enable. + 12 + 1 + read-write + + + BKP + Break polarity. + 13 + 1 + read-write + + + AOE + Automatic output enable. + 14 + 1 + read-write + + + MOE + Main output enable. + 15 + 1 + read-write + + + BKF + Break filter. + 16 + 4 + read-write + + + BK2F + Break 2 filter. + 20 + 4 + read-write + + + BK2E + Break 2 enable. + 24 + 1 + read-write + + + BK2P + Break 2 polarity. + 25 + 1 + read-write + + + + + CCMR3 + CCMR3 + CCMR3 register + 0x54 + 0x20 + read-write + 0x0 + 0xF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable. + 3 + 1 + read-write + + + OC5M_2_0 + Output compare 5 mode. + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable. + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable. + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable. + 11 + 1 + read-write + + + OC6M_2_0 + Output compare 6 mode. + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable. + 15 + 1 + read-write + + + OC5M_3 + Output compare 5 mode - bit 3. + 16 + 1 + read-write + + + OC6M_3 + Output compare 6 mode - bit 3. + 24 + 1 + read-write + + + + + CCMR3_in + CCMR3_in + CCMR3 + 0x54 + 0x20 + read-write + 0x0 + 0xF + + + IC5PSC + IC5PSC: Input capture 1 prescaler + 2 + 2 + read-write + + + IC5F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + 4 + 4 + read-write + + + IC6PSC + IC6PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC6F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCR5 + CCR5 + CCR5 register + 0x58 + 0x20 + read-write + 0x0 + 0xF + + + CCR5 + Capture/compare 5 value + 0 + 16 + read-write + + + GC5C1 + Group channel 5 and channel 1 distortion on channel 1 output: +0: No effect of OC5REF on OC1REFC5 +1: OC1REFC is the logical AND of OC1REFC and OC5REF +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload +feature is selected in TIMxCCMR1). +Note: It is also possible to apply this distortion on combined PWM signals. + 29 + 1 + read-write + + + GC5C2 + Group channel 5 and channel 2 distortion on channel 2 output: +0: No effect of OC5REF on OC2REFC +1: OC2REFC is the logical AND of OC2REFC and OC5REF +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload +feature is selected in TIMxCCMR1). +Note: It is also possible to apply this distortion on combined PWM signals. + 30 + 1 + read-write + + + GC5C3 + Group channel 5 and channel 3 distortion on channel 3 output: +0: No effect of OC5REF on OC3REFC +1: OC3REFC is the logical AND of OC3REFC and OC5REF +This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload +feature is selected in TIMxCCMR2). +Note: It is also possible to apply this distortion on combined PWM signals. + 31 + 1 + read-write + + + + + CCR6 + CCR6 + CCR6 register + 0x5C + 0x20 + read-write + 0x0 + 0xF + + + CCR6 + Capture/compare 6 value + 0 + 16 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x0001 + 0xF + + + BKINE + BRK BKIN input enable + 0 + 1 + read-write + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + read-write + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + read-write + + + BKINP + BRK BKIN input polarity + 9 + 1 + read-write + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + read-write + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + read-write + + + + + AF2 + AF2 + AF2 register + 0x64 + 0x20 + read-write + 0x0001 + 0xF + + + BK2INE + BRK2 BKIN input enable. + 0 + 1 + read-write + + + BK2CMP1E + BRK2 COMP1 enable. + 1 + 1 + read-write + + + BK2CMP2E + BRK2 COMP2 enable. + 2 + 1 + read-write + + + BK2INP + BRK2 BKIN2 input polarity + 9 + 1 + read-write + + + BK2CMP1P + BRK2 COMP1 input polarity. + 10 + 1 + read-write + + + BK2CMP2P + BRK2 COMP2 input polarity. + 11 + 1 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x40 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x0201E041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. + 0: PA0 pin operated in standard mode. + 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. + 0: PA1 pin operated in standard mode. + 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. + 0: PB6 pin operated in standard mode. + 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. + 0: PB7 pin operated in standard mode. + 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA4_DT + PA4_DT:Interrupt Detection Type for port A I/Os. + 4 + 1 + read-write + + + PA5_DT + PA5_DT:Interrupt Detection Type for port A I/Os. + 5 + 1 + read-write + + + PA6_DT + PA6_DT:Interrupt Detection Type for port A I/Os. + 6 + 1 + read-write + + + PA7_DT + PA7_DT:Interrupt Detection Type for port A I/Os. + 7 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. + 0: edge detection. + 1: level detection. + 11 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 23 + 1 + read-write + + + PB8_DT + PB8_DT:Interrupt Detection Type for port B I/Os. + 24 + 1 + read-write + + + PB9_DT + PB9_DT:Interrupt Detection Type for port B I/Os. + 25 + 1 + read-write + + + PB10_DT + PB10_DT:Interrupt Detection Type for port B I/Os. + 26 + 1 + read-write + + + PB11_DT + PB11_DT:Interrupt Detection Type for port B I/Os. + 27 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. + 0: edge detection. + 1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 3 + 1 + read-write + + + PA4_IBE + PA4_IBE: Interrupt edge selection for Port A I/Os. + 4 + 1 + read-write + + + PA5_IBE + PA5_IBE: Interrupt edge selection for Port A I/Os. + 5 + 1 + read-write + + + PA6_IBE + PA6_IBE: Interrupt edge selection for Port A I/Os. + 6 + 1 + read-write + + + PA7_IBE + PA7_IBE: Interrupt edge selection for Port A I/Os. + 7 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. + 0: single edge detection. + 1: both edges detection + 11 + 1 + read-write + + + PA12_IBE + PA12_IBE: Interrupt edge selection for Port A I/Os. + 12 + 1 + read-write + + + PA13_IBE + PA13_IBE: Interrupt edge selection for Port A I/Os. + 13 + 1 + read-write + + + PA14_IBE + PA14_IBE: Interrupt edge selection for Port A I/Os. + 14 + 1 + read-write + + + PA15_IBE + PA15_IBE: Interrupt edge selection for Port A I/Os. + 15 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. + 23 + 1 + read-write + + + PB8_IBE + PB8_IBE: Interrupt edge selection for port B I/Os. + 24 + 1 + read-write + + + PB9_IBE + PB9_IBE: Interrupt edge selection for port B I/Os. + 25 + 1 + read-write + + + PB10_IBE + PB10_IBE: Interrupt edge selection for port B I/Os. + 26 + 1 + read-write + + + PB11_IBE + PB11_IBE: Interrupt edge selection for port B I/Os. + 27 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. + 1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 3 + 1 + read-write + + + PA4_IEV + PA4_IEV : Interrupt polarity event for Port A I/Os. + 4 + 1 + read-write + + + PA5_IEV + PA5_IEV : Interrupt polarity event for Port A I/Os. + 5 + 1 + read-write + + + PA6_IEV + PA6_IEV : Interrupt polarity event for Port A I/Os. + 6 + 1 + read-write + + + PA7_IEV + PA7_IEV : Interrupt polarity event for Port A I/Os. + 7 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 11 + 1 + read-write + + + PA12_IEV + PA12_IEV : Interrupt polarity event for Port A I/Os. + 12 + 1 + read-write + + + PA13_IEV + PA13_IEV : Interrupt polarity event for Port A I/Os. + 13 + 1 + read-write + + + PA14_IEV + PA14_IEV : Interrupt polarity event for Port A I/Os. + 14 + 1 + read-write + + + PA15_IEV + PA15_IEV : Interrupt polarity event for Port A I/Os. + 15 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 23 + 1 + read-write + + + PB8_IEV + PB8_IEV : Interrupt polarity event for Port B I/Os. + 24 + 1 + read-write + + + PB9_IEV + PB9_IEV : Interrupt polarity event for Port B I/Os. + 25 + 1 + read-write + + + PB10_IEV + PB10_IEV : Interrupt polarity event for Port B I/Os. + 26 + 1 + read-write + + + PB11_IEV + PB11_IEV : Interrupt polarity event for Port B I/Os. + 27 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. + 0: falling edge / low level. + 1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 3 + 1 + read-write + + + PA4_IE + PA4_IE: Interrupt enable for port A I/Os. + 4 + 1 + read-write + + + PA5_IE + PA5_IE: Interrupt enable for port A I/Os. + 5 + 1 + read-write + + + PA6_IE + PA6_IE: Interrupt enable for port A I/Os. + 6 + 1 + read-write + + + PA7_IE + PA7_IE: Interrupt enable for port A I/Os. + 7 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 11 + 1 + read-write + + + PA12_IE + PA12_IE: Interrupt enable for port A I/Os. + 12 + 1 + read-write + + + PA13_IE + PA13_IE: Interrupt enable for port A I/Os. + 13 + 1 + read-write + + + PA14_IE + PA14_IE: Interrupt enable for port A I/Os. + 14 + 1 + read-write + + + PA15_IE + PA15_IE: Interrupt enable for port A I/Os. + 15 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 23 + 1 + read-write + + + PB8_IE + PB8_IE: Interrupt enable for port B I/Os. + 24 + 1 + read-write + + + PB9_IE + PB9_IE: Interrupt enable for port B I/Os. + 25 + 1 + read-write + + + PB10_IE + PB10_IE: Interrupt enable for port B I/Os. + 26 + 1 + read-write + + + PB11_IE + PB11_IE: Interrupt enable for port B I/Os. + 27 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. + 1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA4_ISC + PA4_ISC: Interrupt status (before mask) for port a I/Os.. + 4 + 1 + read-write + + + PA5_ISC + PA5_ISC: Interrupt status (before mask) for port a I/Os.. + 5 + 1 + read-write + + + PA6_ISC + PA6_ISC: Interrupt status (before mask) for port a I/Os.. + 6 + 1 + read-write + + + PA7_ISC + PA7_ISC: Interrupt status (before mask) for port a I/Os.. + 7 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PA12_ISC + PA12_ISC: Interrupt status (before mask) for port a I/Os. + 12 + 1 + read-write + + + PA13_ISC + PA13_ISC: Interrupt status (before mask) for port a I/Os. + 13 + 1 + read-write + + + PA14_ISC + PA14_ISC: Interrupt status (before mask) for port a I/Os. + 14 + 1 + read-write + + + PA15_ISC + PA15_ISC: Interrupt status (before mask) for port a I/Os. + 15 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB8_ISC + PB8_ISC: Interrupt status (before mask) for port B I/Os.. + 24 + 1 + read-write + + + PB9_ISC + PB9_ISC: Interrupt status (before mask) for port B I/Os.. + 25 + 1 + read-write + + + PB10_ISC + PB10_ISC: Interrupt status (before mask) for port B I/Os.. + 26 + 1 + read-write + + + PB11_ISC + PB11_ISC: Interrupt status (before mask) for port B I/Os.. + 27 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. + 0: no pending interrupt. + 1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. + 0: PVD interrupt is disabled. + 1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. + 0: Interrupt on wakeup event seen by the PWRC is disabled. + 1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. + 0: no pending interrupt. + 1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. + 0: no pending interrupt. + 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + BLERXTX_DTR + BLERXTX_DTR + BLERXTX_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: + 0: detection on edge (default). + 1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: + 0: detection on edge (default). + 1: detection on level + 1 + 1 + read-write + + + + + BLERXTX_IBER + BLERXTX_IBER + BLERXTX_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: + 0: detection on single edge (default). + 1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: + 0: detection on single edge (default). + 1: detection on both edges + 1 + 1 + read-write + + + + + BLERXTX_IEVR + BLERXTX_IEVR + BLERXTX_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: + 0: detection on falling edge / low level (default). + 1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: + 0: detection on falling edge / low level (default). + 1: detection on rising edge / high level + 1 + 1 + read-write + + + + + BLERXTX_IER + BLERXTX_IER + BLERXTX_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: + 0: TX_SEQUENCE interrupt is disabled (default). + 1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: + 0: RX_SEQUENCE interrupt is disabled (default). + 1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + + + BLERXTX_ISCR + BLERXTX_ISCR + BLERXTX_ISCR register + 0x3C + 8 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): + 0: no activity on TX_SEQUENCE detected. + 1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): + 0: no activity on RX_SEQUENCE detected. + 1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + + + + + diff --git a/svd/STM32WBxx/STM32WB09.svd b/svd/STM32WBxx/STM32WB09.svd new file mode 100644 index 0000000..e4cb467 --- /dev/null +++ b/svd/STM32WBxx/STM32WB09.svd @@ -0,0 +1,28875 @@ + + + + STM32WB09 + 0.4 + STM32WB09 + + CM0+ + r0p0 + little + true + false + 2 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC + 0x41006000 + + 0x0 + 0x68 + registers + + + ADC + ADC interrupt + 12 + + + + VERSION_ID + VERSION_ID + VERSION_ID register + 0x00 + 0x20 + read-only + 0x30 + 0xFF + + + VERSION_ID + VERSION_ID[7:0]: version of the embedded IP. + 0 + 8 + read-only + + + + + CONF + CONF + CONF register + 0x04 + 0x20 + read-write + 0x20002 + 0xFFFFF + + + CONT + CONT: regular sequence runs continuously when ADC mode is enabled: + +0: enable the single conversion: when the sequence is over, the conversion stops + +1: enable the continuous conversion: when the sequence is over, the sequence starts again + +until the software sets the CTRL.STOP_OP_MODE bit. + 0 + 1 + read-write + + + SEQUENCE + SEQUENCE: enable the sequence mode (active by default): + +0: sequence mode is disabled, only SEQ0 is selected + +1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN + +Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can + +be kept high as redundant with keeping high and setting SEQ_LEN=0000. + 1 + 1 + read-write + + + SEQ_LEN + SEQ_LEN[3:0]: number of conversions in a regular sequence: + +0000: 1 conversion, starting from SEQ0 + +0001: 2 conversions, starting from SEQ0 + +... + +1111: 16 conversions, starting from SEQ0 + 2 + 4 + read-write + + + SMPS_SYNCHRO_ENA + SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the + +SMPS: + +0: SMPS synchronization is disabled for all ADC clock frequencies + +1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) + +Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when + +PWRC_CR5.NOSMPS = 1. + 6 + 1 + read-write + + + SAMPLE_RATE_LSB + SAMPLE_RATE_LSB: Sample Rate LSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. + +When this field is set to a value different than 0, SMPS synchronization is not feasible. + +This value is hidden to the user + 9 + 2 + read-write + + + SAMPLE_RATE + SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): + +F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where + +F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency. + 11 + 2 + read-write + + + DMA_DS_ENA + DMA_DS_EN: enable the DMA mode for the Down Sampler data path: + +0: DMA mode is disabled + +1: DMA mode is enabled + 13 + 1 + read-write + + + OVR_DS_CFG + OVR_DS_CFG: Down Sampler overrun configuration: + +0: the previous data is kept, the new one is lost + +1: the previous data is lost, the new one is kept + 15 + 1 + read-write + + + BIT_INVERT_SN + BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single + +negative input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 17 + 1 + read-write + + + BIT_INVERT_DIFF + BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential + +input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 18 + 1 + read-write + + + ADC_CONT_1V2 + ADC_CONT_1V2: select the input sampling method: + +0: sampling only at conversion start (default) + +1: sampling starts at the end of conversion + 19 + 1 + read-write + + + SAMPLE_RATE_MSB + SAMPLE_RATE_MSB: Sample Rate MSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description + 21 + 3 + read-write + + + + + CTRL + CTRL + CTRL register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + ADC_ON_OFF + ADC_ON_OFF: + +0: power off the ADC + +1: power on the ADC + 0 + 1 + read-write + + + START_CONV + START_CONV (1): generate a start pulse to initiate an ADC conversion: + +0: no effect + +1: start the ADC conversion + +Note: this bit is set by software and cleared by hardware. + 1 + 1 + write-only + + + STOP_OP_MODE + STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full + +mode): + +0: no effect + +1: stop on-going ADC mode + +Note: this bit is set by software and cleared by hardware. + +When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit. + 2 + 1 + write-only + + + TEST_MODE + TEST_MODE: select the functional or the test mode of the ADC: + +0: functional mode (one of the four main functional modes is used) + +1: test mode (for debug, test, calibration) + 4 + 1 + read-write + + + ADC_LDO_ENA + ADC_LDO_ENA: enable the LDO associated to the ADC block: + +0: disable the ADC LDO + +1: enable the ADC LDO + 5 + 1 + read-write + + + + + SWITCH + SWITCH + SWITCH register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + SE_VIN_0 + SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 0 + 2 + read-write + + + SE_VIN_1 + SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 2 + 2 + read-write + + + SE_VIN_2 + SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 4 + 2 + read-write + + + SE_VIN_3 + SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 6 + 2 + read-write + + + SE_VIN_4 + SE_VIN_4[1:0]: input voltage for VINP[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 8 + 2 + read-write + + + SE_VIN_5 + SE_VIN_5[1:0]: input voltage for VINP[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 10 + 2 + read-write + + + SE_VIN_6 + SE_VIN_6[1:0]: input voltage for VINP[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 12 + 2 + read-write + + + SE_VIN_7 + SE_VIN_7[1:0]: input voltage for VINP[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 14 + 2 + read-write + + + + + DS_CONF + DS_CONF + DS_CONF register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DS_RATIO + DS_RATIO[2:0]: program the Down Sampler ratio (N factor) + +000: ratio = 1, no down sampling (default) + +001: ratio = 2 + +010: ratio = 4 + +011: ratio = 8 + +100: ratio = 16 + +101: ratio = 32 + +110: ratio = 64 + +111: ratio = 128 + 0 + 3 + read-write + + + DS_WIDTH + DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) + +000: DS_DATA output on 12-bit (default) + +001: DS_DATA output on 13-bit + +010: DS_DATA output on 14-bit + +011: DS_DATA output on 15-bit + +100: DS_DATA output on 16-bit + +1xx: reserved + 3 + 3 + read-write + + + + + SEQ_1 + SEQ_1 + SEQ_1 register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + SEQ0 + SEQ0[3:0]: channel number code for first conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ1 + SEQ1[3:0]: channel number code for second conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ2 + SEQ2[3:0]: channel number code for 3rd conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ3 + SEQ3[3:0]: channel number code for 4th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ4 + SEQ4[3:0]: channel number code for 5th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ5 + SEQ5[3:0]: channel number code for 6th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ6 + SEQ6[3:0]: channel number code for 7th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ7 + SEQ7[3:0]: channel number code for 8th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + SEQ_2 + SEQ_2 + SEQ_2 register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + SEQ8 + SEQ8[3:0]: channel number code for 9th conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ9 + SEQ9[3:0]: channel number code for 10th conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ10 + SEQ10[3:0]: channel number code for 11th conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ11 + SEQ11[3:0]: channel number code for 12th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ12 + SEQ12[3:0]: channel number code for 13th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ13 + SEQ13[3:0]: channel number code for 14th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ14 + SEQ14[3:0]: channel number code for 15th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ15 + SEQ15[3:0]: channel number code for 16th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + COMP_1 + COMP_1 + COMP_1 register + 0x28 + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN1 + GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET1 + OFFSET1[7:0]: first calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_2 + COMP_2 + COMP_2 register + 0x2C + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN2 + GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET2 + OFFSET2[7:0]: second calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_3 + COMP_3 + COMP_3 register + 0x30 + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN3 + GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET3 + OFFSET3[7:0]: third calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_4 + COMP_4 + COMP_4 register + 0x34 + 0x20 + read-write + 0x555 + 0xFFF + + + GAIN4 + GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET4 + OFFSET4[7:0]: fourth calibration point: offset compensation[7:0] with sign + 12 + 8 + read-write + + + + + COMP_SEL + COMP_SEL + COMP_SEL register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + OFFSET_GAIN0 + OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 0 + 2 + read-write + + + OFFSET_GAIN1 + OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 2 + 2 + read-write + + + OFFSET_GAIN2 + OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 4 + 2 + read-write + + + OFFSET_GAIN3 + OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 6 + 2 + read-write + + + OFFSET_GAIN4 + OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 8 + 2 + read-write + + + OFFSET_GAIN5 + OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 10 + 2 + read-write + + + OFFSET_GAIN6 + OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 12 + 2 + read-write + + + OFFSET_GAIN7 + OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 14 + 2 + read-write + + + OFFSET_GAIN8 + OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 16 + 2 + read-write + + + + + WD_TH + WD_TH + WD_TH register + 0x3C + 0x20 + read-write + 0xFFF0000 + 0xFFFFFFF + + + WD_LT + WD_LT[11:0]: analog watchdog low level threshold. + 0 + 12 + read-write + + + WD_HT + WD_HT[11:0]: analog watchdog high level threshold. + 16 + 12 + read-write + + + + + WD_CONF + WD_CONF + WD_CONF register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + AWD_CHX + AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need + +to be guarded by the watchdog. + +Bit0: VINM[0] to ADC negative input + +Bit1: VINM[1] to ADC negative input + +Bit2: VINM[2] to ADC negative input + +Bit3: VINM[3] to ADC negative input + +Bit4: Not used + +Bit5: VBAT to ADC negative input + +Bit6: GND to ADC negative input + +Bit7: VDDA to ADC negative input + +Bit8: VINP[0] to ADC positive input + +Bit9: VINP[1] to ADC positive input + +Bit10: VINP[2] to ADC positive input + +Bit11: VINP[3] to ADC positive input + +Bit12: Not used + +Bit13: TEMP to ADC positive input + +Bit14: GND to ADC positive input + +Bit15: VDDA to ADC positive input + 0 + 16 + read-write + + + + + DS_DATAOUT + DS_DATAOUT + DS_DATAOUT register + 0x44 + 0x20 + read-only + 0x0 + 0xF + + + DS_DATA + DS_DATA[15:0]: contain the converted data at the output of the Down Sampler. + 0 + 16 + read-only + + + + + IRQ_STATUS + IRQ_STATUS + IRQ_STATUS register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + + + CRC + CRC address block description + CRC + 0x48200000 + + 0x0 + 0x400 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits +This register is used to write new data to the CRC calculator. +It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits +These bits can be used as a temporary storage location for four bytes. +This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data +This bitfield controls the reversal of the bit order of the input data + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. + 0 + 32 + read-write + + + + + + + DMA + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + + + GIF1 + GIF1: Channel 1 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 1 +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 1 +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 1 +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TEIF1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 1 +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 2 +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 2 +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 2 +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TEIF2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 2 +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 3 +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 3 +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 3 +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TEIF3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 3 +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 4 +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 4 +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 4 +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TEIF4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 4 +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 5 +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 5 +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 5 +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TEIF5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 5 +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 6 +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 6 +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 6 +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 6 +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 7 +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 7 +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 7 +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 7 +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No TE, HT or TC event on channel 8 +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer complete (TC) event on channel 8 +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No half transfer (HT) event on channel 8 +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. +0: No transfer error (TE) on channel 8 +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + + + CGIF1 + CGIF1: Channel 1 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear +This bit is set and cleared by software. +0: No effect +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear +This bit is set and cleared by software. +0: No effect +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + + + EN + EN: Channel enable +This bit is set and cleared by software. +0: Channel disabled +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable +This bit is set and cleared by software. +0: TC interrupt disabled +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable +This bit is set and cleared by software. +0: HT interrupt disabled +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable +This bit is set and cleared by software. +0: TE interrupt disabled +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction +This bit is set and cleared by software. +0: Read from peripheral +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode +This bit is set and cleared by software. +0: Circular mode disabled +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode +This bit is set and cleared by software. +0: Peripheral increment mode disabled +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode +This bit is set and cleared by software. +0: Memory increment mode disabled +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size +These bits are set and cleared by software. +00: 8-bits +01: 16-bits +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level +These bits are set and cleared by software. +00: Low +01: Medium +10: High +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode +This bit is set and cleared by software. +0: Memory to memory mode disabled +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + + + NDT + NDT[15:0]: Number of data to transfer +Number of data to be transferred (0 up to 65535). This register can only be written when the +channel is disabled. Once the channel is enabled, this register is read-only, indicating the +remaining bytes to be transmitted. This register decrements after each DMA transfer. +Once the transfer is completed, this register can either stay at zero or be reloaded +automatically by the value previously programmed if the channel is configured in auto-reload +mode. +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + + + PA + PA[31:0]: Peripheral address +Base address of the peripheral data register from/to which the data will be read/written. +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + + + MA + MA[31:0]: Memory address +Base address of the memory area from/to which the data will be read/written. +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword +address. +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word +address. + 0 + 32 + read-write + + + + + + + DMAMUX + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + GPIOA + GPIOA + 0x48000000 + + 0x0 + 0x2C + registers + + + GPIOA + GPIOA interrupt + 15 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x000000A0 + + + MODE0 + MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE8 + MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT8 + OT8: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000030 + + + OSPEED0 + OSPEED0[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x00550095 + + + PUPD0 + PUPD0: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD8 + PUPD8: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID8 + ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port A output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port A output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port A output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port A output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD8 + OD8: Port A output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port A output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port A output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port A output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + read-write + 0x00000000 + + + BS0 + BS0: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 3 + 1 + write-only + + + BS8 + BS8: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 8 + 1 + write-only + + + BS9 + BS9: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 9 + 1 + write-only + + + BS10 + BS10: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 10 + 1 + write-only + + + BS11 + BS11: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 11 + 1 + write-only + + + BR0 + BR0: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR8 + BR8: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port A lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port A lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port A lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port A lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK8 + LCK8: Port A lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port A lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port A lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port A lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1' + LCKR[15:0] +WR LCKR[16] = 0' + LCKR[15:0] +WR LCKR[16] = 1' + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1' until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR8 + BR8: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55005555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + read-write + 0x00000000 + + + BS0 + BS0: Port B set bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 7 + 1 + write-only + + + BS12 + BS12: Port B set bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit 14 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit 15 +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Sets the corresponding ODx bit + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit 0 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit 1 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit 2 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit 3 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit 4 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit 5 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit 6 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit 7 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 23 + 1 + write-only + + + BR12 + BR12: Port B reset bit 12 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit 13 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit 14 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit 15 These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1' + LCKR[15:0] +WR LCKR[16] = 0' + LCKR[15:0] +WR LCKR[16] = 1' + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1' (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1' until the next MCU reset or peripheral reset. + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL12 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + read-write + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + read-write + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + read-write + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + read-write + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + read-write + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + read-write + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + read-write + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + read-write + + + BR12 + BR12 Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + read-write + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + read-write + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + read-write + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + read-write + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. +000: divider/4 +001: divider/8 +010: divider/16 +011: divider/32 +100: divider/64 +101: divider/128 +110: divider/256 +111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic 'window' = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART_1 + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + UESM + UESM: LPUART enable in Stop mode +When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. +When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that +the LPUART clock selection is LSE in the RCC. +This bit is set and cleared by software. +-0: LPUART not able to wake up the MCU from Stop mode. +-1: LPUART able to wake up the MCU from Stop mode. When this function is active, the +clock source for the LPUART must be LSE (see RCC chapter) + 1 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + WUS + WUS[1:0]: Wakeup from Stop mode interrupt flag selection +This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). +-00: WUF active on address match (as defined by ADD[7:0] and ADDM7) +-01:Reserved. +-10: WUF active on Start bit detection +-11: WUF active on RXNE. +This bit field can only be written when the LPUART is disabled (UE=0). + 20 + 2 + read-write + + + WUFIE + WUFIE: Wakeup from Stop mode interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register + 22 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0' +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + WUF + WUF: Wakeup from Stop mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the +WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register + 20 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesn't reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesn't reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x200 + registers + + + FLASH + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +0x11 : ERASE +0x22 : MASSERASE +0x33 : WRITE +0x44 : MASSWRITE +0x55 : MASSREAD +0x66 : IFRERASE +0x77 : IFRWRITE +0x88 : IFRMASSWRITE +0x99 : IFRMASSREAD +0xAA : SLEEP +0xBB : WAKEUP +0xCC : BURSTWRITE +0xDD : IFRBURSTWRITE +0xEE : OTPWRITE +0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + LONGACCESS + Additional wait-state for flash read access: +0 : no latency added +1 : 1 clock cycle latency added + 0 + 1 + read-write + + + REMAP + CPU access routing (it supersedes PREMAP configuration): +0 : FLASH memory addressed +1 : SRAM0 memory addressed + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +0 : burst write allowed +1 : burst write forbidden + 2 + 1 + read-write + + + PREMAP + CPU access routing (it can only be set; reset only allowed by POR/PAD reset) +0 : IFR memory addressed +1 : MAIN flash memory addressed + 3 + 1 + read-write + + + WAIT_STATE + Add latency to flash read opeations: +00 : no latency +01 : 1 clock cycle latency +10 : 2 clock cycles latency +11 : 3 clock cycles latency + 4 + 2 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + (1: clear, 0: inactive) CMDDONE_MIS flag + 0 + 1 + read-write + + + CMDSTART_MIS + (1: clear, 0: inactive) CMDSTART_MIS flag + 1 + 1 + read-write + + + CMDBUSYERR_MIS + (1: clear, 0: inactive) CMDBUSYERR_MIS flag + 2 + 1 + read-write + + + ILLCMD_MIS + (1: clear, 0: inactive) ILLCMD_MIS flag + 3 + 1 + read-write + + + READOK_MIS + (1: clear, 0: inactive) READOK_MIS flag + 4 + 1 + read-write + + + FNREADY_MIS + (1: clear, 0: inactive) FNREADY_MIS flag + 5 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + (1: mask, 0: inactive) CMDDONE_MIS mask + 0 + 1 + read-write + + + CMDSTARTM + (1: mask, 0: inactive) CMDSTART_MIS mask + 1 + 1 + read-write + + + CMDBUSYERRM + (1: mask, 0: inactive) CMDBUSYERR_MIS mask + 2 + 1 + read-write + + + ILLCMDM + (1: mask, 0: inactive) ILLCMD_MIS mask + 3 + 1 + read-write + + + READOKM + (1: mask, 0: inactive) READOK_MIS mask + 4 + 1 + read-write + + + FNREADYM + (1: mask, 0: inactive) FNREADY_MIS mask + 5 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + (1: active, 0: inactive) COMMAND sequence ended + 0 + 1 + read-write + + + CMDSTART_RIS + (1: active, 0: inactive) COMMAND sequence started + 1 + 1 + read-write + + + CMDBUSYERR_RIS + (1: active, 0: inactive) COMMAND issued while flash busy + 2 + 1 + read-write + + + ILLCMD_RIS + (1: active, 0: inactive) Illegal command issued + 3 + 1 + read-write + + + READOK_RIS + (1: active, 0: inactive) READ COMMAND completed successfully + 4 + 1 + read-write + + + CMDSLEEPERR_RIS + (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1) + 5 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0006BFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +00 : 0x03FFF (64kb) +01 : 0x07FFF (128kb) +10 : 0x09FFF (160kb) +11 : 0x0BFFF (192kb) + 0 + 17 + read-only + + + RAM_SIZE + RAM memory size selection: +0 : 16kb +1 : 32kb + 17 + 1 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + JTAG_DISABLE + Flash+JTAG protection (0: no JTAG protection see FLASH_SECURE, 1: Flash and JTAG protected) + 20 + 1 + read-only + + + PACKAGE_SIZE + Package selection: +0: CSP +10 : 32pins +11 : 48pins + 21 + 2 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEGSIZE0 + First segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET0 + First segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE1 + Second segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET1 + Second segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEGSIZE2 + Third segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET2 + Third segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE3 + Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET3 + Fourth segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + + + PKA + PKA + 0x48300000 + + 0x0 + 0x1400 + registers + + + PKA + PKA interrupt + 13 + + + + PKA_CR + PKA_CR + PKA_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + EN + Peripheral enable. +0 : Disable PKA. +1 : Enable PKA. + 0 + 1 + read-write + + + START + Start the operation +0: No operation +1: Writing '1' to this bit starts the operation which is selected by MODE[5:0], using the operands and data +already written to the PKA RAM. This bit is always read as '0'. +Nota: START is ignored if PKA is busy. + 1 + 1 + read-write + + + SECLVL + Security enable. +0: No side channel countermeasure +1: Square and Multiply always / Double and Add always + 2 + 1 + read-write + + + MODE + PKA operation code +000000 : Compute Montgomery parameter and modular exponentiation +000001 : Compute Montgomery parameter +000010 : Compute modular exponentiation only (Montgomery parameter should be loaded) +100000 : Compute Montgomery parameter and compute ECC kP operation +100010 : Compute the ECC kP primitive only (Montgomery parameter should be loaded) +100100 : ECDSA sign +100110 : ECDSA Verification +101000 : Point Check +000111 : RSA CRT exponentiation +001000 : Modular inversion +001001 : Arithmetic addition +001010 : Arithmetic Subtraction +001011 : Arithmetic multiplication +001100 : Comparison +001101 : Modular Reduction +001110 : Modular Addition +001111 : Modular Subtraction +010000 : Montgomery Multiplication + 8 + 6 + read-write + + + PROCENDIE + End of operation interrupt enable +0: Interrupt is disabled. +1: An interrupt is generated when PROCENDF (PKA_SR[17]) is set. + 17 + 1 + read-write + + + RAMERRIE + RAM error interrupt enable +0: Interrupt is disabled. +1: An interrupt is generated when RAMERRF (PKA_SR[19]) is set. + 19 + 1 + read-write + + + ADDRERRIE + Address error interrupt enable +0: Interrupt is disabled. +1: An interrupt is generated when ADDRERRF (PKA_SR[20]) is set. + 20 + 1 + read-write + + + FAULTFSMIE + Fault FSM interrupt enable +0: Interrupt is disabled. +1: An interrupt is generated when FAULTFSMF (PKA_SR[22]) is set. + 22 + 1 + read-write + + + FAULTERRORCODEIE + Fault error code interrupt enable +0: Interrupt is disabled. +1: An interrupt is generated when FAULTERRORCODEF (PKA_SR[23]) is set. + 23 + 1 + read-write + + + + + PKA_SR + PKA_SR + PKA_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + BUSY + PKA operation is in progress +This bit is set to '1' whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. +0: No operation is in progress (default) +1: An operation is in progress +Nota: if PKA is started with a wrong opcode the IP will be busy for a couple of cycles then it will abort automatically the operation and go back to ready (BUSY bit is set to '0'). + 16 + 1 + read-only + + + PROCENDF + PKA End of Operation flag +0: Operation in progress +1: PKA operation is completed. This flag is set when the BUSY bit is de-asserted. + 17 + 1 + read-only + + + RAMERRF + PKA RAM error flag +0: No PKA RAM access error +1: An AHB access to the PKA RAM occured while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress). + 19 + 1 + read-only + + + ADDRERRF + Address error flag +0: No Address error +1: Address access is out of range (unmapped address) + 20 + 1 + read-only + + + FAULTFSMF + Fault fsm error flag +0: No fault has been detected +1: A fault on fsm has been detected + 22 + 1 + read-only + + + FAULTERRORCODEF + Fault error code error flag +0: No fault has been detected +1: A fault has altered the execution of the operation and the internal fault check has been skipped + 23 + 1 + read-only + + + + + PKA_CLRFR + PKA_CLRFR + PKA_CLRFR register + 0x08 + 0x20 + read-write + 0x00000000 + + + PROCENDFC + Clear PKA End of Operation flag +0: No action +1: Clear the PROCENDF flag + 17 + 1 + read-write + + + RAMERRFC + Clear PKA RAM error flag +0: No action +1: Clear the RAMERRF flag +Bits 18 Reserved, must be kept at zero + 19 + 1 + read-write + + + ADDRERRFC + Clear Address error flag +0: No action +1: Clear the ADDRERRF flag + 20 + 1 + read-write + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA0 + registers + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. + 0 + 1 + read-write + + + B_0x0 + Deep Stop mode (default) + 0x0 + + + B_0x1 + Shutdown mode + 0x1 + + + + + ENSDNBOR + ENSDNBOR: Enable BOR supply monitoring during shutdown mode. + 1 + 1 + read-write + + + B_0x1 + the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode + 0x1 + + + B_0x0 + the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode. + 0x0 + + + + + IBIAS_RUN_AUTO + IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. +0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) +1: IBIAS control is automatic (default). + 2 + 1 + read-write + + + IBIAS_RUN_STATE + IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is +disabled. +0: IBIAS control is disabled (default). +1: IBIAS control is enabled. + 3 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU + 4 + 1 + read-write + + + B_0x1 + the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. + 0x1 + + + B_0x0 + the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 0x0 + + + + + ENBORH + ENBORH: enable BORH configuration + 5 + 1 + read-write + + + B_0x1 + BORH is enabled, threshold level depends on SELBOR[1:0] + 0x1 + + + B_0x0 + BORH off (VBOR0): threshold level for above 1.60V voltage operation. + 0x0 + + + + + SELBORH + SELBORH[1:0]: BORH selection of Vbor threshold + 6 + 2 + read-write + + + B_0x3 + BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation. + 0x3 + + + B_0x2 + BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation + 0x2 + + + B_0x1 + BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation + 0x1 + + + B_0x0 + BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation. + 0x0 + + + + + ENBORL + ENBORL: Enable BORL reset supervising during RUN mode. +0: No BORL is monitored during RUN mode. +1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below +1.6V during RUN mode) (default). +Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN. + 8 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +then PVDO=1) + 1 + 3 + read-write + + + B_0x0 + 2.05 V Lowest level + 0x0 + + + B_0x1 + 2.20 V + 0x1 + + + B_0x2 + 2.36 V + 0x2 + + + B_0x3 + 2.52 V + 0x3 + + + B_0x4 + 2.64 V + 0x4 + + + B_0x5 + 2.81 V + 0x5 + + + B_0x6 + 2.91 V Highest level + 0x6 + + + B_0x7 + External input analog voltage (compare internally to VBGP; When external input <VBGP + 0x7 + + + + + DBGRET + DBGRET: PA2 and PA3 retention enable after DEEPSTOP +0: PA2, PA3 don't retain their status exiting from DEEPSTOP. (default) +1: PA2, PA3 retain their status exiting from DEEPSTOP. + 4 + 1 + read-write + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode + 5 + 1 + read-write + + + B_0x1 + RAM1 bank is powered during low power mode + 0x1 + + + B_0x0 + RAM1 bank is disabled during low power mode (by default) + 0x0 + + + + + GPIORET + GPIORET: GPIO retention enable. +0: GPIO don't retain their status during DEEPSTOP and exiting from DEEPSTOP (default) +1: GPIO retain their status during DEEPSTOP and exiting from DEEPSTOP. +Note: it's mandatory to ensure this bit is set before entering DEEPSTOP unless DBRG.DEEPSTOP2 bit is set. + 8 + 1 + read-write + + + ENTS + ENTS: Enable Temperature Sensor + 9 + 1 + read-write + + + B_0x1 + Temperature sensor is enabled + 0x1 + + + B_0x0 + Temperature sensor is disabled + 0x0 + + + + + + + CR3 + CR3 + CR3 register + 0x8 + 0x20 + read-write + 0x0000 + + + EWU0 + EWU0 Enable WakeUp line 0 (PB0) +When this bit is set the wakeup line 0 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR4.WP0 bit. + 0 + 1 + read-write + + + EWU1 + EWU1 Enable WakeUp line 1 (PB1) +When this bit is set the wakeup line 1 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR4.WP1 bit. + 1 + 1 + read-write + + + EWU2 + EWU2 Enable WakeUp line 2 (PB2) +When this bit is set the wakeup line 2 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR4.WP2 bit. + 2 + 1 + read-write + + + EWU3 + EWU3 Enable WakeUp line 3 (PB3) +When this bit is set the wakeup line 3 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR4.WP3 bit. + 3 + 1 + read-write + + + EWU4 + EWU4 Enable WakeUp line 4 (PB4) +When this bit is set the wakeup line 4 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR4.WP4 bit. + 4 + 1 + read-write + + + EWU5 + EWU5 Enable WakeUp line 5 (PB5) +When this bit is set the wakeup line 5 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR4.WP5 bit. + 5 + 1 + read-write + + + EWU6 + EWU6 Enable WakeUp line 6 (PB6) +When this bit is set the wakeup line 6 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR4.WP6 bit. + 6 + 1 + read-write + + + EWU7 + EWU7 Enable WakeUp line 7 (PB7) +When this bit is set the wakeup line 7 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR4.WP7 bit. + 7 + 1 + read-write + + + EWU8 + EWU8 Enable WakeUp line 8 (PA8) +When this bit is set the wakeup line 8 is enabled and a rising or falling edge on wakeup line 8 will trigger a CPU wakeup event depending on CR4.WP8 bit. + 8 + 1 + read-write + + + EWU9 + EWU9 Enable WakeUp line 9 (PA9) +When this bit is set the wakeup line 9 is enabled and a rising or falling edge on wakeup line 9 will trigger a CPU wakeup event depending on CR4.WP9 bit. + 9 + 1 + read-write + + + EWU10 + EWU10 Enable WakeUp line 10 (PA10) +When this bit is set the wakeup line 10 is enabled and a rising or falling edge on wakeup line 10 will trigger a CPU wakeup event depending on CR4.WP10 bit. + 10 + 1 + read-write + + + EWU11 + EWU11 Enable WakeUp line 11 (PA11) +When this bit is set the wakeup line 11 is enabled and a rising or falling edge on wakeup line 11 will trigger a CPU wakeup event depending on CR4.WP11 bit. + 11 + 1 + read-write + + + EWBLE + EWBLE: Enable wakeup on BLE event. +0: Wakeup on BLE line is disabled (default). +1: Wakeup on BLE line is enabled. + 12 + 1 + read-write + + + EWBLEHCPU + EWBLEHCPU: Enable wakeup on BLE Host CPU event. +0: Wakeup on BLE Host CPU line is disabled (default). +1: Wakeup on BLE Host CPU line is enabled. + 13 + 1 + read-write + + + EIWL2 + EIWL2: Enable wakeup on Internal event (LPUART). +0: Wakeup on internal line is disabled (default). +1: Wakeup on internal line is enabled. + 14 + 1 + read-write + + + EIWL + EIWL: Enable wakeup on Internal event (RTC). +0: Wakeup on internal line is disabled (default). +1: Wakeup on internal line is enabled. + 15 + 1 + read-write + + + + + CR4 + CR4 + CR4 register + 0xc + 0x20 + read-write + 0x0 + + + WUP0 + WUP0 Wake-up Line Polarity 0 (PB0) +This bit defines the polarity used for event detection on external wake-up line 0 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP1 + WUP1 Wake-up Line Polarity 1 (PB1) +This bit defines the polarity used for event detection on external wake-up line 1 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP2 + WUP2 Wake-up Line Polarity 2 (PB2) +This bit defines the polarity used for event detection on external wake-up line 2 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP3 + WUP3 Wake-up Line Polarity 3 (PB3) +This bit defines the polarity used for event detection on external wake-up line 3 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP4 + WUP4 Wake-up Line Polarity 4 (PB4) +This bit defines the polarity used for event detection on external wake-up line 4 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP5 + WUP5 Wake-up Line Polarity 5 (PB5) +This bit defines the polarity used for event detection on external wake-up line 5 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP6 + WUP6 Wake-up Line Polarity 6 (PB6) +This bit defines the polarity used for event detection on external wake-up line 6 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP7 + WUP7 Wake-up Line Polarity 7 (PB7) +This bit defines the polarity used for event detection on external wake-up line 7 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP8 + WUP8 Wake-up Line Polarity 8 (PA8) +This bit defines the polarity used for event detection on external wake-up line 8 + 8 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP9 + WUP9 Wake-up Line Polarity 9 (PA9) +This bit defines the polarity used for event detection on external wake-up line 9 + 9 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP10 + WUP10 Wake-up Line Polarity 10 (PA10) +This bit defines the polarity used for event detection on external wake-up line 10 + 10 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP11 + WUP11 Wake-up Line Polarity 11 (PA11) +This bit defines the polarity used for event detection on external wake-up line 11 + 11 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + SR1 + SR1 + SR1 register + 0x10 + 0x20 + read-write + 0x0 + + + WUF0 + WUF0 WakeUp Flag 0 (PB0) +This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF1 + WUF1 WakeUp Flag 1 (PB1) +This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF2 + WUF2 WakeUp Flag 2 (PB2) +This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF3 + WUF3 WakeUp Flag 3 (PB3) +This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF4 + WUF4 WakeUp Flag 4 (PB4) +This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF5 + WUF5 WakeUp Flag 5 (PB5) +This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF6 + WUF6 WakeUp Flag 6 (PB6) +This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF7 + WUF7 WakeUp Flag 7 (PB7) +This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF8 + WUF8 WakeUp Flag 8 (PA8) +This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 8 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF9 + WUF9 WakeUp Flag 9 (PA9) +This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 9 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF10 + WUF10 WakeUp Flag 10 (PA10) +This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 10 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF11 + WUF11 WakeUp Flag 11 (PA11) +This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 11 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WBLEF + WBLEF: BLE wakeup flag. +0: no wakeup from BLE occurred since last clear. +1: a wakeup from BLE occurred since last clear. +Cleared by writing 1 in this bit. + 12 + 1 + read-write + + + WBLEHCPUF + WBLEHCPUF: BLE Host CPU wakeup flag. +0: no wakeup from BLE Host CPU occurred since last clear. +1: a wakeup from BLE Host CPU occurred since last clear. +Cleared by writing 1 in this bit. + 13 + 1 + read-write + + + IWUF2 + IWUF2: Internal wakeup 2 flag (LPUART). +0: no wakeup from LPUART occurred since last clear. +1: a wakeup from LPUART occurred since last clear. +Note: The user must clear the LPUART wakeup flag inside the LPUART IP to clear this bit +(mirror of the LPUART wakeup line on the PWRC block). + 14 + 1 + read-only + + + IWUF + IWUF: Internal wakeup flag (RTC). +0: no wakeup from RTC occurred since last clear. +1: a wakeup from RTC occurred since last clear. +Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of +the RTC wakeup line on the PWRC block). + 15 + 1 + read-only + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0x0306 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. + 2 + 1 + read-only + + + B_0x0 + SMPS regulator is not ready + 0x0 + + + B_0x1 + SMPS regulator is ready. + 0x1 + + + + + IOBOOTVAL2 + Bit3: PB15 input value on VDD33 latched at POR +Bit2: PB14 input value on VDD33 latched at POR +Bit1: PB13 input value on VDD33 latched at POR +Bit0: PB12 input value on VDD33 latched at POR + 4 + 4 + read-only + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. + 8 + 1 + read-only + + + B_0x0 + LP regulator is not ready. + 0x0 + + + B_0x1 + LP regulator is ready. + 0x1 + + + + + REGMS + REGMS: Regulator Main LDO Started +This bit provides the information whether main regulator is ready. + 9 + 1 + read-only + + + B_0x0 + Main regulator is not ready. + 0x0 + + + B_0x1 + Main regulator is ready. + 0x1 + + + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: + 4 + 2 + read-write + + + B_0x0 + BOM1 + 0x0 + + + B_0x1 + BOM2 (default) + 0x1 + + + B_0x2 + BOM3 + 0x2 + + + B_0x3 + n/a + 0x3 + + + + + SMPSFRDY + SMPSFB Force ready check +When this bit is set, the SMPS FSM will consider the SMPS ready . + 7 + 1 + read-write + + + B_0x0 + no effect (by default) + 0x0 + + + B_0x1 + SMPS is considered READY + 0x1 + + + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. + 8 + 1 + read-write + + + B_0x0 + in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. + 0x0 + + + B_0x1 + in Low Power mode, SMPS is disabled, output is floating + 0x1 + + + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. + 9 + 1 + read-write + + + B_0x0 + no effect (by default) + 0x0 + + + B_0x1 + SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 0x1 + + + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. + 10 + 1 + read-write + + + B_0x0 + No effect, SMPS is enabled. + 0x0 + + + B_0x1 + SMPS is disabled; + 0x1 + + + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode + 11 + 1 + read-write + + + B_0x0 + disable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. + 12 + 1 + read-write + + + B_0x0 + SMPS clock detection enabled (default) + 0x0 + + + B_0x1 + SMPS clock detection disabled + 0x1 + + + + + SMPS_PRECH_CUR_SEL + SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current + 13 + 2 + read-write + + + B_0x0 + 2.5mA + 0x0 + + + B_0x1 + 5mA + 0x1 + + + B_0x2 + 10mA + 0x2 + + + B_0x3 + 20mA (default) + 0x3 + + + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0x0F07 + + + PU + PU[x] : Pull Up +Pull up activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port A[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRA[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port A[i] + 0x0 + + + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PD + PD[x]: Pull Down +Pull Down activation on port A[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port A[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port A[i] + 0x0 + + + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xF0FF + + + PU + PU[x] : Pull Up +Pull up activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Up activated on port B[i] when APC bit of PWRC CR3 bit is set and PWR_PDCRB[x] is reset + 0x1 + + + B_0x0 + Pull-Up not activated on port B[i] + 0x0 + + + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PD + PD[x]: Pull Down +Pull Down activation on port B[i] pad when APC bit of PWRC CR3 is set + 0 + 16 + read-write + + + B_0x1 + Pull-Down activated on Port B[i] when APC bit of PWRC CR3 bit is set + 0x1 + + + B_0x0 + Pull-Down not activated on Port B[i] + 0x0 + + + + + + + CR6 + CR6 + CR6 register + 0x30 + 0x20 + read-write + 0x0000 + + + EWU12 + EWU12 Enable WakeUp line 12 (PA0) +When this bit is set the wakeup line 12 is enabled and a rising or falling edge on wakeup line 0 will trigger a CPU wakeup event depending on CR7.WP0 bit. + 0 + 1 + read-write + + + EWU13 + EWU13 Enable WakeUp line 13 (PA1) +When this bit is set the wakeup line 13 is enabled and a rising or falling edge on wakeup line 1 will trigger a CPU wakeup event depending on CR7.WP1 bit. + 1 + 1 + read-write + + + EWU14 + EWU14 Enable WakeUp line 14 (PA2) +When this bit is set the wakeup line 14 is enabled and a rising or falling edge on wakeup line 2 will trigger a CPU wakeup event depending on CR7.WP2 bit. + 2 + 1 + read-write + + + EWU15 + EWU15 Enable WakeUp line 15 (PA3) +When this bit is set the wakeup line 15 is enabled and a rising or falling edge on wakeup line 3 will trigger a CPU wakeup event depending on CR7.WP3 bit. + 3 + 1 + read-write + + + EWU16 + EWU16 Enable WakeUp line 16 (PB12) +When this bit is set the wakeup line 16 is enabled and a rising or falling edge on wakeup line 4 will trigger a CPU wakeup event depending on CR7.WP4 bit. + 4 + 1 + read-write + + + EWU17 + EWU17 Enable WakeUp line 17 (PB13) +When this bit is set the wakeup line 17 is enabled and a rising or falling edge on wakeup line 5 will trigger a CPU wakeup event depending on CR7.WP5 bit. + 5 + 1 + read-write + + + EWU18 + EWU18 Enable WakeUp line 18 (PB14) +When this bit is set the wakeup line 18 is enabled and a rising or falling edge on wakeup line 6 will trigger a CPU wakeup event depending on CR7.WP6 bit. + 6 + 1 + read-write + + + EWU19 + EWU19 Enable WakeUp line 19 (PB15) +When this bit is set the wakeup line 19 is enabled and a rising or falling edge on wakeup line 7 will trigger a CPU wakeup event depending on CR7.WP7 bit. + 7 + 1 + read-write + + + + + CR7 + CR7 + CR7 register + 0x34 + 0x20 + read-write + 0x0 + + + WUP12 + WUP12 Wake-up Line Polarity 12 (PA0) +This bit defines the polarity used for event detection on external wake-up line 12 + 0 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP13 + WUP13 Wake-up Line Polarity 13 (PA1) +This bit defines the polarity used for event detection on external wake-up line 13 + 1 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP14 + WUP14 Wake-up Line Polarity 14 (PA2) +This bit defines the polarity used for event detection on external wake-up line 14 + 2 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP15 + WUP15 Wake-up Line Polarity 15 (PA3) +This bit defines the polarity used for event detection on external wake-up line 15 + 3 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP16 + WUP16 Wake-up Line Polarity 16 (PB12) +This bit defines the polarity used for event detection on external wake-up line 16 + 4 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP17 + WUP17 Wake-up Line Polarity 17 (PB13) +This bit defines the polarity used for event detection on external wake-up line 17 + 5 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP18 + WUP18 Wake-up Line Polarity 18 (PB14) +This bit defines the polarity used for event detection on external wake-up line 18 + 6 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + WUP19 + WUP19 Wake-up Line Polarity 19 (PB15) +This bit defines the polarity used for event detection on external wake-up line 19 + 7 + 1 + read-write + + + B_0x0 + Detection on high level (rising edge) + 0x0 + + + B_0x1 + Detection on low level (falling edge) + 0x1 + + + + + + + SR3 + SR3 + SR3 register + 0x38 + 0x20 + read-write + 0x0 + + + WUF12 + WUF12 WakeUp Flag 12 PA0 +This bit is set when a wakeup is detected on wakeup line 12. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 0 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF13 + WUF13 WakeUp Flag 13 PA1 +This bit is set when a wakeup is detected on wakeup line 13. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 1 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF14 + WUF14 WakeUp Flag 14 PA2 +This bit is set when a wakeup is detected on wakeup line 14. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 2 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF15 + WUF15 WakeUp Flag 15 PA3 +This bit is set when a wakeup is detected on wakeup line 15. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 3 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF16 + WUF16 WakeUp Flag 16 PB12 +This bit is set when a wakeup is detected on wakeup line 16. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 4 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF17 + WUF17 WakeUp Flag 17 PB13 +This bit is set when a wakeup is detected on wakeup line 17. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 5 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF18 + WUF18 WakeUp Flag 18 PB14 +This bit is set when a wakeup is detected on wakeup line 18. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 6 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + WUF19 + WUF19 WakeUp Flag 19 PB15 +This bit is set when a wakeup is detected on wakeup line 19. It is cleared by a reset pad or by writing 1 in this bit field. +writting this bit, clears the interrupt: + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear the interrupt + 0x1 + + + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. +0: normal DEEPSTOP will be applied +1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP. + 0 + 1 + read-write + + + DIS_PRECH + DIS_PRECH[2:0]: disable precharge during deepstop (debug) +111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) +101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) +else: No effect (default 0x0) + 13 + 3 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field + 9 + 1 + read-write + + + B_0x0 + System has not been in DEEPSTOP mode + 0x0 + + + B_0x1 + System has been in DEEPSTOP mode + 0x1 + + + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a Radio wake-up event (BLE activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. + 10 + 1 + read-write + + + B_0x0 + RF IP does not require attention + 0x0 + + + B_0x1 + RF IP awake and requesting system attention + 0x1 + + + + + + + + + TRNG + TRNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + TRNG + TRNG + 28 + + + + TRNG_CR + TRNG_CR + TRNG_CR register + 0x00 + 0x20 + read-write + 0x0000FF00 + + + DISABLE + Disable +Bit DISABLE can be used for reading or setting the state of the TRNG core. The value read is always the one available at the rng core clock domain. When changing the value, the change is effective when the value read is the same as the one written. + + 0 + 1 + read-write + + + B_0x0 + The RNG core is enabled + + 0x0 + + + B_0x1 + The RNG core is disabled + 0x1 + + + + + CLR_REVCLK_FLAG + Reset reveal clock error flags when writing a '1' without resetting the whole TRNG. +When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. + 6 + 1 + read-write + + + B_0x0 + no reset + + 0x0 + + + B_0x1 + reset revclk flag + + 0x1 + + + + + RST_HEALTH_FLAGS + Reset Health error flags when writing a '1' without resetting the whole TRNG. +When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. + 7 + 1 + read-write + + + B_0x0 + no reset + + 0x0 + + + B_0x1 + reset health flag + + 0x1 + + + + + CLKDIV_15_0 + Sampling Clock Enable Divider. +CLKDIV[15:0] control the sampling clock enable divider, dividing by a factor equal to CLKDIV[15:0] + 1, values being in the range of 1 to 65536. + 8 + 16 + read-write + + + BP_POSTP + Bypass of Post-Processing. Can be used for getting the random raw values from the random sources. Available only in test mode for analog characterization where tst_bypass_ana_i input of the IP is set to 1. + + 24 + 1 + read-write + + + B_0x0 + Post processing is used + + 0x0 + + + B_0x1 + Post processing is bypassed + 0x1 + + + + + + + TRNG_SR + TRNG_SR + TRNG_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + TRNG_DISABLED + TRNG is disabled. + + 0 + 1 + read-only + + + B_0x0 + Normal operation. + + 0x0 + + + B_0x1 + RNG is disabled. + 0x1 + + + + + ALL_OSCS_DOWN + All oscillators of the random source noise have been powered down. This can cause the rising of OEC3 flag. + + 1 + 1 + read-only + + + B_0x0 + At least one oscillator is ON + 0x0 + + + B_0x1 + All oscillators are down + + 0x1 + + + + + REVEAL_CLK_ERR + The internal clock for the RNG core is not revealed. + + 2 + 1 + read-only + + + B_0x0 + Internal clock for RNG clock is present. + + 0x0 + + + B_0x1 + Internal RNG clock is not present. + 0x1 + + + + + ENTROPY_ERR + The error refers to a fault in the bit sequence detected by the Entropy Monitor. Failed test is given by REPET_ERROR, and ADAPT_ERROR, OSCS_REPET_ERROR and OSCS_ADAPT_ERROR status flags. + + 3 + 1 + read-only + + + B_0x0 + No fault detected + + 0x0 + + + B_0x1 + Embedded heath monitor detects an error in bit stream quality + 0x1 + + + + + VAL_READY + TRNG Value ready +At least one 32-bit random value is available in the data FIFO. Note that application must ensure that a random is available in internal FIFO before starting a read otherwise a bus error will be generated. + + 4 + 1 + read-only + + + B_0x0 + No value is ready in FIFO. + + 0x0 + + + B_0x1 + A 32-bit value is available in the internal FIFO + 0x1 + + + + + FIFO_FULL + Indicates whether random data FIFO is full. + + 5 + 1 + read-only + + + B_0x0 + FIFO is not full. + + 0x0 + + + B_0x1 + The internal data FIFO is full and four 32-bit random values can be read. + 0x1 + + + + + SRC_HEALTH_DONE + First run of noise source health test is completed + 20 + 1 + read-only + + + REPET_ERROR + Noise source Repetition health test error + 21 + 1 + read-only + + + ADAPT_ERROR + Noise source Adaptive 1024 health test error + 22 + 1 + read-only + + + OSCS_HEALTH_DONE + First run of source health tests of individual oscillators composing the noise source are completed.Reserved + 23 + 1 + read-only + + + OSCS_REPET_ERROR + Logical OR of repetition health test errors of individual oscillators composing the noise source. + 24 + 1 + read-only + + + OSCS_ADAPT_ERROR + Logical OR of adaptive health test errors of individual oscillators composing the noise source. + 25 + 1 + read-only + + + + + TRNG_VAL + TRNG_VAL + TRNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RND_VAL + RND_VAL is a 32-bit Random Value. This is the output of the internal four-word FIFO. +Note that application must ensure that a random is available in FIFO by ready VAL_READY flag before starting a read otherwise a null value will be returned. + 0 + 32 + read-only + + + + + TRNG_OSCS_CR + TRNG_OSCS_CR + TRNG_OSCS_CR register + 0x30 + 0x20 + read-write + 0x80000000 + + + PWRD1 + Power down of individual oscillators in triple-oscillator block number 1 + 1 + 3 + read-write + + + PWRD2 + Power down of individual oscillators in triple-oscillator block number 2 + 4 + 3 + read-write + + + PWRD3 + Power down of individual oscillators in triple-oscillator block number 3 + 7 + 3 + read-write + + + SYNC_OSCS + When set, selection of resynchronized output of oscillators. + 31 + 1 + read-write + + + + + TRNG_POSTP_CR + TRNG_POSTP_CR + TRNG_POSTP_CR register + 0x34 + 0x20 + read-write + 0x00000F00 + + + AES_RESET + Reset AES post processing. +When writing a 1, the AES post processing is reinitialized, resulting in a new key and new state generation before 128-bit random words generation. The '1' written is frozen until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. +It also reruns analog source health tests. + + 0 + 1 + read-write + + + B_0x0 + No effect + + 0x0 + + + B_0x1 + Reset AES core + 0x1 + + + + + NB_LOOP_AES + NB_LOOP_AES is the number of 128-bit words got from the noise source that have to be processed by AES for generating a single 128-bit random word. +By default, this value is set to 2 (128 bits generated before an AES processing). +0 value means 16 loops. +A new AES processing is started only when the previous one is completed. + 8 + 4 + read-write + + + NB_RND_REINIT + Number of 128-bit random words generated before AES automatically resets. This number is in the range of 1 to 65535 words. Value 0x0000 means that AES is never reinitialized. + 16 + 16 + read-write + + + + + TRNG_POSTP_SR + TRNG_POSTP_SR + TRNG_POSTP_SR register + 0x38 + 0x20 + read-only + 0x00000000 + + + AES_INIT + AES Post processing has been fully initialized (key and state) and is ready for generating 128-bit random words. + + 1 + 1 + read-only + + + B_0x0 + AES core is not initialized (no key or state set). + + 0x0 + + + B_0x1 + AES core is fully initialized. + 0x1 + + + + + AES_KEY_LD + AES random key has been generated and loaded in AES key register. + + 2 + 1 + read-only + + + B_0x0 + AES core is waiting for 128 random bits from the entropy sources for generating its key + + 0x0 + + + B_0x1 + AES key register has been loaded with a random key. + 0x1 + + + + + AES_BUSY + AES core is busy, generating a random value. + + 3 + 1 + read-only + + + B_0x0 + AES core is idle + + 0x0 + + + B_0x1 + AES core is busy. + 0x1 + + + + + AES_HEALTH_DONE + AES-CMAC health test is completed + 4 + 1 + read-only + + + AES_K12_ERROR + Health test error on AES-CMAC sub-keys generation + 5 + 1 + read-only + + + AES_DOUT_ERROR + Health test error on AES-CMAC output generation + 6 + 1 + read-only + + + + + TRNG_DEFKEY0 + TRNG_DEFKEY0 + TRNG_DEFKEY0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + RNG_DEFKEY0 + Bits 31 to 0 of AES 128-bit Default Key. + 0 + 32 + read-write + + + + + TRNG_DEFKEY1 + TRNG_DEFKEY1 + TRNG_DEFKEY1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + RNG_DEFKEY1 + Bits 63 to 31 of AES 128-bit Default Key. + 0 + 32 + read-write + + + + + TRNG_DEFKEY2 + TRNG_DEFKEY2 + TRNG_DEFKEY2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + RNG_DEFKEY2 + Bits 95 to 64 of AES 128-bit Default Key. + 0 + 32 + read-write + + + + + TRNG_DEFKEY3 + TRNG_DEFKEY3 + TRNG_DEFKEY3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + RNG_DEFKEY3 + Bits 127 to 96 of AES 128-bit Default Key. + 0 + 32 + read-write + + + + + TRNG_HEALTH_CR + TRNG_HEALTH_CR + TRNG_HEALTH_CR register + 0x60 + 0x20 + read-write + 0x02BB0033 + + + REPET_CUTOFF + Cutoff value of Repetition Test. +The default value is set to 51. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 0 + 8 + read-write + + + ADAP_CUTOFF + Cutoff value of Adaptive Test. +The default value is set to 699. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 16 + 10 + read-write + + + ITER_ADAP + Number of iterations minus 1 of Adaptive test during initialization phase. Default value is set to 0 i.e. 1 iteration. + 28 + 2 + read-write + + + + + TRNG_HEALTH_OSC1_CR + TRNG_HEALTH_OSC1_CR + TRNG_HEALTH_OSC1_CR register + 0x68 + 0x20 + read-write + 0x03E300FB + + + REPET_CUTOFF_OSC1 + Cutoff value of Repetition Test. +The default value is set to 51. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 0 + 8 + read-write + + + ADAP_CUTOFF_OSC1 + Cutoff value of Adaptive Test. +The default value is set to 699. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 16 + 10 + read-write + + + + + TRNG_HEALTH_OSC2_CR + TRNG_HEALTH_OSC2_CR + TRNG_HEALTH_OSC2_CR register + 0x6C + 0x20 + read-write + 0x03E300FB + + + REPET_CUTOFF_OSC2 + Cutoff value of Repetition Test. +The default value is set to 51. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 0 + 8 + read-write + + + ADAP_CUTOFF_OSC2 + Cutoff value of Adaptive Test. +The default value is set to 699. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 16 + 10 + read-write + + + + + TRNG_HEALTH_OSC3_CR + TRNG_HEALTH_OSC3_CR + TRNG_HEALTH_OSC3_CR register + 0x70 + 0x20 + read-write + 0x03E300FB + + + REPET_CUTOFF_OSC3 + Cutoff value of Repetition Test. +The default value is set to 51. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 0 + 8 + read-write + + + ADAP_CUTOFF_OSC3 + Cutoff value of Adaptive Test. +The default value is set to 699. +Caution: To be handled with care as any change can lead to misbehavior of TRNG. + 16 + 10 + read-write + + + + + TRNG_HEALTH_OSC1_SR + TRNG_HEALTH_OSC1_SR + TRNG_HEALTH_OSC1_SR register + 0x74 + 0x20 + read-only + 0x00000000 + + + TO1_REPET_ERROR + Repetition error flag of first oscillator of first triple-oscillator cell. + 0 + 1 + read-only + + + TO1_ADAPT_ERROR + Adaptive error flag of first oscillator of first triple-oscillator cell. + 1 + 1 + read-only + + + TO2_REPET_ERROR + Repetition error flag of first oscillator of second triple-oscillator cell. + 2 + 1 + read-only + + + TO2_ADAPT_ERROR + Adaptive error flag of first oscillator of second triple-oscillator cell. + 3 + 1 + read-only + + + TO3_REPET_ERROR + Repetition error flag of first oscillator of third triple-oscillator cell. + 4 + 1 + read-only + + + TO3_ADAPT_ERROR + Adaptive error flag of first oscillator of third triple-oscillator cell. + 5 + 1 + read-only + + + + + TRNG_HEALTH_OSC2_SR + TRNG_HEALTH_OSC2_SR + TRNG_HEALTH_OSC2_SR register + 0x78 + 0x20 + read-only + 0x00000000 + + + TO1_REPET_ERROR + Repetition error flag of first oscillator of first triple-oscillator cell. + 0 + 1 + read-only + + + TO1_ADAPT_ERROR + Adaptive error flag of first oscillator of first triple-oscillator cell. + 1 + 1 + read-only + + + TO2_REPET_ERROR + Repetition error flag of first oscillator of second triple-oscillator cell. + 2 + 1 + read-only + + + TO2_ADAPT_ERROR + Adaptive error flag of first oscillator of second triple-oscillator cell. + 3 + 1 + read-only + + + TO3_REPET_ERROR + Repetition error flag of first oscillator of third triple-oscillator cell. + 4 + 1 + read-only + + + TO3_ADAPT_ERROR + Adaptive error flag of first oscillator of third triple-oscillator cell. + 5 + 1 + read-only + + + + + TRNG_HEALTH_OSC3_SR + TRNG_HEALTH_OSC3_SR + TRNG_HEALTH_OSC3_SR register + 0x7C + 0x20 + read-only + 0x00000000 + + + TO1_REPET_ERROR + Repetition error flag of third oscillator of first triple-oscillator cell. + 0 + 1 + read-only + + + TO1_ADAPT_ERROR + Adaptive error flag of first oscillator of first triple-oscillator cell. + 1 + 1 + read-only + + + TO2_REPET_ERROR + Repetition error flag of first oscillator of second triple-oscillator cell. + 2 + 1 + read-only + + + TO2_ADAPT_ERROR + Adaptive error flag of first oscillator of second triple-oscillator cell. + 3 + 1 + read-only + + + TO3_REPET_ERROR + Repetition error flag of first oscillator of third triple-oscillator cell. + 4 + 1 + read-only + + + TO3_ADAPT_ERROR + Adaptive error flag of first oscillator of third triple-oscillator cell. + 5 + 1 + read-only + + + + + TRNG_IRQ_CR + TRNG_IRQ_CR + TRNG_IRQ_CR register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN_FF_FULL_IRQ + Enable the interrupt when the output fifo is full of new random. + 0 + 1 + read-write + + + EN_ERROR_IRQ + Enable the interrupt when an error is reported by the health tests. + 8 + 1 + read-write + + + + + TRNG_IRQ_SR + TRNG_IRQ_SR + TRNG_IRQ_SR register + 0x84 + 0x20 + read-only + 0x00000000 + + + FF_FULL_IRQ + Set to 1 when the output fifo is full of new random. Flag is cleared by writing a 1. + 0 + 1 + read-only + + + ERROR_IRQ + Set to 1 when an error is reported by the health tests. Flag is cleared by writing a 1. + 8 + 1 + read-only + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-write + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-write + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-write + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-write + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1' when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0'. + 16 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds don't care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes don't care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours don't care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is don't care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day don't care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescaler's counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescaler's counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1' , the 16-second calibration cycle period is selected.This bit must not be set to 1' if CALW8=1. +Note: CALM[0] is stucked at 0' when CALW16='1'. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1' , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at '00' when CALW8='1'. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) CALM. + 15 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescaler's counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are don't care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are don't care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are don't care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are don't care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are don't care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is don't care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKP0R register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKP1R register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x40 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x02028041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. +0: PA0 pin operated in standard mode. +1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. +0: PA1 pin operated in standard mode. +1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. +0: PB6 pin operated in standard mode. +1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. +0: PB7 pin operated in standard mode. +1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 11 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 23 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 3 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 11 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 23 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 3 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 11 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 23 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 3 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 11 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 23 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + BORH_IE + BORH_IE: BORH interrupt enable. +0: BORH interrupt is disabled. +1: BORH interrupt is enabled. + 0 + 1 + read-write + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. +0: PVD interrupt is disabled. +1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. +0: Interrupt on wakeup event seen by the PWRC is disabled. +1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + BORH_ISC + BORH_ISC: BORH interrupt status. +0: no pending interrupt. +1: voltage went under BORH threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. +0: no pending interrupt. +1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. +0: no pending interrupt. +1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + BLERXTX_DTR + BLERXTX_DTR + BLERXTX_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 1 + 1 + read-write + + + + + BLERXTX_IBER + BLERXTX_IBER + BLERXTX_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 1 + 1 + read-write + + + + + BLERXTX_IEVR + BLERXTX_IEVR + BLERXTX_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 1 + 1 + read-write + + + + + BLERXTX_IER + BLERXTX_IER + BLERXTX_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: +0: TX_SEQUENCE interrupt is disabled (default). +1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: +0: RX_SEQUENCE interrupt is disabled (default). +1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + + + BLERXTX_ISCR + BLERXTX_ISCR + BLERXTX_ISCR register + 0x3C + 8 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on TX_SEQUENCE detected. +1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on RX_SEQUENCE detected. +1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + TX_ISEDGE + TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: +0: falling edge on TX_SEQUENCE detected. +1: rising edge on TX_SEQUENCE detected. + 2 + 1 + read-only + + + RX_ISEDGE + RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: +0: falling edge on RX_SEQUENCE detected. +1: rising edge on RX_SEQUENCE detected. + 3 + 1 + read-only + + + + + + + I2C1 + I2C address block description + I2C + 0x41000000 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 interrupt + 3 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable +Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. + 0 + 1 + read-write + + + B_0x0 + Peripheral disable + 0x0 + + + B_0x1 + Peripheral enable + 0x1 + + + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match Interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received Interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection Interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer Complete interrupt enable +Note: Any of these events generate an interrupt: +Note: Transfer Complete (TC) +Note: Transfer Complete Reload (TCR) + 6 + 1 + read-write + + + B_0x0 + Transfer Complete interrupt disabled + 0x0 + + + B_0x1 + Transfer Complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable +Note: Any of these errors generate an interrupt: +Note: Arbitration Loss (ARLO) +Note: Bus Error detection (BERR) +Note: Overrun/Underrun (OVR) +Note: Timeout detection (TIMEOUT) +Note: PEC error detection (PECERR) +Note: Alert pin event detection (ALERT) + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> +<sub>...</sub> +Note: If the analog filter is also enabled, the digital filter is added to the analog filter. +Note: This filter can only be programmed when the I2C is disabled (PE = 0). + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to 1 t<sub>I2CCLK</sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to15 t<sub>I2CCLK</sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wakeup from Stop mode enable +Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. +Note: WUPEN can be set only when DNF = '0000' + 18 + 1 + read-write + + + B_0x0 + Wakeup from Stop mode disable. + 0x0 + + + B_0x1 + Wakeup from Stop mode enable. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus host address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 20 + 1 + read-write + + + B_0x0 + Host address disabled. Address 0b0001000x is NACKed. + 0x0 + + + B_0x1 + Host address enabled. Address 0b0001000x is ACKed. + 0x1 + + + + + SMBDEN + SMBus device default address enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. Address 0b1100001x is NACKed. + 0x0 + + + B_0x1 + Device default address enabled. Address 0b1100001x is ACKed. + 0x1 + + + + + ALERTEN + SMBus alert enable +Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). + 0x1 + + + + + PECEN + PEC enable +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) +In 7-bit addressing mode (ADD10 = 0): +SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. +In 10-bit addressing mode (ADD10 = 1): +SADD[9:0] should be written with the 10-bit slave address to be sent. +Note: Changing these bits when the START bit is set is not allowed. + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer. + 0x0 + + + B_0x1 + Master requests a read transfer. + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) +Note: Changing this bit when the START bit is set is not allowed. + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode, + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) +Note: Changing this bit when the START bit is set is not allowed. + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. + 0x0 + + + B_0x1 + The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 0x1 + + + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit generates a START condition once the bus is free. +Note: Writing '0' to this bit has no effect. +Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. +Note: This bit has no effect when RELOAD is set. + 13 + 1 + read-write + + + B_0x0 + No Start generation. + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. +In Master mode: +Note: Writing '0' to this bit has no effect. + 14 + 1 + read-write + + + B_0x0 + No Stop generation. + 0x0 + + + B_0x1 + Stop generation after current byte transfer. + 0x1 + + + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. +Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. +Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. +Note: Changing these bits when the START bit is set is not allowed. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +Note: This bit has no effect in slave mode or when the RELOAD bit is set. + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. +Note: Writing '0' to this bit has no effect. +Note: This bit has no effect when RELOAD is set. +Note: This bit has no effect is slave mode when SBC=0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 26 + 1 + read-write + + + B_0x0 + No PEC transfer. + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address +7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. +10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. +Note: These bits can be written only when OA1EN=0. + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode +Note: This bit can be written only when OA1EN=0. + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. The received slave address OA1 is NACKed. + 0x0 + + + B_0x1 + Own address 1 enabled. The received slave address OA1 is ACKed. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address +7-bit addressing mode: 7-bit address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks +Note: These bits can be written only when OA2EN=0. +Note: As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don't care. Only OA2[7:2] are compared. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don't care. Only OA2[7:3] are compared. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don't care. Only OA2[7:4] are compared. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don't care. Only OA2[7:5] are compared. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don't care. Only OA2[7:6] are compared. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don't care. Only OA2[7] is compared. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +t<sub>SCLL </sub>= (SCLL+1) x t<sub>PRESC</sub> +Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +t<sub>SCLH </sub>= (SCLH+1) x t<sub>PRESC</sub> +Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. +t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> +Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay t<sub>SCLDEL </sub>between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. +t<sub>SCLDEL </sub>= (SCLDEL+1) x t<sub>PRESC</sub> +Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE=0 +t<sub>TIMEOUT</sub>= (TIMEOUTA+1) x 2048 x t<sub>I2CCLK</sub> +The bus idle condition (both SCL and SDA high) when TIDLE=1 +t<sub>IDLE</sub>= (TIMEOUTA+1) x 4 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled: when SCL is low for more than t<sub>TIMEOUT</sub> (TIDLE=0) or high for more than t<sub>IDLE </sub>(TIDLE=1), a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected +In slave mode, the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected +t<sub>LOW:EXT</sub>= (TIMEOUTB+1) x 2048 x t<sub>I2CCLK</sub> +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than t<sub>LOW:EXT </sub>is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE = 0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1). +Note: This bit is cleared by hardware when PE = 0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE = 0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE = 0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE = 0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE = 0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE = 0. +Note: This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE = 0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE = 0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or t<sub>LOW</sub> detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE = 0. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE = 0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR = 1). + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the NACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to Section 52.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE = 0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data +Data byte received from the I<sup>2</sup>C bus + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data +Data byte to be transmitted to the I<sup>2</sup>C bus +Note: These bits can be written only when TXE = 1. + 0 + 8 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xA0 + registers + + + RCC + Reset and Clock Controller + 1 + + + PVD + PVD + 2 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn + 2 + 1 + read-write + + + B_0x0 + LSI RC oscillator OFF + 0x0 + + + B_0x1 + LSI RC oscillator ON + 0x1 + + + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn + 3 + 1 + read-only + + + B_0x0 + LSI RC oscillator not ready + 0x0 + + + B_0x1 + LSI RC oscillator ready + 0x1 + + + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn + 4 + 1 + read-write + + + B_0x0 + LSE oscillator OFF + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. + 5 + 1 + read-only + + + B_0x0 + LSE oscillator not ready + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn + 6 + 1 + read-write + + + B_0x0 + LSE oscillator bypass OFF + 0x0 + + + B_0x1 + LSE oscillator bypass ON + 0x1 + + + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). + 10 + 1 + read-only + + + B_0x0 + internal RC 64 MHz oscillator not ready + 0x0 + + + B_0x1 + internal RC 64 MHz oscillator ready + 0x1 + + + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF2G4 enable. +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + HSE PLL Buffer OFF + 0x0 + + + B_0x1 + HSE PLL Buffer ON + 0x1 + + + + + HSIPLLON + Internal High Speed Clock PLL enable + 13 + 1 + read-write + + + B_0x0 + PLL is OFF + 0x0 + + + B_0x1 + PLL is ON + 0x1 + + + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. + 14 + 1 + read-only + + + B_0x0 + PLL is unlocked + 0x0 + + + B_0x1 + PLL is locked + 0x1 + + + + + FMRAT + Force MR_BLE active transmission status (for debug purpose) + 15 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + active_transmission is force to '1' whatever the HSIPLLRDY status + 0x1 + + + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. + 16 + 1 + read-write + + + B_0x0 + HSE oscillator OFF + 0x0 + + + B_0x1 + HSE oscillator ON + 0x1 + + + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. + 17 + 1 + read-only + + + B_0x0 + HSE oscillator not ready + 0x0 + + + B_0x1 + HSE oscillator ready + 0x1 + + + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + SMPSINV + bit to control inversion of the SMPS clock + 0 + 1 + read-write + + + B_0x0 + SMPS clock not inverted (default value) + 0x0 + + + B_0x1 + SMPS clock inverted (for debug) + 0x1 + + + + + HSESEL + Clock source selection request: + 1 + 1 + read-write + + + B_0x0 + HSI clock source is requested (default) + 0x0 + + + B_0x1 + HSE clock source is requested + 0x1 + + + + + STOPHSI + Stop HSI clock source request + 2 + 1 + read-write + + + B_0x0 + HSI is enabled (default) + 0x0 + + + B_0x1 + disable HSI is requested + 0x1 + + + + + HSESEL_STATUS + Clock source selection Status + 3 + 1 + read-only + + + B_0x0 + HSI clock source is requested (default) + 0x0 + + + B_0x1 + HSE clock source is requested + 0x1 + + + + + CLKSYSDIV + CLKSYSDIV: system clock divided factor from HSI_64M. +000: system clock frequency is 64 MHz (not available when HSESEL=1) +001: system clock frequency is 32 MHz +010: system clock frequency is 16 MHz +011: system clock frequency is 8 MHz * +100: system clock frequency is 4 MHz * +101: system clock frequency is 2 MHz * +110: system clock frequency is 1 MHz * +111: not used. +*: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. +Warning: +if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on +HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) +To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. +the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio. + 5 + 3 + read-write + + + CLKSYSDIV_STATUS + CLKSYSDIV_STATUS: system clock frequency status +Set and cleared by hardware to indicate the actual system clock frequency. This register must +be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. +000: system clock frequency is 64 MHz +001: system clock frequency is 32 MHz +010: system clock frequency is 16 MHz +011: system clock frequency is 8 MHz +100: system clock frequency is 4 MHz +101: system clock frequency is 2 MHz +110: system clock frequency is 1 MHz +111: not used. +The actual clock frequency switching can be delayed of up to 128 system clock cycles, +depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied + 8 + 3 + read-only + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz + 12 + 1 + read-write + + + B_0x0 + div 2 when ANADIV=2 or 4 (default ) + 0x0 + + + B_0x1 + div 4 when ANADIV=1 or 2 + 0x1 + + + + + LPUCLKSEL + Selection of LPUART clock: + 13 + 1 + read-write + + + B_0x0 + 16MHz peripheral clock (default) + 0x0 + + + B_0x1 + LSE clock + 0x1 + + + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn + 15 + 2 + read-write + + + B_0x0 + LSILMPU oscillator clock (default) + 0x0 + + + B_0x1 + LSE oscillator clock used as slow clock + 0x1 + + + B_0x2 + LSI oscillator clock used as slow clock + 0x2 + + + B_0x3 + HSI_64M divided by 2048 used as slow clock + 0x3 + + + + + IOBOOSTEN + IO BOOSTER enable +Set and reset by software. + 17 + 1 + read-write + + + B_0x0 + does not enable IO BOOSTER + 0x0 + + + B_0x1 + enable IO BOOSTER + 0x1 + + + + + IOBOOSTCLKEXTEN + IO BOOSTER clock enable as external clock +Set and reset by software. + 18 + 1 + read-write + + + B_0x0 + does not use rcc clock (default) + 0x0 + + + B_0x1 + uses rcc clock + 0x1 + + + + + LCOEN + LCO output enable + 19 + 1 + read-write + + + SPI3I2SCLKSEL + Selection of I2S1 clock: +1x:64MHz peripheral clock + 22 + 2 + read-write + + + B_0x0 + 16MHz peripheral clock (default) + 0x0 + + + B_0x1 + 32MHz peripheral clock + 0x1 + + + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn + 24 + 2 + read-write + + + B_0x0 + LCO output disabled, no clock on LCO + 0x0 + + + B_0x1 + internal 32 KHz (LSI_LPMU) oscillator clock selected + 0x1 + + + B_0x2 + internal 32 KHz (LSI) oscillator clock selected + 0x2 + + + B_0x3 + external 32 KHz (LSE) oscillator clock selected + 0x3 + + + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. + 26 + 3 + read-write + + + B_0x0 + MCO output disabled, no clock on MCO + 0x0 + + + B_0x1 + system clock selected + 0x1 + + + B_0x2 + na + 0x2 + + + B_0x3 + internal RC 64 MHz (HSI) oscillator clock selected + 0x3 + + + B_0x4 + external oscillator (HSE) clock selected + 0x4 + + + B_0x5 + internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected + 0x5 + + + B_0x6 + SMPS clock selected + 0x6 + + + B_0x7 + AUX ADC ANA clock selected + 0x7 + + + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +Others: not used + 29 + 3 + read-write + + + B_0x0 + CCO clock is divided by 1 + 0x0 + + + B_0x1 + CCO clock is divided by 2 + 0x1 + + + B_0x2 + CCO clock is divided by 4 + 0x2 + + + B_0x3 + CCO clock is divided by 8 + 0x3 + + + B_0x4 + CCO clock is divided by 16 + 0x4 + + + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. + 3 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. + 5 + 1 + read-write + + + B_0x0 + HSI PLL ready interrupt disabled + 0x0 + + + B_0x1 + HSI PLL ready interrupt enabled + 0x1 + + + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. + 6 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. + 7 + 1 + read-write + + + B_0x0 + HSI PLL unlock detection interrupt disabled + 0x0 + + + B_0x1 + HSI PLL unlock detection interrupt enabled + 0x1 + + + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPURSTIE + LPURSTIE: LPUART reset release interrupt enable. + 9 + 1 + read-write + + + B_0x0 + LPUART reset release interrupt is disabled + 0x0 + + + B_0x1 + LPUART reset release interrupt is enabled + 0x1 + + + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. + 0 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the internal RC 32 KHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0x1 + + + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. + 1 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the LSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the LSE oscillator + 0x1 + + + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. + 3 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI oscillator + 0x1 + + + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. + 4 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSE oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSE oscillator + 0x1 + + + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. + 5 + 1 + read-write + + + B_0x0 + No clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x0 + + + B_0x1 + Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 0x1 + + + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + LPURSTF + LPUART reset release flag + 9 + 1 + read-write + + + B_0x0 + no LPUART reset release event occurred + 0x0 + + + B_0x1 + LPUART reset release event occurred + 0x1 + + + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done + 0 + 1 + read-write + + + B_0x0 + To cancel an ongiong request still possible until IRQ assertion + 0x0 + + + B_0x1 + To update the system clock frequency + 0x1 + + + + + CLKSYSDIV_REQ + system clock dividing factor from HSI_64M requested +Note: behavior depends on BLEEN in APB2ENR register + 1 + 3 + read-write + + + B_0x0 + div 1 (sys clock 64M) + 0x0 + + + B_0x1 + div 2 (sys clock 32M) + 0x1 + + + B_0x2 + div 4 (sys clock 16M) + 0x2 + + + B_0x3 + div 8 (sys clock 8M) + 0x3 + + + B_0x4 + div 16 (sys clock 4M) + 0x4 + + + B_0x5 + div 32 (sys clock 2M) + 0x5 + + + B_0x6 + div 64 (sys clock 1M) + 0x6 + + + + + STATUS + Status of clock switch sequence + 4 + 2 + read-only + + + B_0x0 + IDLE no switch requested + 0x0 + + + B_0x1 + ONGOING clock frequency switch is ongoing + 0x1 + + + B_0x2 + DONE clock frequency switch done + 0x2 + + + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. + 6 + 1 + read-write + + + B_0x0 + End of sequence interrupt disabled + 0x0 + + + B_0x1 + End of sequence interrupt enabled + 0x1 + + + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended + 7 + 1 + read-write + + + B_0x0 + No end of sequence event occured + 0x0 + + + B_0x1 + End of sequece event occured + 0x1 + + + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset DMA + 0x0 + + + B_0x1 + resets DMA + 0x1 + + + + + GPIOARST + GPIOA reset +Set and reset by software. + 2 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + GPIOBRST + GPIOB reset +Set and reset by software. + 3 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + CRCRST + CRC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset CRC + 0x0 + + + B_0x1 + resets CRC + 0x1 + + + + + PKARST + PKA reset +Set and reset by software. + 16 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RNGRST + RNG reset +Set and reset by software. + 18 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1: Advanced Timer reset +Set and reset by software. + 0 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + TIM16RST + TIM16 reset + 1 + 1 + read-write + + + B_0x0 + TIM16 IP is not under reset + 0x0 + + + B_0x1 + TIM16 IP is under reset + 0x1 + + + + + TIM17RST + TIM17 reset + 2 + 1 + read-write + + + B_0x0 + TIM17 IP is not under reset + 0x0 + + + B_0x1 + TIM17 IP is under reset + 0x1 + + + + + SYSCFGRST + SYSTEM CONFIG reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + RTCRST + RTC reset +Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + WDRST + WATCHDOG reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + AUXADCRST + AUXADC reset for Aux-ADC digital clock +Set and reset by software. + 4 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + LPUARTRST + LPUART reset +Set and reset by software. + 8 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + USARTRST + USART reset +Set and reset by software. + 10 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + SPI3RST + SPI3 reset +Set and reset by software. + 14 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + I2C21RST + I2C1 reset +Set and reset by software. + 21 + 1 + read-write + + + B_0x0 + does not reset + 0x0 + + + B_0x1 + resets + 0x1 + + + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + BLERST + BLE reset. + 0 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + PKAEN + PKA clock enable +Set and enable by software. + 16 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RNGEN + RNG clock enable +Set and enable by software. + 18 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2: Advanced Timer clock enable +Set and enable by software. + 0 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + TIM16EN + TIM16 enable + 1 + 1 + read-write + + + B_0x0 + TIM16 IP is clock gated + 0x0 + + + B_0x1 + TIM16 IP is clocked + 0x1 + + + + + TIM17EN + TIM17 enable + 2 + 1 + read-write + + + B_0x0 + TIM17 IP is clock gated + 0x0 + + + B_0x1 + TIM17 IP is clocked + 0x1 + + + + + SYSCFGEN + SYSTEM CONFIG enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn + 12 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + WDGEN + Watchdog clock enable. +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + ADCDIGEN + AUXADC clock enable for Aux-ADC digital clock +Set and enable by software. + 4 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + ADCANAEN + ADC clock enable for Aux-ADC analog clock +Set and enable by software. + 5 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + LPUARTEN + LPUART clock enable +Set and enable by software. + 8 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + USART1EN + USART clock enable +Set and enable by software. + 10 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + SPI3EN + SPI3 clock enable +Set and enable by software. + 14 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + I2C1EN + I2C1 clock enable +Set and enable by software. + 21 + 1 + read-write + + + B_0x0 + does not enable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRBLEEN + MR_BLE enable + 0 + 1 + read-write + + + B_0x0 + MR_BLE IP is clock gated + 0x0 + + + B_0x1 + MR_BLE IP is clocked + 0x1 + + + + + CLKBLEDIV + MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1 + 2 + 1 + read-write + + + B_0x0 + 32MHz + 0x0 + + + B_0x1 + 16MHz + 0x1 + + + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags + 23 + 1 + write-only + + + B_0x0 + Nothing done + 0x0 + + + B_0x1 + Reset the value of the reset flags + 0x1 + + + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. + 26 + 1 + read-only + + + B_0x0 + No reset from pad occurred + 0x0 + + + B_0x1 + Reset from pad occurred + 0x1 + + + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. + 27 + 1 + read-only + + + B_0x0 + No POWER reset occurred + 0x0 + + + B_0x1 + POWER reset occurred + 0x1 + + + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. + 28 + 1 + read-only + + + B_0x0 + No software reset occurred + 0x0 + + + B_0x1 + Software reset occurred + 0x1 + + + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. + 29 + 1 + read-only + + + B_0x0 + No watchdog reset occurred + 0x0 + + + B_0x1 + Watchdog reset occurred + 0x1 + + + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. + 30 + 1 + read-only + + + B_0x0 + No lockup reset occurred + 0x0 + + + B_0x1 + lockup reset occurred + 0x1 + + + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x000000030 + + + SATRG + Sense Amplifier threshold +Set by software. + 3 + 1 + read-write + + + B_0x0 + the bias current is confronted to a reference current with a ratio of 1/2. + 0x0 + + + B_0x1 + the bias current is confronted to a reference current with a ratio of 3/4 + 0x1 + + + + + GMC + High Speed External XO current control +Set by software. + 4 + 3 + read-write + + + B_0x0 + max 0.0 001: max 0.57 mA/V + 0x0 + + + B_0x2 + max 0.78 mA/V + 0x2 + + + B_0x3 + max 1.13 mA/V (Default) + 0x3 + + + B_0x4 + max 0.61 mA/V + 0x4 + + + B_0x5 + max 1.65 mA/V + 0x5 + + + B_0x6 + max 2.12 mA/V + 0x6 + + + B_0x7 + max 2.84 mA/V + 0x7 + + + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + 0x000000000 + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + + + + + SPI3 + SPI address block description + SPI + 0x41007000 + + 0x0 + 0x400 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPIx_CR1 + SPIx_CR1 + SPI control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CPHA + Clock phase +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 0 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode. + 1 + 1 + read-write + + + B_0x0 + CK to 0 when idle + 0x0 + + + B_0x1 + CK to 1 when idle + 0x1 + + + + + MSTR + Master selection +Note: This bit should not be changed when communication is ongoing. +Note: This bit is not used in I<sup>2</sup>S mode. + 2 + 1 + read-write + + + B_0x0 + Slave configuration + 0x0 + + + B_0x1 + Master configuration + 0x1 + + + + + BR + Baud rate control +Note: These bits should not be changed when communication is ongoing. +Note: These bits are not used in I<sup>2</sup>S mode. + 3 + 3 + read-write + + + B_0x0 + f<sub>PCLK</sub>/2 + 0x0 + + + B_0x1 + f<sub>PCLK</sub>/4 + 0x1 + + + B_0x2 + f<sub>PCLK</sub>/8 + 0x2 + + + B_0x3 + f<sub>PCLK</sub>/16 + 0x3 + + + B_0x4 + f<sub>PCLK</sub>/32 + 0x4 + + + B_0x5 + f<sub>PCLK</sub>/64 + 0x5 + + + B_0x6 + f<sub>PCLK</sub>/128 + 0x6 + + + B_0x7 + f<sub>PCLK</sub>/256 + 0x7 + + + + + SPE + SPI enable +Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. +Note: This bit is not used in I<sup>2</sup>S mode. + 6 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + LSBFIRST + Frame format +Note: 1. This bit should not be changed when communication is ongoing. +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 7 + 1 + read-write + + + B_0x0 + data is transmitted / received with the MSB first + 0x0 + + + B_0x1 + data is transmitted / received with the LSB first + 0x1 + + + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 9 + 1 + read-write + + + B_0x0 + Software slave management disabled + 0x0 + + + B_0x1 + Software slave management enabled + 0x1 + + + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +Note: This bit is not used in I<sup>2</sup>S mode. + 10 + 1 + read-write + + + B_0x0 + Full-duplex (Transmit and receive) + 0x0 + + + B_0x1 + Output disabled (Receive-only mode) + 0x1 + + + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 1 + read-write + + + B_0x0 + 8-bit CRC length + 0x0 + + + B_0x1 + 16-bit CRC length + 0x1 + + + + + CRCNEXT + Transmit CRC next +Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + Next transmit value is from Tx buffer. + 0x0 + + + B_0x1 + Next transmit value is from Tx CRC register. + 0x1 + + + + + CRCEN + Hardware CRC calculation enable +Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. +Note: This bit is not used in I<sup>2</sup>S mode. + 13 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. +Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. +Note: This bit is not used in I<sup>2</sup>S mode. + 14 + 1 + read-write + + + B_0x0 + Output disabled (receive-only mode) + 0x0 + + + B_0x1 + Output enabled (transmit-only mode) + 0x1 + + + + + BIDIMODE + Bidirectional data mode enable. +This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. +Note: This bit is not used in I<sup>2</sup>S mode. + 15 + 1 + read-write + + + B_0x0 + 2-line unidirectional data mode selected + 0x0 + + + B_0x1 + 1-line bidirectional data mode selected + 0x1 + + + + + + + SPIx_CR2 + SPIx_CR2 + SPI control register 2 + 0x04 + 16 + read-write + 0x0700 + 0xFFFF + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. + 0 + 1 + read-write + + + B_0x0 + Rx buffer DMA disabled + 0x0 + + + B_0x1 + Rx buffer DMA enabled + 0x1 + + + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. + 1 + 1 + read-write + + + B_0x0 + Tx buffer DMA disabled + 0x0 + + + B_0x1 + Tx buffer DMA enabled + 0x1 + + + + + SSOE + SS output enable +Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 2 + 1 + read-write + + + B_0x0 + SS output is disabled in master mode and the SPI interface can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 0x1 + + + + + NSSP + NSS pulse management +This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1 , or FRF = 1 . +Note: 1. This bit must be written only when the SPI is disabled (SPE=0). +Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode. + 3 + 1 + read-write + + + B_0x0 + No NSS pulse + 0x0 + + + B_0x1 + NSS pulse generated + 0x1 + + + + + FRF + Frame format +1 SPI TI mode +Note: This bit must be written only when the SPI is disabled (SPE=0). +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + SPI Motorola mode + 0x0 + + + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I<sup>2</sup>S mode). + 5 + 1 + read-write + + + B_0x0 + Error interrupt is masked + 0x0 + + + B_0x1 + Error interrupt is enabled + 0x1 + + + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + read-write + + + B_0x0 + RXNE interrupt masked + 0x0 + + + B_0x1 + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 0x1 + + + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + read-write + + + B_0x0 + TXE interrupt masked + 0x0 + + + B_0x1 + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 0x1 + + + + + DS + Data size +These bits configure the data length for SPI transfers. +If software attempts to write one of the Not used values, they are forced to the value 0111 +(8-bit) +Note: These bits are not used in I<sup>2</sup>S mode. + 8 + 4 + read-write + + + B_0x0 + Not used + 0x0 + + + B_0x1 + Not used + 0x1 + + + B_0x2 + Not used + 0x2 + + + B_0x3 + 4-bit + 0x3 + + + B_0x4 + 5-bit + 0x4 + + + B_0x5 + 6-bit + 0x5 + + + B_0x6 + 7-bit + 0x6 + + + B_0x7 + 8-bit + 0x7 + + + B_0x8 + 9-bit + 0x8 + + + B_0x9 + 10-bit + 0x9 + + + B_0xA + 11-bit + 0xA + + + B_0xB + 12-bit + 0xB + + + B_0xC + 13-bit + 0xC + + + B_0xD + 14-bit + 0xD + + + B_0xE + 15-bit + 0xE + + + B_0xF + 16-bit + 0xF + + + + + FRXTH + FIFO reception threshold +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +Note: This bit is not used in I<sup>2</sup>S mode. + 12 + 1 + read-write + + + B_0x0 + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0x0 + + + B_0x1 + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 0x1 + + + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 13 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. +Note: This bit is not used in I S mode. + 14 + 1 + read-write + + + B_0x0 + Number of data to transfer is even + 0x0 + + + B_0x1 + Number of data to transfer is odd + 0x1 + + + + + + + SPIx_SR + SPIx_SR + SPI status register + 0x08 + 16 + read-write + 0x0002 + 0xFFFF + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + B_0x0 + Rx buffer empty + 0x0 + + + B_0x1 + Rx buffer not empty + 0x1 + + + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + B_0x0 + Tx buffer not empty + 0x0 + + + B_0x1 + Tx buffer empty + 0x1 + + + + + CHSIDE + Channel side +Note: This bit is not used in SPI mode. It has no significance in PCM mode. + 2 + 1 + read-only + + + B_0x0 + Channel Left has to be transmitted or has been received + 0x0 + + + B_0x1 + Channel Right has to be transmitted or has been received + 0x1 + + + + + UDR + Underrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. +Note: This bit is not used in SPI mode. + 3 + 1 + read-only + + + B_0x0 + No underrun occurred + 0x0 + + + B_0x1 + Underrun occurred + 0x1 + + + + + CRCERR + CRC error flag +Note: This flag is set by hardware and cleared by software writing 0. +Note: This bit is not used in I<sup>2</sup>S mode. + 4 + 1 + read-write + + + B_0x0 + CRC value received matches the SPIx_RXCRCR value + 0x0 + + + B_0x1 + CRC value received does not match the SPIx_RXCRCR value + 0x1 + + + + + MODF + Mode fault +This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. +Note: This bit is not used in I<sup>2</sup>S mode. + 5 + 1 + read-only + + + B_0x0 + No mode fault occurred + 0x0 + + + B_0x1 + Mode fault occurred + 0x1 + + + + + OVR + Overrun flag +This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. + 6 + 1 + read-only + + + B_0x0 + No overrun occurred + 0x0 + + + B_0x1 + Overrun occurred + 0x1 + + + + + BSY + Busy flag +This flag is set and cleared by hardware. +Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. + 7 + 1 + read-only + + + B_0x0 + SPI (or I2S) not busy + 0x0 + + + B_0x1 + SPI (or I2S) is busy in communication or Tx buffer is not empty + 0x1 + + + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I<sup>2</sup>S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. + 8 + 1 + read-only + + + B_0x0 + No frame format error + 0x0 + + + B_0x1 + A frame format error occurred + 0x1 + + + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. + 9 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full + 0x3 + + + + + FTLVL + FIFO transmission level +These bits are set and cleared by hardware. +Note: This bit is not used in I<sup>2</sup>S mode. + 11 + 2 + read-only + + + B_0x0 + FIFO empty + 0x0 + + + B_0x1 + 1/4 FIFO + 0x1 + + + B_0x2 + 1/2 FIFO + 0x2 + + + B_0x3 + FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 0x3 + + + + + + + SPIx_DR + SPIx_DR + SPI data register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPIx_CRCPR + SPIx_CRCPR + SPI CRC polynomial register + 0x10 + 16 + read-write + 0x0007 + 0xFFFF + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPIx_RXCRCR + SPIx_RXCRCR + SPI Rx CRC register + 0x14 + 16 + read-only + 0x0000 + 0xFFFF + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY Flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_TXCRCR + SPIx_TXCRCR + SPI Tx CRC register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. +Note: These bits are not used in I<sup>2</sup>S mode. + 0 + 16 + read-only + + + + + SPIx_I2SCFGR + SPIx_I2SCFGR + SPIx_I2S configuration register + 0x1C + 16 + read-write + 0x0000 + 0xFFFF + + + CHLEN + Channel length (number of bits per audio channel) +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. + 0 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + DATLEN + Data length to be transferred +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 1 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CKPOL + Inactive state clock polarity +Note: For correct operation, this bit should be configured when the I2S is disabled. +Note: It is not used in SPI mode. +Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. + 3 + 1 + read-write + + + B_0x0 + I2S clock inactive state is low level + 0x0 + + + B_0x1 + I2S clock inactive state is high level + 0x1 + + + + + I2SSTD + I2S standard selection +For more details on I<sup>2</sup>S standards, refer to Section 27.7.2 on page 805 +Note: For correct operation, these bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 4 + 2 + read-write + + + B_0x0 + I<sup>2</sup>S Philips standard + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). +Note: It is not used in SPI mode. + 7 + 1 + read-write + + + B_0x0 + Short frame synchronization + 0x0 + + + B_0x1 + Long frame synchronization + 0x1 + + + + + I2SCFG + I2S configuration mode +Note: These bits should be configured when the I2S is disabled. +Note: They are not used in SPI mode. + 8 + 2 + read-write + + + B_0x0 + Slave transmit + 0x0 + + + B_0x1 + Slave receive + 0x1 + + + B_0x2 + Master transmit + 0x2 + + + B_0x3 + Master receive + 0x3 + + + + + I2SE + I2S enable +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + B_0x0 + I2S peripheral is disabled + 0x0 + + + B_0x1 + I2S peripheral is enabled + 0x1 + + + + + I2SMOD + I2S mode selection +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S mode is selected + 0x1 + + + + + ASTRTEN + Asynchronous start enable. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. +When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. +Note: The appropriate transition is a falling edge on WS signal when I<sup>2</sup>S Philips Standard is used, or a rising edge for other standards. +Note: The appropriate level is a low level on WS signal when I<sup>2</sup>S Philips Standard is used, or a high level for other standards. +Note: Please refer to Section 27.7.3: Start-up description for additional information. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. + 0x0 + + + B_0x1 + The Asynchronous start is enabled. + 0x1 + + + + + + + SPIx_I2SPR + SPIx_I2SPR + SPIx_I2S prescaler register + 0x20 + 16 + read-write + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. +Refer to Section 27.7.3 on page 812. +Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. +Note: They are not used in SPI mode. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +Refer to Section 27.7.3 on page 812. +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 8 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + Master clock output enable +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. +Note: It is not used in SPI mode. + 9 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + TIM2 + TIM2 + 0x40002000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +Counter overflow/underflow + +Setting the UG bit + +Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +Counter overflow/underflow + +Setting the UG bit + +Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS: Master Mode Selection. + +This field is not available in IUM as Timer2 is not connected to ant other timer for master/slave synchronization. + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follow : + +is generated by the trigger input (slave mode controller configured in reset mode) then the signal + +on TRGO is delayed compared to the actual reset. + +start several timers at the same time or to control a window in which a slave timer is enable. The + +Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input + +when configured in gated mode. When the Counter Enable signal is controlled by the trigger + +input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit + +description in GPT_SMCR register). + +can then be used as a prescaler for a slave timer. + +(even if it was already high), as soon as a capture or a compare match occured. (TRGO). + 4 + 3 + read-write + + + B_0x0 + Reset the UG bit from the GPT_EGR register is used as trigger output (TRGO). If the reset + 0x0 + + + B_0x1 + Enable the Counter Enable signal cnt_en is used as trigger output (TRGO). It is useful to + 0x1 + + + B_0x2 + Update The update event is selected as trigger output (TRGO). For instance a master timer + 0x2 + + + B_0x3 + Compare Pulse The trigger output send a positive pulse when the CC1IF flag is to be set + 0x3 + + + B_0x4 + Compare OC1REF signal is used as trigger output (TRGO). + 0x4 + + + B_0x5 + Compare OC2REF signal is used as trigger output (TRGO). + 0x5 + + + B_0x6 + Compare OC3REF signal is used as trigger output (TRGO). + 0x6 + + + B_0x7 + Compare OC4REF signal is used as trigger output (TRGO). + 0x7 + + + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS + TS[2:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +101: Filtered Timer Input 1 (TI1FP1) + +110: Filtered Timer Input 2 (TI2FP2) + +others: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + MSM + MSM: Master/Slave mode + +Not vailable in IUM. Not used in Blue51 as TRGO is not connected to any slave timer + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection bit 3 + +Refer to SMS description bits2:0 + 16 + 1 + read-write + + + TS_4_3 + Extended trigger selection. Not used. Not available in IUM + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CC2DE + CC2DE: Capture/Compare 2 DMA request enable + +0: CC2 DMA request disabled + +1: CC2 DMA request enabled + 10 + 1 + read-write + + + CC3DE + CC3DE: Capture/Compare 3 DMA request enable + +0: CC3 DMA request disabled + +1: CC3 DMA request enabled + 11 + 1 + read-write + + + CC4DE + CC4DE: Capture/Compare 4 DMA request enable + +0: CC4 DMA request disabled + +1: CC4 DMA request enabled + 12 + 1 + read-write + + + TDE + TDE: Trigger DMA request Enable. + +Not used in Blue51. Not available in IUM. + +0: Trigger DMA request disabled. + +1: Trigger DMA request enabled. + 14 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level OC1REF is forced low. + +0101: Force active level OC1REF is forced high. + +0110: PWM mode 1 In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 In upcounting, channel 1 is inactive as long as + +TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. . + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIM2_CR1 address) + (DBA + DMA index) x 4 + +where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIM2_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). + 0 + 16 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + 0x0 + 0xF + + + TI1SEL + selects TI1[0] to TI1[15] input + 0 + 4 + read-write + + + TI2SEL + selects TI2[0] to TI2[15] inputt + 8 + 4 + read-write + + + TI3SEL + selects TI3[0] to TI3[15] input + 16 + 4 + read-write + + + TI4SEL + selects TI4[0] to TI4[15] input + 24 + 4 + read-write + + + + + + + TIM16 + TIM16 + 0x40005000 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 interrupt + 26 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +Counter overflow/underflow + +Setting the UG bit + +Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +Counter overflow/underflow + +Setting the UG bit + +Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x00000000 + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x00000000 + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs. + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level OC1REF is forced low. + +0101: Force active level OC1REF is forced high. + +0110: PWM mode 1 Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. + +0111: PWM mode 2 Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. + +All other values: Reserved + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the + +comparison changes or when the output compare mode switches from 'frozen' mode + +to 'PWM' mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x00000000 + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x00000000 + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKCMP2E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 2 + 1 + read-write + + + AF1_8_3 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 3 + 6 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + BKCMP2P + BKCMP2P: BRK COMP2 input polarity. + +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP2 input is active low. + +1: COMP2 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 11 + 1 + read-write + + + AF1_13_12 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 12 + 2 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + 0x0 + 0xF + + + TI1SEL + selects TI1[0] to TI1[15] input + 0 + 4 + read-write + + + + + + + TIM17 + TIM17 + 0x40006000 + + 0x0 + 0x64 + registers + + + TIM17 + TIM16 interrupt + 27 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +Counter overflow/underflow + +Setting the UG bit + +Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +Counter overflow/underflow + +Setting the UG bit + +Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture/compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs. + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level OC1REF is forced low. + +0101: Force active level OC1REF is forced high. + +0110: PWM mode 1 Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. + +0111: PWM mode 2 Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. + +All other values: Reserved + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the + +comparison changes or when the output compare mode switches from 'frozen' mode + +to 'PWM' mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + TI1_RMP + TI1_RMP[1:0]: Timer 17 input 1 connection + +This bit is set and cleared by software. + +00: TIM17 TI1 is connected to GPIO + +01: TIM17 TI1 is connected to LCO + +1x: TIM17 TI1 is connected to MCO + 0 + 2 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x1 + 0xF + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKCMP2E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 2 + 1 + read-write + + + AF1_8_3 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 3 + 6 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + BKCMP2P + BKCMP2P: BRK COMP2 input polarity. + +This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP2 input is active low. + +1: COMP2 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 11 + 1 + read-write + + + AF1_13_12 + AF1[13:12] + +Not used in Blue51. Not available in IUM + 12 + 2 + read-write + + + + + + + USART + USART + 0x41004000 + + 0x0 + 0x30 + registers + + + USART_1 + USART interrupt + 8 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + OVER8 + OVER8: Oversampling mode +-0: Oversampling by 16 +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + RTOIE + RTOIE: Receiver timeout interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register + 26 + 1 + read-write + + + EOBIE + EOBIE: End of Block interrupt enable +This bit is set and cleared by software. + + 27 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + + 0x0 + + + B_0x1 + A USART interrupt is generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SLVEN + SLVEN: Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +-0: Slave mode disabled. +-1: Slave mode enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 0 + 1 + read-write + + + DIS_NSS + DIS_NSS +When the DSI_NSS bit is set, the NSS pin input will be ignored. +-0: SPI slave selection depends on NSS input pin. +-1: SPI slave will be always selected and NSS input pin will be ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 3 + 1 + read-write + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + LBDL + LBDL: LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +-0: 10-bit break detection +-1: 11-bit break detection +This bit can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + LBDIE + LBDIE: LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +-0: Interrupt is inhibited +-1: An interrupt is generated whenever LBDF=1 in the USART_ISR register + 6 + 1 + read-write + + + LBCL + LBCL: Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) +has to be output on the SCLK pin in synchronous mode. +-0: The clock pulse of the last data bit is not output to the SCLK pin +-1: The clock pulse of the last data bit is output to the SCLK pin +Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit +format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CPHA + CPHA: Clock phase +This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It +works in conjunction with the CPOL bit to produce the desired clock/data relationship (see +Figure 137 and Figure 138) +-0: The first clock transition is the first data capture edge +-1: The second clock transition is the first data capture edge +This bit can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + CPOL + CPOL: Clock polarity +This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous +mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +-0: Steady low value on SCLK pin outside transmission window +-1: Steady high value on SCLK pin outside transmission window +This bit can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + CLKEN + CLKEN: Clock enable +This bit allows the user to enable the SCLK pin. +-0: SCLK pin disabled +-1: SCLK pin enabled +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced +by hardware to 0'. Please refer to Section 23.4: USART implementation on page 483. +Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps +below must be respected: +UE = 0 +SCEN = 1 +GTPR configuration +CLKEN= 1 +UE = 1 + 11 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + LINEN + LINEN: LIN mode enable +This bit is set and cleared by software. +-0: LIN mode disabled +-1: LIN mode enabled +The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit +in the USART_CR1 register, and to detect LIN Sync breaks. +This bit field can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ABREN + ABREN: Auto baud rate enable +This bit is set and cleared by software. +-0: Auto baud rate detection is disabled. +-1: Auto baud rate detection is enabled. + 20 + 1 + read-write + + + ABRMOD + ABRMOD[1:0]: Auto baud rate mode +These bits are set and cleared by software. +-00: Measurement of the start bit is used to detect the baud rate. +-01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> +Frame = Start10xxxxxx) +-10: 0x7F frame detection. +-11: 0x55 frame detection +This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). + 21 + 2 + read-write + + + RTOEN + RTOEN: Receiver timeout enable +This bit is set and cleared by software. +-0: Receiver timeout feature disabled. +-1: Receiver timeout feature enabled. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle +(no reception) for the duration programmed in the RTOR (receiver timeout register). + 23 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + IREN + IREN: IrDA mode enable +This bit is set and cleared by software. +-0: IrDA disabled +-1: IrDA enabled +This bit can only be written when the USART is disabled (UE=0). + 1 + 1 + read-write + + + IRLP + IRLP: IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +-0: Normal mode +-1: Low-power mode +This bit can only be written when the USART is disabled (UE=0). + 2 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + NACK + NACK: Smartcard NACK enable +-0: NACK transmission in case of parity error is disabled +-1: NACK transmission during parity error is enabled +This bit field can only be written when the USART is disabled (UE=0). + 4 + 1 + read-write + + + SCEN + SCEN: Smartcard mode enable +This bit is used for enabling Smartcard mode. +-0: Smartcard Mode disabled +-1: Smartcard Mode enabled +This bit field can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + ONEBIT + ONEBIT: One sample bit method enable +This bit allows the user to select the sample method. When the one sample bit method is +selected the noise detection flag (NF) is disabled. +-0: Three sample bit method +-1: One sample bit method +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + SCARCNT + SCARCNT[2:0]: Smartcard auto-retry count +This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before +generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a +reception error (RXNE/RXFNE and PE bits set). +This bit field must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to +stop retransmission. +-0x0: retransmission disabled No automatic retransmission in transmit mode. +-0x1 to 0x7: number of automatic retransmission attempts (before signaling error) + 17 + 3 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + TCBGTIE + TCBGTIE: Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register + 24 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[15:4] +BRR[15:4] = USARTDIV[15:4]BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared + 0 + 16 + read-write + + + + + GTPR + GTPR + GTPR register + 0x10 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[7:0]: Prescaler value +In IrDA Low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power Baud Rate +Used for programming the prescaler for dividing the USART source clock to achieve the lowpower +frequency: +The source clock is divided by the value given in the register (8 significant bits): +-00000000: Reserved do not program this value +-00000001: divides the source clock by 1 +-00000010: divides the source clock by 2 +... +In Smartcard mode: +PSC[4:0]: Prescaler value +Used for programming the prescaler for dividing the USART source clock to provide the +Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor +of the source clock frequency: +-00000: Reserved do not program this value +-00001: divides the source clock by 2 +-00010: divides the source clock by 4 +-00011: divides the source clock by 6 +... +This bit field can only be written when the USART is disabled (UE=0). + 0 + 8 + read-write + + + GT + GT[7:0]: Guard time value +This bit-field is used to program the Guard time value in terms of number of baud clock +periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time +value. +This bit field can only be written when the USART is disabled (UE=0). + 8 + 8 + read-write + + + + + RTOR + RTOR + RTOR register + 0x14 + 0x20 + read-write + 0x00000000 + + + RTO + RTO[23:0]: Receiver timeout value +This bit-field gives the Receiver timeout value in terms of number of baud clocks. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is +detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard +chapter for more details. In the standard, the CWT/BWT measurement is done starting from +the Start Bit of the last received character. + 0 + 24 + read-write + + + BLEN + BLEN[7:0]: Block Length +This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number +of information characters + the length of the Epilogue Field (1-LEC/2-CRC) 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO +mode is enabled). +This bit-field can be used also in other modes. In this case, the Block length counter is reset +when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. + 24 + 8 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + ABRRQ + ABRRQ: Auto baud rate request +Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud +rate measurement on the next received data frame. + 0 + 1 + write-only + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0' +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + LBDF + LBDF: LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by +writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +-0: LIN Break not detected +-1: LIN break detected + 8 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + RTOF + RTOF: Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has +lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in +the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +-0: Timeout value not reached +-1: Timeout value reached without any data reception + 11 + 1 + read-only + + + EOBF + EOBF: End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 +Smartcard mode). The detection is done when the number of received bytes (from the start +of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR2 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +-0: End of Block not reached +-1: End of Block (number of characters) reached + 12 + 1 + read-only + + + UDR + UDR: SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock for data transmission appears +while the software has not yet loaded any value into USARTx_DR. +-0: No underrun error +-1: underrun error + 13 + 1 + read-only + + + ABRE + ABRE: Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or +character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register + 14 + 1 + read-only + + + ABRF + ABRF: Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE will also be +set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was +completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to +the ABRRQ in the USART_RQR register. + 15 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + TCBGT + TCBGT: Transmission complete before guard time flagl +This bit indicates when the last data written in the USART_TDR has been transmitted +correctly out of the shift register . +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is +complete and if there is no NACK from the smartcard. An interrupt is generated if +TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the +TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +-0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is +received from the card) +-1: Transmission is complete successfully (before Guard time completion and there is no +NACK from the smart card). + 25 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesn't reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesn't reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFECF: TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register + 5 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + TCBGTCF + TCBGTCF: Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LBDCF: LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. + 8 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + RTOCF + RTOCF: Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. + 11 + 1 + write-only + + + EOBCF + EOBCF: End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register + 12 + 1 + write-only + + + UDRCF + UDRCF:SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register + 13 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + BLUE + BLUE + 0x60000000 + + 0x0 + 0x1000 + registers + + + + INTERRUPT1REG + INTERRUPT1REG + INTERRUPT1REG register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error. + 4 + 1 + read-write + + + RXOVERFLOWERROR + Receive Overflow error. + 5 + 1 + read-write + + + SEQDONE + Sequencer end of task. + 7 + 1 + read-write + + + TXERROR_0 + Transmission error 0: transmit block missing data error. + 8 + 1 + read-write + + + TXERROR_1 + Transmission error 1: a TX skip happened during an on-going transmission. + 9 + 1 + read-write + + + TXERROR_2 + Transmission error 2: channel index is greater than 39. + 10 + 1 + read-write + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state. + 11 + 1 + read-write + + + TXERROR_4 + Transmission error 4: a CTE issue occurred. + 12 + 1 + read-write + + + ENCERROR + Encryption error on reception. + 13 + 1 + read-write + + + ALLTABLEREADYERROR + All RAM Table not ready on time. + 14 + 1 + read-write + + + TXDATAREADYERROR + Transmit data pack not ready error + + 15 + 1 + read-write + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-write + + + RCVLENGTHERROR + Receive length error. + 18 + 1 + read-write + + + SEMATIMEOUTERROR + Semaphore timeout error + + 19 + 1 + read-write + + + TXRXSKIP + Transmission/Reception skip. + 21 + 1 + read-write + + + ACTIVE2ERROR + Active2 Radio state error. + 22 + 1 + read-write + + + CONFIGERROR + Data pointer configuration error. + 23 + 1 + read-write + + + TXOK + Previous transmitted packet received OK by the peer device. + 24 + 1 + read-write + + + DONE + Receive/Transmit done. + 25 + 1 + read-write + + + RCVTIMEOUT + Receive timeout (no preamble found). + 26 + 1 + read-write + + + RCVNOMD + Received low MD bit. + 27 + 1 + read-write + + + RCVCMD + Received command + + 28 + 1 + read-write + + + TIMECAPTURETRIG + A time has been captured in TIMERCAPTUREREG. + 29 + 1 + read-write + + + RCVCRCERR + Receive data fail + + 30 + 1 + read-write + + + RCVOK + Receive data OK. + 31 + 1 + read-write + + + + + INTERRUPT2REG + INTERRUPT2REG + INTERRUPT2REG register + 0x8 + 0x20 + read-write + 0x00000000 + + + AESMANENCINT + AES manual encryption. + 0 + 1 + read-write + + + AESLEPRIVINT + AES LE privacy engine. + 1 + 1 + read-write + + + + + TIMEOUTDESTREG + TIMEOUTDESTREG + TIMEOUTDESTREG register + 0xc + 0x20 + read-write + 0x00000000 + + + DESTINATION + Timeout timer Destination + + 0 + 2 + read-write + + + + + TIMEOUTREG + TIMEOUTREG + TIMEOUTREG register + 0x10 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timer1 or Timer2 Timeout value (depending on Destination register) + + 0 + 32 + read-write + + + + + TIMERCAPTUREREG + TIMERCAPTUREREG + TIMERCAPTUREREG register + 0x14 + 0x20 + read-only + 0x00000000 + + + TIMERCAPTURE + Interpolated absolute time capture register + + 0 + 32 + read-only + + + + + CMDREG + CMDREG + CMDREG register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXRXSKIP + Transmission/Reception skip command. + 0 + 1 + write-only + + + CLEARSEMAREQ + Semaphore Clear command. + 3 + 1 + write-only + + + + + STATUSREG + STATUSREG + STATUSREG register + 0x1c + 0x20 + read-only + 0x00000000 + + + AESONFLYBUSY + AES on the fligh encryption busy status + 0 + 1 + read-only + + + NOTSUPPORTED_FUNCTION + indicates the SW requests an unsupported feature. + 3 + 1 + read-only + + + ADDPOINTERROR + Address Pointer Error status + + 4 + 1 + read-only + + + RXOVERFLOWERROR + AHB arbiter is full and there is no more storage capability available in RX datapath + 5 + 1 + read-only + + + PREVTRANSMIT + Previous event was a Transmission (1) or Reception (0) status + 6 + 1 + read-only + + + SEQDONE + Sequencer end of task status. + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 status: Transmit block missing data error. + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 status + + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 status. + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach. + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 status + + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive status + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready status + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready status. + 15 + 1 + read-only + + + NOACTIVELERROR + GlobalStatMach. + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error status + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error status + + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip status. + 21 + 1 + read-only + + + ACTIVE2ERROR + Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step. + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error status + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK by the peer device status. + 24 + 1 + read-only + + + DONE + Receive/Transmit done status. + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout status (no access address found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit status (valid only on Data Physical Channel PDU reception) + + 27 + 1 + read-only + + + RCVCMD + Received command status (valid only on Data Physical Channel PDU reception). + 28 + 1 + read-only + + + TIMECAPTURETRIG + indicates a time has been captured in TIMERCAPTUREREG when set. + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail (CRC error or invalid CI field) status. + 30 + 1 + read-only + + + RCVOK + Receive data OK status + 31 + 1 + read-only + + + + + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG + INTERRUPT1ENABLEREG register + 0x20 + 0x20 + read-only + 0x00000000 + + + ADDPOINTERROR + Address Pointer Error enable interruption + 4 + 1 + read-only + + + RXOVERFLOWERROR + Rx Overflow Error enable interruption + 5 + 1 + read-only + + + SEQDONE + Sequencer end of task enable interruption + 7 + 1 + read-only + + + TXERROR_0 + Transmission error 0 enable interruption + 8 + 1 + read-only + + + TXERROR_1 + Transmission error 1 enable interruption + 9 + 1 + read-only + + + TXERROR_2 + Transmission error 2 enable interruption + 10 + 1 + read-only + + + TXERROR_3 + Transmission error 3 enable interruption + 11 + 1 + read-only + + + TXERROR_4 + Transmission error 4 enable interruption + 12 + 1 + read-only + + + ENCERROR + Encryption error on receive enable interruption + 13 + 1 + read-only + + + ALLTABLEREADYERROR + All RAM Table not ready enable interruption + 14 + 1 + read-only + + + TXDATAREADYERROR + Transmit data pack not ready enable interruption + 15 + 1 + read-only + + + NOACTIVELERROR + active bit error enable interruption + 16 + 1 + read-only + + + RCVLENGTHERROR + Receive length error enable interruption + 18 + 1 + read-only + + + SEMATIMEOUTERROR + Semaphore timeout error enable interruption + 19 + 1 + read-only + + + TXRXSKIP + Transmission/Reception skip enable interruption + 21 + 1 + read-only + + + ACTIVE2ERROR + Active2 Radio state error enable interruption + 22 + 1 + read-only + + + CONFIGERROR + Data pointer configuration error enable interruption + 23 + 1 + read-only + + + TXOK + Previous transmitted packet received OK enable interruption + 24 + 1 + read-only + + + DONE + Receive/Transmit done interruption + 25 + 1 + read-only + + + RCVTIMEOUT + Receive timeout enable interruption (no preamble found) + 26 + 1 + read-only + + + RCVNOMD + Received MD bit embedded in the PDU data packet header was zero enable interruption + 27 + 1 + read-only + + + RCVCMD + Received command enable interruption + 28 + 1 + read-only + + + TIMECAPTURETRIG + TimerCaptureReg time capture enable interruption + 29 + 1 + read-only + + + RCVCRCERR + Receive data fail enable interruption + 30 + 1 + read-only + + + RCVOK + Receive data OK enable interruption + 31 + 1 + read-only + + + + + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG + INTERRUPT1LATENCYREG register + 0x24 + 0x20 + read-only + 0x00000000 + + + INTERRUPT1LATENCY + relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence. + 0 + 8 + read-only + + + + + MANAESKEY0REG + MANAESKEY0REG + MANAESKEY0REG register + 0x28 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_31_0 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY1REG + MANAESKEY1REG + MANAESKEY1REG register + 0x2c + 0x20 + read-write + 0x00000000 + + + MANAESKEY_63_32 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY2REG + MANAESKEY2REG + MANAESKEY2REG register + 0x30 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_95_64 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESKEY3REG + MANAESKEY3REG + MANAESKEY3REG register + 0x34 + 0x20 + read-write + 0x00000000 + + + MANAESKEY_127_96 + Manual mode AES key + 0 + 32 + read-write + + + + + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG + MANAESCLEARTEXT0REG register + 0x38 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG + MANAESCLEARTEXT1REG register + 0x3c + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG + MANAESCLEARTEXT2REG register + 0x40 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG + MANAESCLEARTEXT3REG register + 0x44 + 0x20 + read-write + 0x00000000 + + + AES + Manual Aes Clear Text + 0 + 32 + read-write + + + + + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG + MANAESCIPHERTEXT0REG register + 0x48 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG + MANAESCIPHERTEXT1REG register + 0x4c + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG + MANAESCIPHERTEXT2REG register + 0x50 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG + MANAESCIPHERTEXT3REG register + 0x54 + 0x20 + read-only + 0x00000000 + + + AES + Manual AES Cipher Text + 0 + 32 + read-only + + + + + MANAESCMDREG + MANAESCMDREG + MANAESCMDREG register + 0x58 + 0x20 + read-write + 0x00000000 + + + START + AES Manual encryption Start command. + 0 + 1 + write-only + + + INTENA + AES Manual encryption interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + + + MANAESSTATREG + MANAESSTATREG + MANAESSTATREG register + 0x5c + 0x20 + read-only + 0x00000000 + + + BUSY + AES manual encryption busy status + 0 + 1 + read-only + + + + + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG + AESLEPRIVPOINTERREG register + 0x60 + 0x20 + read-write + 0x00000000 + + + POINTER + AES Le privacy pointer + 0 + 24 + read-write + + + + + AESLEPRIVHASHREG + AESLEPRIVHASHREG + AESLEPRIVHASHREG register + 0x64 + 0x20 + read-write + 0x00000000 + + + HASH + AES Le privacy Reference Hash + 0 + 24 + read-write + + + + + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG + AESLEPRIVPRANDREG register + 0x68 + 0x20 + read-write + 0x00000000 + + + PRAND + AES Le privacy Prand + 0 + 24 + read-write + + + + + AESLEPRIVCMDREG + AESLEPRIVCMDREG + AESLEPRIVCMDREG register + 0x6c + 0x20 + read-write + 0x00000000 + + + START + AES Le privacy Start command. + 0 + 1 + write-only + + + INTENA + AES Le privacy interrupt enable on Interrupt2Reg + 1 + 1 + read-write + + + NBKEYS + AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list. + 2 + 8 + read-write + + + + + AESLEPRIVSTATREG + AESLEPRIVSTATREG + AESLEPRIVSTATREG register + 0x70 + 0x20 + read-only + 0x00000000 + + + BUSY + AES Le privacy busy status + 0 + 1 + read-only + + + KEYFND + AES Le privacy key finding status + 1 + 1 + read-only + + + KEYFNDINDEX + AES Le privacy index of the key found in the resolution key list. + 2 + 8 + read-only + + + + + STATUS2REG + STATUS2REG + STATUS2REG register + 0x7c + 0x20 + read-only + 0x00000000 + + + IQSAMPLESREADY + indicates if IQ samples have been received on the last reception. + 0 + 1 + read-only + + + IQSAMPLESNUMBER + indicate the number of IQ samples stored in the RAM buffer addressed by StatMach. + 1 + 7 + read-only + + + IQSAMPLESMISSINGERROR + IQ sample internal buffer overflow error flag. + 29 + 1 + read-only + + + ANTENNASWITCHINGPATTERNACCESSERROR + timing error flag related to Antenna Pattern not read on-time. + 30 + 1 + read-only + + + ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR + AHB access error flag. + 31 + 1 + read-only + + + + + + + GLOBALSTATMACH + GLOBALSTATMACH + 0x200000C0 + + 0x0 + 0x1C + registers + + + + WORD0 + WORD0 + WORD0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + RadioConfigPtr + Radio Configuration address Pointer. + 0 + 32 + read-write + + + + + WORD1 + WORD1 + WORD1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + CurStMachNum + current connection machine number. + 0 + 7 + read-write + + + Active + Must be at '1' when the trig event (Wakeup Timer, Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence. + 7 + 1 + read-write + + + WakeupInitDelay + Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM. + 8 + 8 + read-write + + + Timer12InitDelayCal + Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 16 + 8 + read-write + + + Timer2InitDelayNoCal + Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM. + 24 + 8 + read-write + + + + + WORD2 + WORD2 + WORD2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + TransmitCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block. + 0 + 8 + read-write + + + TransmitNoCalDelayChk + Delay between TX request sent to the Radio FSM and the start pulse to the transmit block. + 8 + 8 + read-write + + + ReceiveCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block. + 16 + 8 + read-write + + + ReceiveNoCalDelayChk + Delay between RX request sent to the Radio FSM and the start pulse to the receive block. + 24 + 8 + read-write + + + + + WORD3 + WORD3 + WORD3 register + 0xc + 0x20 + read-write + 0x00000000 + + + ConfigEndDuration + Duration for the Sequencer to execute the final configuration. + 0 + 8 + read-write + + + TxdataReadyCheck + Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table. + 8 + 8 + read-write + + + TxdelayStart + Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator. + 16 + 8 + read-write + + + TxdelayEnd + Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer. + 24 + 6 + read-write + + + TimeCaptureSel + - 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event). + 30 + 1 + read-write + + + TimeCapture + - 0: No capture is requested to monitor the Bluetooth LE sequence. + 31 + 1 + read-write + + + + + WORD4 + WORD4 + WORD4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + TxReadyTimeout + Transmission ready timeout. + 0 + 8 + read-write + + + RcvTimeout + Receive window timeout. + 8 + 20 + read-write + + + + + WORD5 + WORD5 + WORD5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + AutoTxRxskipEn + Automatic transfer (TX or RX) skip enable. + 0 + 1 + read-write + + + ChkFlagAutoClearEna + Active bit Auto Clear Enable. + 2 + 1 + read-write + + + IntAddPointError + Address pointer error interrupt enable. + 20 + 1 + read-write + + + IntAllTableReadyError + All table ready error interrupt enable. + 21 + 1 + read-write + + + IntTxDataReadyError + Transmission data payload ready error interrupt enable. + 22 + 1 + read-write + + + IntNoActiveLError + Active bit low value reading interrupt enable. + 23 + 1 + read-write + + + IntRcvLengthError + Too long received payload length interrupt enable. + 25 + 1 + read-write + + + IntSemaTimeoutError + Semaphore timeout error interrupt enable. + 26 + 1 + read-write + + + IntSeqDone + Sequencer end of task interrupt enable. + 28 + 1 + read-write + + + intTxRxSkip + Transmission or reception skip interrupt enable. + 29 + 1 + read-write + + + IntActive2Err + not in ACTIVE2 information from Radio FSM received on time interrupt enable. + 30 + 1 + read-write + + + IntConfigError + Configuration error interrupt enable. + 31 + 1 + read-write + + + + + WORD6 + WORD6 + WORD6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + DefaultAntennaID + Default Antenna ID corresponding to the number of the antenna used to receive/transmit: + + 0 + 7 + + + + + + + RADIO_CONTROL + RADIO_CONTROL + 0x60001000 + + 0x0 + 0x400 + registers + + + + RADIO_CONTROL_ID + RADIO_CONTROL_ID + RADIO_CONTROL_ID register + 0x0 + 0x20 + read-only + 0x00003000 + + + REVISION + Incremented for metal fix version + 4 + 4 + read-only + + + VERSION + Cut Number + 8 + 4 + read-only + + + PRODUCT + incremented on major features add-on like new Bluetooth LE SIG version support + + 12 + 4 + read-only + + + + + CLK32COUNT_REG + CLK32COUNT_REG + CLK32COUNT_REG register + 0x4 + 0x20 + read-write + 0x00000017 + + + SLOW_COUNT + program the window length (in slow clock period) for slow clock measurement. + 0 + 9 + read-write + + + + + CLK32PERIOD_REG + CLK32PERIOD_REG + CLK32PERIOD_REG register + 0x8 + 0x20 + read-only + 0x00000000 + + + SLOW_PERIOD + indicates slow clock period information. + 0 + 19 + read-only + + + + + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG + CLK32FREQUENCY_REG register + 0xc + 0x20 + read-only + 0x00000000 + + + SLOW_FREQUENCY + value equal to (2^39/ SLOW_PERIOD). + 0 + 27 + read-only + + + + + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS + RADIO_CONTROL_IRQ_STATUS register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ + slow clock measurement end of calculation interrupt status + + 0 + 1 + read-write + + + RADIO_FSM_IRQ + Radio FSM interrupt status (aka RfFsm_event_irq). + 8 + 6 + read-write + + + + + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE + RADIO_CONTROL_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLOW_CLK_IRQ_MASK + mask slow clock measurement interrupt + + 0 + 1 + read-write + + + RADIO_FSM_IRQ_MASK + mask for each RfFsm_event (Radio FSM) interrupt. + 8 + 6 + read-write + + + + + + + RADIO + RADIO + 0x60001500 + + 0x0 + 0x300 + registers + + + RADIO_TXRX + RADIO Tx/Rx interrupt + 18 + + + RADIO_ERROR + RADIO Error interrupt + 20 + + + RADIO_CPU_WKUP + RADIO CPU Wakeup interrupt + 23 + + + RADIO_TXRX_WKUP + RADIO Wakeup interrupt + 24 + + + RADIO_TXRX_SEQ + RADIO RX/TX sequence interrupt + 25 + + + + AA0_DIG_USR + AA0_DIG_USR + AA0_DIG_USR register + 0x0 + 0x20 + read-write + 0x000000D6 + + + AA_7_0 + Least significant byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA1_DIG_USR + AA1_DIG_USR + AA1_DIG_USR register + 0x4 + 0x20 + read-write + 0x000000BE + + + AA_15_8 + Next byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + AA2_DIG_USR + AA2_DIG_USR + AA2_DIG_USR register + 0x8 + 0x20 + read-write + 0x00000089 + + + AA_23_16 + Next byte of the Bluetooth LE Access Address code + + 0 + 8 + read-write + + + + + AA3_DIG_USR + AA3_DIG_USR + AA3_DIG_USR register + 0xc + 0x20 + read-write + 0x0000008E + + + AA_31_24 + Most significant byte of the Bluetooth LE Access Address code. + 0 + 8 + read-write + + + + + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR + DEM_MOD_DIG_USR register + 0x10 + 0x20 + read-write + 0x00000026 + + + CHANNEL_NUM + Index for internal lock up table in which the synthesizer setup is contained. + 1 + 7 + read-write + + + + + RADIO_FSM_USR + RADIO_FSM_USR + RADIO_FSM_USR register + 0x14 + 0x20 + read-write + 0x00000004 + + + EN_CALIB_CBP + CBP calibration enable bit. + 1 + 1 + read-write + + + EN_CALIB_SYNTH + SYNTH calibration enable bit. + 2 + 1 + read-write + + + PA_POWER + PA Power coefficient. + 3 + 5 + read-write + + + + + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR + PHYCTRL_DIG_USR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RXTXPHY + RXTXPHY selection. + 0 + 3 + read-write + + + + + AFC1_DIG_ENG + AFC1_DIG_ENG + AFC1_DIG_ENG register + 0x48 + 0x20 + read-write + 0x00000044 + + + AFC_DELAY_AFTER + Set the decay factor of the AFC loop after Access Address detection + 0 + 4 + read-write + + + AFC_DELAY_BEFORE + Set the decay factor of the AFC loop before Access Address detection + 4 + 4 + read-write + + + + + CR0_DIG_ENG + CR0_DIG_ENG + CR0_DIG_ENG register + 0x54 + 0x20 + read-write + 0x00000044 + + + CR_GAIN_AFTER + Set the gain of the clock recovery loop before Access Address detection to the value + + 0 + 4 + read-write + + + CR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value + + 4 + 4 + read-write + + + + + CR0_LR + CR0_LR + CR0_LR register + 0x68 + 0x20 + read-write + 0x00000066 + + + CR_LR_GAIN_AFTER + Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use + 0 + 4 + read-write + + + CR_LR_GAIN_BEFORE + Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use + 4 + 4 + read-write + + + + + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG + VIT_CONF_DIG_ENG register + 0x6c + 0x20 + read-write + 0x00000000 + + + VIT_EN + Viterbi enable + + 0 + 1 + read-write + + + SPARE + spare + 2 + 6 + read-write + + + + + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG + LR_PD_THR_DIG_ENG register + 0x84 + 0x20 + read-write + 0x00000050 + + + LR_PD_THR + preamble detect threshold value + 0 + 8 + read-write + + + + + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG + LR_RSSI_THR_DIG_ENG register + 0x88 + 0x20 + read-write + 0x0000001B + + + LR_RSSI_THR + RSSI or peak threshold value + 0 + 8 + read-write + + + + + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG + LR_AAC_THR_DIG_ENG register + 0x8c + 0x20 + read-write + 0x00000038 + + + LR_AAC_THR + address coded correlation threshold + 0 + 8 + read-write + + + + + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG + SYNTHCAL0_DIG_ENG register + 0xa8 + 0x20 + read-write + 0x00000000 + + + SYNTHCAL_DEBUG_BUS_SEL + for Debug purpose + + 0 + 4 + read-write + + + SYNTH_IF_FREQ_CAL + Define the frequency applied on the PLL during calibration phase + + 6 + 2 + read-write + + + + + DTB5_DIG_ENG + DTB5_DIG_ENG + DTB5_DIG_ENG register + 0xf0 + 0x20 + read-write + 0x00000000 + + + RXTX_START_SEL + enable the possibility to control some signals by the other register bits instead of system design: + + 0 + 1 + read-write + + + TX_ACTIVE + Force TX_ACTIVE signal + 1 + 1 + read-write + + + RX_ACTIVE + Force RX_ACTIVE signal + 2 + 1 + read-write + + + INITIALIZE + Force INITIALIZE signal (emulate a token request of the IP_BLE) + 3 + 1 + read-write + + + PORT_SELECTED_EN + enable port selection + 4 + 1 + read-write + + + PORT_SELECTED_0 + force port_selected[0] signal + 5 + 1 + read-write + + + + + RXADC_ANA_USR + RXADC_ANA_USR + RXADC_ANA_USR register + 0x148 + 0x20 + read-write + 0x0000001B + + + RFD_RXADC_DELAYTRIM_I + ADC loop delay control bits for I channel to apply when SW overload is enabled + 0 + 3 + read-write + + + RFD_RXADC_DELAYTRIM_Q + ADC loop delay control bits for Q channel to apply when SW overload is enabled + 3 + 3 + read-write + + + RXADC_DELAYTRIM_I_TST_SEL + Enable the SW overload on RXADX delay trimming + + 6 + 1 + read-write + + + RXADC_DELAYTRIM_Q_TST_SEL + Enable the SW overload on RXADX delay trimming + + 7 + 1 + read-write + + + + + LDO_ANA_ENG + LDO_ANA_ENG + LDO_ANA_ENG register + 0x154 + 0x20 + read-write + 0x00000000 + + + RFD_RF_REG_BYPASS + RF_REG Bypass mode: + + 0 + 1 + read-write + + + + + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG + CBIAS0_ANA_ENG register + 0x174 + 0x20 + read-write + 0x00000088 + + + RFD_CBIAS_IBIAS_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 0 + 4 + read-write + + + RFD_CBIAS_IPTAT_TRIM + overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1) + 4 + 4 + read-write + + + + + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG + CBIAS1_ANA_ENG register + 0x178 + 0x20 + read-write + 0x00000000 + + + CBIAS0_TRIM_TST_SEL + When set, RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings + 7 + 1 + read-write + + + + + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT + SYNTHCAL0_DIG_OUT register + 0x180 + 0x20 + read-only + 0x00000000 + + + VCO_CALAMP_OUT_6_0 + VCO CALAMP value + 0 + 7 + read-only + + + + + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT + SYNTHCAL1_DIG_OUT register + 0x184 + 0x20 + read-only + 0x00000001 + + + VCO_CALAMP_OUT_10_7 + VCO CALAMP value + 0 + 4 + read-only + + + + + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT + SYNTHCAL2_DIG_OUT register + 0x188 + 0x20 + read-only + 0x00000040 + + + VCO_CALFREQ_OUT + VCO CALFREQ value + 0 + 7 + read-only + + + + + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT + SYNTHCAL3_DIG_OUT register + 0x18c + 0x20 + read-only + 0x00000000 + + + SYNTHCAL_DEBUG_BUS + Calibration debug bus. + 0 + 8 + read-only + + + + + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT + SYNTHCAL4_DIG_OUT register + 0x190 + 0x20 + read-only + 0x00000018 + + + MOD_REF_DAC_WORD_OUT + Calibration word + 0 + 6 + read-only + + + + + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT + SYNTHCAL5_DIG_OUT register + 0x194 + 0x20 + read-only + 0x00000007 + + + CBP_CALIB_WORD + CBP Calibration word + 0 + 4 + read-only + + + + + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT + FSM_STATUS_DIG_OUT register + 0x198 + 0x20 + read-only + 0x00000000 + + + STATUS + RF FSM state: + + 0 + 5 + read-only + + + SYNTH_CAL_ERROR + PLL calibration error + 7 + 1 + read-only + + + + + RSSI0_DIG_OUT + RSSI0_DIG_OUT + RSSI0_DIG_OUT register + 0x1a4 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_7_0 + Measure of the received signal strength. + 0 + 8 + read-only + + + + + RSSI1_DIG_OUT + RSSI1_DIG_OUT + RSSI1_DIG_OUT register + 0x1a8 + 0x20 + read-only + 0x00000008 + + + RSSI_MEAS_OUT_15_8 + Measure of the received signal strength + 0 + 8 + read-only + + + + + AGC_DIG_OUT + AGC_DIG_OUT + AGC_DIG_OUT register + 0x1ac + 0x20 + read-only + 0x00000000 + + + AGC_ATT_OUT + AGC attenuation value + 0 + 4 + read-only + + + + + DEMOD_DIG_OUT + DEMOD_DIG_OUT + DEMOD_DIG_OUT register + 0x1b0 + 0x20 + read-only + 0x00000000 + + + CI_FIELD + CI field + 0 + 2 + read-only + + + AAC_FOUND + aac_found + 2 + 1 + read-only + + + PD_FOUND + pd_found + 3 + 1 + read-only + + + RX_END + rx_end + 4 + 1 + read-only + + + + + AGC2_ANA_TST + AGC2_ANA_TST + AGC2_ANA_TST register + 0x1bc + 0x20 + read-write + 0x00000000 + + + AGC2_ANA_TST_SEL + Selection: + + 0 + 1 + read-write + + + AGC_ANTENNAE_USR_TRIM + the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1) + 1 + 3 + read-write + + + + + AGC0_DIG_ENG + AGC0_DIG_ENG + AGC0_DIG_ENG register + 0x1c0 + 0x20 + read-write + 0x0000004A + + + AGC_THR_HIGH + High AGC threshold + 0 + 6 + read-write + + + AGC_ENABLE + Enable AGC + 6 + 1 + read-write + + + + + AGC1_DIG_ENG + AGC1_DIG_ENG + AGC1_DIG_ENG register + 0x1c4 + 0x20 + read-write + 0x00000084 + + + AGC_THR_LOW_6 + Low threshold for 6dB steps + 0 + 6 + read-write + + + AGC_AUTOLOCK + AGC locks when level is steady between high threshold and lock threshold + 6 + 1 + read-write + + + AGC_LOCK_SYNC + AGC locks when Access Address is detected (recommended) + 7 + 1 + read-write + + + + + AGC10_DIG_ENG + AGC10_DIG_ENG + AGC10_DIG_ENG register + 0x1e8 + 0x20 + read-write + 0x00000000 + + + ATT_IF_0 + Attenuation at IF Level for the AGC step 0: + + 0 + 3 + read-write + + + ATT_LNA_0 + Attenuation at LNA Level for the AGC step 0: + + 3 + 1 + read-write + + + ATT_ANT_0 + Attenuation at Antenna Level for the AGC step 0: + + 4 + 2 + read-write + + + + + AGC11_DIG_ENG + AGC11_DIG_ENG + AGC11_DIG_ENG register + 0x1ec + 0x20 + read-write + 0x00000010 + + + ATT_IF_1 + Attenuation at IF Level for the AGC step 1 + 0 + 3 + read-write + + + ATT_LNA_1 + Attenuation at LNA Level for the AGC step 1 + 3 + 1 + read-write + + + ATT_ANT_1 + Attenuation at Antenna Level for the AGC step 1 + 4 + 2 + read-write + + + + + AGC12_DIG_ENG + AGC12_DIG_ENG + AGC12_DIG_ENG register + 0x1f0 + 0x20 + read-write + 0x000000020 + + + ATT_IF_2 + Attenuation at IF Level for the AGC step 2 + 0 + 3 + read-write + + + ATT_LNA_2 + Attenuation at LNA Level for the AGC step 2 + 3 + 1 + read-write + + + ATT_ANT_2 + Attenuation at Antenna Level for the AGC step 2 + 4 + 2 + read-write + + + + + AGC13_DIG_ENG + AGC13_DIG_ENG + AGC13_DIG_ENG register + 0x1f4 + 0x20 + read-write + 0x00000030 + + + ATT_IF_3 + Attenuation at IF Level for the AGC step 3 + 0 + 3 + read-write + + + ATT_LNA_3 + Attenuation at LNA Level for the AGC step 3 + 3 + 1 + read-write + + + ATT_ANT_3 + Attenuation at Antenna Level for the AGC step 3 + 4 + 2 + read-write + + + + + AGC14_DIG_ENG + AGC14_DIG_ENG + AGC14_DIG_ENG register + 0x1f8 + 0x20 + read-write + 0x00000038 + + + ATT_IF_4 + Attenuation at IF Level for the AGC step 4 + 0 + 3 + read-write + + + ATT_LNA_4 + Attenuation at LNA Level for the AGC step 4 + 3 + 1 + read-write + + + ATT_ANT_4 + Attenuation at Antenna Level for the AGC step 4 + 4 + 2 + read-write + + + + + AGC15_DIG_ENG + AGC15_DIG_ENG + AGC15_DIG_ENG register + 0x1fc + 0x20 + read-write + 0x00000039 + + + ATT_IF_5 + Attenuation at IF Level for the AGC step 5 + 0 + 3 + read-write + + + ATT_LNA_5 + Attenuation at LNA Level for the AGC step 5 + 3 + 1 + read-write + + + ATT_ANT_5 + Attenuation at Antenna Level for the AGC step 5 + 4 + 2 + read-write + + + + + AGC16_DIG_ENG + AGC16_DIG_ENG + AGC16_DIG_ENG register + 0x200 + 0x20 + read-write + 0x0000003A + + + ATT_IF_6 + Attenuation at IF Level for the AGC step 6 + 0 + 3 + read-write + + + ATT_LNA_6 + Attenuation at LNA Level for the AGC step 6 + 3 + 1 + read-write + + + ATT_ANT_6 + Attenuation at Antenna Level for the AGC step 6 + 4 + 2 + read-write + + + + + AGC17_DIG_ENG + AGC17_DIG_ENG + AGC17_DIG_ENG register + 0x204 + 0x20 + read-write + 0x0000003B + + + ATT_IF_7 + Attenuation at IF Level for the AGC step 7 + 0 + 3 + read-write + + + ATT_LNA_7 + Attenuation at LNA Level for the AGC step 7 + 3 + 1 + read-write + + + ATT_ANT_7 + Attenuation at Antenna Level for the AGC step 7 + 4 + 2 + read-write + + + + + AGC18_DIG_ENG + AGC18_DIG_ENG + AGC18_DIG_ENG register + 0x208 + 0x20 + read-write + 0x0000003C + + + ATT_IF_8 + Attenuation at IF Level for the AGC step 8 + 0 + 3 + read-write + + + ATT_LNA_8 + Attenuation at LNA Level for the AGC step 8 + 3 + 1 + read-write + + + ATT_ANT_8 + Attenuation at Antenna Level for the AGC step 8 + 4 + 2 + read-write + + + + + AGC19_DIG_ENG + AGC19_DIG_ENG + AGC19_DIG_ENG register + 0x20c + 0x20 + read-write + 0x0000003D + + + ATT_IF_9 + Attenuation at IF Level for the AGC step 9 + 0 + 3 + read-write + + + ATT_LNA_9 + Attenuation at LNA Level for the AGC step 9 + 3 + 1 + read-write + + + ATT_ANT_9 + Attenuation at Antenna Level for the AGC step 9 + 4 + 2 + read-write + + + + + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT + RXADC_HW_TRIM_OUT register + 0x224 + 0x20 + read-only + 0x0000001B + + + HW_RXADC_DELAYTRIM_I + control bits of the RX ADC loop delay for I channel (provided by the HW trimming, automatically loaded on POR). + 0 + 3 + read-only + + + HW_RXADC_DELAYTRIM_Q + control bits of the RX ADC loop delay for Q channel (provided by the HW trimming, automatically loaded on POR). + 3 + 3 + read-only + + + + + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT + CBIAS0_HW_TRIM_OUT register + 0x228 + 0x20 + read-only + 0x00000088 + + + HW_CBIAS_IBIAS_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 0 + 4 + read-only + + + HW_CBIAS_IPTAT_TRIM + CBIAS current (provided by the HW trimming, automatically loaded on POR). + 4 + 4 + read-only + + + + + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT + AGC_HW_TRIM_OUT register + 0x230 + 0x20 + read-only + 0x00000006 + + + HW_AGC_ANTENNAE_TRIM + AGC trim value (provided by the HW trimming, automatically loaded on POR). + 1 + 3 + read-only + + + + + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST + DEMOD_IQ2_DIG_TST register + 0x23c + 0x20 + read-write + 0x00000000 + + + EXTCFG_SAMPLING_TIME + Defines the sampling time, when extended configuration is enabled: + + 0 + 2 + read-write + + + EXTCFG_TRIG_SELECTION + Defines the trigger/anchor point of the IQ sampling, when extended configuration is enabled: + + 2 + 2 + read-write + + + + + ANTSW0_DIG_USR + ANTSW0_DIG_USR + ANTSW0_DIG_USR register + 0x240 + 0x20 + read-write + 0x0000001C + + + RX_TIME_TO_SAMPLE + specifies the exact timing of the first I/Q sampling in the reference period. + 0 + 7 + read-write + + + + + ANTSW1_DIG_USR + ANTSW1_DIG_USR + ANTSW1_DIG_USR register + 0x244 + 0x20 + read-write + 0x0000000B + + + RX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching at receiver level (in AoA). + 0 + 6 + read-write + + + + + ANTSW2_DIG_USR + ANTSW2_DIG_USR + ANTSW2_DIG_USR register + 0x248 + 0x20 + read-write + 0x00000029 + + + TX_TIME_TO_SWITCH + specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD). + 0 + 7 + read-write + + + + + ANTSW3_DIG_USR + ANTSW3_DIG_USR + ANTSW3_DIG_USR register + 0x24c + 0x20 + read-write + 0x00000023 + + + TX_TIME_TO_SWITCH_2M + specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD). + 0 + 7 + read-write + + + + + + + RRM + RRM + 0x60001400 + + 0x0 + 0x100 + registers + + + + UDRA_CTRL0 + UDRA_CTRL0 + UDRA_CTRL0 register + 0x10 + 0x20 + read-write + 0x00000000 + + + RELOAD_RDCFGPTR + reload the radio configuration pointer from RAM. + 0 + 1 + read-write + + + + + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE + UDRA_IRQ_ENABLE register + 0x14 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + UDRA interrupt enable (reload radio config pointer) + 0 + 1 + read-write + + + CMD_START + UDRA interrupt enable (command start) + 1 + 1 + read-write + + + CMD_END + UDRA interrupt enable (command end) + 2 + 1 + read-write + + + + + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS + UDRA_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + RADIO_CFG_PTR_RELOADED + On read, returns the UDRA reload radio configuration pointer interrupt status. + 0 + 1 + read-write + + + CMD_STARD + On read, returns the UDRA command start interrupt status. + 1 + 1 + read-write + + + CMD_END + On read, returns the UDRA command end interrupt status + + 2 + 1 + read-write + + + + + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR + UDRA_RADIO_CFG_PTR register + 0x1c + 0x20 + read-only + 0x00000000 + + + RADIO_CONFIG_ADDRESS + UDRA radio configuration address. + 0 + 32 + read-only + + + + + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE + SEMA_IRQ_ENABLE register + 0x20 + 0x20 + read-write + 0x00000000 + + + LOCK + semaphore locked (= one port granted) interrupt enable + 0 + 1 + read-write + + + UNLOCK + semaphore unlocked (=no port selected) interrupt enable + 1 + 1 + read-write + + + + + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS + SEMA_IRQ_STATUS register + 0x24 + 0x20 + read-write + 0x00000000 + + + LOCK + On read, returns the semaphore locked interrupt status. + 0 + 1 + read-write + + + UNLOCK + On read, returns the semaphore unlocked interrupt status. + 1 + 1 + read-write + + + + + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE + BLE_IRQ_ENABLE register + 0x28 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE Port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE Port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + IP_BLE Port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + IP_BLE Port command end interrup enable + 4 + 1 + read-write + + + + + BLE_IRQ_STATUS + BLE_IRQ_STATUS + BLE_IRQ_STATUS register + 0x2c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + IP_BLE hardware port granted interrupt status: + + 0 + 1 + read-write + + + PORT_RELEASE + IP_BLE hardware port released interrupt status. + 1 + 1 + read-write + + + CMD_START + IP_BLE hardware port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + IP_BLE hardware port command end interrupt status. + 4 + 1 + read-write + + + + + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS + VP_CPU_CMD_BUS register + 0x60 + 0x20 + read-write + 0x00000000 + + + COMMAND + command number + 0 + 3 + read-write + + + COMMAND_REQ + CPU Virtual port command request: + + 3 + 1 + read-write + + + + + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS + VP_CPU_SEMA_BUS register + 0x64 + 0x20 + read-write + 0x00000000 + + + TAKE_PRIO + semaphore priority: priority value (between 0 and 7) of the take request. + 0 + 3 + read-write + + + TAKE_REQ + semaphore token request: + + 3 + 1 + read-write + + + + + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE + VP_CPU_IRQ_ENABLE register + 0x68 + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port grant interrupt enable + 0 + 1 + read-write + + + PORT_RELEASE + CPU virtual port release interrupt enable + 1 + 1 + read-write + + + PORT_CMD_START + CPU virtual port command start interrup enable + 3 + 1 + read-write + + + PORT_CMD_END + CPU virtual port command end interrup enable + 4 + 1 + read-write + + + + + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS + VP_CPU_IRQ_STATUS register + 0x6c + 0x20 + read-write + 0x00000000 + + + PORT_GRANT + CPU virtual port granted interrupt status. + 0 + 1 + read-write + + + PORT_RELEASE + virtual port released interrupt status. + 1 + 1 + read-write + + + PORT_PREEMPT + CPU virtual port preemption (at semaphore level) interrupt status. + 2 + 1 + read-write + + + CMD_START + CPU virtual port command start interrupt status. + 3 + 1 + read-write + + + CMD_END + CPU virtual port command end interrupt status. + 4 + 1 + read-write + + + + + + + WAKEUP + WAKEUP + 0x60001800 + + 0x0 + 0x400 + registers + + + + WAKEUP_OFFSET + WAKEUP_OFFSET + WAKEUP_OFFSET register + 0x8 + 0x20 + read-write + 0x00000000 + + + WAKEUP_OFFSET + delay of anticipation of the Soc device to settle power and clock + + 0 + 8 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0x10 + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + absolute time + + 0 + 32 + read-only + + + + + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH + MINIMUM_PERIOD_LENGTH register + 0x14 + 0x20 + read-only + 0x00000000 + + + LENGTH + minimum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH + AVERAGE_PERIOD_LENGTH register + 0x18 + 0x20 + read-only + 0x00000000 + + + LENGTH_FRACT + additional information/precision on slow clock frequency. + 0 + 4 + read-only + + + LENGTH_INT + average period length computed by Time Interpolator. + 4 + 10 + read-only + + + AVERAGE_COUNT + Number of slow clock cycles. + 24 + 8 + read-only + + + + + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH + MAXIMUM_PERIOD_LENGTH register + 0x1c + 0x20 + read-only + 0x00000000 + + + LENGTH + maximum period length computed by Time Interpolator + 4 + 10 + read-only + + + + + STATISTICS_RESTART + STATISTICS_RESTART + STATISTICS_RESTART register + 0x20 + 0x20 + read-write + 0x00000000 + + + CLR_MIN_MAX + Write '1' to clear the minimum and maximum registers. + 0 + 1 + read-write + + + CLR_AVR + Write '1' to clear the AVERAGE_PERIOD_LENGTH register value. + 1 + 1 + read-write + + + + + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME + BLUE_WAKEUP_TIME register + 0x24 + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for the IP_BLE. + 0 + 32 + read-write + + + + + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE + BLUE_SLEEP_REQUEST_MODE register + 0x28 + 0x20 + read-write + 0x00000007 + + + SLEEP_EN + IP_BLE sleeping mode enable: + + 29 + 1 + read-write + + + BLE_WAKEUP_EN + IP_BLE wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + IP_BLE sleeping control: + + 31 + 1 + read-write + + + + + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME + CM0_WAKEUP_TIME register + 0x2c + 0x20 + read-write + 0x00000000 + + + WAKEUP_TIME + programmed wakeup time for CPU. + 4 + 28 + read-write + + + + + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE + CM0_SLEEP_REQUEST_MODE register + 0x30 + 0x20 + read-write + 0x80000007 + + + CPU_WAKEUP_EN + CPU wakeup enable: + + 30 + 1 + read-write + + + FORCE_SLEEPING + CPU sleeping control: + + 31 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE + WAKEUP_BLE_IRQ_ENABLE register + 0x40 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + IP_BLE wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS + WAKEUP_BLE_IRQ_STATUS register + 0x44 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the IP_BLE wakeup interrupt status. + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE + WAKEUP_CM0_IRQ_ENABLE register + 0x48 + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + CPU wakeup interrupt enable: + + 0 + 1 + read-write + + + + + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS + WAKEUP_CM0_IRQ_STATUS register + 0x4c + 0x20 + read-write + 0x00000000 + + + WAKEUP_IT + On read, returns the CPU wakeup interrupt status. + 0 + 1 + read-write + + + + + + + \ No newline at end of file diff --git a/svd/STM32WLxx/STM32WL5x_CM0P.svd b/svd/STM32WLxx/STM32WL5x_CM0P.svd index 6923da7..baba3c8 100644 --- a/svd/STM32WLxx/STM32WL5x_CM0P.svd +++ b/svd/STM32WLxx/STM32WL5x_CM0P.svd @@ -1,6 +1,6 @@ STM32WL5x_CM0P - 2.0 + 2.1 STM32WL5x_CM0P CM0 diff --git a/svd/STM32WLxx/STM32WL5x_CM4.svd b/svd/STM32WLxx/STM32WL5x_CM4.svd index 7aa9da4..e6fb498 100644 --- a/svd/STM32WLxx/STM32WL5x_CM4.svd +++ b/svd/STM32WLxx/STM32WL5x_CM4.svd @@ -1,6 +1,6 @@ STM32WL5x_CM4 - 2.0 + 2.2 STM32WL5x_CM4 CM4 r0p1 little true - true + false 4 false diff --git a/svd/STM32WLxx/STM32WLE5_CM4.svd b/svd/STM32WLxx/STM32WLE5_CM4.svd index 9563ea0..93d1b8f 100644 --- a/svd/STM32WLxx/STM32WLE5_CM4.svd +++ b/svd/STM32WLxx/STM32WLE5_CM4.svd @@ -1,6 +1,6 @@ STM32WLE5_CM4 - 1.4 - STM32WLE5_CM4 + 1.6 + STM32WLE5_CM4 CM4 r0p1 little true - true + false 4 false - - 8 - 32 + + 8 + 32 0x20 0x0 0xFFFFFFFF @@ -1243,7 +1243,7 @@ Copyright (c) 2020 STMicroelectronics. - + COMP Comparator @@ -1674,7 +1674,7 @@ Copyright (c) 2020 STMicroelectronics. 0x4 0x20 0x00000000 - + SWTRIG1 DAC channel1 software trigger @@ -1884,7 +1884,7 @@ Copyright (c) 2020 STMicroelectronics. 10 - + SHHR SHHR @@ -1918,7 +1918,7 @@ Copyright (c) 2020 STMicroelectronics. 8 - + @@ -2065,7 +2065,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + APB2FZR APB2FZR @@ -2094,7 +2094,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + @@ -3606,7 +3606,7 @@ Copyright (c) 2020 STMicroelectronics. 32 - + @@ -4829,7 +4829,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + @@ -5003,7 +5003,7 @@ Copyright (c) 2020 STMicroelectronics. Rising trigger event configuration bit of Configurable Event input 2 1 - + RT45 Rising trigger event configuration bit of Configurable Event input @@ -5238,7 +5238,7 @@ Copyright (c) 2020 STMicroelectronics. Wakeup with event generation Mask on Event input 22 1 - + @@ -5269,7 +5269,7 @@ Copyright (c) 2020 STMicroelectronics. 5 - + @@ -5347,7 +5347,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + KEYR KEYR @@ -5614,7 +5614,7 @@ Copyright (c) 2020 STMicroelectronics. 24 1 read-write - + ECCC ECC correction @@ -5735,7 +5735,7 @@ Copyright (c) 2020 STMicroelectronics. CPU1 CM4 Unique Boot entry enable option bit 30 1 - + @@ -5858,7 +5858,7 @@ Copyright (c) 2020 STMicroelectronics. 8 - + @@ -10393,7 +10393,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + HSEM_ICR HSEM_ICR @@ -10500,7 +10500,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + HSEM_ISR HSEM_ISR @@ -10607,7 +10607,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + HSEM_MISR HSEM_MISR @@ -10714,7 +10714,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + HSEM_CR HSEM_CR @@ -10754,7 +10754,7 @@ Copyright (c) 2020 STMicroelectronics. 16 - + @@ -11508,7 +11508,7 @@ Copyright (c) 2020 STMicroelectronics. 12 - + @@ -12861,7 +12861,7 @@ Copyright (c) 2020 STMicroelectronics. Word length 28 1 - + DEAT DEAT @@ -12987,7 +12987,7 @@ Copyright (c) 2020 STMicroelectronics. Word length 28 1 - + DEAT DEAT @@ -13091,8 +13091,8 @@ Copyright (c) 2020 STMicroelectronics. USART enable 0 1 - - + + CR2 @@ -13108,7 +13108,7 @@ Copyright (c) 2020 STMicroelectronics. Address of the LPUART node 24 8 - + MSBFIRST Most significant bit first @@ -13150,7 +13150,7 @@ Copyright (c) 2020 STMicroelectronics. 7-bit Address Detection/4-bit Address Detection 4 1 - + @@ -13688,4067 +13688,3042 @@ Copyright (c) 2020 STMicroelectronics. - MPU - Memory protection unit - MPU - 0xE000ED90 + PKA + Public key accelerator + PKA + 0x58002000 0x0 - 0x15 + 0x2000 registers + + PKA + Private key accelerator + interrupt + 53 + - MPU_TYPER - MPU_TYPER - MPU type register + CR + CR + control register 0x0 0x20 - read-only - 0X00000800 + read-write + 0x00000000 - SEPARATE - Separate flag - 0 + ADDRERRIE + Address error interrupt enable + 20 1 - DREGION - Number of MPU data regions - 8 - 8 + RAMERRIE + RAM error interrupt enable + 19 + 1 - IREGION - Number of MPU instruction regions - 16 - 8 + PROCENDIE + PROCENDIE + 17 + 1 - - - - MPU_CTRL - MPU_CTRL - MPU control register - 0x4 - 0x20 - read-only - 0X00000000 - - ENABLE - Enables the MPU - 0 - 1 + MODE + PKA operation code + 8 + 6 - HFNMIENA - Enables the operation of MPU during hard fault + START + start the operation 1 1 - PRIVDEFENA - Enable priviliged software access to default memory map - 2 + EN + PKA enable. + 0 1 - MPU_RNR - MPU_RNR - MPU region number register - 0x8 + SR + SR + status register + 0x4 0x20 - read-write - 0X00000000 + read-only + 0x00000000 - REGION - MPU region - 0 - 8 + ADDRERRF + Address error flag + 20 + 1 - - - - MPU_RBAR - MPU_RBAR - MPU region base address register - 0xC - 0x20 - read-write - 0X00000000 - - REGION - MPU region field - 0 - 4 + RAMERRF + PKA RAM error flag + 19 + 1 - VALID - MPU region number valid - 4 + PROCENDF + PKA End of Operation flag + 17 1 - ADDR - Region base address field - 5 - 27 + BUSY + PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. + 16 + 1 - MPU_RASR - MPU_RASR - MPU region attribute and size register - 0x10 + CLRFR + CLRFR + clear flag register + 0x8 0x20 - read-write - 0X00000000 + write-only + 0x00000000 - ENABLE - Region enable bit. - 0 + ADDRERRFC + Clear Address error flag + 20 1 - SIZE - Size of the MPU protection region - 1 - 5 - - - SRD - Subregion disable bits - 8 - 8 - - - B - memory attribute - 16 + RAMERRFC + Clear PKA RAM error flag + 19 1 - C - memory attribute + PROCENDFC + Clear PKA End of Operation flag 17 1 - - - S - Shareable memory attribute - 18 - 1 - - - TEX - memory attribute - 19 - 3 - - - AP - Access permission - 24 - 3 - - - XN - Instruction access disable bit - 28 - 1 - + - NVIC - Nested Vectored Interrupt Controller - NVIC - 0xE000E100 + PWR + Power control + PWR + 0x58000400 0x0 - 0x355 + 0x400 registers + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00000200 + + + LPR + Low-power run + 14 + 1 + + + VOS + Voltage scaling range selection + 9 + 2 + + + DBP + Disable backup domain write protection + 8 + 1 + + + FPDS + Flash memory power down mode during LPSleep for CPU1 + 5 + 1 + + + FPDR + Flash memory power down mode during LPRun for CPU1 + 4 + 1 + + + SUBGHZSPINSSSEL + sub-GHz SPI NSS source select + 3 + 1 + + + LPMS + Low-power mode selection for CPU1 + 0 + 3 + + + - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x0 + CR2 + CR2 + Power control register 2 + 0x4 0x20 read-write 0x00000000 - SETENA - SETENA - 0 - 32 + PVME3 + Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + 6 + 1 + + + PLS + Power voltage detector level selection. + 1 + 3 - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x4 - 0x20 - read-write - 0x00000000 - - SETENA - SETENA + PVDE + Power voltage detector enable 0 - 32 + 1 - ICER0 - ICER0 - Interrupt Clear-Enable Register - 0x80 + CR3 + CR3 + Power control register 3 + 0x8 0x20 read-write - 0x00000000 + 0x00008000 - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable Register - 0x84 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 + EIWUL + Enable internal wakeup line for CPU1 + 15 + 1 - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x104 - 0x20 - read-write - 0x00000000 - - SETPEND - SETPEND - 0 - 32 + EWRFIRQ + akeup for CPU1 + 13 + 1 - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending Register - 0x180 - 0x20 - read-write - 0x00000000 - - CLRPEND - CLRPEND - 0 - 32 + EWRFBUSY + Enable Radio BUSY Wakeup from Standby for CPU1 + 11 + 1 - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending Register - 0x184 - 0x20 - read-write - 0x00000000 - - CLRPEND - CLRPEND - 0 - 32 + APC + Apply pull-up and pull-down configuration from CPU1 + 10 + 1 - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x200 - 0x20 - read-only - 0x00000000 - - ACTIVE - ACTIVE - 0 - 32 + RRS + SRAM2 retention in Standby mode + 9 + 1 - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x204 - 0x20 - read-only - 0x00000000 - - ACTIVE - ACTIVE - 0 - 32 + EWPVD + Enable wakeup PVD for CPU1 + 8 + 1 - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x300 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + EULPEN + Ultra-low-power enable + 7 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + EWUP3 + Enable Wakeup pin WKUP3 for CPU1 + 2 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + EWUP2 + Enable Wakeup pin WKUP2 for CPU1 + 1 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + EWUP1 + Enable Wakeup pin WKUP1 for CPU1 + 0 + 1 - IPR1 - IPR1 - Interrupt Priority Register - 0x304 + CR4 + CR4 + Power control register 4 + 0xC 0x20 read-write 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 + WRFBUSYP + Wakeup Radio BUSY polarity + 11 + 1 + + + VBRS + VBAT battery charging resistor selection + 9 + 1 - IPR_N1 - IPR_N1 + VBE + VBAT battery charging enable 8 - 8 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + WP3 + Wakeup pin WKUP3 polarity + 2 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + WP2 + Wakeup pin WKUP2 polarity + 1 + 1 + + + WP1 + Wakeup pin WKUP1 polarity + 0 + 1 - IPR2 - IPR2 - Interrupt Priority Register - 0x308 + SR1 + SR1 + Power status register 1 + 0x10 0x20 - read-write + read-only 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 + WUFI + Internal wakeup interrupt flag + 15 + 1 + + + WRFBUSYF + Radio BUSY wakeup flag + 11 + 1 - IPR_N1 - IPR_N1 + WPVDF + Wakeup PVD flag 8 - 8 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + WUF3 + Wakeup flag 3 + 2 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + WUF2 + Wakeup flag 2 + 1 + 1 + + + WUF1 + Wakeup flag 1 + 0 + 1 - IPR3 - IPR3 - Interrupt Priority Register - 0x30C + SR2 + SR2 + Power status register 2 + 0x14 0x20 - read-write + read-only 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 + PVMO3 + Peripheral voltage monitoring output: VDDA vs. 1.62 V + 14 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PVDO + Power voltage detector output + 11 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + VOSF + Voltage scaling flag + 10 + 1 - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x310 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + REGLPF + regulator1 low power flag + 9 + 1 - IPR_N1 - IPR_N1 + REGLPS + regulator1 started 8 - 8 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + FLASHRDY + Flash ready + 7 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + REGMRS + regulator2 low power flag + 6 + 1 + + + RFEOLF + Radio end of life flag + 5 + 1 - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x314 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + LDORDY + LDO ready flag + 4 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + SMPSRDY + SMPS ready flag + 3 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + RFBUSYMS + Radio BUSY masked signal status + 2 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + RFBUSYS + Radio BUSY signal status + 1 + 1 - IPR6 - IPR6 - Interrupt Priority Register - 0x318 + SCR + SCR + Power status clear register + 0x18 0x20 - read-write + write-only 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 + CWRFBUSYF + Clear wakeup Radio BUSY flag + 11 + 1 - IPR_N1 - IPR_N1 + CWPVDF + Clear wakeup PVD interrupt flag 8 - 8 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + CWUF3 + Clear wakeup flag 3 + 2 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + CWUF2 + Clear wakeup flag 2 + 1 + 1 + + + CWUF1 + Clear wakeup flag 1 + 0 + 1 - IPR7 - IPR7 - Interrupt Priority Register - 0x31C + CR5 + CR5 + Power control register 5 + 0x1C 0x20 read-write 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 + SMPSEN + Enable SMPS Step Down converter SMPS mode enabled. + 15 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + RFEOLEN + Enable Radio End Of Life detector enabled + 14 + 1 - IPR8 - IPR8 - Interrupt Priority Register - 0x320 + PUCRA + PUCRA + Power Port A pull-up control register + 0x20 0x20 read-write 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 + PU15 + Port PA15 pull-up + 15 + 1 - - IPR_N1 - IPR_N1 - 8 - 8 + + PU14 + PU14 + 14 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PU13 + Port PA[y] pull-up bit y (y=0 to 13) + 13 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PU12 + PU12 + 12 + 1 - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x324 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PU11 + PU11 + 11 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PU10 + PU10 + 10 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PU9 + PU9 + 9 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PU8 + PU8 + 8 + 1 - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x328 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PU7 + PU7 + 7 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PU6 + PU6 + 6 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PU5 + PU5 + 5 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PU4 + PU4 + 4 + 1 - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x32C - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PU3 + PU3 + 3 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PU2 + PU2 + 2 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PU1 + PU1 + 1 + 1 - IPR_N3 - IPR_N3 - 24 - 8 - + PU0 + PU0 + 0 + 1 + - IPR12 - IPR12 - Interrupt Priority Register - 0x330 + PDCRA + PDCRA + Power Port A pull-down control register + 0x24 0x20 read-write 0x00000000 + + PD15 + PD15 + 15 + 1 + - IPR_N0 - IPR_N0 - 0 - 8 + PD14 + ull-down + 14 + 1 + + PD13 + PD13 + 13 + 1 + - IPR_N1 - IPR_N1 - 8 - 8 + PD12 + Port PA[y] pull-down (y=0 to 12) + 12 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PD11 + PD11 + 11 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PD10 + PD10 + 10 + 1 - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x334 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PD9 + PD9 + 9 + 1 - IPR_N1 - IPR_N1 + PD8 + PD8 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 + 1 - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x338 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PD7 + PD7 + 7 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PD6 + PD6 + 6 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PD5 + PD5 + 5 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PD4 + PD4 + 4 + 1 - - - - IPR15 - IPR15 - Interrupt Priority Register - 0x33C - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PD3 + PD3 + 3 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PD2 + PD2 + 2 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PD1 + PD1 + 1 + 1 - IPR_N3 - IPR_N3 - 24 - 8 - + PD0 + PD0 + 0 + 1 + - IPR16 - IPR16 - Interrupt Priority Register - 0x340 + PUCRB + PUCRB + Power Port B pull-up control register + 0x28 0x20 read-write 0x00000000 - IPR_N0 - IPR_N0 - 0 - 8 + PU15 + Port PB[y] pull-up (y=0 to 15) + 15 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PU14 + PU14 + 14 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PU13 + PU13 + 13 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PU12 + PU12 + 12 + 1 - - - - IPR17 - IPR17 - Interrupt Priority Register - 0x344 - 0x20 - read-write - 0x00000000 - - IPR_N0 - IPR_N0 - 0 - 8 + PU11 + PU11 + 11 + 1 - IPR_N1 - IPR_N1 - 8 - 8 + PU10 + PU10 + 10 + 1 - IPR_N2 - IPR_N2 - 16 - 8 + PU9 + PU9 + 9 + 1 - IPR_N3 - IPR_N3 - 24 - 8 + PU8 + PU8 + 8 + 1 - - - - - - NVIC_STIR - Nested vectored interrupt controller - NVIC - 0xE000EF00 - - 0x0 - 0x5 - registers - - - - STIR - STIR - Software trigger interrupt register - 0x0 - 0x20 - read-write - 0x00000000 - - INTID - Software generated interrupt ID - 0 - 9 + PU7 + PU7 + 7 + 1 - - - - - - PKA - Public key accelerator - PKA - 0x58002000 - - 0x0 - 0x2000 - registers - - - PKA - Private key accelerator - interrupt - 53 - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00000000 - - ADDRERRIE - Address error interrupt enable - 20 + PU6 + PU6 + 6 1 - RAMERRIE - RAM error interrupt enable - 19 + PU5 + PU5 + 5 1 - PROCENDIE - PROCENDIE - 17 + PU4 + PU4 + 4 1 - MODE - PKA operation code - 8 - 6 + PU3 + PU3 + 3 + 1 - START - start the operation + PU2 + PU2 + 2 + 1 + + + PU1 + PU1 1 1 - EN - PKA enable. + PU0 + PU0 0 1 - SR - SR - status register - 0x4 + PDCRB + PDCRB + Power Port B pull-down control register + 0x2C 0x20 - read-only + read-write 0x00000000 - ADDRERRF - Address error flag - 20 - 1 - - - RAMERRF - PKA RAM error flag - 19 - 1 - - - PROCENDF - PKA End of Operation flag - 17 - 1 - - - BUSY - PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. - 16 + PD15 + Port PB[y] pull-down (y=5 to 15) + 15 1 - - - - CLRFR - CLRFR - clear flag register - 0x8 - 0x20 - write-only - 0x00000000 - - ADDRERRFC - Clear Address error flag - 20 + PD14 + PD14 + 14 1 - RAMERRFC - Clear PKA RAM error flag - 19 + PD13 + PD13 + 13 1 - PROCENDFC - Clear PKA End of Operation flag - 17 + PD12 + PD12 + 12 1 - - - - - - PWR - Power control - PWR - 0x58000400 - - 0x0 - 0x400 - registers - - - - CR1 - CR1 - Power control register 1 - 0x0 - 0x20 - read-write - 0x00000200 - - - LPR - Low-power run - 14 - 1 - - - VOS - Voltage scaling range selection - 9 - 2 - - - DBP - Disable backup domain write protection - 8 - 1 - - - FPDS - Flash memory power down mode during LPSleep for CPU1 - 5 - 1 - - - FPDR - Flash memory power down mode during LPRun for CPU1 - 4 - 1 - - - SUBGHZSPINSSSEL - sub-GHz SPI NSS source select - 3 - 1 - - - LPMS - Low-power mode selection for CPU1 - 0 - 3 - - - - - CR2 - CR2 - Power control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - PVME3 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V - 6 + PD11 + PD11 + 11 1 - PLS - Power voltage detector level selection. - 1 - 3 - - - PVDE - Power voltage detector enable - 0 + PD10 + PD10 + 10 1 - - - - CR3 - CR3 - Power control register 3 - 0x8 - 0x20 - read-write - 0x00008000 - - EIWUL - Enable internal wakeup line for CPU1 - 15 + PD9 + PD9 + 9 1 - EWRFIRQ - akeup for CPU1 - 13 + PD8 + PD8 + 8 1 - EWRFBUSY - Enable Radio BUSY Wakeup from Standby for CPU1 - 11 + PD7 + PD7 + 7 1 - APC - Apply pull-up and pull-down configuration from CPU1 - 10 + PD6 + PD6 + 6 1 - RRS - SRAM2 retention in Standby mode - 9 + PD5 + PD5 + 5 1 - - EWPVD - Enable wakeup PVD for CPU1 - 8 + + PD4 + PD4 + 4 1 - EULPEN - Ultra-low-power enable - 7 + PD3 + Port PB[y] pull-down (y=0 to 3) + 3 1 - EWUP3 - Enable Wakeup pin WKUP3 for CPU1 + PD2 + PD2 2 1 - EWUP2 - Enable Wakeup pin WKUP2 for CPU1 + PD1 + PD1 1 1 - EWUP1 - Enable Wakeup pin WKUP1 for CPU1 + PD0 + PD0 0 1 - + - CR4 - CR4 - Power control register 4 - 0xC + PUCRC + PUCRC + Power Port C pull-up control register + 0x30 0x20 read-write 0x00000000 - WRFBUSYP - Wakeup Radio BUSY polarity - 11 + PU15 + Port PC[y] pull-up (y=13 to 15) + 15 1 - VBRS - VBAT battery charging resistor selection - 9 + PU14 + PU14 + 14 1 - VBE - VBAT battery charging enable - 8 + PU13 + PU13 + 13 1 - WP3 - Wakeup pin WKUP3 polarity + PU2 + PU2 2 1 - WP2 - Wakeup pin WKUP2 polarity + PU1 + PU1 1 1 - WP1 - Wakeup pin WKUP1 polarity + PU0 + PU0 0 1 - - - - SR1 - SR1 - Power status register 1 - 0x10 - 0x20 - read-only - 0x00000000 - - - WUFI - Internal wakeup interrupt flag - 15 - 1 - - - WRFBUSYF - Radio BUSY wakeup flag - 11 - 1 - - WPVDF - Wakeup PVD flag - 8 + PU3 + PU3 + 3 1 - WUF3 - Wakeup flag 3 - 2 + PU4 + PU4 + 4 1 - WUF2 - Wakeup flag 2 - 1 + PU5 + PU5 + 5 1 - WUF1 - Wakeup flag 1 - 0 + PU6 + PU6 + 6 1 - SR2 - SR2 - Power status register 2 - 0x14 + PDCRC + PDCRC + Power Port C pull-down control register + 0x34 0x20 - read-only + read-write 0x00000000 - PVMO3 - Peripheral voltage monitoring output: VDDA vs. 1.62 V - 14 + PD15 + Port PC[y] pull-down (y=13 to 15) + 15 1 - PVDO - Power voltage detector output - 11 + PD14 + PD14 + 14 1 - VOSF - Voltage scaling flag - 10 + PD13 + PD13 + 13 1 - REGLPF - regulator1 low power flag - 9 + PD2 + PD2 + 2 1 - REGLPS - regulator1 started - 8 + PD1 + PD1 + 1 1 - FLASHRDY - Flash ready - 7 + PD0 + PD0 + 0 1 - REGMRS - regulator2 low power flag - 6 - 1 - - - RFEOLF - Radio end of life flag - 5 + PD3 + PD3 + 3 1 - LDORDY - LDO ready flag + PD4 + PD4 4 1 - SMPSRDY - SMPS ready flag - 3 - 1 - - - RFBUSYMS - Radio BUSY masked signal status - 2 + PD5 + PD5 + 5 1 - RFBUSYS - Radio BUSY signal status - 1 + PD6 + PD6 + 6 1 - SCR - SCR - Power status clear register - 0x18 + PUCRH + PUCRH + Power Port H pull-up control register + 0x58 0x20 - write-only + read-write 0x00000000 - CWRFBUSYF - Clear wakeup Radio BUSY flag - 11 - 1 - - - CWPVDF - Clear wakeup PVD interrupt flag - 8 - 1 - - - CWUF3 - Clear wakeup flag 3 - 2 - 1 - - - CWUF2 - Clear wakeup flag 2 - 1 - 1 - - - CWUF1 - Clear wakeup flag 1 - 0 + PU3 + pull-up + 3 1 - CR5 - CR5 - Power control register 5 - 0x1C + PDCRH + PDCRH + Power Port H pull-down control register + 0x5C 0x20 read-write 0x00000000 - SMPSEN - Enable SMPS Step Down converter SMPS mode enabled. - 15 - 1 - - - RFEOLEN - Enable Radio End Of Life detector enabled - 14 + PD3 + pull-down + 3 1 - + - PUCRA - PUCRA - Power Port A pull-up control register - 0x20 + EXTSCR + EXTSCR + Power extended status and status clear register + 0x88 0x20 - read-write 0x00000000 - + - PU15 - Port PA15 pull-up - 15 - 1 - - - PU14 - PU14 + C1DS + CPU1 deepsleep mode 14 1 - - - PU13 - Port PA[y] pull-up bit y (y=0 to 13) - 13 - 1 - - - PU12 - PU12 - 12 - 1 - - - PU11 - PU11 - 11 - 1 - + read-only + - PU10 - PU10 + C1STOPF + System Stop0, 1 flag for CPU1. (All core states retained) 10 1 + read-only - PU9 - PU9 + C1STOP2F + System Stop2 flag for CPU1. (partial core states retained) 9 1 + read-only - PU8 - PU8 + C1SBF + System Standby flag for CPU1. (no core states retained) 8 1 + read-only - PU7 - PU7 - 7 - 1 - - - PU6 - PU6 - 6 - 1 - - - PU5 - PU5 - 5 + C1CSSF + Clear CPU1 Stop Standby flags + 0 1 + write-only + + + + SUBGHZSPICR + SUBGHZSPICR + Power SPI3 control register + 0x90 + 0x20 + read-write + 0x00008000 + - PU4 - PU4 - 4 + NSS + sub-GHz SPI NSS control + 15 1 + + + + + + RCC + Reset and clock control + RCC + 0x58000000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000061 + + + PLLRDY + Main PLL clock ready flag + 25 + 1 + read-only + + + PLLON + Main PLL enable + 24 + 1 + read-write + + + HSEBYPPWR + Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. + 21 + 1 + read-write + + + HSEPRE + HSE32 sysclk prescaler + 20 + 1 + read-write + + + CSSON + HSE32 Clock security system enable + 19 + 1 + read-write + + + HSERDY + HSE32 clock ready flag + 17 + 1 + read-only + + + HSEON + HSE32 clock enable + 16 + 1 + read-write + + + HSIKERDY + HSI16 kernel clock ready flag for peripherals requests. + 12 + 1 + read-only + + + HSIASFS + HSI16 automatic start from Stop + 11 + 1 + read-write + + + HSIRDY + HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) + 10 + 1 + read-only + + + HSIKERON + HSI16 always enable for peripheral kernel clocks. + 9 + 1 + read-write + + + HSION + HSI16 clock enable + 8 + 1 + read-write + + + MSIRANGE + MSI clock ranges + 4 + 4 + read-write + + + MSIRGSEL + MSI range control selection + 3 + 1 + read-write + + + MSIPLLEN + MSI clock PLL enable + 2 + 1 + read-write + + + MSIRDY + MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) + 1 + 1 + read-only + + + MSION + MSI clock enable + 0 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration register + 0x4 + 0x20 + 0x40000000 + - PU3 - PU3 - 3 - 1 + HSITRIM + HSI16 clock trimming + 24 + 7 + read-write - PU2 - PU2 - 2 - 1 + HSICAL + HSI16 clock calibration + 16 + 8 + read-only - PU1 - PU1 - 1 - 1 + MSITRIM + MSI clock trimming + 8 + 8 + read-write - PU0 - PU0 + MSICAL + MSI clock calibration 0 - 1 + 8 + read-only - PDCRA - PDCRA - Power Port A pull-down control register - 0x24 + CFGR + CFGR + Clock configuration register + 0x8 0x20 - read-write - 0x00000000 + 0x00070000 - - PD15 - PD15 - 15 - 1 - - PD14 - ull-down - 14 - 1 + MCOPRE + Microcontroller clock output prescaler + 28 + 3 + read-write - - PD13 - PD13 - 13 - 1 + + MCOSEL + Microcontroller clock output + 24 + 4 + read-write - PD12 - Port PA[y] pull-down (y=0 to 12) - 12 + PPRE2F + PCLK2 prescaler flag (APB2) + 18 1 + read-only - PD11 - PD11 - 11 - 1 - - - PD10 - PD10 - 10 - 1 - - - PD9 - PD9 - 9 + PPRE1F + PCLK1 prescaler flag (APB1) + 17 1 + read-only - PD8 - PD8 - 8 + HPREF + HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) + 16 1 + read-only - PD7 - PD7 - 7 + STOPWUCK + Wakeup from Stop and CSS backup clock selection + 15 1 + read-write - PD6 - PD6 - 6 - 1 + PPRE2 + PCLK2 high-speed prescaler (APB2) + 11 + 3 + read-write - PD5 - PD5 - 5 - 1 + PPRE1 + PCLK1 low-speed prescaler (APB1) + 8 + 3 + read-write - PD4 - PD4 + HPRE + HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) 4 - 1 - - - PD3 - PD3 - 3 - 1 + 4 + read-write - PD2 - PD2 + SWS + System clock switch status 2 - 1 - - - PD1 - PD1 - 1 - 1 + 2 + read-only - PD0 - PD0 + SW + System clock switch 0 - 1 + 2 + read-write - PUCRB - PUCRB - Power Port B pull-up control register - 0x28 + PLLCFGR + PLLCFGR + PLL configuration register + 0xC 0x20 read-write - 0x00000000 + 0x22040100 - PU15 - Port PB[y] pull-up (y=0 to 15) - 15 - 1 + PLLR + Main PLL division factor for PLLRCLK + 29 + 3 - PU14 - PU14 - 14 + PLLREN + Main PLL PLLRCLK output enable + 28 1 - PU13 - PU13 - 13 - 1 + PLLQ + Main PLL division factor for PLLQCLK + 25 + 3 - PU12 - PU12 - 12 + PLLQEN + Main PLL PLLQCLK output enable + 24 1 - PU11 - PU11 - 11 - 1 + PLLP + Main PLL division factor for PLLPCLK. + 17 + 5 - PU10 - PU10 - 10 + PLLPEN + Main PLL PLLPCLK output enable + 16 1 - PU9 - PU9 - 9 - 1 + PLLN + Main PLL multiplication factor for VCO + 8 + 7 - PU8 - PU8 - 8 - 1 + PLLM + Division factor for the main PLL input clock + 4 + 3 - PU7 - PU7 - 7 - 1 + PLLSRC + Main PLL entry clock source + 0 + 2 + + + + CIER + CIER + Clock interrupt enable register + 0x18 + 0x20 + read-write + 0x00000000 + - PU6 - PU6 - 6 + LSECSSIE + LSE clock security system interrupt enable + 9 1 - PU5 - PU5 + PLLRDYIE + PLL ready interrupt enable 5 1 - PU4 - PU4 + HSERDYIE + HSE32 ready interrupt enable 4 1 - PU3 - PU3 + HSIRDYIE + HSI16 ready interrupt enable 3 1 - PU2 - PU2 + MSIRDYIE + MSI ready interrupt enable 2 1 - PU1 - PU1 + LSERDYIE + LSE ready interrupt enable 1 1 - PU0 - PU0 + LSIRDYIE + LSI ready interrupt enable 0 1 - PDCRB - PDCRB - Power Port B pull-down control register - 0x2C + CIFR + CIFR + Clock interrupt flag register + 0x1C 0x20 - read-write + read-only 0x00000000 - PD15 - Port PB[y] pull-down (y=5 to 15) - 15 + LSECSSF + LSE Clock security system interrupt flag + 9 1 - PD14 - PD14 - 14 + CSSF + HSE32 Clock security system interrupt flag + 8 1 - PD13 - PD13 - 13 + PLLRDYF + PLL ready interrupt flag + 5 1 - PD12 - PD12 - 12 + HSERDYF + HSE32 ready interrupt flag + 4 1 - PD11 - PD11 - 11 + HSIRDYF + HSI16 ready interrupt flag + 3 1 - PD10 - PD10 - 10 + MSIRDYF + MSI ready interrupt flag + 2 1 - PD9 - PD9 - 9 + LSERDYF + LSE ready interrupt flag + 1 1 - PD8 - PD8 - 8 - 1 - + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + - PD7 - PD7 - 7 + LSECSSC + LSE Clock security system interrupt clear + 9 1 - PD6 - PD6 - 6 + CSSC + HSE32 Clock security system interrupt clear + 8 1 - PD5 - PD5 + PLLRDYC + PLL ready interrupt clear 5 1 - - PD4 - PD4 + + HSERDYC + HSE32 ready interrupt clear 4 1 - PD3 - Port PB[y] pull-down (y=0 to 3) + HSIRDYC + HSI16 ready interrupt clear 3 1 - PD2 - PD2 + MSIRDYC + MSI ready interrupt clear 2 1 - PD1 - PD1 + LSERDYC + LSE ready interrupt clear 1 1 - PD0 - PD0 + LSIRDYC + LSI ready interrupt clear 0 1 - PUCRC - PUCRC - Power Port C pull-up control register - 0x30 + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x28 0x20 read-write - 0x00000000 + 0x000000000 - PU15 - Port PC[y] pull-up (y=13 to 15) - 15 + CRCRST + CRC reset + 12 1 - PU14 - PU14 - 14 + DMAMUX1RST + DMAMUX1 reset + 2 1 - PU13 - PU13 - 13 + DMA2RST + DMA2 reset + 1 1 - PU2 - PU2 + DMA1RST + DMA1 reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + read-write + 0x000000000 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOCRST + IO port C reset 2 1 - PU1 - PU1 + GPIOBRST + IO port B reset 1 1 - PU0 - PU0 + GPIOARST + IO port A reset 0 1 + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + read-write + 0x000000000 + + + FLASHRST + Flash interface reset + 25 + 1 + - PU3 - PU3 - 3 + HSEMRST + HSEMRST + 19 1 - PU4 - PU4 - 4 + RNGRST + RNGRST + 18 1 - PU5 - PU5 - 5 + AESRST + AESRST + 17 1 - PU6 - PU6 - 6 + PKARST + PKARST + 16 1 - PDCRC - PDCRC - Power Port C pull-down control register - 0x34 + APB1RSTR1 + APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 0x20 read-write 0x00000000 - PD15 - Port PC[y] pull-down (y=13 to 15) - 15 + LPTIM1RST + Low Power Timer 1 reset + 31 1 - PD14 - PD14 - 14 + DACRST + DAC reset + 29 1 - PD13 - PD13 - 13 + I2C3RST + I2C3 reset + 23 1 - PD2 - PD2 - 2 + I2C2RST + I2C2 reset + 22 1 - PD1 - PD1 - 1 + I2C1RST + I2C1 reset + 21 1 - PD0 - PD0 - 0 + USART2RST + USART2 reset + 17 1 - PD3 - PD3 - 3 + SPI2S2RST + SPI2S2 reset + 14 1 - PD4 - PD4 - 4 + TIM2RST + TIM2 timer reset + 0 + 1 + + + + + APB1RSTR2 + APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + read-write + 0x000000000 + + + LPTIM3RST + Low-power timer 3 reset + 6 1 - PD5 - PD5 + LPTIM2RST + Low-power timer 2 reset 5 1 - PD6 - PD6 - 6 + LPUART1RST + Low-power UART 1 reset + 0 1 - PUCRH - PUCRH - Power Port H pull-up control register - 0x58 + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x40 0x20 read-write - 0x00000000 + 0x000000000 - PU3 - pull-up - 3 - 1 - + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + ADCRST + ADC reset + 9 + 1 + - PDCRH - PDCRH - Power Port H pull-down control register - 0x5C + APB3RSTR + APB3RSTR + APB3 peripheral reset register + 0x44 0x20 read-write - 0x00000000 + 0x000000000 - PD3 - pull-down - 3 + SUBGHZSPIRST + Sub-GHz radio SPI reset + 0 1 - EXTSCR - EXTSCR - Power extended status and status clear register - 0x88 + AHB1ENR + AHB1ENR + AHB1 peripheral clock enable register + 0x48 0x20 + read-write 0x00000000 - C1DS - CPU1 deepsleep mode - 14 + CRCEN + CPU1 CRC clock enable + 12 1 - read-only - C1STOPF - System Stop0, 1 flag for CPU1. (All core states retained) - 10 + DMAMUX1EN + CPU1 DMAMUX1 clock enable + 2 1 - read-only - C1STOP2F - System Stop2 flag for CPU1. (partial core states retained) - 9 + DMA2EN + CPU1 DMA2 clock enable + 1 1 - read-only - C1SBF - System Standby flag for CPU1. (no core states retained) - 8 + DMA1EN + CPU1 DMA1 clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + read-write + 0x00000000 + + + GPIOHEN + CPU1 IO port H clock enable + 7 1 - read-only - C1CSSF - Clear CPU1 Stop Standby flags + GPIOCEN + CPU1 IO port C clock enable + 2 + 1 + + + GPIOBEN + CPU1 IO port B clock enable + 1 + 1 + + + GPIOAEN + CPU1 IO port A clock enable 0 1 - write-only - SUBGHZSPICR - SUBGHZSPICR - Power SPI3 control register - 0x90 + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable register + 0x50 0x20 read-write - 0x00008000 + 0x02080000 - NSS - sub-GHz SPI NSS control - 15 + FLASHEN + CPU1 Flash interface clock enable + 25 + 1 + + + HSEMEN + HSEMEN + 19 + 1 + + + RNGEN + RNGEN + 18 + 1 + + + AESEN + AESEN + 17 + 1 + + + PKAEN + PKAEN + 16 1 - - - - RCC - Reset and clock control - RCC - 0x58000000 - - 0x0 - 0x400 - registers - - - RCC - RCC global interrupt - 5 - - - CR - CR - Clock control register - 0x0 + APB1ENR1 + APB1ENR1 + APB1 peripheral clock enable register 1 + 0x58 0x20 - 0x00000061 - - - PLLRDY - Main PLL clock ready flag - 25 - 1 - read-only - - - PLLON - Main PLL enable - 24 - 1 - read-write - - - HSEBYPPWR - Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO. - 21 - 1 - read-write - - - HSEPRE - HSE32 sysclk prescaler - 20 - 1 - read-write - - - CSSON - HSE32 Clock security system enable - 19 - 1 - read-write - - - HSERDY - HSE32 clock ready flag - 17 - 1 - read-only - - - HSEON - HSE32 clock enable - 16 - 1 - read-write - - - HSIKERDY - HSI16 kernel clock ready flag for peripherals requests. - 12 - 1 - read-only - - - HSIASFS - HSI16 automatic start from Stop - 11 - 1 - read-write - - - HSIRDY - HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready) - 10 - 1 - read-only - - - HSIKERON - HSI16 always enable for peripheral kernel clocks. - 9 - 1 - read-write - - - HSION - HSI16 clock enable - 8 - 1 - read-write - - - MSIRANGE - MSI clock ranges - 4 - 4 - read-write - - - MSIRGSEL - MSI range control selection - 3 - 1 - read-write - - - MSIPLLEN - MSI clock PLL enable - 2 - 1 - read-write - - - MSIRDY - MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) - 1 - 1 - read-only - - - MSION - MSI clock enable - 0 - 1 - read-write - - - - - ICSCR - ICSCR - Internal clock sources calibration register - 0x4 - 0x20 - 0x40000000 + 0x00000000 - HSITRIM - HSI16 clock trimming - 24 - 7 + LPTIM1EN + CPU1 Low power timer 1 clocks enable + 31 + 1 read-write - HSICAL - HSI16 clock calibration - 16 - 8 - read-only - - - MSITRIM - MSI clock trimming - 8 - 8 + DAC1EN + CPU1 DAC1 clock enable + 29 + 1 read-write - MSICAL - MSI clock calibration - 0 - 8 - read-only - - - - - CFGR - CFGR - Clock configuration register - 0x8 - 0x20 - 0x00070000 - - - MCOPRE - Microcontroller clock output prescaler - 28 - 3 + I2C3EN + CPU1 I2C3 clocks enable + 23 + 1 read-write - MCOSEL - Microcontroller clock output - 24 - 4 + I2C2EN + CPU1 I2C2 clocks enable + 22 + 1 read-write - PPRE2F - PCLK2 prescaler flag (APB2) - 18 + I2C1EN + CPU1 I2C1 clocks enable + 21 1 - read-only + read-write - PPRE1F - PCLK1 prescaler flag (APB1) + USART2EN + CPU1 USART2 clock enable 17 1 - read-only + read-write - HPREF - HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) - 16 + SPI2S2EN + CPU1 SPI2S2 clock enable + 14 1 - read-only + read-write - STOPWUCK - Wakeup from Stop and CSS backup clock selection - 15 + WWDGEN + CPU1 Window watchdog clock enable + 11 1 read-write - PPRE2 - PCLK2 high-speed prescaler (APB2) - 11 - 3 + RTCAPBEN + CPU1 RTC APB clock enable + 10 + 1 read-write - PPRE1 - PCLK1 low-speed prescaler (APB1) - 8 - 3 + TIM2EN + CPU1 TIM2 timer clock enable + 0 + 1 read-write + + + + APB1ENR2 + APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + read-write + 0x000000000 + - HPRE - HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) - 4 - 4 - read-write + LPTIM3EN + CPU1 Low power timer 3 clocks enable + 6 + 1 - SWS - System clock switch status - 2 - 2 - read-only + LPTIM2EN + CPU1 Low power timer 2 clocks enable + 5 + 1 - SW - System clock switch + LPUART1EN + CPU1 Low power UART 1 clocks enable 0 - 2 - read-write + 1 - PLLCFGR - PLLCFGR - PLL configuration register - 0xC + APB2ENR + APB2ENR + APB2 peripheral clock enable register + 0x60 0x20 read-write - 0x22040100 + 0x00000000 - PLLR - Main PLL division factor for PLLRCLK - 29 - 3 + TIM17EN + CPU1 TIM17 timer clock enable + 18 + 1 - PLLREN - Main PLL PLLRCLK output enable - 28 + TIM16EN + CPU1 TIM16 timer clock enable + 17 1 - PLLQ - Main PLL division factor for PLLQCLK - 25 - 3 + USART1EN + CPU1 USART1clocks enable + 14 + 1 - PLLQEN - Main PLL PLLQCLK output enable - 24 + SPI1EN + CPU1 SPI1 clock enable + 12 1 - PLLP - Main PLL division factor for PLLPCLK. - 17 - 5 + TIM1EN + CPU1 TIM1 timer clock enable + 11 + 1 - PLLPEN - Main PLL PLLPCLK output enable - 16 + ADCEN + CPU1 ADC clocks enable + 9 1 + + + + APB3ENR + APB3ENR + APB3 peripheral clock enable register + 0x64 + 0x20 + read-write + 0x000000000 + - PLLN - Main PLL multiplication factor for VCO - 8 - 7 - - - PLLM - Division factor for the main PLL input clock - 4 - 3 - - - PLLSRC - Main PLL entry clock source + SUBGHZSPIEN + sub-GHz radio SPI clock enable 0 - 2 + 1 - CIER - CIER - Clock interrupt enable register - 0x18 + AHB1SMENR + AHB1SMENR + AHB1 peripheral clocks enable in Sleep modes register + 0x68 0x20 read-write - 0x00000000 + 0x00001007 - LSECSSIE - LSE clock security system interrupt enable - 9 + CRCSMEN + CRC clock enable during CPU1 CSleep mode. + 12 1 - PLLRDYIE - PLL ready interrupt enable - 5 + DMAMUX1SMEN + DMAMUX1 clock enable during CPU1 CSleep mode. + 2 1 - HSERDYIE - HSE32 ready interrupt enable - 4 + DMA2SMEN + DMA2 clock enable during CPU1 CSleep mode + 1 1 - HSIRDYIE - HSI16 ready interrupt enable - 3 + DMA1SMEN + DMA1 clock enable during CPU1 CSleep mode. + 0 + 1 + + + + + AHB2SMENR + AHB2SMENR + AHB2 peripheral clocks enable in Sleep modes register + 0x6C + 0x20 + read-write + 0x00000087 + + + GPIOHSMEN + IO port H clock enable during CPU1 CSleep mode. + 7 1 - MSIRDYIE - MSI ready interrupt enable + GPIOCSMEN + IO port C clock enable during CPU1 CSleep mode. 2 1 - LSERDYIE - LSE ready interrupt enable + GPIOBSMEN + IO port B clock enable during CPU1 CSleep mode. 1 1 - LSIRDYIE - LSI ready interrupt enable + GPIOASMEN + IO port A clock enable during CPU1 CSleep mode. 0 1 - CIFR - CIFR - Clock interrupt flag register - 0x1C + AHB3SMENR + AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 0x20 - read-only - 0x00000000 + read-write + 0x03870000 - LSECSSF - LSE Clock security system interrupt flag - 9 + FLASHSMEN + Flash interface clock enable during CPU1 CSleep mode. + 25 1 - CSSF - HSE32 Clock security system interrupt flag - 8 + SRAM2SMEN + SRAM2 memory interface clock enable during CPU1 CSleep mode + 24 1 - PLLRDYF - PLL ready interrupt flag - 5 + SRAM1SMEN + SRAM1 interface clock enable during CPU1 CSleep mode. + 23 1 - HSERDYF - HSE32 ready interrupt flag - 4 + RNGSMEN + True RNG clocks enable during CPU1 Csleep and CStop modes + 18 1 - HSIRDYF - HSI16 ready interrupt flag - 3 + AESSMEN + AES accelerator clock enable during CPU1 CSleep mode. + 17 1 - MSIRDYF - MSI ready interrupt flag - 2 + PKASMEN + PKA accelerator clock enable during CPU1 CSleep mode. + 16 1 + + + + APB1SMENR1 + APB1SMENR1 + APB1 peripheral clocks enable in Sleep mode register 1 + 0x78 + 0x20 + read-write + 0xA0E24C01 + - LSERDYF - LSE ready interrupt flag - 1 + LPTIM1SMEN + Low power timer 1 clock enable during CPU1 Csleep and CStop mode + 31 1 - LSIRDYF - LSI ready interrupt flag - 0 + DACSMEN + DAC clock enable during CPU1 CSleep mode. + 29 1 - - - - CICR - CICR - Clock interrupt clear register - 0x20 - 0x20 - write-only - 0x00000000 - - LSECSSC - LSE Clock security system interrupt clear - 9 + I2C3SMEN + I2C3 clock enable during CPU1 Csleep and CStop modes + 23 1 - CSSC - HSE32 Clock security system interrupt clear - 8 + I2C2SMEN + I2C2 clock enable during CPU1 Csleep and CStop modes + 22 1 - PLLRDYC - PLL ready interrupt clear - 5 + I2C1SMEN + I2C1 clock enable during CPU1 Csleep and CStop modes + 21 1 - HSERDYC - HSE32 ready interrupt clear - 4 + USART2SMEN + USART2 clock enable during CPU1 CSleep mode. + 17 1 - HSIRDYC - HSI16 ready interrupt clear - 3 + SPI2S2SMEN + SPI2S2 clock enable during CPU1 CSleep mode. + 14 1 - MSIRDYC - MSI ready interrupt clear - 2 + WWDGSMEN + Window watchdog clocks enable during CPU1 CSleep mode. + 11 1 - LSERDYC - LSE ready interrupt clear - 1 + RTCAPBSMEN + RTC bus clock enable during CPU1 CSleep mode. + 10 1 - LSIRDYC - LSI ready interrupt clear + TIM2SMEN + TIM2 timer clock enable during CPU1 CSleep mode. 0 1 - AHB1RSTR - AHB1RSTR - AHB1 peripheral reset register - 0x28 + APB1SMENR2 + APB1SMENR2 + APB1 peripheral clocks enable in Sleep mode register 2 + 0x7C 0x20 read-write - 0x000000000 + 0x00000061 - CRCRST - CRC reset - 12 - 1 - - - DMAMUX1RST - DMAMUX1 reset - 2 + LPTIM3SMEN + Low power timer 3 clock enable during CPU1 Csleep and CStop modes + 6 1 - DMA2RST - DMA2 reset - 1 + LPTIM2SMEN + Low power timer 2 clock enable during CPU1 Csleep and CStop modes + 5 1 - DMA1RST - DMA1 reset + LPUART1SMEN + Low power UART 1 clock enable during CPU1 Csleep and CStop modes. 0 1 - AHB2RSTR - AHB2RSTR - AHB2 peripheral reset register - 0x2C + APB2SMENR + APB2SMENR + APB2 peripheral clocks enable in Sleep mode register + 0x80 0x20 read-write - 0x000000000 + 0x00065A00 - GPIOHRST - IO port H reset - 7 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIOBRST - IO port B reset - 1 + TIM17SMEN + TIM17 timer clock enable during CPU1 CSleep mode. + 18 1 - GPIOARST - IO port A reset - 0 + TIM16SMEN + TIM16 timer clock enable during CPU1 CSleep mode. + 17 1 - - - - AHB3RSTR - AHB3RSTR - AHB3 peripheral reset register - 0x30 - 0x20 - read-write - 0x000000000 - - FLASHRST - Flash interface reset - 25 + USART1SMEN + USART1 clock enable during CPU1 Csleep and CStop modes. + 14 1 - HSEMRST - HSEMRST - 19 + SPI1SMEN + SPI1 clock enable during CPU1 CSleep mode. + 12 1 - RNGRST - RNGRST - 18 + TIM1SMEN + TIM1 timer clock enable during CPU1 CSleep mode. + 11 1 - AESRST - AESRST - 17 + ADCSMEN + ADC clocks enable during CPU1 Csleep and CStop modes + 9 1 + + + + APB3SMENR + APB3SMENR + APB3 peripheral clock enable in Sleep mode register + 0x84 + 0x20 + read-write + 0x000000001 + - PKARST - PKARST - 16 + SUBGHZSPISMEN + Sub-GHz radio SPI clock enable during Sleep and Stop modes + 0 1 - APB1RSTR1 - APB1RSTR1 - APB1 peripheral reset register 1 - 0x38 + CCIPR + CCIPR + Peripherals independent clock configuration register + 0x88 0x20 read-write 0x00000000 - LPTIM1RST - Low Power Timer 1 reset - 31 - 1 + RNGSEL + RNG clock source selection + 30 + 2 - DACRST - DAC reset - 29 - 1 + ADCSEL + ADC clock source selection + 28 + 2 - I2C3RST - I2C3 reset - 23 - 1 + LPTIM3SEL + Low power timer 3 clock source selection + 22 + 2 - I2C2RST - I2C2 reset - 22 - 1 + LPTIM2SEL + Low power timer 2 clock source selection + 20 + 2 - I2C1RST - I2C1 reset - 21 - 1 + LPTIM1SEL + Low power timer 1 clock source selection + 18 + 2 - USART2RST - USART2 reset - 17 - 1 + I2C3SEL + I2C3 clock source selection + 16 + 2 - SPI2S2RST - SPI2S2 reset + I2C2SEL + I2C2 clock source selection 14 - 1 + 2 - TIM2RST - TIM2 timer reset - 0 - 1 + I2C1SEL + I2C1 clock source selection + 12 + 2 - - - - APB1RSTR2 - APB1RSTR2 - APB1 peripheral reset register 2 - 0x3C - 0x20 - read-write - 0x000000000 - - LPTIM3RST - Low-power timer 3 reset - 6 - 1 + LPUART1SEL + LPUART1 clock source selection + 10 + 2 - LPTIM2RST - Low-power timer 2 reset - 5 - 1 + SPI2S2SEL + SPI2S2 I2S clock source selection + 8 + 2 - LPUART1RST - Low-power UART 1 reset + USART2SEL + USART2 clock source selection + 2 + 2 + + + USART1SEL + USART1 clock source selection 0 - 1 + 2 - APB2RSTR - APB2RSTR - APB2 peripheral reset register - 0x40 + BDCR + BDCR + Backup domain control register + 0x90 0x20 - read-write - 0x000000000 + 0x00000000 - TIM17RST - TIM17 timer reset - 18 + LSCOSEL + Low speed clock output selection + 25 1 + read-write - TIM16RST - TIM16 timer reset - 17 + LSCOEN + Low speed clock output enable + 24 1 + read-write - USART1RST - USART1 reset - 14 + BDRST + Backup domain software reset + 16 1 + read-write - SPI1RST - SPI1 reset - 12 + RTCEN + RTC clock enable + 15 1 + read-write - TIM1RST - TIM1 timer reset + LSESYSRDY + LSE system clock ready 11 1 + read-only - ADCRST - ADC reset - 9 - 1 + RTCSEL + RTC clock source selection + 8 + 2 + read-write - - - - APB3RSTR - APB3RSTR - APB3 peripheral reset register - 0x44 - 0x20 - read-write - 0x000000000 - - SUBGHZSPIRST - Sub-GHz radio SPI reset - 0 - 1 - - - - - AHB1ENR - AHB1ENR - AHB1 peripheral clock enable register - 0x48 - 0x20 - read-write - 0x00000000 - - - CRCEN - CPU1 CRC clock enable - 12 - 1 - - - DMAMUX1EN - CPU1 DMAMUX1 clock enable - 2 + LSESYSEN + LSE system clock enable + 7 1 + read-write - DMA2EN - CPU1 DMA2 clock enable - 1 + LSECSSD + CSS on LSE failure Detection + 6 1 + read-only - DMA1EN - CPU1 DMA1 clock enable - 0 + LSECSSON + CSS on LSE enable + 5 1 + read-write - - - - AHB2ENR - AHB2ENR - AHB2 peripheral clock enable register - 0x4C - 0x20 - read-write - 0x00000000 - - GPIOHEN - CPU1 IO port H clock enable - 7 - 1 + LSEDRV + LSE oscillator drive capability + 3 + 2 + read-write - GPIOCEN - CPU1 IO port C clock enable + LSEBYP + LSE oscillator bypass 2 1 + read-write - GPIOBEN - CPU1 IO port B clock enable + LSERDY + LSE oscillator ready 1 1 + read-only - GPIOAEN - CPU1 IO port A clock enable + LSEON + LSE oscillator enable 0 1 + read-write - AHB3ENR - AHB3ENR - AHB3 peripheral clock enable register - 0x50 + CSR + CSR + Control/status register + 0x94 0x20 - read-write - 0x02080000 + 0x0C01C600 - FLASHEN - CPU1 Flash interface clock enable - 25 + LPWRRSTF + Low-power reset flag + 31 1 + read-only - HSEMEN - HSEMEN - 19 + WWDGRSTF + Window watchdog reset flag + 30 1 + read-only - RNGEN - RNGEN - 18 + IWDGRSTF + Independent window watchdog reset flag + 29 1 + read-only - AESEN - AESEN - 17 + SFTRSTF + Software reset flag + 28 1 + read-only - PKAEN - PKAEN - 16 + BORRSTF + BOR flag + 27 1 + read-only - - - - APB1ENR1 - APB1ENR1 - APB1 peripheral clock enable register 1 - 0x58 - 0x20 - 0x00000000 - - LPTIM1EN - CPU1 Low power timer 1 clocks enable - 31 + PINRSTF + Pin reset flag + 26 1 - read-write + read-only - DAC1EN - CPU1 DAC1 clock enable - 29 + OBLRSTF + Option byte loader reset flag + 25 1 - read-write + read-only - I2C3EN - CPU1 I2C3 clocks enable - 23 + RFILARSTF + Radio illegal access flag + 24 1 - read-write + read-only - I2C2EN - CPU1 I2C2 clocks enable - 22 + RMVF + Remove reset flag + 23 1 read-write - I2C1EN - CPU1 I2C1 clocks enable - 21 + RFRST + Radio reset + 15 1 read-write - USART2EN - CPU1 USART2 clock enable - 17 + RFRSTF + Radio in reset status flag + 14 1 - read-write + read-only - SPI2S2EN - CPU1 SPI2S2 clock enable - 14 - 1 + MSISRANGE + MSI clock ranges + 8 + 4 read-write - - WWDGEN - CPU1 Window watchdog clock enable - 11 + + LSIPRE + LSI frequency prescaler + 4 1 read-write - RTCAPBEN - CPU1 RTC APB clock enable - 10 + LSIRDY + LSI oscillator ready + 1 1 - read-write + read-only - TIM2EN - CPU1 TIM2 timer clock enable + LSION + LSI oscillator enable 0 1 read-write - + - APB1ENR2 - APB1ENR2 - APB1 peripheral clock enable register 2 - 0x5C + EXTCFGR + EXTCFGR + Extended clock recovery register + 0x108 0x20 - read-write - 0x000000000 + 0x00030000 - LPTIM3EN - CPU1 Low power timer 3 clocks enable - 6 - 1 - - - LPTIM2EN - CPU1 Low power timer 2 clocks enable - 5 + SHDHPREF + HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) + 16 1 + read-only - LPUART1EN - CPU1 Low power UART 1 clocks enable + SHDHPRE + HCLK3 shared prescaler (AHB3, Flash, and SRAM2) 0 - 1 + 4 + read-write - + + + + + RNG + True random number generator + RNG + 0x58001000 + + 0x0 + 0x400 + registers + + + True_RNG + True random number generator + interrupt + 52 + + - APB2ENR - APB2ENR - APB2 peripheral clock enable register - 0x60 + CR + CR + control register + 0x0 0x20 read-write - 0x00000000 - - - TIM17EN - CPU1 TIM17 timer clock enable - 18 - 1 - + 0x00800000 + - TIM16EN - CPU1 TIM16 timer clock enable - 17 + RNGEN + True random number generator enable + 2 1 - + - USART1EN - CPU1 USART1clocks enable - 14 + IE + Interrupt Enable + 3 1 - + - SPI1EN - CPU1 SPI1 clock enable - 12 - 1 - + CED + Interrupt Enable + 5 + 1 + - TIM1EN - CPU1 TIM1 timer clock enable - 11 - 1 + RNG_CONFIG3 + RNG_CONFIG3 + 8 + 4 - ADCEN - CPU1 ADC clocks enable - 9 + NISTC + NISTC + 12 1 - - - - APB3ENR - APB3ENR - APB3 peripheral clock enable register - 0x64 - 0x20 - read-write - 0x000000000 - - SUBGHZSPIEN - sub-GHz radio SPI clock enable - 0 - 1 + RNG_CONFIG2 + RNG_CONFIG2 + 13 + 3 - - - - AHB1SMENR - AHB1SMENR - AHB1 peripheral clocks enable in Sleep modes register - 0x68 - 0x20 - read-write - 0x00001007 - - CRCSMEN - CRC clock enable during CPU1 CSleep mode. - 12 - 1 + CLKDIV + CLKDIV + 16 + 4 - DMAMUX1SMEN - DMAMUX1 clock enable during CPU1 CSleep mode. - 2 - 1 + RNG_CONFIG1 + RNG_CONFIG1 + 20 + 6 - DMA2SMEN - DMA2 clock enable during CPU1 CSleep mode - 1 + CONDRST + Conditioning soft reset + 30 1 - DMA1SMEN - DMA1 clock enable during CPU1 CSleep mode. - 0 + CONFIGLOCK + CONFIGLOCK + 31 1 - AHB2SMENR - AHB2SMENR - AHB2 peripheral clocks enable in Sleep modes register - 0x6C + SR + SR + status register + 0x4 0x20 - read-write - 0x00000087 + 0x00000000 - GPIOHSMEN - IO port H clock enable during CPU1 CSleep mode. - 7 + SEIS + Seed error interrupt status + 6 1 + read-write - GPIOCSMEN - IO port C clock enable during CPU1 CSleep mode. + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status 2 1 + read-only - GPIOBSMEN - IO port B clock enable during CPU1 CSleep mode. + CECS + Clock error current status 1 1 + read-only - GPIOASMEN - IO port A clock enable during CPU1 CSleep mode. + DRDY + Data Ready 0 1 + read-only - AHB3SMENR - AHB3SMENR - AHB3 peripheral clocks enable in Sleep and Stop modes register - 0x70 + DR + DR + data register + 0x8 0x20 - read-write - 0x03870000 + read-only + 0x00000000 - FLASHSMEN - Flash interface clock enable during CPU1 CSleep mode. - 25 - 1 - - - SRAM2SMEN - SRAM2 memory interface clock enable during CPU1 CSleep mode - 24 - 1 - - - SRAM1SMEN - SRAM1 interface clock enable during CPU1 CSleep mode. - 23 - 1 - - - RNGSMEN - True RNG clocks enable during CPU1 Csleep and CStop modes - 18 - 1 - - - AESSMEN - AES accelerator clock enable during CPU1 CSleep mode. - 17 - 1 - - - PKASMEN - PKA accelerator clock enable during CPU1 CSleep mode. - 16 - 1 + RNDATA + Random data + 0 + 32 - - APB1SMENR1 - APB1SMENR1 - APB1 peripheral clocks enable in Sleep mode register 1 - 0x78 + + HTCR + HTCR + health test control register + 0x10 0x20 read-write - 0xA0E24C01 + 0x00005A4E - LPTIM1SMEN - Low power timer 1 clock enable during CPU1 Csleep and CStop mode - 31 - 1 - - - DACSMEN - DAC clock enable during CPU1 CSleep mode. - 29 - 1 - - - I2C3SMEN - I2C3 clock enable during CPU1 Csleep and CStop modes - 23 - 1 - - - I2C2SMEN - I2C2 clock enable during CPU1 Csleep and CStop modes - 22 - 1 - - - I2C1SMEN - I2C1 clock enable during CPU1 Csleep and CStop modes - 21 - 1 - - - USART2SMEN - USART2 clock enable during CPU1 CSleep mode. - 17 - 1 - - - SPI2S2SMEN - SPI2S2 clock enable during CPU1 CSleep mode. - 14 - 1 - - - WWDGSMEN - Window watchdog clocks enable during CPU1 CSleep mode. - 11 - 1 - - - RTCAPBSMEN - RTC bus clock enable during CPU1 CSleep mode. - 10 - 1 - - - TIM2SMEN - TIM2 timer clock enable during CPU1 CSleep mode. - 0 - 1 - - - - - APB1SMENR2 - APB1SMENR2 - APB1 peripheral clocks enable in Sleep mode register 2 - 0x7C - 0x20 - read-write - 0x00000061 - - - LPTIM3SMEN - Low power timer 3 clock enable during CPU1 Csleep and CStop modes - 6 - 1 - - - LPTIM2SMEN - Low power timer 2 clock enable during CPU1 Csleep and CStop modes - 5 - 1 - - - LPUART1SMEN - Low power UART 1 clock enable during CPU1 Csleep and CStop modes. - 0 - 1 - - - - - APB2SMENR - APB2SMENR - APB2 peripheral clocks enable in Sleep mode register - 0x80 - 0x20 - read-write - 0x00065A00 - - - TIM17SMEN - TIM17 timer clock enable during CPU1 CSleep mode. - 18 - 1 - - - TIM16SMEN - TIM16 timer clock enable during CPU1 CSleep mode. - 17 - 1 - - - USART1SMEN - USART1 clock enable during CPU1 Csleep and CStop modes. - 14 - 1 - - - SPI1SMEN - SPI1 clock enable during CPU1 CSleep mode. - 12 - 1 - - - TIM1SMEN - TIM1 timer clock enable during CPU1 CSleep mode. - 11 - 1 - - - ADCSMEN - ADC clocks enable during CPU1 Csleep and CStop modes - 9 - 1 - - - - - APB3SMENR - APB3SMENR - APB3 peripheral clock enable in Sleep mode register - 0x84 - 0x20 - read-write - 0x000000001 - - - SUBGHZSPISMEN - Sub-GHz radio SPI clock enable during Sleep and Stop modes - 0 - 1 - - - - - CCIPR - CCIPR - Peripherals independent clock configuration register - 0x88 - 0x20 - read-write - 0x00000000 - - - RNGSEL - RNG clock source selection - 30 - 2 - - - ADCSEL - ADC clock source selection - 28 - 2 - - - LPTIM3SEL - Low power timer 3 clock source selection - 22 - 2 - - - LPTIM2SEL - Low power timer 2 clock source selection - 20 - 2 - - - LPTIM1SEL - Low power timer 1 clock source selection - 18 - 2 - - - I2C3SEL - I2C3 clock source selection - 16 - 2 - - - I2C2SEL - I2C2 clock source selection - 14 - 2 - - - I2C1SEL - I2C1 clock source selection - 12 - 2 - - - LPUART1SEL - LPUART1 clock source selection - 10 - 2 - - - SPI2S2SEL - SPI2S2 I2S clock source selection - 8 - 2 - - - USART2SEL - USART2 clock source selection - 2 - 2 - - - USART1SEL - USART1 clock source selection - 0 - 2 + HTCFG + health test configuration + 0 + 32 - - - BDCR - BDCR - Backup domain control register - 0x90 - 0x20 - 0x00000000 - - - LSCOSEL - Low speed clock output selection - 25 - 1 - read-write - - - LSCOEN - Low speed clock output enable - 24 - 1 - read-write - - - BDRST - Backup domain software reset - 16 - 1 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - LSESYSRDY - LSE system clock ready - 11 - 1 - read-only - - - RTCSEL - RTC clock source selection - 8 - 2 - read-write - - - LSESYSEN - LSE system clock enable - 7 - 1 - read-write - - - LSECSSD - CSS on LSE failure Detection - 6 - 1 - read-only - - - LSECSSON - CSS on LSE enable - 5 - 1 - read-write - - - LSEDRV - LSE oscillator drive capability - 3 - 2 - read-write - - - LSEBYP - LSE oscillator bypass - 2 - 1 - read-write - - - LSERDY - LSE oscillator ready - 1 - 1 - read-only - - - LSEON - LSE oscillator enable - 0 - 1 - read-write - - - - - CSR - CSR - Control/status register - 0x94 - 0x20 - 0x0C01C600 - - - LPWRRSTF - Low-power reset flag - 31 - 1 - read-only - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - read-only - - - IWDGRSTF - Independent window watchdog reset flag - 29 - 1 - read-only - - - SFTRSTF - Software reset flag - 28 - 1 - read-only - - - BORRSTF - BOR flag - 27 - 1 - read-only - - - PINRSTF - Pin reset flag - 26 - 1 - read-only - - - OBLRSTF - Option byte loader reset flag - 25 - 1 - read-only - - - RFILARSTF - Radio illegal access flag - 24 - 1 - read-only - - - RMVF - Remove reset flag - 23 - 1 - read-write - - - RFRST - Radio reset - 15 - 1 - read-write - - - RFRSTF - Radio in reset status flag - 14 - 1 - read-only - - - MSISRANGE - MSI clock ranges - 8 - 4 - read-write - - - LSIPRE - LSI frequency prescaler - 4 - 1 - read-write - - - LSIRDY - LSI oscillator ready - 1 - 1 - read-only - - - LSION - LSI oscillator enable - 0 - 1 - read-write - - - - - EXTCFGR - EXTCFGR - Extended clock recovery register - 0x108 - 0x20 - 0x00030000 - - - SHDHPREF - HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) - 16 - 1 - read-only - - - SHDHPRE - HCLK3 shared prescaler (AHB3, Flash, and SRAM2) - 0 - 4 - read-write - - - + - RNG - True random number generator - RNG - 0x58001000 - - 0x0 - 0x400 - registers - - - True_RNG - True random number generator - interrupt - 52 - - - - CR - CR - control register - 0x0 - 0x20 - read-write - 0x00800000 - - - RNGEN - True random number generator enable - 2 - 1 - - - IE - Interrupt Enable - 3 - 1 - - - CED - Interrupt Enable - 5 - 1 - - - RNG_CONFIG3 - RNG_CONFIG3 - 8 - 4 - - - NISTC - NISTC - 12 - 1 - - - RNG_CONFIG2 - RNG_CONFIG2 - 13 - 3 - - - CLKDIV - CLKDIV - 16 - 4 - - - RNG_CONFIG1 - RNG_CONFIG1 - 20 - 6 - - - CONDRST - Conditioning soft reset - 30 - 1 - - - CONFIGLOCK - CONFIGLOCK - 31 - 1 - - - - - SR - SR - status register - 0x4 - 0x20 - 0x00000000 - - - SEIS - Seed error interrupt status - 6 - 1 - read-write - - - CEIS - Clock error interrupt status - 5 - 1 - read-write - - - SECS - Seed error current status - 2 - 1 - read-only - - - CECS - Clock error current status - 1 - 1 - read-only - - - DRDY - Data Ready - 0 - 1 - read-only - - - - - DR - DR - data register - 0x8 - 0x20 - read-only - 0x00000000 - - - RNDATA - Random data - 0 - 32 - - - - - HTCR - HTCR - health test control register - 0x10 - 0x20 - read-write - 0x00005A4E - - - HTCFG - health test configuration - 0 - 32 - - - - - - - RTC - Real-time clock - RTC - 0x40002800 - + RTC + Real-time clock + RTC + 0x40002800 + 0x0 0x400 registers @@ -17920,7 +16895,7 @@ Copyright (c) 2020 STMicroelectronics. 8 2 read-write - + INIT Initialization mode @@ -17962,7 +16937,7 @@ Copyright (c) 2020 STMicroelectronics. 2 1 read-only - + @@ -18670,856 +17645,180 @@ Copyright (c) 2020 STMicroelectronics. Internal timestamp flag 5 1 - - - TSOVF - Timestamp overflow flag - 4 - 1 - - - TSF - Timestamp flag - 3 - 1 - - - WUTF - Wakeup timer flag - 2 - 1 - - - ALRBF - Alarm B flag - 1 - 1 - - - ALRAF - Alarm A flag - 0 - 1 - - - - - MISR - MISR - MISR - 0x54 - 0x20 - read-only - 0x00000000 - - - SSRUMF - SSR underflow masked flag - 6 - 1 - - - ITSMF - Internal timestamp masked flag - 5 - 1 - - - TSOVMF - Timestamp overflow masked flag - 4 - 1 - - - TSMF - Timestamp masked flag - 3 - 1 - - - WUTMF - Wakeup timer masked flag - 2 - 1 - - - ALRBMF - Alarm B masked flag - 1 - 1 - - - ALRAMF - Alarm A masked flag - 0 - 1 - - - - - SCR - SCR - SCR - 0x5C - 0x20 - write-only - 0x00000000 - - - CSSRUF - Clear SSR underflow flag - 6 - 1 - - - CITSF - Clear internal timestamp flag - 5 - 1 - - - CTSOVF - Clear timestamp overflow flag - 4 - 1 - - - CTSF - Clear timestamp flag - 3 - 1 - - - CWUTF - Clear wakeup timer flag - 2 - 1 - - - CALRBF - Clear alarm B flag - 1 - 1 - - - CALRAF - Clear alarm A flag - 0 - 1 - - - - - ALRABINR - ALRABINR - RTC alarm A binary mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - SS - Synchronous counter alarm value in Binary mode - 0 - 32 - - - - - ALRBBINR - ALRBBINR - RTC alarm B binary mode register - 0x74 - 0x20 - read-write - 0x00000000 - - - SS - Synchronous counter alarm value in Binary mode - 0 - 32 - - - - - - - SCB - System control block - SCB - 0xE000ED00 - - 0x0 - 0x41 - registers - - - - CPUID - CPUID - CPUID base register - 0x0 - 0x20 - read-only - 0x410FC241 - - - Revision - Revision number - 0 - 4 - - - PartNo - Part number of the processor - 4 - 12 - - - Constant - Reads as 0xF - 16 - 4 - - - Variant - Variant number - 20 - 4 - - - Implementer - Implementer code - 24 - 8 - - - - - ICSR - ICSR - Interrupt control and state register - 0x4 - 0x20 - read-write - 0x00000000 - - - VECTACTIVE - Active vector - 0 - 9 - - - RETTOBASE - Return to base level - 11 - 1 - - - VECTPENDING - Pending vector - 12 - 7 - - - ISRPENDING - Interrupt pending flag - 22 - 1 - - - PENDSTCLR - SysTick exception clear-pending bit - 25 - 1 - - - PENDSTSET - SysTick exception set-pending bit - 26 - 1 - - - PENDSVCLR - PendSV clear-pending bit - 27 - 1 - - - PENDSVSET - PendSV set-pending bit - 28 - 1 - - - NMIPENDSET - NMI set-pending bit. - 31 - 1 - - - - - VTOR - VTOR - Vector table offset register - 0x8 - 0x20 - read-write - 0x00000000 - - - TBLOFF - Vector table base offset field - 9 - 21 - - - - - AIRCR - AIRCR - Application interrupt and reset control register - 0xC - 0x20 - read-write - 0x00000000 - - - VECTRESET - VECTRESET - 0 - 1 - - - VECTCLRACTIVE - VECTCLRACTIVE - 1 - 1 - - - SYSRESETREQ - SYSRESETREQ - 2 - 1 - - - PRIGROUP - PRIGROUP - 8 - 3 - - - ENDIANESS - ENDIANESS - 15 - 1 - - - VECTKEYSTAT - Register key - 16 - 16 - - - - - SCR - SCR - System control register - 0x10 - 0x20 - read-write - 0x00000000 - - - SLEEPONEXIT - SLEEPONEXIT - 1 - 1 - - - SLEEPDEEP - SLEEPDEEP - 2 - 1 - - - SEVEONPEND - Send Event on Pending bit - 4 - 1 - - - - - CCR - CCR - Configuration and control register - 0x14 - 0x20 - read-write - 0x00000000 - - - NONBASETHRDENA - Configures how the processor enters Thread mode - 0 - 1 - - - USERSETMPEND - USERSETMPEND - 1 - 1 - - - UNALIGN__TRP - UNALIGN_ TRP - 3 - 1 - - - DIV_0_TRP - DIV_0_TRP - 4 - 1 - - - BFHFNMIGN - BFHFNMIGN - 8 - 1 - - - STKALIGN - STKALIGN - 9 - 1 - - - - - SHPR1 - SHPR1 - System handler priority registers - 0x18 - 0x20 - read-write - 0x00000000 - - - PRI_4 - Priority of system handler 4 - 0 - 8 - - - PRI_5 - Priority of system handler 5 - 8 - 8 - - - PRI_6 - Priority of system handler 6 - 16 - 8 - - - - - SHPR2 - SHPR2 - System handler priority registers - 0x1C - 0x20 - read-write - 0x00000000 - - - PRI_11 - Priority of system handler 11 - 24 - 8 - - - - - SHPR3 - SHPR3 - System handler priority registers - 0x20 - 0x20 - read-write - 0x00000000 - - - PRI_14 - Priority of system handler 14 - 16 - 8 - - - PRI_15 - Priority of system handler 15 - 24 - 8 - - - - - SHCSR - SHCSR - System handler control and state register - 0x24 - 0x20 - read-write - 0x00000000 - - - MEMFAULTACT - Memory management fault exception active bit - 0 - 1 - - - BUSFAULTACT - Bus fault exception active bit - 1 - 1 - - - USGFAULTACT - Usage fault exception active bit - 3 - 1 - - - SVCALLACT - SVC call active bit - 7 - 1 - - - MONITORACT - Debug monitor active bit - 8 - 1 - - - PENDSVACT - PendSV exception active bit - 10 - 1 - - - SYSTICKACT - SysTick exception active bit - 11 - 1 - - - USGFAULTPENDED - Usage fault exception pending bit - 12 - 1 - - - MEMFAULTPENDED - Memory management fault exception pending bit - 13 - 1 - - - BUSFAULTPENDED - Bus fault exception pending bit - 14 - 1 - - - SVCALLPENDED - SVC call pending bit - 15 - 1 - - - MEMFAULTENA - Memory management fault enable bit - 16 - 1 - - - BUSFAULTENA - Bus fault enable bit - 17 - 1 - - - USGFAULTENA - Usage fault enable bit - 18 - 1 - - - - - CFSR_UFSR_BFSR_MMFSR - CFSR_UFSR_BFSR_MMFSR - Configurable fault status register - 0x28 - 0x20 - read-write - 0x00000000 - - - IACCVIOL - Instruction access violation flag - 1 - 1 - - - MUNSTKERR - Memory manager fault on unstacking for a return from exception - 3 - 1 - - - MSTKERR - Memory manager fault on stacking for exception entry. - 4 - 1 - - - MLSPERR - MLSPERR - 5 - 1 - - - MMARVALID - Memory Management Fault Address Register (MMAR) valid flag - 7 - 1 - - - IBUSERR - Instruction bus error - 8 - 1 - - - PRECISERR - Precise data bus error - 9 - 1 - - - IMPRECISERR - Imprecise data bus error - 10 - 1 - - - UNSTKERR - Bus fault on unstacking for a return from exception - 11 - 1 - - - STKERR - Bus fault on stacking for exception entry - 12 - 1 - - - LSPERR - Bus fault on floating-point lazy state preservation - 13 - 1 - - - BFARVALID - Bus Fault Address Register (BFAR) valid flag - 15 - 1 - - - UNDEFINSTR - Undefined instruction usage fault - 16 - 1 - - - INVSTATE - Invalid state usage fault - 17 - 1 - - - INVPC - Invalid PC load usage fault - 18 - 1 - - - NOCP - No coprocessor usage fault. - 19 - 1 - - - UNALIGNED - Unaligned access usage fault - 24 - 1 - - - DIVBYZERO - Divide by zero usage fault - 25 - 1 - - - - - HFSR - HFSR - Hard fault status register - 0x2C - 0x20 - read-write - 0x00000000 - - - VECTTBL - Vector table hard fault - 1 - 1 - - - FORCED - Forced hard fault - 30 - 1 - - - DEBUG_VT - Reserved for Debug use - 31 - 1 - - - - - MMFAR - MMFAR - Memory management fault address register - 0x34 - 0x20 - read-write - 0x00000000 - - - MMFAR - Memory management fault address - 0 - 32 - - - - - BFAR - BFAR - Bus fault address register - 0x38 - 0x20 - read-write - 0x00000000 - - - BFAR - Bus fault address - 0 - 32 - - - - - AFSR - AFSR - Auxiliary fault status register - 0x3C - 0x20 - read-write - 0x00000000 - - - IMPDEF - Implementation defined - 0 - 32 - - - - - - - SCB_ACTRL - System control block ACTLR - SCB - 0xE000E008 - - 0x0 - 0x5 - registers - - - - ACTRL - ACTRL - Auxiliary control register - 0x0 - 0x20 - read-write - 0x00000000 - - - DISMCYCINT - DISMCYCINT - 0 - 1 - - - DISDEFWBUF - DISDEFWBUF - 1 - 1 - - - DISFOLD - DISFOLD - 2 - 1 - - - DISFPCA - DISFPCA - 8 - 1 - - - DISOOFP - DISOOFP - 9 - 1 - - - - + + + TSOVF + Timestamp overflow flag + 4 + 1 + + + TSF + Timestamp flag + 3 + 1 + + + WUTF + Wakeup timer flag + 2 + 1 + + + ALRBF + Alarm B flag + 1 + 1 + + + ALRAF + Alarm A flag + 0 + 1 + + + + + MISR + MISR + MISR + 0x54 + 0x20 + read-only + 0x00000000 + + + SSRUMF + SSR underflow masked flag + 6 + 1 + + + ITSMF + Internal timestamp masked flag + 5 + 1 + + + TSOVMF + Timestamp overflow masked flag + 4 + 1 + + + TSMF + Timestamp masked flag + 3 + 1 + + + WUTMF + Wakeup timer masked flag + 2 + 1 + + + ALRBMF + Alarm B masked flag + 1 + 1 + + + ALRAMF + Alarm A masked flag + 0 + 1 + + + + + SCR + SCR + SCR + 0x5C + 0x20 + write-only + 0x00000000 + + + CSSRUF + Clear SSR underflow flag + 6 + 1 + + + CITSF + Clear internal timestamp flag + 5 + 1 + + + CTSOVF + Clear timestamp overflow flag + 4 + 1 + + + CTSF + Clear timestamp flag + 3 + 1 + + + CWUTF + Clear wakeup timer flag + 2 + 1 + + + CALRBF + Clear alarm B flag + 1 + 1 + + + CALRAF + Clear alarm A flag + 0 + 1 + + + + + ALRABINR + ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + read-write + 0x00000000 + + + SS + Synchronous counter alarm value in Binary mode + 0 + 32 + + + + + ALRBBINR + ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + read-write + 0x00000000 + + + SS + Synchronous counter alarm value in Binary mode + 0 + 32 + + + + SPI1 @@ -19963,7 +18262,7 @@ Copyright (c) 2020 STMicroelectronics. 1 - + @@ -19977,119 +18276,8 @@ Copyright (c) 2020 STMicroelectronics. SPI3 - 0x58010000 - - - STK - SysTick timer - STK - 0xE000E010 - - 0x0 - 0x11 - registers - - - - CTRL - CTRL - SysTick control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - ENABLE - Counter enable - 0 - 1 - - - TICKINT - SysTick exception request enable - 1 - 1 - - - CLKSOURCE - Clock source selection - 2 - 1 - - - COUNTFLAG - COUNTFLAG - 16 - 1 - - - - - LOAD - LOAD - SysTick reload value register - 0x4 - 0x20 - read-write - 0x00000000 - - - RELOAD - RELOAD value - 0 - 24 - - - - - VAL - VAL - SysTick current value register - 0x8 - 0x20 - read-write - 0x00000000 - - - CURRENT - Current counter value - 0 - 24 - - - - - CALIB - CALIB - SysTick calibration value register - 0xC - 0x20 - read-write - 0x00000000 - - - TENMS - Calibration value - 0 - 24 - - - SKEW - SKEW flag: Indicates whether the TENMS value is exact - 30 - 1 - - - NOREF - NOREF flag. Reads as zero - 31 - 1 - - - - - + 0x58010000 + SYSCFG System configuration controller @@ -26514,7 +24702,7 @@ Copyright (c) 2020 STMicroelectronics. 4 - +