[SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.

topperc · topperc · commit 6b9cd72c1b55 · 2019-05-06T19:50:14.000Z
It's possible to use the 'y' mmx constraint with a type narrower than 64-bits. This patch supports this by bitcasting the mmx type to 64-bits and then truncating to the desired type. There are probably other missing type combinations we need to support, but this is the case we have a bug report for. Fixes PR41748. Differential Revision: https://reviews.llvm.org/D61582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360069 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -322,6 +322,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
     return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
   }
 
+  // Handle MMX to a narrower integer type by bitcasting MMX to integer and
+  // then truncating.
+  if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
+      ValueVT.bitsLT(PartEVT)) {
+    Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);
+    return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
+  }
+
   report_fatal_error("Unknown mismatch in getCopyFromParts!");
 }
 
diff --git a/test/CodeGen/X86/pr41748.ll b/test/CodeGen/X86/pr41748.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.14.0 -mattr=mmx | FileCheck %s
+
+define i32 @foo(i32 %a) {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    movd %edi, %mm0
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    movd %mm0, %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i32 asm sideeffect "movd    $1, $0", "=y,r,~{dirflag},~{fpsr},~{flags}"(i32 %a)
+  ret i32 %0
+}

Original file line number	Diff line number	Diff line change
`@@ -322,6 +322,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,`
`322`	`322`	`return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);`
`323`	`323`	`}`
`324`	`324`
	`325`	`+ // Handle MMX to a narrower integer type by bitcasting MMX to integer and`
	`326`	`+ // then truncating.`
	`327`	`+ if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&`
	`328`	`+ ValueVT.bitsLT(PartEVT)) {`
	`329`	`+ Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);`
	`330`	`+ return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);`
	`331`	`+ }`
	`332`	`+`
`325`	`333`	`report_fatal_error("Unknown mismatch in getCopyFromParts!");`
`326`	`334`	`}`
`327`	`335`