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arsenmarsenm
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AMDGPU: Update tests to use modern buffer intrinsics
1 parent c0d909a commit 20ca49b

13 files changed

+137
-132
lines changed

‎llvm/test/CodeGen/AMDGPU/amdpal.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,13 +77,13 @@ entry:
7777
%e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx
7878
%x = load i32, i32 addrspace(5)* %e
7979
%xf = bitcast i32 %x to float
80-
call void @llvm.amdgcn.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
80+
call void @llvm.amdgcn.raw.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i32 0)
8181
ret void
8282
}
8383

8484
attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
8585

86-
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1)
86+
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg)
8787

8888

8989
; Check we have CS_NUM_USED_VGPRS in PAL metadata.

‎llvm/test/CodeGen/AMDGPU/else.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,12 +49,12 @@ else:
4949

5050
end:
5151
%r = phi float [ %v.if, %if ], [ %v.else, %else ]
52-
call void @llvm.amdgcn.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
52+
call void @llvm.amdgcn.raw.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i32 0)
5353
ret void
5454
}
5555

56-
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
57-
declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
56+
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #1
57+
declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
5858

5959
attributes #0 = { nounwind }
6060
attributes #1 = { nounwind writeonly }

‎llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ for.body:
2929
br i1 %cc, label %mid.loop, label %for.end
3030

3131
mid.loop:
32-
%v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i1 false, i1 false)
32+
%v = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i32 0, i32 0)
3333
%cc2 = fcmp oge float %v, 0.0
3434
br i1 %cc2, label %end.loop, label %for.end
3535

@@ -48,7 +48,7 @@ end:
4848
ret void
4949
}
5050

51-
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
51+
declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
5252
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
5353

5454
attributes #0 = { nounwind readonly }

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@
99
;CHECK: v_add_f32_e32
1010
define amdgpu_ps float @test1(i32 inreg %idx0, i32 inreg %idx1) {
1111
main_body:
12-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
13-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
12+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
13+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
1414
%out = fadd float %src0, %src1
1515
%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
1616
ret float %out.0
@@ -25,8 +25,8 @@ main_body:
2525
;CHECK: v_add_f32_e32
2626
define amdgpu_ps float @test2(i32 inreg %idx0, i32 inreg %idx1) {
2727
main_body:
28-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
29-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
28+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
29+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
3030
%out = fadd float %src0, %src1
3131
%out.0 = bitcast float %out to i32
3232
%out.1 = call i32 @llvm.amdgcn.softwqm.i32(i32 %out.0)
@@ -45,10 +45,10 @@ main_body:
4545
;CHECK: v_add_f32_e32
4646
define amdgpu_ps float @test_softwqm1(i32 inreg %idx0, i32 inreg %idx1) {
4747
main_body:
48-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
49-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
48+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
49+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
5050
%temp = fadd float %src0, %src1
51-
call void @llvm.amdgcn.buffer.store.f32(float %temp, <4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
51+
call void @llvm.amdgcn.struct.buffer.store.f32(float %temp, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
5252
%out = fadd float %temp, %temp
5353
%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
5454
ret float %out.0
@@ -67,11 +67,11 @@ main_body:
6767
;CHECK: v_add_f32_e32
6868
define amdgpu_ps float @test_softwqm2(i32 inreg %idx0, i32 inreg %idx1) {
6969
main_body:
70-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
71-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
70+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
71+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
7272
%temp = fadd float %src0, %src1
7373
%temp.0 = call float @llvm.amdgcn.wqm.f32(float %temp)
74-
call void @llvm.amdgcn.buffer.store.f32(float %temp.0, <4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
74+
call void @llvm.amdgcn.struct.buffer.store.f32(float %temp.0, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
7575
%out = fadd float %temp, %temp
7676
%out.0 = call float @llvm.amdgcn.softwqm.f32(float %out)
7777
ret float %out.0
@@ -89,9 +89,9 @@ main_body:
8989
;CHECK-NOT: s_wqm_b64
9090
define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1) {
9191
main_body:
92-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
93-
call void @llvm.amdgcn.buffer.store.f32(float %src0, <4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
94-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
92+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
93+
call void @llvm.amdgcn.struct.buffer.store.f32(float %src0, <4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
94+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
9595
%temp = fadd float %src0, %src1
9696
%temp.0 = call float @llvm.amdgcn.wwm.f32(float %temp)
9797
%out = fadd float %temp.0, %temp.0
@@ -115,14 +115,14 @@ main_body:
115115
br i1 %cmp, label %IF, label %ELSE
116116

117117
IF:
118-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
119-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
118+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
119+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
120120
%out = fadd float %src0, %src1
121121
%data.if = call float @llvm.amdgcn.softwqm.f32(float %out)
122122
br label %END
123123

124124
ELSE:
125-
call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 %c, i32 0, i1 0, i1 0)
125+
call void @llvm.amdgcn.struct.buffer.store.f32(float %data, <4 x i32> undef, i32 %c, i32 0, i32 0, i32 0)
126126
br label %END
127127

128128
END:
@@ -157,24 +157,24 @@ main_body:
157157
br i1 %cmp, label %IF, label %ELSE
158158

159159
IF:
160-
%src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0)
161-
%src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0)
160+
%src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
161+
%src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
162162
%out = fadd float %src0, %src1
163163
%data.if = call float @llvm.amdgcn.softwqm.f32(float %out)
164164
br label %END
165165

166166
ELSE:
167-
call void @llvm.amdgcn.buffer.store.f32(float %data.sample, <4 x i32> undef, i32 %c, i32 0, i1 0, i1 0)
167+
call void @llvm.amdgcn.struct.buffer.store.f32(float %data.sample, <4 x i32> undef, i32 %c, i32 0, i32 0, i32 0)
168168
br label %END
169169

170170
END:
171171
%r = phi float [ %data.if, %IF ], [ %data, %ELSE ]
172172
ret float %r
173173
}
174174

175-
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #2
176-
declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #2
177-
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #3
175+
declare void @llvm.amdgcn.struct.buffer.store.f32(float, <4 x i32>, i32, i32, i32, i32 immarg) #2
176+
declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg) #2
177+
declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg) #3
178178
declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3
179179
declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3
180180
declare void @llvm.amdgcn.kill(i1) #1

‎llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ loop:
2222
br i1 %tmp27, label %then, label %endif
2323

2424
then: ; preds = %bb
25-
call void @llvm.amdgcn.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i1 false, i1 false) #1
25+
call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i32 0)
2626
br label %endif
2727

2828
endif: ; preds = %bb28, %bb
@@ -49,7 +49,7 @@ loop:
4949
%tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ]
5050
%tmp23 = add nuw i32 %tmp23phi, 1
5151
%tmp27 = icmp ult i32 %arg, %tmp23
52-
call void @llvm.amdgcn.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i1 false, i1 false) #1
52+
call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i32 0)
5353
br i1 %tmp27, label %loop, label %loopexit
5454

5555
loopexit:
@@ -76,7 +76,7 @@ loop:
7676
br i1 %tmp27, label %then, label %endif
7777

7878
then: ; preds = %bb
79-
call void @llvm.amdgcn.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i1 false, i1 false) #1
79+
call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> undef, i32 0, i32 undef, i32 0)
8080
br label %endif
8181

8282
endif: ; preds = %bb28, %bb
@@ -86,8 +86,6 @@ loopexit:
8686
ret void
8787
}
8888

89+
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
8990

90-
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #3
91-
92-
attributes #3 = { nounwind writeonly }
93-
91+
attributes #0 = { nounwind writeonly }

‎llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
; W32: v_mov_b32_e32 v0, [[RES]]
4343

4444
define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 {
45-
%call = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i1 zeroext false, i1 zeroext false) #1
45+
%call = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i32 0, i32 0) #1
4646
ret float %call
4747
}
4848

@@ -128,8 +128,8 @@ define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 {
128128

129129
define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, float addrspace(1)* %out0, float addrspace(1)* %out1) #0 {
130130
entry:
131-
%val0 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i1 zeroext false, i1 zeroext false) #1
132-
%val1 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %j, i32 %c, i32 0, i1 zeroext false, i1 zeroext false) #1
131+
%val0 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %c, i32 0, i32 0, i32 0) #1
132+
%val1 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %j, i32 %c, i32 0, i32 0, i32 0) #1
133133
store volatile float %val0, float addrspace(1)* %out0
134134
store volatile float %val1, float addrspace(1)* %out1
135135
ret void
@@ -317,13 +317,13 @@ entry:
317317
define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, float addrspace(1)* %in, float addrspace(1)* %out) #0 {
318318
entry:
319319
%live.out.reg = call i32 asm sideeffect "s_mov_b32 $0, 17", "={s4}" ()
320-
%val0 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %i, i32 %live.out.reg, i32 0, i1 zeroext false, i1 zeroext false) #1
320+
%val0 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i, i32 %live.out.reg, i32 0, i32 0, i32 0) #1
321321
%idx = call i32 @llvm.amdgcn.workitem.id.x() #1
322322
%cmp = icmp eq i32 %idx, 0
323323
br i1 %cmp, label %bb1, label %bb2
324324

325325
bb1:
326-
%val1 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %j, i32 %live.out.reg, i32 0, i1 zeroext false, i1 zeroext false) #1
326+
%val1 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %j, i32 %live.out.reg, i32 0, i32 0, i32 0) #1
327327
br label %bb2
328328

329329
bb2:
@@ -333,7 +333,7 @@ bb2:
333333
}
334334

335335
declare i32 @llvm.amdgcn.workitem.id.x() #1
336-
declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
336+
declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #1
337337

338338
attributes #0 = { nounwind }
339-
attributes #1 = { nounwind readnone }
339+
attributes #1 = { nounwind readonly }

‎llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define amdgpu_vs float @test_none(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
99
main_body:
1010
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
1111
%tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
12-
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i1 0, i1 0)
12+
%tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i32 0)
1313
ret float %tmp7
1414
}
1515

@@ -19,7 +19,7 @@ define amdgpu_vs float @test_idxen(<4 x i32> addrspace(4)* inreg %base, i32 %i)
1919
main_body:
2020
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
2121
%tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
22-
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i1 0, i1 0)
22+
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0, i32 0)
2323
ret float %tmp7
2424
}
2525

@@ -29,7 +29,7 @@ define amdgpu_vs float @test_offen(<4 x i32> addrspace(4)* inreg %base, i32 %i)
2929
main_body:
3030
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
3131
%tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
32-
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 undef, i1 0, i1 0)
32+
%tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0)
3333
ret float %tmp7
3434
}
3535

@@ -39,10 +39,12 @@ define amdgpu_vs float @test_both(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
3939
main_body:
4040
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
4141
%tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
42-
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i1 0, i1 0)
42+
%tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i32 0, i32 0)
4343
ret float %tmp7
4444
}
4545

46-
declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) nounwind readonly
46+
declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #1
47+
declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32 immarg) #1
4748

4849
attributes #0 = { nounwind readnone }
50+
attributes #1 = { nounwind readonly }

‎llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
; CHECK: s_cbranch_vccnz
99
define amdgpu_ps float @main(<4 x i32> inreg %rsrc) {
1010
main_body:
11-
%v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 true, i1 false)
11+
%v = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 1)
1212
%cc = fcmp une float %v, 1.000000e+00
1313
br i1 %cc, label %if, label %else
1414

@@ -22,7 +22,6 @@ else:
2222
ret float %r
2323
}
2424

25-
; Function Attrs: nounwind readonly
26-
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
25+
declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32 immarg) #0
2726

2827
attributes #0 = { nounwind readonly }

‎llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,10 @@ entry:
3939

4040
bb0:
4141
%desc = load <4 x i32>, <4 x i32>* %arg, align 8
42-
tail call void @llvm.amdgcn.buffer.store.f32(float undef, <4 x i32> %desc, i32 0, i32 undef, i1 zeroext false, i1 zeroext false)
42+
tail call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> %desc, i32 undef, i32 0, i32 0)
4343
br label %bb0
4444
}
4545

46-
; Function Attrs: nounwind writeonly
47-
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1 immarg, i1 immarg)
46+
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
47+
48+
attributes #0 = { nounwind writeonly }

‎llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ bb:
3838
%tmp16 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp15, align 16, !tbaa !0
3939
%tmp17 = add i32 %arg5, %arg7
4040
%tmp16.cast = bitcast <4 x i32> %tmp16 to <4 x i32>
41-
%tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp16.cast, i32 %tmp17, i32 0, i1 false, i1 false)
41+
%tmp18 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %tmp16.cast, i32 %tmp17, i32 0, i32 0, i32 0)
4242
%tmp19 = extractelement <4 x float> %tmp18, i32 0
4343
%tmp20 = extractelement <4 x float> %tmp18, i32 1
4444
%tmp21 = extractelement <4 x float> %tmp18, i32 2
@@ -489,7 +489,7 @@ declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
489489
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
490490

491491
declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1
492-
declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
492+
declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #2
493493

494494
attributes #0 = { nounwind }
495495
attributes #1 = { nounwind readnone }

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