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kaz7Simon Moll
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[VE] i<N> and fp32/64 arguments, return values and constants
Summary: Support for i<N> and fp32/64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73092
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-195
lines changed

11 files changed

+1627
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‎llvm/lib/Target/VE/VECallingConv.td

Lines changed: 28 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,14 +17,40 @@
1717
def CC_VE : CallingConv<[
1818
// All arguments get passed in generic registers if there is space.
1919

20+
// Promote i1/i8/i16 arguments to i32.
21+
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
22+
23+
// bool, char, int, enum, long --> generic integer 32 bit registers
24+
CCIfType<[i32], CCAssignToRegWithShadow<
25+
[SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],
26+
[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
27+
28+
// float --> generic floating point 32 bit registers
29+
CCIfType<[f32], CCAssignToRegWithShadow<
30+
[SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],
31+
[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
32+
2033
// long long/double --> generic 64 bit registers
21-
CCIfType<[i64],
34+
CCIfType<[i64, f64],
2235
CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
2336
]>;
2437

2538
def RetCC_VE : CallingConv<[
39+
// Promote i1/i8/i16 arguments to i32.
40+
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
41+
42+
// bool, char, int, enum, long --> generic integer 32 bit registers
43+
CCIfType<[i32], CCAssignToRegWithShadow<
44+
[SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],
45+
[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
46+
47+
// float --> generic floating point 32 bit registers
48+
CCIfType<[f32], CCAssignToRegWithShadow<
49+
[SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],
50+
[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
51+
2652
// long long/double --> generic 64 bit registers
27-
CCIfType<[i64],
53+
CCIfType<[i64, f64],
2854
CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
2955
]>;
3056

‎llvm/lib/Target/VE/VEISelLowering.cpp

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,8 @@ VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
8989
llvm_unreachable("Unknown loc info!");
9090
}
9191

92+
assert(!VA.needsCustom() && "Unexpected custom lowering");
93+
9294
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
9395

9496
// Guarantee that all emitted copies are stuck together with flags.
@@ -136,8 +138,10 @@ SDValue VETargetLowering::LowerFormalArguments(
136138
MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));
137139
SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
138140

139-
assert((VA.getValVT() == MVT::i64) &&
140-
"TODO implement other argument types than i64");
141+
// Get the high bits for i32 struct elements.
142+
if (VA.getValVT() == MVT::i32 && VA.needsCustom())
143+
Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
144+
DAG.getConstant(32, DL, MVT::i32));
141145

142146
// The caller promoted the argument, so insert an Assert?ext SDNode so we
143147
// won't promote the value again in this function.
@@ -193,6 +197,14 @@ Register VETargetLowering::getRegisterByName(const char *RegName, LLT VT,
193197
// TargetLowering Implementation
194198
//===----------------------------------------------------------------------===//
195199

200+
/// isFPImmLegal - Returns true if the target can instruction select the
201+
/// specified FP immediate natively. If false, the legalizer will
202+
/// materialize the FP immediate as a load from a constant pool.
203+
bool VETargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
204+
bool ForCodeSize) const {
205+
return VT == MVT::f32 || VT == MVT::f64;
206+
}
207+
196208
VETargetLowering::VETargetLowering(const TargetMachine &TM,
197209
const VESubtarget &STI)
198210
: TargetLowering(TM), Subtarget(&STI) {
@@ -205,7 +217,10 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
205217
setBooleanVectorContents(ZeroOrOneBooleanContent);
206218

207219
// Set up the register classes.
220+
addRegisterClass(MVT::i32, &VE::I32RegClass);
208221
addRegisterClass(MVT::i64, &VE::I64RegClass);
222+
addRegisterClass(MVT::f32, &VE::F32RegClass);
223+
addRegisterClass(MVT::f64, &VE::I64RegClass);
209224

210225
setStackPointerRegisterToSaveRestore(VE::SX11);
211226

‎llvm/lib/Target/VE/VEISelLowering.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,9 @@ class VETargetLowering : public TargetLowering {
3434
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
3535

3636
const char *getTargetNodeName(unsigned Opcode) const override;
37+
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
38+
return MVT::i32;
39+
}
3740

3841
Register getRegisterByName(const char *RegName, LLT VT,
3942
const MachineFunction &MF) const override;
@@ -56,6 +59,9 @@ class VETargetLowering : public TargetLowering {
5659
const SmallVectorImpl<ISD::OutputArg> &Outs,
5760
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
5861
SelectionDAG &DAG) const override;
62+
63+
bool isFPImmLegal(const APFloat &Imm, EVT VT,
64+
bool ForCodeSize) const override;
5965
};
6066
} // namespace llvm
6167

‎llvm/lib/Target/VE/VEInstrFormats.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,8 @@ class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
4444
let Inst{63-32} = imm32;
4545
}
4646

47-
class RR<bits<8>opVal, dag outs, dag ins, string asmstr>
48-
: RM<opVal, outs, ins, asmstr> {
47+
class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
48+
: RM<opVal, outs, ins, asmstr, pattern> {
4949
bits<1> cw = 0;
5050
bits<1> cw2 = 0;
5151
bits<4> cfw = 0;

‎llvm/lib/Target/VE/VEInstrInfo.cpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,12 +38,18 @@ VEInstrInfo::VEInstrInfo(VESubtarget &ST)
3838
: VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI(),
3939
Subtarget(ST) {}
4040

41+
static bool IsAliasOfSX(Register Reg) {
42+
return VE::I8RegClass.contains(Reg) || VE::I16RegClass.contains(Reg) ||
43+
VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
44+
VE::F32RegClass.contains(Reg);
45+
}
46+
4147
void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4248
MachineBasicBlock::iterator I, const DebugLoc &DL,
4349
MCRegister DestReg, MCRegister SrcReg,
4450
bool KillSrc) const {
4551

46-
if (VE::I64RegClass.contains(SrcReg) && VE::I64RegClass.contains(DestReg)) {
52+
if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {
4753
BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
4854
.addReg(SrcReg, getKillRegState(KillSrc))
4955
.addImm(0);

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