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AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
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8 files changed

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8 files changed

+285
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‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,30 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg,
8888
return RB->getID() == AMDGPU::VCCRegBankID;
8989
}
9090

91+
bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
92+
unsigned NewOpc) const {
93+
MI.setDesc(TII.get(NewOpc));
94+
MI.RemoveOperand(1); // Remove intrinsic ID.
95+
MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
96+
97+
MachineOperand &Dst = MI.getOperand(0);
98+
MachineOperand &Src = MI.getOperand(1);
99+
100+
// TODO: This should be legalized to s32 if needed
101+
if (MRI->getType(Dst.getReg()) == LLT::scalar(1))
102+
return false;
103+
104+
const TargetRegisterClass *DstRC
105+
= TRI.getConstrainedRegClassForOperand(Dst, *MRI);
106+
const TargetRegisterClass *SrcRC
107+
= TRI.getConstrainedRegClassForOperand(Src, *MRI);
108+
if (!DstRC || DstRC != SrcRC)
109+
return false;
110+
111+
return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
112+
RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
113+
}
114+
91115
bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
92116
const DebugLoc &DL = I.getDebugLoc();
93117
MachineBasicBlock *BB = I.getParent();
@@ -706,6 +730,12 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
706730
}
707731
case Intrinsic::amdgcn_interp_p1_f16:
708732
return selectInterpP1F16(I);
733+
case Intrinsic::amdgcn_wqm:
734+
return constrainCopyLikeIntrin(I, AMDGPU::WQM);
735+
case Intrinsic::amdgcn_softwqm:
736+
return constrainCopyLikeIntrin(I, AMDGPU::SOFT_WQM);
737+
case Intrinsic::amdgcn_wwm:
738+
return constrainCopyLikeIntrin(I, AMDGPU::WWM);
709739
default:
710740
return selectImpl(I, *CoverageInfo);
711741
}

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,8 @@ class AMDGPUInstructionSelector : public InstructionSelector {
8080
MachineOperand getSubOperand64(MachineOperand &MO,
8181
const TargetRegisterClass &SubRC,
8282
unsigned SubIdx) const;
83+
84+
bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
8385
bool selectCOPY(MachineInstr &I) const;
8486
bool selectPHI(MachineInstr &I) const;
8587
bool selectG_TRUNC(MachineInstr &I) const;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3096,15 +3096,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
30963096
case Intrinsic::amdgcn_udot4:
30973097
case Intrinsic::amdgcn_sdot8:
30983098
case Intrinsic::amdgcn_udot8:
3099-
case Intrinsic::amdgcn_wwm:
3100-
case Intrinsic::amdgcn_wqm:
31013099
return getDefaultMappingVOP(MI);
31023100
case Intrinsic::amdgcn_ds_swizzle:
31033101
case Intrinsic::amdgcn_ds_permute:
31043102
case Intrinsic::amdgcn_ds_bpermute:
31053103
case Intrinsic::amdgcn_update_dpp:
31063104
case Intrinsic::amdgcn_mov_dpp8:
31073105
case Intrinsic::amdgcn_mov_dpp:
3106+
case Intrinsic::amdgcn_wwm:
3107+
case Intrinsic::amdgcn_wqm:
3108+
case Intrinsic::amdgcn_softwqm:
31083109
return getDefaultMappingAllVGPR(MI);
31093110
case Intrinsic::amdgcn_kernarg_segment_ptr:
31103111
case Intrinsic::amdgcn_s_getpc:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3+
4+
define amdgpu_ps float @softwqm_f32(float %val) {
5+
; GCN-LABEL: name: softwqm_f32
6+
; GCN: bb.1 (%ir-block.0):
7+
; GCN: liveins: $vgpr0
8+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
9+
; GCN: [[SOFT_WQM:%[0-9]+]]:vgpr_32 = SOFT_WQM [[COPY]], implicit $exec
10+
; GCN: $vgpr0 = COPY [[SOFT_WQM]]
11+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
12+
%ret = call float @llvm.amdgcn.softwqm.f32(float %val)
13+
ret float %ret
14+
}
15+
16+
define amdgpu_ps float @softwqm_v2f16(float %arg) {
17+
; GCN-LABEL: name: softwqm_v2f16
18+
; GCN: bb.1 (%ir-block.0):
19+
; GCN: liveins: $vgpr0
20+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21+
; GCN: [[SOFT_WQM:%[0-9]+]]:vgpr_32 = SOFT_WQM [[COPY]], implicit $exec
22+
; GCN: $vgpr0 = COPY [[SOFT_WQM]]
23+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
24+
%val = bitcast float %arg to <2 x half>
25+
%ret = call <2 x half> @llvm.amdgcn.softwqm.v2f16(<2 x half> %val)
26+
%bc = bitcast <2 x half> %ret to float
27+
ret float %bc
28+
}
29+
30+
define amdgpu_ps <2 x float> @softwqm_f64(double %val) {
31+
; GCN-LABEL: name: softwqm_f64
32+
; GCN: bb.1 (%ir-block.0):
33+
; GCN: liveins: $vgpr0, $vgpr1
34+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
35+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
36+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
37+
; GCN: [[SOFT_WQM:%[0-9]+]]:vreg_64 = SOFT_WQM [[REG_SEQUENCE]], implicit $exec
38+
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub0
39+
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub1
40+
; GCN: $vgpr0 = COPY [[COPY2]]
41+
; GCN: $vgpr1 = COPY [[COPY3]]
42+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
43+
%ret = call double @llvm.amdgcn.softwqm.f64(double %val)
44+
%bitcast = bitcast double %ret to <2 x float>
45+
ret <2 x float> %bitcast
46+
}
47+
48+
; TODO
49+
; define amdgpu_ps float @softwqm_i1_vcc(float %val) {
50+
; %vcc = fcmp oeq float %val, 0.0
51+
; %ret = call i1 @llvm.amdgcn.softwqm.i1(i1 %vcc)
52+
; %select = select i1 %ret, float 1.0, float 0.0
53+
; ret float %select
54+
; }
55+
56+
define amdgpu_ps <3 x float> @softwqm_v3f32(<3 x float> %val) {
57+
; GCN-LABEL: name: softwqm_v3f32
58+
; GCN: bb.1 (%ir-block.0):
59+
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
60+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
61+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
62+
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
63+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
64+
; GCN: [[SOFT_WQM:%[0-9]+]]:vreg_96 = SOFT_WQM [[REG_SEQUENCE]], implicit $exec
65+
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub0
66+
; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub1
67+
; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub2
68+
; GCN: $vgpr0 = COPY [[COPY3]]
69+
; GCN: $vgpr1 = COPY [[COPY4]]
70+
; GCN: $vgpr2 = COPY [[COPY5]]
71+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
72+
%ret = call <3 x float> @llvm.amdgcn.softwqm.v3f32(<3 x float> %val)
73+
ret <3 x float> %ret
74+
}
75+
76+
declare i1 @llvm.amdgcn.softwqm.i1(i1) #0
77+
declare float @llvm.amdgcn.softwqm.f32(float) #0
78+
declare <2 x half> @llvm.amdgcn.softwqm.v2f16(<2 x half>) #0
79+
declare <3 x float> @llvm.amdgcn.softwqm.v3f32(<3 x float>) #0
80+
declare double @llvm.amdgcn.softwqm.f64(double) #0
81+
82+
attributes #0 = { nounwind readnone speculatable }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3+
4+
define amdgpu_ps float @wqm_f32(float %val) {
5+
; GCN-LABEL: name: wqm_f32
6+
; GCN: bb.1 (%ir-block.0):
7+
; GCN: liveins: $vgpr0
8+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
9+
; GCN: [[WQM:%[0-9]+]]:vgpr_32 = WQM [[COPY]], implicit $exec
10+
; GCN: $vgpr0 = COPY [[WQM]]
11+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
12+
%ret = call float @llvm.amdgcn.wqm.f32(float %val)
13+
ret float %ret
14+
}
15+
16+
define amdgpu_ps float @wqm_v2f16(float %arg) {
17+
; GCN-LABEL: name: wqm_v2f16
18+
; GCN: bb.1 (%ir-block.0):
19+
; GCN: liveins: $vgpr0
20+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21+
; GCN: [[WQM:%[0-9]+]]:vgpr_32 = WQM [[COPY]], implicit $exec
22+
; GCN: $vgpr0 = COPY [[WQM]]
23+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
24+
%val = bitcast float %arg to <2 x half>
25+
%ret = call <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half> %val)
26+
%bc = bitcast <2 x half> %ret to float
27+
ret float %bc
28+
}
29+
30+
define amdgpu_ps <2 x float> @wqm_f64(double %val) {
31+
; GCN-LABEL: name: wqm_f64
32+
; GCN: bb.1 (%ir-block.0):
33+
; GCN: liveins: $vgpr0, $vgpr1
34+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
35+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
36+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
37+
; GCN: [[WQM:%[0-9]+]]:vreg_64 = WQM [[REG_SEQUENCE]], implicit $exec
38+
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub0
39+
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub1
40+
; GCN: $vgpr0 = COPY [[COPY2]]
41+
; GCN: $vgpr1 = COPY [[COPY3]]
42+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
43+
%ret = call double @llvm.amdgcn.wqm.f64(double %val)
44+
%bitcast = bitcast double %ret to <2 x float>
45+
ret <2 x float> %bitcast
46+
}
47+
48+
; TODO
49+
; define amdgpu_ps float @wqm_i1_vcc(float %val) {
50+
; %vcc = fcmp oeq float %val, 0.0
51+
; %ret = call i1 @llvm.amdgcn.wqm.i1(i1 %vcc)
52+
; %select = select i1 %ret, float 1.0, float 0.0
53+
; ret float %select
54+
; }
55+
56+
define amdgpu_ps <3 x float> @wqm_v3f32(<3 x float> %val) {
57+
; GCN-LABEL: name: wqm_v3f32
58+
; GCN: bb.1 (%ir-block.0):
59+
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
60+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
61+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
62+
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
63+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
64+
; GCN: [[WQM:%[0-9]+]]:vreg_96 = WQM [[REG_SEQUENCE]], implicit $exec
65+
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub0
66+
; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub1
67+
; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[WQM]].sub2
68+
; GCN: $vgpr0 = COPY [[COPY3]]
69+
; GCN: $vgpr1 = COPY [[COPY4]]
70+
; GCN: $vgpr2 = COPY [[COPY5]]
71+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
72+
%ret = call <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float> %val)
73+
ret <3 x float> %ret
74+
}
75+
76+
declare i1 @llvm.amdgcn.wqm.i1(i1) #0
77+
declare float @llvm.amdgcn.wqm.f32(float) #0
78+
declare <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half>) #0
79+
declare <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float>) #0
80+
declare double @llvm.amdgcn.wqm.f64(double) #0
81+
82+
attributes #0 = { nounwind readnone speculatable }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3+
4+
define amdgpu_ps float @wwm_f32(float %val) {
5+
; GCN-LABEL: name: wwm_f32
6+
; GCN: bb.1 (%ir-block.0):
7+
; GCN: liveins: $vgpr0
8+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
9+
; GCN: [[WWM:%[0-9]+]]:vgpr_32 = WWM [[COPY]], implicit $exec
10+
; GCN: $vgpr0 = COPY [[WWM]]
11+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
12+
%ret = call float @llvm.amdgcn.wwm.f32(float %val)
13+
ret float %ret
14+
}
15+
16+
define amdgpu_ps float @wwm_v2f16(float %arg) {
17+
; GCN-LABEL: name: wwm_v2f16
18+
; GCN: bb.1 (%ir-block.0):
19+
; GCN: liveins: $vgpr0
20+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21+
; GCN: [[WWM:%[0-9]+]]:vgpr_32 = WWM [[COPY]], implicit $exec
22+
; GCN: $vgpr0 = COPY [[WWM]]
23+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
24+
%val = bitcast float %arg to <2 x half>
25+
%ret = call <2 x half> @llvm.amdgcn.wwm.v2f16(<2 x half> %val)
26+
%bc = bitcast <2 x half> %ret to float
27+
ret float %bc
28+
}
29+
30+
define amdgpu_ps <2 x float> @wwm_f64(double %val) {
31+
; GCN-LABEL: name: wwm_f64
32+
; GCN: bb.1 (%ir-block.0):
33+
; GCN: liveins: $vgpr0, $vgpr1
34+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
35+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
36+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
37+
; GCN: [[WWM:%[0-9]+]]:vreg_64 = WWM [[REG_SEQUENCE]], implicit $exec
38+
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub0
39+
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub1
40+
; GCN: $vgpr0 = COPY [[COPY2]]
41+
; GCN: $vgpr1 = COPY [[COPY3]]
42+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
43+
%ret = call double @llvm.amdgcn.wwm.f64(double %val)
44+
%bitcast = bitcast double %ret to <2 x float>
45+
ret <2 x float> %bitcast
46+
}
47+
48+
; TODO
49+
; define amdgpu_ps float @wwm_i1_vcc(float %val) {
50+
; %vcc = fcmp oeq float %val, 0.0
51+
; %ret = call i1 @llvm.amdgcn.wwm.i1(i1 %vcc)
52+
; %select = select i1 %ret, float 1.0, float 0.0
53+
; ret float %select
54+
; }
55+
56+
define amdgpu_ps <3 x float> @wwm_v3f32(<3 x float> %val) {
57+
; GCN-LABEL: name: wwm_v3f32
58+
; GCN: bb.1 (%ir-block.0):
59+
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
60+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
61+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
62+
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
63+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
64+
; GCN: [[WWM:%[0-9]+]]:vreg_96 = WWM [[REG_SEQUENCE]], implicit $exec
65+
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub0
66+
; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub1
67+
; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub2
68+
; GCN: $vgpr0 = COPY [[COPY3]]
69+
; GCN: $vgpr1 = COPY [[COPY4]]
70+
; GCN: $vgpr2 = COPY [[COPY5]]
71+
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
72+
%ret = call <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float> %val)
73+
ret <3 x float> %ret
74+
}
75+
76+
declare i1 @llvm.amdgcn.wwm.i1(i1) #0
77+
declare float @llvm.amdgcn.wwm.f32(float) #0
78+
declare <2 x half> @llvm.amdgcn.wwm.v2f16(<2 x half>) #0
79+
declare <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float>) #0
80+
declare double @llvm.amdgcn.wwm.f64(double) #0
81+
82+
attributes #0 = { nounwind readnone speculatable }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,8 @@ body: |
1111
liveins: $sgpr0
1212
; CHECK-LABEL: name: wqm_s
1313
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14-
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY]](s32)
14+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
15+
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY1]](s32)
1516
%0:_(s32) = COPY $sgpr0
1617
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0
1718
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,8 @@ body: |
1111
liveins: $sgpr0
1212
; CHECK-LABEL: name: wwm_s
1313
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14-
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), [[COPY]](s32)
14+
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
15+
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), [[COPY1]](s32)
1516
%0:_(s32) = COPY $sgpr0
1617
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), %0
1718
...

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