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arsenmarsenm
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AMDGPU/GlobalISel: Fix using illegal situations in tests
These were using illegal copies as the side effecting use, so make them legal. llvm-svn: 363168
1 parent 7eddb16 commit 61f6395

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2 files changed

+25
-28
lines changed

2 files changed

+25
-28
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -36,12 +36,12 @@ body: |
3636
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
3737
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
3838
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
39-
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
39+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
4040
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
4141
%1:_(s32) = COPY $sgpr0
4242
%2:_(s32) = COPY $sgpr1
4343
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
44-
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
44+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
4545
...
4646

4747
---
@@ -58,12 +58,12 @@ body: |
5858
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
5959
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
6060
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
61-
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
61+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
6262
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
6363
%1:_(s32) = COPY $vgpr0
6464
%2:_(s32) = COPY $sgpr4
6565
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
66-
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
66+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
6767
...
6868

6969
---
@@ -80,12 +80,12 @@ body: |
8080
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
8181
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
8282
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
83-
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
83+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
8484
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
8585
%1:_(s32) = COPY $sgpr4
8686
%2:_(s32) = COPY $vgpr0
8787
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
88-
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
88+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
8989
...
9090

9191
---
@@ -102,12 +102,12 @@ body: |
102102
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
103103
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
104104
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
105-
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
105+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
106106
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
107107
%1:_(s32) = COPY $vgpr0
108108
%2:_(s32) = COPY $vgpr1
109109
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
110-
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
110+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
111111
...
112112

113113
---
@@ -123,12 +123,12 @@ body: |
123123
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
124124
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
125125
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
126-
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
126+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
127127
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
128128
%1:_(s32) = COPY $sgpr4
129129
%2:_(s32) = COPY $vgpr0
130130
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
131-
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
131+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
132132
...
133133

134134
---
@@ -144,12 +144,12 @@ body: |
144144
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
145145
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
146146
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
147-
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
147+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
148148
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
149149
%1:_(s32) = COPY $vgpr0
150150
%2:_(s32) = COPY $sgpr0
151151
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
152-
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
152+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
153153
...
154154

155155
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir

Lines changed: 13 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
34

45
---
56
name: phi_s32_ss_sbranch
@@ -74,7 +75,7 @@ body: |
7475
; CHECK: G_BR %bb.2
7576
; CHECK: bb.2:
7677
; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
77-
; CHECK: $sgpr0 = COPY [[PHI]](s32)
78+
; CHECK: $vgpr0 = COPY [[PHI]](s32)
7879
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
7980
bb.0:
8081
successors: %bb.1, %bb.2
@@ -96,7 +97,7 @@ body: |
9697
9798
bb.2:
9899
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
99-
$sgpr0 = COPY %6
100+
$vgpr0 = COPY %6
100101
S_SETPC_B64 undef $sgpr30_sgpr31
101102
102103
...
@@ -124,7 +125,7 @@ body: |
124125
; CHECK: G_BR %bb.2
125126
; CHECK: bb.2:
126127
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
127-
; CHECK: $sgpr0 = COPY [[PHI]](s32)
128+
; CHECK: $vgpr0 = COPY [[PHI]](s32)
128129
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
129130
bb.0:
130131
successors: %bb.1, %bb.2
@@ -146,7 +147,7 @@ body: |
146147
147148
bb.2:
148149
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
149-
$sgpr0 = COPY %6
150+
$vgpr0 = COPY %6
150151
S_SETPC_B64 undef $sgpr30_sgpr31
151152
152153
...
@@ -174,7 +175,7 @@ body: |
174175
; CHECK: G_BR %bb.2
175176
; CHECK: bb.2:
176177
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
177-
; CHECK: $sgpr0 = COPY [[PHI]](s32)
178+
; CHECK: $vgpr0 = COPY [[PHI]](s32)
178179
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
179180
bb.0:
180181
successors: %bb.1, %bb.2
@@ -196,7 +197,7 @@ body: |
196197
197198
bb.2:
198199
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
199-
$sgpr0 = COPY %6
200+
$vgpr0 = COPY %6
200201
S_SETPC_B64 undef $sgpr30_sgpr31
201202
202203
...
@@ -273,7 +274,7 @@ body: |
273274
; CHECK: G_BR %bb.2
274275
; CHECK: bb.2:
275276
; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
276-
; CHECK: $sgpr0 = COPY [[PHI]](s32)
277+
; CHECK: $vgpr0 = COPY [[PHI]](s32)
277278
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
278279
bb.0:
279280
successors: %bb.1, %bb.2
@@ -295,7 +296,7 @@ body: |
295296
296297
bb.2:
297298
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
298-
$sgpr0 = COPY %6
299+
$vgpr0 = COPY %6
299300
S_SETPC_B64 undef $sgpr30_sgpr31
300301
301302
...
@@ -323,7 +324,7 @@ body: |
323324
; CHECK: G_BR %bb.2
324325
; CHECK: bb.2:
325326
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
326-
; CHECK: $sgpr0 = COPY [[PHI]](s32)
327+
; CHECK: $vgpr0 = COPY [[PHI]](s32)
327328
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
328329
bb.0:
329330
successors: %bb.1, %bb.2
@@ -345,7 +346,7 @@ body: |
345346
346347
bb.2:
347348
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
348-
$sgpr0 = COPY %6
349+
$vgpr0 = COPY %6
349350
S_SETPC_B64 undef $sgpr30_sgpr31
350351
351352
...
@@ -373,7 +374,7 @@ body: |
373374
; CHECK: G_BR %bb.2
374375
; CHECK: bb.2:
375376
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
376-
; CHECK: $sgpr0 = COPY [[PHI]](s32)
377+
; CHECK: $vgpr0 = COPY [[PHI]](s32)
377378
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
378379
bb.0:
379380
successors: %bb.1, %bb.2
@@ -395,7 +396,7 @@ body: |
395396
396397
bb.2:
397398
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
398-
$sgpr0 = COPY %6
399+
$vgpr0 = COPY %6
399400
S_SETPC_B64 undef $sgpr30_sgpr31
400401
401402
...
@@ -898,10 +899,6 @@ body: |
898899
899900
...
900901

901-
902-
903-
904-
905902
---
906903
name: phi_s1_vcc_s_sbranch
907904
legalized: true

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