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HsiangkaiEvandro Menezes
Hsiangkai
authored and
Evandro Menezes
committed
[RISCV] Scheduler description for the Rocket core
Pipeline scheduler model for the RISC-V Rocket micro-architecture using the MIScheduler interface. Support for both 32 and 64-bit Rocket cores is implemented. Differential revision: https://reviews.llvm.org/D68685
1 parent 90e630a commit 838a28e

11 files changed

+900
-186
lines changed

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,10 +92,13 @@ include "RISCVSystemOperands.td"
9292
// Registers, calling conventions, instruction descriptions.
9393
//===----------------------------------------------------------------------===//
9494

95+
include "RISCVSchedule.td"
9596
include "RISCVRegisterInfo.td"
9697
include "RISCVCallingConv.td"
9798
include "RISCVInstrInfo.td"
9899
include "RISCVRegisterBanks.td"
100+
include "RISCVSchedRocket32.td"
101+
include "RISCVSchedRocket64.td"
99102

100103
//===----------------------------------------------------------------------===//
101104
// RISC-V processors supported.
@@ -106,6 +109,12 @@ def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
106109
def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
107110
FeatureRVCHints]>;
108111

112+
def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
113+
114+
def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
115+
FeatureRVCHints]>;
116+
117+
109118
//===----------------------------------------------------------------------===//
110119
// Define the RISC-V target.
111120
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
103103

104104
// Pseudo instructions
105105
class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
106-
: RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
106+
: RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo>,
107+
Sched<[]> {
107108
let isPseudo = 1;
108109
let isCodeGenOnly = 1;
109110
}

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 61 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
298298
class BranchCC_rri<bits<3> funct3, string opcodestr>
299299
: RVInstB<funct3, OPC_BRANCH, (outs),
300300
(ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
301-
opcodestr, "$rs1, $rs2, $imm12"> {
301+
opcodestr, "$rs1, $rs2, $imm12">,
302+
Sched<[WriteJmp]> {
302303
let isBranch = 1;
303304
let isTerminator = 1;
304305
}
@@ -320,13 +321,15 @@ class Store_rri<bits<3> funct3, string opcodestr>
320321
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
321322
class ALU_ri<bits<3> funct3, string opcodestr>
322323
: RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
323-
opcodestr, "$rd, $rs1, $imm12">;
324+
opcodestr, "$rd, $rs1, $imm12">,
325+
Sched<[WriteIALU, ReadIALU]>;
324326

325327
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
326328
class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr>
327329
: RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
328330
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
329-
"$rd, $rs1, $shamt">;
331+
"$rd, $rs1, $shamt">,
332+
Sched<[WriteShift, ReadShift]>;
330333

331334
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
332335
class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
@@ -336,19 +339,20 @@ class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
336339
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
337340
class CSR_ir<bits<3> funct3, string opcodestr>
338341
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
339-
opcodestr, "$rd, $imm12, $rs1">;
342+
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
340343

341344
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
342345
class CSR_ii<bits<3> funct3, string opcodestr>
343346
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
344347
(ins csr_sysreg:$imm12, uimm5:$rs1),
345-
opcodestr, "$rd, $imm12, $rs1">;
348+
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>;
346349

347350
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
348351
class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr>
349352
: RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
350353
(ins GPR:$rs1, uimm5:$shamt), opcodestr,
351-
"$rd, $rs1, $shamt">;
354+
"$rd, $rs1, $shamt">,
355+
Sched<[WriteShift32, ReadShift32]>;
352356

353357
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
354358
class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
@@ -367,19 +371,20 @@ class Priv<string opcodestr, bits<7> funct7>
367371
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
368372
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
369373
def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
370-
"lui", "$rd, $imm20">;
374+
"lui", "$rd, $imm20">, Sched<[WriteIALU]>;
371375

372376
def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
373-
"auipc", "$rd, $imm20">;
377+
"auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
374378

375379
let isCall = 1 in
376380
def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
377-
"jal", "$rd, $imm20">;
381+
"jal", "$rd, $imm20">, Sched<[WriteJal]>;
378382

379383
let isCall = 1 in
380384
def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
381385
(ins GPR:$rs1, simm12:$imm12),
382-
"jalr", "$rd, ${imm12}(${rs1})">;
386+
"jalr", "$rd, ${imm12}(${rs1})">,
387+
Sched<[WriteJalr, ReadJalr]>;
383388
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
384389

385390
def BEQ : BranchCC_rri<0b000, "beq">;
@@ -389,15 +394,15 @@ def BGE : BranchCC_rri<0b101, "bge">;
389394
def BLTU : BranchCC_rri<0b110, "bltu">;
390395
def BGEU : BranchCC_rri<0b111, "bgeu">;
391396

392-
def LB : Load_ri<0b000, "lb">;
393-
def LH : Load_ri<0b001, "lh">;
394-
def LW : Load_ri<0b010, "lw">;
395-
def LBU : Load_ri<0b100, "lbu">;
396-
def LHU : Load_ri<0b101, "lhu">;
397+
def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
398+
def LH : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
399+
def LW : Load_ri<0b010, "lw">, Sched<[WriteLDW, ReadMemBase]>;
400+
def LBU : Load_ri<0b100, "lbu">, Sched<[WriteLDB, ReadMemBase]>;
401+
def LHU : Load_ri<0b101, "lhu">, Sched<[WriteLDH, ReadMemBase]>;
397402

398-
def SB : Store_rri<0b000, "sb">;
399-
def SH : Store_rri<0b001, "sh">;
400-
def SW : Store_rri<0b010, "sw">;
403+
def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
404+
def SH : Store_rri<0b001, "sh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
405+
def SW : Store_rri<0b010, "sw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
401406

402407
// ADDI isn't always rematerializable, but isReMaterializable will be used as
403408
// a hint which is verified in isReallyTriviallyReMaterializable.
@@ -418,21 +423,21 @@ def SLLI : Shift_ri<0, 0b001, "slli">;
418423
def SRLI : Shift_ri<0, 0b101, "srli">;
419424
def SRAI : Shift_ri<1, 0b101, "srai">;
420425

421-
def ADD : ALU_rr<0b0000000, 0b000, "add">;
422-
def SUB : ALU_rr<0b0100000, 0b000, "sub">;
423-
def SLL : ALU_rr<0b0000000, 0b001, "sll">;
424-
def SLT : ALU_rr<0b0000000, 0b010, "slt">;
425-
def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
426-
def XOR : ALU_rr<0b0000000, 0b100, "xor">;
427-
def SRL : ALU_rr<0b0000000, 0b101, "srl">;
428-
def SRA : ALU_rr<0b0100000, 0b101, "sra">;
429-
def OR : ALU_rr<0b0000000, 0b110, "or">;
430-
def AND : ALU_rr<0b0000000, 0b111, "and">;
426+
def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
427+
def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
428+
def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
429+
def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
430+
def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
431+
def XOR : ALU_rr<0b0000000, 0b100, "xor">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
432+
def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
433+
def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
434+
def OR : ALU_rr<0b0000000, 0b110, "or">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
435+
def AND : ALU_rr<0b0000000, 0b111, "and">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
431436

432437
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
433438
def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
434439
(ins fencearg:$pred, fencearg:$succ),
435-
"fence", "$pred, $succ"> {
440+
"fence", "$pred, $succ">, Sched<[]> {
436441
bits<4> pred;
437442
bits<4> succ;
438443

@@ -441,25 +446,26 @@ def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
441446
let imm12 = {0b0000,pred,succ};
442447
}
443448

444-
def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", ""> {
449+
def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
445450
let rs1 = 0;
446451
let rd = 0;
447452
let imm12 = {0b1000,0b0011,0b0011};
448453
}
449454

450-
def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", ""> {
455+
def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
451456
let rs1 = 0;
452457
let rd = 0;
453458
let imm12 = 0;
454459
}
455460

456-
def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", ""> {
461+
def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[WriteJmp]> {
457462
let rs1 = 0;
458463
let rd = 0;
459464
let imm12 = 0;
460465
}
461466

462-
def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> {
467+
def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", "">,
468+
Sched<[]> {
463469
let rs1 = 0;
464470
let rd = 0;
465471
let imm12 = 1;
@@ -468,7 +474,8 @@ def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> {
468474
// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented
469475
// instruction (i.e., it should always trap, if your implementation has invalid
470476
// instruction traps).
471-
def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", ""> {
477+
def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">,
478+
Sched<[]> {
472479
let rs1 = 0;
473480
let rd = 0;
474481
let imm12 = 0b110000000000;
@@ -486,51 +493,57 @@ def CSRRCI : CSR_ii<0b111, "csrrci">;
486493
/// RV64I instructions
487494

488495
let Predicates = [IsRV64] in {
489-
def LWU : Load_ri<0b110, "lwu">;
490-
def LD : Load_ri<0b011, "ld">;
491-
def SD : Store_rri<0b011, "sd">;
496+
def LWU : Load_ri<0b110, "lwu">, Sched<[WriteLDWU, ReadMemBase]>;
497+
def LD : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>;
498+
def SD : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
492499

493500
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
494501
def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),
495502
(ins GPR:$rs1, simm12:$imm12),
496-
"addiw", "$rd, $rs1, $imm12">;
503+
"addiw", "$rd, $rs1, $imm12">,
504+
Sched<[WriteIALU32, ReadIALU32]>;
497505

498506
def SLLIW : ShiftW_ri<0, 0b001, "slliw">;
499507
def SRLIW : ShiftW_ri<0, 0b101, "srliw">;
500508
def SRAIW : ShiftW_ri<1, 0b101, "sraiw">;
501509

502-
def ADDW : ALUW_rr<0b0000000, 0b000, "addw">;
503-
def SUBW : ALUW_rr<0b0100000, 0b000, "subw">;
504-
def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">;
505-
def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">;
506-
def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">;
510+
def ADDW : ALUW_rr<0b0000000, 0b000, "addw">,
511+
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
512+
def SUBW : ALUW_rr<0b0100000, 0b000, "subw">,
513+
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
514+
def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">,
515+
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
516+
def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">,
517+
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
518+
def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
519+
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
507520
} // Predicates = [IsRV64]
508521

509522
//===----------------------------------------------------------------------===//
510523
// Privileged instructions
511524
//===----------------------------------------------------------------------===//
512525

513526
let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
514-
def URET : Priv<"uret", 0b0000000> {
527+
def URET : Priv<"uret", 0b0000000>, Sched<[]> {
515528
let rd = 0;
516529
let rs1 = 0;
517530
let rs2 = 0b00010;
518531
}
519532

520-
def SRET : Priv<"sret", 0b0001000> {
533+
def SRET : Priv<"sret", 0b0001000>, Sched<[]> {
521534
let rd = 0;
522535
let rs1 = 0;
523536
let rs2 = 0b00010;
524537
}
525538

526-
def MRET : Priv<"mret", 0b0011000> {
539+
def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
527540
let rd = 0;
528541
let rs1 = 0;
529542
let rs2 = 0b00010;
530543
}
531544
} // isBarrier = 1, isReturn = 1, isTerminator = 1
532545

533-
def WFI : Priv<"wfi", 0b0001000> {
546+
def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
534547
let rd = 0;
535548
let rs1 = 0;
536549
let rs2 = 0b00101;
@@ -539,7 +552,7 @@ def WFI : Priv<"wfi", 0b0001000> {
539552
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
540553
def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
541554
(ins GPR:$rs1, GPR:$rs2),
542-
"sfence.vma", "$rs1, $rs2"> {
555+
"sfence.vma", "$rs1, $rs2">, Sched<[]> {
543556
let rd = 0;
544557
}
545558

‎llvm/lib/Target/RISCV/RISCVInstrInfoA.td

Lines changed: 42 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -77,31 +77,51 @@ multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
7777
//===----------------------------------------------------------------------===//
7878

7979
let Predicates = [HasStdExtA] in {
80-
defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
81-
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
82-
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
83-
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
84-
defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
85-
defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
86-
defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
87-
defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
88-
defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
89-
defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
90-
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
80+
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
81+
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
82+
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
83+
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
84+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
85+
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
86+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
87+
defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">,
88+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
89+
defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">,
90+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
91+
defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
92+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
93+
defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">,
94+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
95+
defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">,
96+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
97+
defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
98+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
99+
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
100+
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
91101
} // Predicates = [HasStdExtA]
92102

93103
let Predicates = [HasStdExtA, IsRV64] in {
94-
defm LR_D : LR_r_aq_rl<0b011, "lr.d">;
95-
defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
96-
defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
97-
defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
98-
defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
99-
defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
100-
defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
101-
defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
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defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
104+
defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
105+
defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">,
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Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
107+
defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
109+
defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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} // Predicates = [HasStdExtA, IsRV64]
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//===----------------------------------------------------------------------===//

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