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arsenmarsenm
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AMDGPU/GlobalISel: Fix RegBanKSelect for llvm.amdgcn.exp.compr
This wasn't updated for the immarg handling change. We really need a verifier for this.
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-47
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2 files changed

+8
-47
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3310,16 +3310,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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break;
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}
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case Intrinsic::amdgcn_exp_compr:
3313-
OpdsMapping[0] = nullptr; // IntrinsicID
3314-
// FIXME: These are immediate values which can't be read from registers.
3315-
OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
3316-
OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
3317-
// FIXME: Could we support packed types here?
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OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
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OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
3320-
// FIXME: These are immediate values which can't be read from registers.
3321-
OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
3322-
OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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break;
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case Intrinsic::amdgcn_exp:
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// FIXME: Could we support packed types here?

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir

Lines changed: 8 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -2,21 +2,6 @@
22
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
44

5-
--- |
6-
define void @exp_compr_v2f16_s() {
7-
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0)
8-
ret void
9-
}
10-
define void @exp_compr_v2f16_v() {
11-
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0)
12-
ret void
13-
}
14-
15-
declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1)
16-
declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1)
17-
18-
...
19-
205
---
216
name: exp_compr_v2f16_s
227
legalized: true
@@ -25,22 +10,14 @@ body: |
2510
bb.0:
2611
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
2712
; CHECK-LABEL: name: exp_compr_v2f16_s
28-
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
29-
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
3013
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
3114
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
32-
; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
33-
; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
3415
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
3516
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
36-
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1)
37-
%0:_(s32) = G_CONSTANT i32 0
38-
%1:_(s32) = G_CONSTANT i32 0
39-
%2:_(s32) = COPY $sgpr0
40-
%3:_(s32) = COPY $sgpr1
41-
%6:_(s1) = G_CONSTANT i1 0
42-
%7:_(s1) = G_CONSTANT i1 0
43-
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
17+
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), 0, 0, [[COPY2]](s32), [[COPY3]](s32), 0, 0
18+
%0:_(s32) = COPY $sgpr0
19+
%1:_(s32) = COPY $sgpr1
20+
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), 0, 0, %0, %1, 0, 0
4421
...
4522
---
4623
name: exp_compr_v2f16_v
@@ -50,18 +27,10 @@ body: |
5027
bb.0:
5128
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
5229
; CHECK-LABEL: name: exp_compr_v2f16_v
53-
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
54-
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
5530
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
5631
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
57-
; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
58-
; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
59-
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[C2]](s1), [[C3]](s1)
60-
%0:_(s32) = G_CONSTANT i32 0
61-
%1:_(s32) = G_CONSTANT i32 0
62-
%2:_(s32) = COPY $vgpr0
63-
%3:_(s32) = COPY $vgpr1
64-
%6:_(s1) = G_CONSTANT i1 0
65-
%7:_(s1) = G_CONSTANT i1 0
66-
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
32+
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), 0, 0, [[COPY]](s32), [[COPY1]](s32), 0, 0
33+
%0:_(s32) = COPY $vgpr0
34+
%1:_(s32) = COPY $vgpr1
35+
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), 0, 0, %0, %1, 0, 0
6736
...

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