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Krzysztof Parzyszek
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[Hexagon] Add a target feature to disable compound instructions
This affects the following instructions: Tag: M4_mpyrr_addr Syntax: Ry32 = add(Ru32,mpyi(Ry32,Rs32)) Tag: M4_mpyri_addr_u2 Syntax: Rd32 = add(Ru32,mpyi(#u6:2,Rs32)) Tag: M4_mpyri_addr Syntax: Rd32 = add(Ru32,mpyi(Rs32,#u6)) Tag: M4_mpyri_addi Syntax: Rd32 = add(#u6,mpyi(Rs32,#U6)) Tag: M4_mpyrr_addi Syntax: Rd32 = add(#u6,mpyi(Rs32,Rt32)) Tag: S4_addaddi Syntax: Rd32 = add(Rs32,add(Ru32,#s6)) Tag: S4_subaddi Syntax: Rd32 = add(Rs32,sub(#s6,Ru32)) Tag: S4_or_andix Syntax: Rx32 = or(Ru32,and(Rx32,#s10)) Tag: S4_andi_asl_ri Syntax: Rx32 = and(#u8,asl(Rx32,#U5)) Tag: S4_ori_asl_ri Syntax: Rx32 = or(#u8,asl(Rx32,#U5)) Tag: S4_addi_asl_ri Syntax: Rx32 = add(#u8,asl(Rx32,#U5)) Tag: S4_subi_asl_ri Syntax: Rx32 = sub(#u8,asl(Rx32,#U5)) Tag: S4_andi_lsr_ri Syntax: Rx32 = and(#u8,lsr(Rx32,#U5)) Tag: S4_ori_lsr_ri Syntax: Rx32 = or(#u8,lsr(Rx32,#U5)) Tag: S4_addi_lsr_ri Syntax: Rx32 = add(#u8,lsr(Rx32,#U5)) Tag: S4_subi_lsr_ri Syntax: Rx32 = sub(#u8,lsr(Rx32,#U5))
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-68
lines changed

8 files changed

+125
-68
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‎llvm/lib/Target/Hexagon/Hexagon.td

Lines changed: 17 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
4848
def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
4949
"true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
5050

51+
def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",
52+
"Use compound instructions">;
5153
def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
5254
"Support for instruction packets">;
5355
def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
@@ -91,6 +93,7 @@ def UseHVXV66 : Predicate<"HST->useHVXOps()">,
9193
AssemblerPredicate<"ExtensionHVXV66">;
9294
def UseZReg : Predicate<"HST->useZRegOps()">,
9395
AssemblerPredicate<"ExtensionZReg">;
96+
def UseCompound : Predicate<"HST->useCompound()">;
9497

9598
def Hvx64: HwMode<"+hvx-length64b">;
9699
def Hvx128: HwMode<"+hvx-length128b">;
@@ -335,32 +338,32 @@ class Proc<string Name, SchedMachineModel Model,
335338

336339
def : Proc<"generic", HexagonModelV60,
337340
[ArchV5, ArchV55, ArchV60,
338-
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
339-
FeaturePackets, FeatureSmallData]>;
341+
FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
342+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
340343
def : Proc<"hexagonv5", HexagonModelV5,
341344
[ArchV5,
342-
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
343-
FeaturePackets, FeatureSmallData]>;
345+
FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
346+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
344347
def : Proc<"hexagonv55", HexagonModelV55,
345348
[ArchV5, ArchV55,
346-
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
347-
FeaturePackets, FeatureSmallData]>;
349+
FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
350+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
348351
def : Proc<"hexagonv60", HexagonModelV60,
349352
[ArchV5, ArchV55, ArchV60,
350-
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
351-
FeaturePackets, FeatureSmallData]>;
353+
FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
354+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
352355
def : Proc<"hexagonv62", HexagonModelV62,
353356
[ArchV5, ArchV55, ArchV60, ArchV62,
354-
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
355-
FeaturePackets, FeatureSmallData]>;
357+
FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
358+
FeatureNVS, FeaturePackets, FeatureSmallData]>;
356359
def : Proc<"hexagonv65", HexagonModelV65,
357360
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
358-
FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
359-
FeatureNVS, FeaturePackets, FeatureSmallData]>;
361+
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
362+
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
360363
def : Proc<"hexagonv66", HexagonModelV66,
361364
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
362-
FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
363-
FeatureNVS, FeaturePackets, FeatureSmallData]>;
365+
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
366+
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
364367

365368
//===----------------------------------------------------------------------===//
366369
// Declare the target which we are implementing

‎llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -379,6 +379,7 @@ namespace {
379379
using AssignmentMap = std::map<ExtenderInit, IndexList>;
380380
using LocDefList = std::vector<std::pair<Loc, IndexList>>;
381381

382+
const HexagonSubtarget *HST = nullptr;
382383
const HexagonInstrInfo *HII = nullptr;
383384
const HexagonRegisterInfo *HRI = nullptr;
384385
MachineDominatorTree *MDT = nullptr;
@@ -1562,13 +1563,31 @@ HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) {
15621563
.add(ExtOp);
15631564
}
15641565
} else {
1565-
unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
1566-
: Hexagon::S4_addi_asl_ri;
1567-
// DefR = add(##EV,asl(Rb,S))
1568-
InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
1569-
.add(ExtOp)
1570-
.add(MachineOperand(Ex.Rs))
1571-
.addImm(Ex.S);
1566+
if (HST->useCompound()) {
1567+
unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
1568+
: Hexagon::S4_addi_asl_ri;
1569+
// DefR = add(##EV,asl(Rb,S))
1570+
InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
1571+
.add(ExtOp)
1572+
.add(MachineOperand(Ex.Rs))
1573+
.addImm(Ex.S);
1574+
} else {
1575+
// No compounds are available. It is not clear whether we should
1576+
// even process such extenders where the initializer cannot be
1577+
// a single instruction, but do it for now.
1578+
unsigned TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1579+
BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR)
1580+
.add(MachineOperand(Ex.Rs))
1581+
.addImm(Ex.S);
1582+
if (Ex.Neg)
1583+
InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1584+
.add(ExtOp)
1585+
.add(MachineOperand(Register(TmpR, 0)));
1586+
else
1587+
InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1588+
.add(MachineOperand(Register(TmpR, 0)))
1589+
.add(ExtOp);
1590+
}
15721591
}
15731592
}
15741593

@@ -1952,8 +1971,9 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) {
19521971
}
19531972
LLVM_DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr));
19541973

1955-
HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
1956-
HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1974+
HST = &MF.getSubtarget<HexagonSubtarget>();
1975+
HII = HST->getInstrInfo();
1976+
HRI = HST->getRegisterInfo();
19571977
MDT = &getAnalysis<MachineDominatorTree>();
19581978
MRI = &MF.getRegInfo();
19591979
AssignmentMap IMap;

‎llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -17106,7 +17106,7 @@ def M4_mpyri_addi : HInst<
1710617106
(outs IntRegs:$Rd32),
1710717107
(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
1710817108
"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17109-
tc_05d3a09b, TypeALU64>, Enc_322e1b, ImmRegRel {
17109+
tc_05d3a09b, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
1711017110
let Inst{31-24} = 0b11011000;
1711117111
let hasNewValue = 1;
1711217112
let opNewValue = 0;
@@ -17122,7 +17122,7 @@ def M4_mpyri_addr : HInst<
1712217122
(outs IntRegs:$Rd32),
1712317123
(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
1712417124
"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17125-
tc_05d3a09b, TypeALU64>, Enc_420cf3, ImmRegRel {
17125+
tc_05d3a09b, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
1712617126
let Inst{31-23} = 0b110111111;
1712717127
let hasNewValue = 1;
1712817128
let opNewValue = 0;
@@ -17139,7 +17139,7 @@ def M4_mpyri_addr_u2 : HInst<
1713917139
(outs IntRegs:$Rd32),
1714017140
(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
1714117141
"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17142-
tc_1a2fd869, TypeALU64>, Enc_277737 {
17142+
tc_1a2fd869, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
1714317143
let Inst{31-23} = 0b110111110;
1714417144
let hasNewValue = 1;
1714517145
let opNewValue = 0;
@@ -17149,7 +17149,7 @@ def M4_mpyrr_addi : HInst<
1714917149
(outs IntRegs:$Rd32),
1715017150
(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
1715117151
"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17152-
tc_d773585a, TypeALU64>, Enc_a7b8e8, ImmRegRel {
17152+
tc_d773585a, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
1715317153
let Inst{31-23} = 0b110101110;
1715417154
let hasNewValue = 1;
1715517155
let opNewValue = 0;
@@ -17166,7 +17166,7 @@ def M4_mpyrr_addr : HInst<
1716617166
(outs IntRegs:$Ry32),
1716717167
(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
1716817168
"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17169-
tc_d773585a, TypeM>, Enc_7f1a05, ImmRegRel {
17169+
tc_d773585a, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
1717017170
let Inst{7-5} = 0b000;
1717117171
let Inst{13-13} = 0b0;
1717217172
let Inst{31-21} = 0b11100011000;
@@ -22001,7 +22001,7 @@ def S4_addaddi : HInst<
2200122001
(outs IntRegs:$Rd32),
2200222002
(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
2200322003
"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22004-
tc_f675fee8, TypeALU64>, Enc_8b8d61 {
22004+
tc_f675fee8, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
2200522005
let Inst{31-23} = 0b110110110;
2200622006
let hasNewValue = 1;
2200722007
let opNewValue = 0;
@@ -22016,7 +22016,7 @@ def S4_addi_asl_ri : HInst<
2201622016
(outs IntRegs:$Rx32),
2201722017
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2201822018
"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22019-
tc_f675fee8, TypeALU64>, Enc_c31910 {
22019+
tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2202022020
let Inst{2-0} = 0b100;
2202122021
let Inst{4-4} = 0b0;
2202222022
let Inst{31-24} = 0b11011110;
@@ -22034,7 +22034,7 @@ def S4_addi_lsr_ri : HInst<
2203422034
(outs IntRegs:$Rx32),
2203522035
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2203622036
"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22037-
tc_f675fee8, TypeALU64>, Enc_c31910 {
22037+
tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2203822038
let Inst{2-0} = 0b100;
2203922039
let Inst{4-4} = 0b1;
2204022040
let Inst{31-24} = 0b11011110;
@@ -22052,7 +22052,7 @@ def S4_andi_asl_ri : HInst<
2205222052
(outs IntRegs:$Rx32),
2205322053
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2205422054
"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22055-
tc_f429765c, TypeALU64>, Enc_c31910 {
22055+
tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2205622056
let Inst{2-0} = 0b000;
2205722057
let Inst{4-4} = 0b0;
2205822058
let Inst{31-24} = 0b11011110;
@@ -22070,7 +22070,7 @@ def S4_andi_lsr_ri : HInst<
2207022070
(outs IntRegs:$Rx32),
2207122071
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2207222072
"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22073-
tc_f429765c, TypeALU64>, Enc_c31910 {
22073+
tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2207422074
let Inst{2-0} = 0b000;
2207522075
let Inst{4-4} = 0b1;
2207622076
let Inst{31-24} = 0b11011110;
@@ -22208,7 +22208,7 @@ def S4_or_andix : HInst<
2220822208
(outs IntRegs:$Rx32),
2220922209
(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
2221022210
"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22211-
tc_f429765c, TypeALU64>, Enc_b4e6cf {
22211+
tc_f429765c, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
2221222212
let Inst{31-22} = 0b1101101001;
2221322213
let hasNewValue = 1;
2221422214
let opNewValue = 0;
@@ -22241,7 +22241,7 @@ def S4_ori_asl_ri : HInst<
2224122241
(outs IntRegs:$Rx32),
2224222242
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2224322243
"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22244-
tc_f429765c, TypeALU64>, Enc_c31910 {
22244+
tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2224522245
let Inst{2-0} = 0b010;
2224622246
let Inst{4-4} = 0b0;
2224722247
let Inst{31-24} = 0b11011110;
@@ -22259,7 +22259,7 @@ def S4_ori_lsr_ri : HInst<
2225922259
(outs IntRegs:$Rx32),
2226022260
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2226122261
"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22262-
tc_f429765c, TypeALU64>, Enc_c31910 {
22262+
tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2226322263
let Inst{2-0} = 0b010;
2226422264
let Inst{4-4} = 0b1;
2226522265
let Inst{31-24} = 0b11011110;
@@ -25106,7 +25106,7 @@ def S4_subaddi : HInst<
2510625106
(outs IntRegs:$Rd32),
2510725107
(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
2510825108
"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25109-
tc_f675fee8, TypeALU64>, Enc_8b8d61 {
25109+
tc_f675fee8, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
2511025110
let Inst{31-23} = 0b110110111;
2511125111
let hasNewValue = 1;
2511225112
let opNewValue = 0;
@@ -25121,7 +25121,7 @@ def S4_subi_asl_ri : HInst<
2512125121
(outs IntRegs:$Rx32),
2512225122
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2512325123
"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25124-
tc_f675fee8, TypeALU64>, Enc_c31910 {
25124+
tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2512525125
let Inst{2-0} = 0b110;
2512625126
let Inst{4-4} = 0b0;
2512725127
let Inst{31-24} = 0b11011110;
@@ -25139,7 +25139,7 @@ def S4_subi_lsr_ri : HInst<
2513925139
(outs IntRegs:$Rx32),
2514025140
(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
2514125141
"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25142-
tc_f675fee8, TypeALU64>, Enc_c31910 {
25142+
tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
2514325143
let Inst{2-0} = 0b110;
2514425144
let Inst{4-4} = 0b1;
2514525145
let Inst{31-24} = 0b11011110;

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