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AMDGPU/GlobalISel: Add pre-legalize combiner pass
Just copy the AArch64 pass as-is for now, except for removing the memcpy handling.
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10 files changed

+263
-118
lines changed

10 files changed

+263
-118
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.h

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@@ -27,6 +27,10 @@ class TargetOptions;
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class PassRegistry;
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class Module;
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// GlobalISel passes
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void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
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// R600 Passes
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FunctionPass *createR600VectorRegMerger();
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FunctionPass *createR600ExpandSpecialInstrsPass();

‎llvm/lib/Target/AMDGPU/AMDGPUCombine.td

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@@ -0,0 +1,15 @@
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//=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
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"AMDGPUGenPreLegalizerCombinerHelper", [all_combines,
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elide_br_by_inverting_cond]> {
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let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
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}

‎llvm/lib/Target/AMDGPU/AMDGPUGISel.td

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@@ -11,6 +11,7 @@
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//===----------------------------------------------------------------------===//
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include "AMDGPU.td"
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include "AMDGPUCombine.td"
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def sd_vsrc0 : ComplexPattern<i32, 1, "">;
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def gi_vsrc0 :

‎llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

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//=== lib/CodeGen/GlobalISel/AMDGPUPreLegalizerCombiner.cpp ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "amdgpu-prelegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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#define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AMDGPUGenGICombiner.inc"
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#undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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namespace {
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#define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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#include "AMDGPUGenGICombiner.inc"
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#undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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class AMDGPUPreLegalizerCombinerInfo : public CombinerInfo {
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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public:
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AMDGPUGenPreLegalizerCombinerHelper Generated;
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AMDGPUPreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
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GISelKnownBits *KB, MachineDominatorTree *MDT)
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
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KB(KB), MDT(MDT) {
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if (!Generated.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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bool AMDGPUPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
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MachineInstr &MI,
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MachineIRBuilder &B) const {
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CombinerHelper Helper(Observer, B, KB, MDT);
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if (Generated.tryCombineAll(Observer, MI, B, Helper))
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return true;
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switch (MI.getOpcode()) {
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case TargetOpcode::G_CONCAT_VECTORS:
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return Helper.tryCombineConcatVectors(MI);
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case TargetOpcode::G_SHUFFLE_VECTOR:
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return Helper.tryCombineShuffleVector(MI);
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}
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return false;
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}
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#define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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#include "AMDGPUGenGICombiner.inc"
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#undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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// Pass boilerplate
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// ================
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class AMDGPUPreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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AMDGPUPreLegalizerCombiner(bool IsOptNone = false);
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StringRef getPassName() const override { return "AMDGPUPreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool IsOptNone;
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};
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} // end anonymous namespace
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void AMDGPUPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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if (!IsOptNone) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
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: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
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initializeAMDGPUPreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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const Function &F = MF.getFunction();
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bool EnableOpt =
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MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
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GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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MachineDominatorTree *MDT =
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IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
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AMDGPUPreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
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F.hasMinSize(), KB, MDT);
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Combiner C(PCInfo, TPC);
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return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
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}
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char AMDGPUPreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(AMDGPUPreLegalizerCombiner, DEBUG_TYPE,
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"Combine AMDGPU machine instrs before legalization",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_END(AMDGPUPreLegalizerCombiner, DEBUG_TYPE,
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"Combine AMDGPU machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone) {
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return new AMDGPUPreLegalizerCombiner(IsOptNone);
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}
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} // end namespace llvm

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

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@@ -217,6 +217,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
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initializeAMDGPULowerKernelAttributesPass(*PR);
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initializeAMDGPULowerIntrinsicsPass(*PR);
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initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
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initializeAMDGPUPreLegalizerCombinerPass(*PR);
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initializeAMDGPUPromoteAllocaPass(*PR);
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initializeAMDGPUCodeGenPreparePass(*PR);
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initializeAMDGPUPropagateAttributesEarlyPass(*PR);
@@ -617,6 +618,7 @@ class GCNPassConfig final : public AMDGPUPassConfig {
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bool addILPOpts() override;
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bool addInstSelector() override;
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bool addIRTranslator() override;
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void addPreLegalizeMachineIR() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
@@ -895,6 +897,11 @@ bool GCNPassConfig::addIRTranslator() {
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return false;
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}
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void GCNPassConfig::addPreLegalizeMachineIR() {
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bool IsOptNone = getOptLevel() == CodeGenOpt::None;
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addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
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}
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bool GCNPassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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return false;

‎llvm/lib/Target/AMDGPU/CMakeLists.txt

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@@ -15,6 +15,8 @@ tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
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tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
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tablegen(LLVM AMDGPUGenGICombiner.inc -gen-global-isel-combiner
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-combiners="AMDGPUPreLegalizerCombinerHelper")
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set(LLVM_TARGET_DEFINITIONS R600.td)
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tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
@@ -58,6 +60,7 @@ add_llvm_target(AMDGPUCodeGen
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AMDGPUMacroFusion.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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AMDGPUPreLegalizerCombiner.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPUPropagateAttributes.cpp
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AMDGPURegisterBankInfo.cpp

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