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Add intrinsics for unary narrowing operations
Summary: The following intrinsics for unary narrowing operations are added: * @llvm.aarch64.sve.sqxtnb * @llvm.aarch64.sve.uqxtnb * @llvm.aarch64.sve.sqxtunb * @llvm.aarch64.sve.sqxtnt * @llvm.aarch64.sve.uqxtnt * @llvm.aarch64.sve.sqxtunt Reviewers: sdesmalen, rengolin, efriedma Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71270
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4 files changed

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‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -974,6 +974,17 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
974974
llvm_i32_ty],
975975
[IntrNoMem]>;
976976

977+
class SVE2_1VectorArg_Narrowing_Intrinsic
978+
: Intrinsic<[LLVMSubdivide2VectorType<0>],
979+
[llvm_anyvector_ty],
980+
[IntrNoMem]>;
981+
982+
class SVE2_Merged1VectorArg_Narrowing_Intrinsic
983+
: Intrinsic<[LLVMSubdivide2VectorType<0>],
984+
[LLVMSubdivide2VectorType<0>,
985+
llvm_anyvector_ty],
986+
[IntrNoMem]>;
987+
977988
// NOTE: There is no relationship between these intrinsics beyond an attempt
978989
// to reuse currently identical class definitions.
979990
class AdvSIMD_SVE_LOGB_Intrinsic : AdvSIMD_SVE_CNT_Intrinsic;
@@ -1383,4 +1394,15 @@ def int_aarch64_sve_fmlslt_lane : SVE2_3VectorArgIndexed_Long_Intrinsic;
13831394
//
13841395

13851396
def int_aarch64_sve_flogb : AdvSIMD_SVE_LOGB_Intrinsic;
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1398+
//
1399+
// SVE2 - Unary narrowing operations
1400+
//
1401+
1402+
def int_aarch64_sve_sqxtnb : SVE2_1VectorArg_Narrowing_Intrinsic;
1403+
def int_aarch64_sve_sqxtnt : SVE2_Merged1VectorArg_Narrowing_Intrinsic;
1404+
def int_aarch64_sve_sqxtunb : SVE2_1VectorArg_Narrowing_Intrinsic;
1405+
def int_aarch64_sve_sqxtunt : SVE2_Merged1VectorArg_Narrowing_Intrinsic;
1406+
def int_aarch64_sve_uqxtnb : SVE2_1VectorArg_Narrowing_Intrinsic;
1407+
def int_aarch64_sve_uqxtnt : SVE2_Merged1VectorArg_Narrowing_Intrinsic;
13861408
}

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1427,14 +1427,14 @@ let Predicates = [HasSVE2] in {
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defm RSUBHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b11, "rsubhnt">;
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14291429
// SVE2 saturating extract narrow (bottom)
1430-
defm SQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b00, "sqxtnb">;
1431-
defm UQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b01, "uqxtnb">;
1432-
defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b10, "sqxtunb">;
1430+
defm SQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b00, "sqxtnb", int_aarch64_sve_sqxtnb>;
1431+
defm UQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b01, "uqxtnb", int_aarch64_sve_uqxtnb>;
1432+
defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b10, "sqxtunb", int_aarch64_sve_sqxtunb>;
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14341434
// SVE2 saturating extract narrow (top)
1435-
defm SQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b00, "sqxtnt">;
1436-
defm UQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b01, "uqxtnt">;
1437-
defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow_top<0b10, "sqxtunt">;
1435+
defm SQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b00, "sqxtnt", int_aarch64_sve_sqxtnt>;
1436+
defm UQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b01, "uqxtnt", int_aarch64_sve_uqxtnt>;
1437+
defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow_top<0b10, "sqxtunt", int_aarch64_sve_sqxtunt>;
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14391439
// SVE2 character match
14401440
defm MATCH_PPzZZ : sve2_char_match<0b0, "match">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3034,10 +3034,15 @@ class sve2_int_sat_extract_narrow_bottom<bits<3> tsz8_64, bits<2> opc, string as
30343034
let Inst{4-0} = Zd;
30353035
}
30363036

3037-
multiclass sve2_int_sat_extract_narrow_bottom<bits<2> opc, string asm> {
3037+
multiclass sve2_int_sat_extract_narrow_bottom<bits<2> opc, string asm,
3038+
SDPatternOperator op> {
30383039
def _B : sve2_int_sat_extract_narrow_bottom<0b001, opc, asm, ZPR8, ZPR16>;
30393040
def _H : sve2_int_sat_extract_narrow_bottom<0b010, opc, asm, ZPR16, ZPR32>;
30403041
def _S : sve2_int_sat_extract_narrow_bottom<0b100, opc, asm, ZPR32, ZPR64>;
3042+
3043+
def : SVE_1_Op_Pat<nxv16i8, op, nxv8i16, !cast<Instruction>(NAME # _B)>;
3044+
def : SVE_1_Op_Pat<nxv8i16, op, nxv4i32, !cast<Instruction>(NAME # _H)>;
3045+
def : SVE_1_Op_Pat<nxv4i32, op, nxv2i64, !cast<Instruction>(NAME # _S)>;
30413046
}
30423047

30433048
class sve2_int_sat_extract_narrow_top<bits<3> tsz8_64, bits<2> opc, string asm,
@@ -3059,10 +3064,15 @@ class sve2_int_sat_extract_narrow_top<bits<3> tsz8_64, bits<2> opc, string asm,
30593064
let Constraints = "$Zd = $_Zd";
30603065
}
30613066

3062-
multiclass sve2_int_sat_extract_narrow_top<bits<2> opc, string asm> {
3067+
multiclass sve2_int_sat_extract_narrow_top<bits<2> opc, string asm,
3068+
SDPatternOperator op> {
30633069
def _B : sve2_int_sat_extract_narrow_top<0b001, opc, asm, ZPR8, ZPR16>;
30643070
def _H : sve2_int_sat_extract_narrow_top<0b010, opc, asm, ZPR16, ZPR32>;
30653071
def _S : sve2_int_sat_extract_narrow_top<0b100, opc, asm, ZPR32, ZPR64>;
3072+
3073+
def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv8i16, !cast<Instruction>(NAME # _B)>;
3074+
def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv4i32, !cast<Instruction>(NAME # _H)>;
3075+
def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
30663076
}
30673077

30683078
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll

Lines changed: 202 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,202 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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3+
;
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; SQXTNB
5+
;
6+
7+
define <vscale x 16 x i8> @sqxtnb_h(<vscale x 8 x i16> %a) {
8+
; CHECK-LABEL: sqxtnb_h:
9+
; CHECK: sqxtnb z0.b, z0.h
10+
; CHECK-NEXT: ret
11+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16> %a)
12+
ret <vscale x 16 x i8> %out
13+
}
14+
15+
define <vscale x 8 x i16> @sqxtnb_s(<vscale x 4 x i32> %a) {
16+
; CHECK-LABEL: sqxtnb_s:
17+
; CHECK: sqxtnb z0.h, z0.s
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; CHECK-NEXT: ret
19+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32> %a)
20+
ret <vscale x 8 x i16> %out
21+
}
22+
23+
define <vscale x 4 x i32> @sqxtnb_d(<vscale x 2 x i64> %a) {
24+
; CHECK-LABEL: sqxtnb_d:
25+
; CHECK: sqxtnb z0.s, z0.d
26+
; CHECK-NEXT: ret
27+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64> %a)
28+
ret <vscale x 4 x i32> %out
29+
}
30+
31+
;
32+
; UQXTNB
33+
;
34+
35+
define <vscale x 16 x i8> @uqxtnb_h(<vscale x 8 x i16> %a) {
36+
; CHECK-LABEL: uqxtnb_h:
37+
; CHECK: uqxtnb z0.b, z0.h
38+
; CHECK-NEXT: ret
39+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16> %a)
40+
ret <vscale x 16 x i8> %out
41+
}
42+
43+
define <vscale x 8 x i16> @uqxtnb_s(<vscale x 4 x i32> %a) {
44+
; CHECK-LABEL: uqxtnb_s:
45+
; CHECK: uqxtnb z0.h, z0.s
46+
; CHECK-NEXT: ret
47+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32> %a)
48+
ret <vscale x 8 x i16> %out
49+
}
50+
51+
define <vscale x 4 x i32> @uqxtnb_d(<vscale x 2 x i64> %a) {
52+
; CHECK-LABEL: uqxtnb_d:
53+
; CHECK: uqxtnb z0.s, z0.d
54+
; CHECK-NEXT: ret
55+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64> %a)
56+
ret <vscale x 4 x i32> %out
57+
}
58+
59+
;
60+
; SQXTUNB
61+
;
62+
63+
define <vscale x 16 x i8> @sqxtunb_h(<vscale x 8 x i16> %a) {
64+
; CHECK-LABEL: sqxtunb_h:
65+
; CHECK: sqxtunb z0.b, z0.h
66+
; CHECK-NEXT: ret
67+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16> %a)
68+
ret <vscale x 16 x i8> %out
69+
}
70+
71+
define <vscale x 8 x i16> @sqxtunb_s(<vscale x 4 x i32> %a) {
72+
; CHECK-LABEL: sqxtunb_s:
73+
; CHECK: sqxtunb z0.h, z0.s
74+
; CHECK-NEXT: ret
75+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32> %a)
76+
ret <vscale x 8 x i16> %out
77+
}
78+
79+
define <vscale x 4 x i32> @sqxtunb_d(<vscale x 2 x i64> %a) {
80+
; CHECK-LABEL: sqxtunb_d:
81+
; CHECK: sqxtunb z0.s, z0.d
82+
; CHECK-NEXT: ret
83+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64> %a)
84+
ret <vscale x 4 x i32> %out
85+
}
86+
87+
;
88+
; SQXTNT
89+
;
90+
91+
define <vscale x 16 x i8> @sqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
92+
; CHECK-LABEL: sqxtnt_h:
93+
; CHECK: sqxtnt z0.b, z1.h
94+
; CHECK-NEXT: ret
95+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8> %a,
96+
<vscale x 8 x i16> %b)
97+
ret <vscale x 16 x i8> %out
98+
}
99+
100+
define <vscale x 8 x i16> @sqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
101+
; CHECK-LABEL: sqxtnt_s:
102+
; CHECK: sqxtnt z0.h, z1.s
103+
; CHECK-NEXT: ret
104+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16> %a,
105+
<vscale x 4 x i32> %b)
106+
ret <vscale x 8 x i16> %out
107+
}
108+
109+
define <vscale x 4 x i32> @sqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
110+
; CHECK-LABEL: sqxtnt_d:
111+
; CHECK: sqxtnt z0.s, z1.d
112+
; CHECK-NEXT: ret
113+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32> %a,
114+
<vscale x 2 x i64> %b)
115+
ret <vscale x 4 x i32> %out
116+
}
117+
118+
;
119+
; UQXTNT
120+
;
121+
122+
define <vscale x 16 x i8> @uqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
123+
; CHECK-LABEL: uqxtnt_h:
124+
; CHECK: uqxtnt z0.b, z1.h
125+
; CHECK-NEXT: ret
126+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8> %a,
127+
<vscale x 8 x i16> %b)
128+
ret <vscale x 16 x i8> %out
129+
}
130+
131+
define <vscale x 8 x i16> @uqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
132+
; CHECK-LABEL: uqxtnt_s:
133+
; CHECK: uqxtnt z0.h, z1.s
134+
; CHECK-NEXT: ret
135+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16> %a,
136+
<vscale x 4 x i32> %b)
137+
ret <vscale x 8 x i16> %out
138+
}
139+
140+
define <vscale x 4 x i32> @uqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
141+
; CHECK-LABEL: uqxtnt_d:
142+
; CHECK: uqxtnt z0.s, z1.d
143+
; CHECK-NEXT: ret
144+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32> %a,
145+
<vscale x 2 x i64> %b)
146+
ret <vscale x 4 x i32> %out
147+
}
148+
149+
;
150+
; SQXTUNT
151+
;
152+
153+
define <vscale x 16 x i8> @sqxtunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
154+
; CHECK-LABEL: sqxtunt_h:
155+
; CHECK: sqxtunt z0.b, z1.h
156+
; CHECK-NEXT: ret
157+
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8> %a,
158+
<vscale x 8 x i16> %b)
159+
ret <vscale x 16 x i8> %out
160+
}
161+
162+
define <vscale x 8 x i16> @sqxtunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
163+
; CHECK-LABEL: sqxtunt_s:
164+
; CHECK: sqxtunt z0.h, z1.s
165+
; CHECK-NEXT: ret
166+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16> %a,
167+
<vscale x 4 x i32> %b)
168+
ret <vscale x 8 x i16> %out
169+
}
170+
171+
define <vscale x 4 x i32> @sqxtunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
172+
; CHECK-LABEL: sqxtunt_d:
173+
; CHECK: sqxtunt z0.s, z1.d
174+
; CHECK-NEXT: ret
175+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32> %a,
176+
<vscale x 2 x i64> %b)
177+
ret <vscale x 4 x i32> %out
178+
}
179+
180+
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16>)
181+
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32>)
182+
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64>)
183+
184+
declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16>)
185+
declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32>)
186+
declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64>)
187+
188+
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16>)
189+
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32>)
190+
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64>)
191+
192+
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
193+
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
194+
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
195+
196+
declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
197+
declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
198+
declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
199+
200+
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
201+
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
202+
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)

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