[AMDGPU] override isHighLatencyDef

rampitec · rampitec · commit c2ad7ee1a9ad · 2020-01-29T08:01:29.000-08:00
SIMachineScheduler uses isHighLatencyInstruction with the same sematincs, but TargetInstrInfo has virtual isHighLatencyDef method, so override it instead. Added FLAT to the list of high latency opcodes and a check for mayLoad since stores are not technically high latency in terms of data dependency. This change did not produce any visible impact on our tests. Differential Revision: https://reviews.llvm.org/D73582
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6005,10 +6005,9 @@ bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {
   return isSMRD(Opc);
 }
 
-bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {
-  unsigned Opc = MI.getOpcode();
-
-  return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc);
+bool SIInstrInfo::isHighLatencyDef(int Opc) const {
+  return get(Opc).mayLoad() &&
+         (isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc) || isFLAT(Opc));
 }
 
 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -931,7 +931,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
   uint64_t getScratchRsrcWords23() const;
 
   bool isLowLatencyInstruction(const MachineInstr &MI) const;
-  bool isHighLatencyInstruction(const MachineInstr &MI) const;
+  bool isHighLatencyDef(int Opc) const override;
 
   /// Return the descriptor of the target-specific machine instruction
   /// that corresponds to the specified pseudo or native opcode.
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -1955,7 +1955,7 @@ void SIScheduleDAGMI::schedule()
       if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
                                          TRI))
         LowLatencyOffset[i] = OffLatReg;
-    } else if (SITII->isHighLatencyInstruction(*SU->getInstr()))
+    } else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))
       IsHighLatencySU[i] = 1;
   }
 

Original file line number	Diff line number	Diff line change
`@@ -6005,10 +6005,9 @@ bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {`
`6005`	`6005`	`return isSMRD(Opc);`
`6006`	`6006`	`}`
`6007`	`6007`
`6008`		`-bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {`
`6009`		`- unsigned Opc = MI.getOpcode();`
`6010`		`-`
`6011`		`- return isMUBUF(Opc) \|\| isMTBUF(Opc) \|\| isMIMG(Opc);`
	`6008`	`+bool SIInstrInfo::isHighLatencyDef(int Opc) const {`
	`6009`	`+ return get(Opc).mayLoad() &&`
	`6010`	`+ (isMUBUF(Opc) \|\| isMTBUF(Opc) \|\| isMIMG(Opc) \|\| isFLAT(Opc));`
`6012`	`6011`	`}`
`6013`	`6012`
`6014`	`6013`	`unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,`
Original file line number	Diff line number	Diff line change
`@@ -1955,7 +1955,7 @@ void SIScheduleDAGMI::schedule()`
`1955`	`1955`	`if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,`
`1956`	`1956`	`TRI))`
`1957`	`1957`	`LowLatencyOffset[i] = OffLatReg;`
`1958`		`- } else if (SITII->isHighLatencyInstruction(*SU->getInstr()))`
	`1958`	`+ } else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))`
`1959`	`1959`	`IsHighLatencySU[i] = 1;`
`1960`	`1960`	`}`
`1961`	`1961`