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AMDGPU/GlobalISel: Select buffer atomics
The cmpswap handling is incomplete and fails to select.
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8 files changed

+717
-21
lines changed

8 files changed

+717
-21
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUGISel.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,6 +153,20 @@ def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>;
153153
def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>;
154154
def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>;
155155

156+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>;
157+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>;
158+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>;
159+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>;
160+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>;
161+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>;
162+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>;
163+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>;
164+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>;
165+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
166+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
167+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
168+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
169+
156170

157171
class GISelSop2Pat <
158172
SDPatternOperator node,

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2654,6 +2654,114 @@ bool AMDGPULegalizerInfo::legalizeAtomicIncDec(MachineInstr &MI,
26542654
return true;
26552655
}
26562656

2657+
static unsigned getBufferAtomicPseudo(Intrinsic::ID IntrID) {
2658+
switch (IntrID) {
2659+
case Intrinsic::amdgcn_raw_buffer_atomic_swap:
2660+
case Intrinsic::amdgcn_struct_buffer_atomic_swap:
2661+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP;
2662+
case Intrinsic::amdgcn_raw_buffer_atomic_add:
2663+
case Intrinsic::amdgcn_struct_buffer_atomic_add:
2664+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD;
2665+
case Intrinsic::amdgcn_raw_buffer_atomic_sub:
2666+
case Intrinsic::amdgcn_struct_buffer_atomic_sub:
2667+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB;
2668+
case Intrinsic::amdgcn_raw_buffer_atomic_smin:
2669+
case Intrinsic::amdgcn_struct_buffer_atomic_smin:
2670+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN;
2671+
case Intrinsic::amdgcn_raw_buffer_atomic_umin:
2672+
case Intrinsic::amdgcn_struct_buffer_atomic_umin:
2673+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN;
2674+
case Intrinsic::amdgcn_raw_buffer_atomic_smax:
2675+
case Intrinsic::amdgcn_struct_buffer_atomic_smax:
2676+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX;
2677+
case Intrinsic::amdgcn_raw_buffer_atomic_umax:
2678+
case Intrinsic::amdgcn_struct_buffer_atomic_umax:
2679+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX;
2680+
case Intrinsic::amdgcn_raw_buffer_atomic_and:
2681+
case Intrinsic::amdgcn_struct_buffer_atomic_and:
2682+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND;
2683+
case Intrinsic::amdgcn_raw_buffer_atomic_or:
2684+
case Intrinsic::amdgcn_struct_buffer_atomic_or:
2685+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR;
2686+
case Intrinsic::amdgcn_raw_buffer_atomic_xor:
2687+
case Intrinsic::amdgcn_struct_buffer_atomic_xor:
2688+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR;
2689+
case Intrinsic::amdgcn_raw_buffer_atomic_inc:
2690+
case Intrinsic::amdgcn_struct_buffer_atomic_inc:
2691+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC;
2692+
case Intrinsic::amdgcn_raw_buffer_atomic_dec:
2693+
case Intrinsic::amdgcn_struct_buffer_atomic_dec:
2694+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC;
2695+
default:
2696+
llvm_unreachable("unhandled atomic opcode");
2697+
}
2698+
}
2699+
2700+
bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI,
2701+
MachineIRBuilder &B,
2702+
Intrinsic::ID IID) const {
2703+
B.setInstr(MI);
2704+
2705+
const bool IsCmpSwap = IID == Intrinsic::amdgcn_raw_buffer_atomic_cmpswap ||
2706+
IID == Intrinsic::amdgcn_struct_buffer_atomic_cmpswap;
2707+
2708+
Register Dst = MI.getOperand(0).getReg();
2709+
Register VData = MI.getOperand(2).getReg();
2710+
2711+
Register CmpVal;
2712+
int OpOffset = 0;
2713+
2714+
if (IsCmpSwap) {
2715+
CmpVal = MI.getOperand(3 + OpOffset).getReg();
2716+
++OpOffset;
2717+
}
2718+
2719+
Register RSrc = MI.getOperand(3 + OpOffset).getReg();
2720+
const unsigned NumVIndexOps = IsCmpSwap ? 9 : 8;
2721+
2722+
// The struct intrinsic variants add one additional operand over raw.
2723+
const bool HasVIndex = MI.getNumOperands() == NumVIndexOps;
2724+
Register VIndex;
2725+
if (HasVIndex) {
2726+
VIndex = MI.getOperand(4).getReg();
2727+
++OpOffset;
2728+
}
2729+
2730+
Register VOffset = MI.getOperand(4 + OpOffset).getReg();
2731+
Register SOffset = MI.getOperand(5 + OpOffset).getReg();
2732+
unsigned AuxiliaryData = MI.getOperand(6 + OpOffset).getImm();
2733+
2734+
MachineMemOperand *MMO = *MI.memoperands_begin();
2735+
2736+
unsigned ImmOffset;
2737+
unsigned TotalOffset;
2738+
std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset);
2739+
if (TotalOffset != 0)
2740+
MMO = B.getMF().getMachineMemOperand(MMO, TotalOffset, MMO->getSize());
2741+
2742+
if (!VIndex)
2743+
VIndex = B.buildConstant(LLT::scalar(32), 0).getReg(0);
2744+
2745+
auto MIB = B.buildInstr(getBufferAtomicPseudo(IID))
2746+
.addDef(Dst)
2747+
.addUse(VData); // vdata
2748+
2749+
if (IsCmpSwap)
2750+
MIB.addReg(CmpVal);
2751+
2752+
MIB.addUse(RSrc) // rsrc
2753+
.addUse(VIndex) // vindex
2754+
.addUse(VOffset) // voffset
2755+
.addUse(SOffset) // soffset
2756+
.addImm(ImmOffset) // offset(imm)
2757+
.addImm(AuxiliaryData) // cachepolicy, swizzled buffer(imm)
2758+
.addImm(HasVIndex ? -1 : 0) // idxen(imm)
2759+
.addMemOperand(MMO);
2760+
2761+
MI.eraseFromParent();
2762+
return true;
2763+
}
2764+
26572765
// FIMXE: Needs observer like custom
26582766
bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
26592767
MachineRegisterInfo &MRI,
@@ -2787,6 +2895,33 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
27872895
case Intrinsic::amdgcn_raw_tbuffer_load:
27882896
case Intrinsic::amdgcn_struct_tbuffer_load:
27892897
return legalizeBufferLoad(MI, MRI, B, true, true);
2898+
case Intrinsic::amdgcn_raw_buffer_atomic_swap:
2899+
case Intrinsic::amdgcn_struct_buffer_atomic_swap:
2900+
case Intrinsic::amdgcn_raw_buffer_atomic_add:
2901+
case Intrinsic::amdgcn_struct_buffer_atomic_add:
2902+
case Intrinsic::amdgcn_raw_buffer_atomic_sub:
2903+
case Intrinsic::amdgcn_struct_buffer_atomic_sub:
2904+
case Intrinsic::amdgcn_raw_buffer_atomic_smin:
2905+
case Intrinsic::amdgcn_struct_buffer_atomic_smin:
2906+
case Intrinsic::amdgcn_raw_buffer_atomic_umin:
2907+
case Intrinsic::amdgcn_struct_buffer_atomic_umin:
2908+
case Intrinsic::amdgcn_raw_buffer_atomic_smax:
2909+
case Intrinsic::amdgcn_struct_buffer_atomic_smax:
2910+
case Intrinsic::amdgcn_raw_buffer_atomic_umax:
2911+
case Intrinsic::amdgcn_struct_buffer_atomic_umax:
2912+
case Intrinsic::amdgcn_raw_buffer_atomic_and:
2913+
case Intrinsic::amdgcn_struct_buffer_atomic_and:
2914+
case Intrinsic::amdgcn_raw_buffer_atomic_or:
2915+
case Intrinsic::amdgcn_struct_buffer_atomic_or:
2916+
case Intrinsic::amdgcn_raw_buffer_atomic_xor:
2917+
case Intrinsic::amdgcn_struct_buffer_atomic_xor:
2918+
case Intrinsic::amdgcn_raw_buffer_atomic_inc:
2919+
case Intrinsic::amdgcn_struct_buffer_atomic_inc:
2920+
case Intrinsic::amdgcn_raw_buffer_atomic_dec:
2921+
case Intrinsic::amdgcn_struct_buffer_atomic_dec:
2922+
case Intrinsic::amdgcn_raw_buffer_atomic_cmpswap:
2923+
case Intrinsic::amdgcn_struct_buffer_atomic_cmpswap:
2924+
return legalizeBufferAtomic(MI, B, IntrID);
27902925
case Intrinsic::amdgcn_atomic_inc:
27912926
return legalizeAtomicIncDec(MI, B, true);
27922927
case Intrinsic::amdgcn_atomic_dec:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,8 @@ class AMDGPULegalizerInfo : public LegalizerInfo {
123123
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
124124
MachineIRBuilder &B, bool IsTyped,
125125
bool IsFormat) const;
126+
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
127+
Intrinsic::ID IID) const;
126128

127129
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B,
128130
bool IsInc) const;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2263,6 +2263,27 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
22632263
executeInWaterfallLoop(MI, MRI, {1, 4});
22642264
return;
22652265
}
2266+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP:
2267+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD:
2268+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB:
2269+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN:
2270+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN:
2271+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX:
2272+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX:
2273+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND:
2274+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR:
2275+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR:
2276+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC:
2277+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: {
2278+
applyDefaultMapping(OpdMapper);
2279+
executeInWaterfallLoop(MI, MRI, {2, 5});
2280+
return;
2281+
}
2282+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP: {
2283+
applyDefaultMapping(OpdMapper);
2284+
executeInWaterfallLoop(MI, MRI, {3, 6});
2285+
return;
2286+
}
22662287
case AMDGPU::G_INTRINSIC: {
22672288
switch (MI.getIntrinsicID()) {
22682289
case Intrinsic::amdgcn_s_buffer_load: {
@@ -3095,6 +3116,40 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
30953116
// initialized.
30963117
break;
30973118
}
3119+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP:
3120+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD:
3121+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB:
3122+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN:
3123+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN:
3124+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX:
3125+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX:
3126+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND:
3127+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR:
3128+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR:
3129+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC:
3130+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: {
3131+
// vdata_out
3132+
OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
3133+
3134+
// vdata_in
3135+
OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
3136+
3137+
// rsrc
3138+
OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
3139+
3140+
// vindex
3141+
OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
3142+
3143+
// voffset
3144+
OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
3145+
3146+
// soffset
3147+
OpdsMapping[5] = getSGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);
3148+
3149+
// Any remaining operands are immediates and were correctly null
3150+
// initialized.
3151+
break;
3152+
}
30983153
case AMDGPU::G_INTRINSIC: {
30993154
switch (MI.getIntrinsicID()) {
31003155
default:

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,37 +1342,37 @@ defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_short, i32, "BUFFER_STORE_SHORT">;
13421342
multiclass BufferAtomicPatterns<SDPatternOperator name, ValueType vt,
13431343
string opcode> {
13441344
def : GCNPat<
1345-
(vt (name vt:$vdata_in, v4i32:$rsrc, 0,
1346-
0, i32:$soffset, timm:$offset,
1347-
timm:$cachepolicy, 0)),
1348-
(!cast<MUBUF_Pseudo>(opcode # _OFFSET_RTN) $vdata_in, $rsrc, $soffset,
1349-
(as_i16imm $offset), (extract_slc $cachepolicy))
1345+
(vt (name vt:$vdata_in, v4i32:$rsrc, 0, 0, i32:$soffset,
1346+
timm:$offset, timm:$cachepolicy, 0)),
1347+
(!cast<MUBUF_Pseudo>(opcode # _OFFSET_RTN)
1348+
getVregSrcForVT<vt>.ret:$vdata_in, SReg_128:$rsrc, SCSrc_b32:$soffset,
1349+
(as_i16timm $offset), (extract_slc $cachepolicy))
13501350
>;
13511351

13521352
def : GCNPat<
1353-
(vt (name vt:$vdata_in, v4i32:$rsrc, i32:$vindex,
1354-
0, i32:$soffset, timm:$offset,
1355-
timm:$cachepolicy, timm)),
1356-
(!cast<MUBUF_Pseudo>(opcode # _IDXEN_RTN) $vdata_in, $vindex, $rsrc, $soffset,
1357-
(as_i16imm $offset), (extract_slc $cachepolicy))
1353+
(vt (name vt:$vdata_in, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset,
1354+
timm:$offset, timm:$cachepolicy, timm)),
1355+
(!cast<MUBUF_Pseudo>(opcode # _IDXEN_RTN) getVregSrcForVT<vt>.ret:$vdata_in,
1356+
VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset,
1357+
(as_i16timm $offset), (extract_slc $cachepolicy))
13581358
>;
13591359

13601360
def : GCNPat<
1361-
(vt (name vt:$vdata_in, v4i32:$rsrc, 0,
1362-
i32:$voffset, i32:$soffset, timm:$offset,
1363-
timm:$cachepolicy, 0)),
1364-
(!cast<MUBUF_Pseudo>(opcode # _OFFEN_RTN) $vdata_in, $voffset, $rsrc, $soffset,
1365-
(as_i16imm $offset), (extract_slc $cachepolicy))
1361+
(vt (name vt:$vdata_in, v4i32:$rsrc, 0, i32:$voffset,
1362+
i32:$soffset, timm:$offset, timm:$cachepolicy, 0)),
1363+
(!cast<MUBUF_Pseudo>(opcode # _OFFEN_RTN) getVregSrcForVT<vt>.ret:$vdata_in,
1364+
VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset,
1365+
(as_i16timm $offset), (extract_slc $cachepolicy))
13661366
>;
13671367

13681368
def : GCNPat<
1369-
(vt (name vt:$vdata_in, v4i32:$rsrc, i32:$vindex,
1370-
i32:$voffset, i32:$soffset, timm:$offset,
1371-
timm:$cachepolicy, timm)),
1369+
(vt (name vt:$vdata_in, v4i32:$rsrc, i32:$vindex, i32:$voffset,
1370+
i32:$soffset, timm:$offset, timm:$cachepolicy, timm)),
13721371
(!cast<MUBUF_Pseudo>(opcode # _BOTHEN_RTN)
1373-
$vdata_in,
1374-
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1375-
$rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy))
1372+
getVregSrcForVT<vt>.ret:$vdata_in,
1373+
(REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1374+
SReg_128:$rsrc, SCSrc_b32:$soffset, (as_i16timm $offset),
1375+
(extract_slc $cachepolicy))
13761376
>;
13771377
}
13781378

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2216,3 +2216,36 @@ let Namespace = "AMDGPU" in {
22162216
def G_AMDGPU_ATOMIC_INC : G_ATOMICRMW_OP;
22172217
def G_AMDGPU_ATOMIC_DEC : G_ATOMICRMW_OP;
22182218
}
2219+
2220+
class BufferAtomicGenericInstruction : AMDGPUGenericInstruction {
2221+
let OutOperandList = (outs type0:$dst);
2222+
let InOperandList = (ins type0:$vdata, type1:$rsrc, type2:$vindex, type2:$voffset,
2223+
type2:$soffset, untyped_imm_0:$offset,
2224+
untyped_imm_0:$cachepolicy, untyped_imm_0:$idxen);
2225+
let hasSideEffects = 0;
2226+
let mayLoad = 1;
2227+
let mayStore = 1;
2228+
}
2229+
2230+
def G_AMDGPU_BUFFER_ATOMIC_SWAP : BufferAtomicGenericInstruction;
2231+
def G_AMDGPU_BUFFER_ATOMIC_ADD : BufferAtomicGenericInstruction;
2232+
def G_AMDGPU_BUFFER_ATOMIC_SUB : BufferAtomicGenericInstruction;
2233+
def G_AMDGPU_BUFFER_ATOMIC_SMIN : BufferAtomicGenericInstruction;
2234+
def G_AMDGPU_BUFFER_ATOMIC_UMIN : BufferAtomicGenericInstruction;
2235+
def G_AMDGPU_BUFFER_ATOMIC_SMAX : BufferAtomicGenericInstruction;
2236+
def G_AMDGPU_BUFFER_ATOMIC_UMAX : BufferAtomicGenericInstruction;
2237+
def G_AMDGPU_BUFFER_ATOMIC_AND : BufferAtomicGenericInstruction;
2238+
def G_AMDGPU_BUFFER_ATOMIC_OR : BufferAtomicGenericInstruction;
2239+
def G_AMDGPU_BUFFER_ATOMIC_XOR : BufferAtomicGenericInstruction;
2240+
def G_AMDGPU_BUFFER_ATOMIC_INC : BufferAtomicGenericInstruction;
2241+
def G_AMDGPU_BUFFER_ATOMIC_DEC : BufferAtomicGenericInstruction;
2242+
2243+
def G_AMDGPU_BUFFER_ATOMIC_CMPSWAP : AMDGPUGenericInstruction {
2244+
let OutOperandList = (outs type0:$dst);
2245+
let InOperandList = (ins type0:$vdata, type0:$cmp, type1:$rsrc, type2:$vindex,
2246+
type2:$voffset, type2:$soffset, untyped_imm_0:$offset,
2247+
untyped_imm_0:$cachepolicy, untyped_imm_0:$idxen);
2248+
let hasSideEffects = 0;
2249+
let mayLoad = 1;
2250+
let mayStore = 1;
2251+
}

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