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Get my dirty fingers out of the SDK.
This commit should return the SDK files (i2c_struct.h,i2c_reg.h) back to
factory defaults. The required typedef's were duplicated in
esp32-hal-i2c.h instead.
With this Commit, the only changes are in Wire.h, Wire.cpp,
esp32-hal-i2c.h, esp32-hal-i2c.c
Copy file name to clipboardExpand all lines: cores/esp32/esp32-hal-i2c.h
+52-10
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@@ -11,6 +11,7 @@
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// modified Nov 2017 by Chuck Todd <StickBreaker> to support Interrupt Driven I/O
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#ifndef_ESP32_HAL_I2C_H_
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#define_ESP32_HAL_I2C_H_
@@ -25,7 +26,41 @@ extern "C" {
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#include"freertos/FreeRTOS.h"
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#include"freertos/event_groups.h"
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-
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// start from tools/sdk/include/soc/soc/i2c_struct.h
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typedefunion {
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struct {
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uint32_tbyte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
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uint32_tack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_tack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_tack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_top_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
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uint32_treserved14: 17;
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uint32_tdone: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
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};
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uint32_tval;
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} I2C_COMMAND_t;
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typedefunion {
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struct {
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uint32_trx_fifo_full_thrhd: 5;
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uint32_ttx_fifo_empty_thrhd:5; //Config tx_fifo empty threhd value when using apb fifo access * /
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uint32_tnonfifo_en: 1; //Set this bit to enble apb nonfifo access. * /
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uint32_tfifo_addr_cfg_en: 1; //When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. * /
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uint32_trx_fifo_rst: 1; //Set this bit to reset rx fifo when using apb fifo access. * /
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// chuck while this bit is 1, the RX fifo is held in REST, Toggle it * /
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uint32_ttx_fifo_rst: 1; //Set this bit to reset tx fifo when using apb fifo access. * /
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// chuck while this bit is 1, the TX fifo is held in REST, Toggle it * /
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uint32_tnonfifo_rx_thres: 6; //when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.* /
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uint32_tnonfifo_tx_thres: 6; //when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. * /
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uint32_treserved26: 6;
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};
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uint32_tval;
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} I2C_FIFO_CONF_t;
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// end from tools/sdk/include/soc/soc/i2c_struct.h
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// External Wire.h equivalent error Codes
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typedefenum {
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I2C_ERROR_OK=0,
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I2C_ERROR_DEV,
@@ -38,6 +73,7 @@ typedef enum {
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I2C_ERROR_NO_BEGIN
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} i2c_err_t;
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// sync between dispatch(i2cProcQueue) and worker(i2c_isr_handler_default)
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typedefenum {
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//I2C_NONE=0,
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I2C_STARTUP=1,
@@ -52,7 +88,7 @@ typedef enum {
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I2C_MASTERSLAVE
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}I2C_MODE_t;
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-
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// internal Error condition
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typedefenum {
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// I2C_NONE=0,
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I2C_OK=1,
@@ -63,22 +99,26 @@ typedef enum {
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I2C_TIMEOUT
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}I2C_ERROR_t;
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// i2c_event bits
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// i2c_event bits for EVENTGROUP bits
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// needed to minimize change events, FreeRTOS Daemon overload, so ISR will only set values
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// on Exit. Dispatcher will set bits for each dq before/after ISR completion
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#defineEVENT_ERROR_NAK (BIT(0))
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#defineEVENT_ERROR (BIT(1))
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//#define EVENT_RUNNING (BIT(3))
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#defineEVENT_RUNNING (BIT(3))
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#defineEVENT_DONE (BIT(4))
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#defineEVENT_IN_END (BIT(5))
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#defineEVENT_ERROR_PREV (BIT(6))
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#defineEVENT_ERROR_TIMEOUT (BIT(7))
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#defineEVENT_ERROR_ARBITRATION (BIT(8))
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#defineEVENT_ERROR_DATA_NAK (BIT(9))
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#defineEVENT_MASK 0x3F
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// control record for each dq entry
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typedefunion{
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struct {
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uint32_taddr: 16; // I2C address, if 10bit must have 0x7800 mask applied, else 8bit
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uint32_tmode: 1; // 0 write, 1 read
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uint32_tstop: 1; // 0 no, 1 yes
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uint32_tmode: 1; // transaction direction 0 write, 1 read
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uint32_tstop: 1; // sendStop 0 no, 1 yes
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uint32_tstartCmdSent: 1; // START cmd has been added to command[]
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uint32_taddrCmdSent: 1; // addr WRITE cmd has been added to command[]
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uint32_tdataCmdSent: 1; // all necessary DATA(READ/WRITE) cmds added to command[]
@@ -89,15 +129,17 @@ typedef union{
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};
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uint32_tval;
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}I2C_DATA_CTRL_t;
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// individual dq element
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typedefstruct {
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uint8_t*data; // datapointer for read/write buffer
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uint16_tlength; // size of data buffer
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uint16_tposition; // current position for next char in buffer (<length)
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uint16_tcmdBytesNeeded; // number of data bytes needing (READ/WRITE)Command[]
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uint16_tqueueLength;
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uint16_tcmdBytesNeeded; // used to control number of I2C_COMMAND_t blocks added to queu
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uint16_tqueueLength; // number of data bytes needing moved, used to control
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// current queuePos for fifo fills
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I2C_DATA_CTRL_tctrl;
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EventGroupHandle_tqueueEvent;
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EventGroupHandle_tqueueEvent;// optional user supplied for Async feedback EventBits
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