International journal of next-generation computing, Apr 27, 2021
The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified ... more The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified information of Military and Banking services. This has led to intensifying the research on various attacks on AES algorithm either to test the security of the algorithm itself or to obtain the secret information i.e. the key. The AES algorithm is constantly subjected to various cryptanalytic attacks since its release in 2001. However, most of these attacks are theoretical and have been incapable of breaking the AES algorithm completely. These attacks are performed on the reduced rounds of the AES algorithm are compared with the brute force attack for time and data complexity. The brute force attack tries all possible values of keys and is the most effective technique of cryptanalytic technique. This research paper presents an extensive survey on various existing cryptanalytic attacks on the AES Algorithm.
Advances in intelligent systems and computing, Oct 17, 2019
Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic... more Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic attacks against AES algorithm target reduced-round variants. These attacks are theoretical and are generally considered infeasible due to the demand for a large number of computations. To meet this high-computational requirement, an FPGA-based High-Performance Computing (HPC) platform is presented in this paper. FPGAs are advantageous for implementing cryptanalytic attacks, as the modular arithmetic is implemented more efficiently in FPGAs as compared to GPUs. The proposed HPC platform consists of four Spartan6 FPGAs connected in a mesh topology. A brute force cryptanalytic attack on the AES algorithm with a 128-bit key is implemented on the proposed HPC platform. Four-AES key search engines are designed in each FPGA. Thus, 16-AES key search engines are instantiated in parallel to perform AES cryptanalysis using different keys in parallel. To allocate distinct the key space to the 16 AES key search engines, an efficient key generator is also proposed in this work. The proposed architecture achieves a computational complexity of 2124 for an attack against 10-rounds AES algorithm.
International journal of engineering trends and technology, Jan 25, 2016
In an age of technological advancements, security and privacy plays an important role in day to d... more In an age of technological advancements, security and privacy plays an important role in day to day communication. Cryptanalysis of modern cryptography algorithm involves massive and parallel computations. In absence of the mathematical breakthroughs to a cryptanalytical problem, a promising way to tackle these computations is to build special purpose hardware which will provide better costperformance ratio. In this paper, the cryptanalysis of AES algorithm using brute force attack is used as a proof of concept. The basic concept is to create multiple instances of the design which can be instantiated simultaneously so that the solution space is exposed at a faster rate. For implementation of AES, Spartan-6 (XC6LX9) device is used. FPGA implementation of the AES requiring 1918 slices on a Xilinx Spartan3 (XC3S50) device, while achieving throughput of 1114.624 Mbps. Time required for cryptanalysis of AES is reduced from seconds to miliseconds as 3 multiple instances of design are instantiated parallel. The low-cost implementation and moderate throughput makes it practically suitable for low resource security applications.[1] Keywords— AES, FPGA, VHDL, Cryptanalysis, Brute-Force Attack, Cipher Key.
The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified ... more The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified information of Military and Banking services. This has led to intensifying the research on various attacks on AES algorithm either to test the security of the algorithm itself or to obtain the secret information i.e. the key. The AES algorithm is constantly subjected to various cryptanalytic attacks since its release in 2001. However, most of these attacks are theoretical and have been incapable of breaking the AES algorithm completely. These attacks are performed on the reduced rounds of the AES algorithm are compared with the brute force attack for time and data complexity. The brute force attack tries all possible values of keys and is the most effective technique of cryptanalytic technique. This research paper presents an extensive survey on various existing cryptanalytic attacks on the AES Algorithm.
international journal of engineering trends and technology, 2016
In an age of technological advancements, security and privacy plays an important role in day to d... more In an age of technological advancements, security and privacy plays an important role in day to day communication. Cryptanalysis of modern cryptography algorithm involves massive and parallel computations. In absence of the mathematical breakthroughs to a cryptanalytical problem, a promising way to tackle these computations is to build special purpose hardware which will provide better costperformance ratio. In this paper, the cryptanalysis of AES algorithm using brute force attack is used as a proof of concept. The basic concept is to create multiple instances of the design which can be instantiated simultaneously so that the solution space is exposed at a faster rate. For implementation of AES, Spartan-6 (XC6LX9) device is used. FPGA implementation of the AES requiring 1918 slices on a Xilinx Spartan3 (XC3S50) device, while achieving throughput of 1114.624 Mbps. Time required for cryptanalysis of AES is reduced from seconds to miliseconds as 3 multiple instances of design are inst...
Advances in Intelligent Systems and Computing, 2019
Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic... more Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic attacks against AES algorithm target reduced-round variants. These attacks are theoretical and are generally considered infeasible due to the demand for a large number of computations. To meet this high-computational requirement, an FPGA-based High-Performance Computing (HPC) platform is presented in this paper. FPGAs are advantageous for implementing cryptanalytic attacks, as the modular arithmetic is implemented more efficiently in FPGAs as compared to GPUs. The proposed HPC platform consists of four Spartan6 FPGAs connected in a mesh topology. A brute force cryptanalytic attack on the AES algorithm with a 128-bit key is implemented on the proposed HPC platform. Four-AES key search engines are designed in each FPGA. Thus, 16-AES key search engines are instantiated in parallel to perform AES cryptanalysis using different keys in parallel. To allocate distinct the key space to the 16 AE...
International Journal of Innovative Technology and Exploring Engineering, 2019
Fuel injection system is an indispensible part of the present day automobiles. The depletion of t... more Fuel injection system is an indispensible part of the present day automobiles. The depletion of the fuels along with continuous surge in the fuel prices has made it imperative to use fuel economically and restricting the wastage to a minimum. Contrary to the carburetor, using predefined amount of fuel irrespective of the environment, Fuel Injection System uses just the required amount of fuel based on the operating conditions as sensed by the Engine Control Module (ECM). Numerous parameters are required to be sensed by the ECM to achieve optimum efficiency of the engine. To handle the processing of such large number of parameters, a robust architecture is required. This paper presents the design and implementation of ECM utilized in Electronic Fuel Injection (EFI) system on a Field Programmable Gate Array. The ECM architecture discussed in the proposed system is computationally efficient enough to fulfill ever-increasing functionalities of the ECM. The main objective of this researc...
Journal of King Saud University - Engineering Sciences, 2018
Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for s... more Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security features is proposed in this work. Abysmal analysis of the AES algorithm implies that the security of AES lies in the S-box operations. This paper presents a new approach for generating S-box values (modified S-box) and initial key required for encryption/encryption (improved key generation) using PN Sequence Generator. The AES algorithm with proposed modifications shows significant improvement in the encryption quality as compared to traditional AES algorithm. The traditional AES algorithm equipped with proposed novel modified S-box technique and improved key generation technique gives an avalanche effect of 60% making it invulnerable to attacks. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and compared to the existing designs resulting in significant improvement in throughput. The proposed design is implemented on Spartan6 FPGA device.
2016 International Conference on Inventive Computation Technologies (ICICT), 2016
Information Security is a major issue worldwide. Various steps are being taken to improve and upg... more Information Security is a major issue worldwide. Various steps are being taken to improve and upgrade security measures. Border crossings across countries have become one of them. Therefore the use of traditional passports has lead to an improvement in the name of E-passports. E-passports are a more secured and are denoted by a symbol. E-passports contain a small chip which stores the data of passport holder. To protect this data Cryptography is widely used. This paper shows the comparison of modular multiplication methods used for RSA algorithm for 1024 bit key length. Xilinx ISE 14.3 platform is used to perform this encryption and decryption process targeting Virtex-5 FPGA board.
2012 12th International Conference on Hybrid Intelligent Systems (HIS), 2012
With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose... more With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose hardware for computationally intensive applications has now become possible. Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. This paper presents the design for Hardware implementation of Data Encryption Standard (DES) cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Iterative and Loop unrolled DES architecture are implemented. The aim of this work is to make cryptanalysis faster and better.
International Journal on Cryptography and Information Security, 2013
Cryptanalysis of block ciphers involves massive computations which are independent of each other ... more Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.
2014 International Conference on Embedded Systems (ICES), 2014
In a country like India, patients are monitored in their recovery period, so the cost of hospital... more In a country like India, patients are monitored in their recovery period, so the cost of hospitalization is also increasing day by day. The physiological parameters like body temperature, heart beat rate are monitored during recovery period of patients. This is done using a “Smart Non-Invasive Wireless Physiological Monitoring System”, where patients are monitored remotely. Impact sensors are used, which detects the fall of patients, so that immediate help is provided to them. In this paper the temperature, heart beat rate and impact sensors are used to measure physiological parameters which are then analysed and transmitted to PC through ZIGBEE wirelessly. Using GUI, parameters are monitored on PC by medical professionals. The high fluctuations in the parameters will be reported to doctors as a critical condition through GSM.
International journal of next-generation computing, Apr 27, 2021
The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified ... more The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified information of Military and Banking services. This has led to intensifying the research on various attacks on AES algorithm either to test the security of the algorithm itself or to obtain the secret information i.e. the key. The AES algorithm is constantly subjected to various cryptanalytic attacks since its release in 2001. However, most of these attacks are theoretical and have been incapable of breaking the AES algorithm completely. These attacks are performed on the reduced rounds of the AES algorithm are compared with the brute force attack for time and data complexity. The brute force attack tries all possible values of keys and is the most effective technique of cryptanalytic technique. This research paper presents an extensive survey on various existing cryptanalytic attacks on the AES Algorithm.
Advances in intelligent systems and computing, Oct 17, 2019
Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic... more Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic attacks against AES algorithm target reduced-round variants. These attacks are theoretical and are generally considered infeasible due to the demand for a large number of computations. To meet this high-computational requirement, an FPGA-based High-Performance Computing (HPC) platform is presented in this paper. FPGAs are advantageous for implementing cryptanalytic attacks, as the modular arithmetic is implemented more efficiently in FPGAs as compared to GPUs. The proposed HPC platform consists of four Spartan6 FPGAs connected in a mesh topology. A brute force cryptanalytic attack on the AES algorithm with a 128-bit key is implemented on the proposed HPC platform. Four-AES key search engines are designed in each FPGA. Thus, 16-AES key search engines are instantiated in parallel to perform AES cryptanalysis using different keys in parallel. To allocate distinct the key space to the 16 AES key search engines, an efficient key generator is also proposed in this work. The proposed architecture achieves a computational complexity of 2124 for an attack against 10-rounds AES algorithm.
International journal of engineering trends and technology, Jan 25, 2016
In an age of technological advancements, security and privacy plays an important role in day to d... more In an age of technological advancements, security and privacy plays an important role in day to day communication. Cryptanalysis of modern cryptography algorithm involves massive and parallel computations. In absence of the mathematical breakthroughs to a cryptanalytical problem, a promising way to tackle these computations is to build special purpose hardware which will provide better costperformance ratio. In this paper, the cryptanalysis of AES algorithm using brute force attack is used as a proof of concept. The basic concept is to create multiple instances of the design which can be instantiated simultaneously so that the solution space is exposed at a faster rate. For implementation of AES, Spartan-6 (XC6LX9) device is used. FPGA implementation of the AES requiring 1918 slices on a Xilinx Spartan3 (XC3S50) device, while achieving throughput of 1114.624 Mbps. Time required for cryptanalysis of AES is reduced from seconds to miliseconds as 3 multiple instances of design are instantiated parallel. The low-cost implementation and moderate throughput makes it practically suitable for low resource security applications.[1] Keywords— AES, FPGA, VHDL, Cryptanalysis, Brute-Force Attack, Cipher Key.
The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified ... more The Advanced Encryption Standard (AES) Algorithm is popularly being used for securing classified information of Military and Banking services. This has led to intensifying the research on various attacks on AES algorithm either to test the security of the algorithm itself or to obtain the secret information i.e. the key. The AES algorithm is constantly subjected to various cryptanalytic attacks since its release in 2001. However, most of these attacks are theoretical and have been incapable of breaking the AES algorithm completely. These attacks are performed on the reduced rounds of the AES algorithm are compared with the brute force attack for time and data complexity. The brute force attack tries all possible values of keys and is the most effective technique of cryptanalytic technique. This research paper presents an extensive survey on various existing cryptanalytic attacks on the AES Algorithm.
international journal of engineering trends and technology, 2016
In an age of technological advancements, security and privacy plays an important role in day to d... more In an age of technological advancements, security and privacy plays an important role in day to day communication. Cryptanalysis of modern cryptography algorithm involves massive and parallel computations. In absence of the mathematical breakthroughs to a cryptanalytical problem, a promising way to tackle these computations is to build special purpose hardware which will provide better costperformance ratio. In this paper, the cryptanalysis of AES algorithm using brute force attack is used as a proof of concept. The basic concept is to create multiple instances of the design which can be instantiated simultaneously so that the solution space is exposed at a faster rate. For implementation of AES, Spartan-6 (XC6LX9) device is used. FPGA implementation of the AES requiring 1918 slices on a Xilinx Spartan3 (XC3S50) device, while achieving throughput of 1114.624 Mbps. Time required for cryptanalysis of AES is reduced from seconds to miliseconds as 3 multiple instances of design are inst...
Advances in Intelligent Systems and Computing, 2019
Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic... more Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic attacks against AES algorithm target reduced-round variants. These attacks are theoretical and are generally considered infeasible due to the demand for a large number of computations. To meet this high-computational requirement, an FPGA-based High-Performance Computing (HPC) platform is presented in this paper. FPGAs are advantageous for implementing cryptanalytic attacks, as the modular arithmetic is implemented more efficiently in FPGAs as compared to GPUs. The proposed HPC platform consists of four Spartan6 FPGAs connected in a mesh topology. A brute force cryptanalytic attack on the AES algorithm with a 128-bit key is implemented on the proposed HPC platform. Four-AES key search engines are designed in each FPGA. Thus, 16-AES key search engines are instantiated in parallel to perform AES cryptanalysis using different keys in parallel. To allocate distinct the key space to the 16 AE...
International Journal of Innovative Technology and Exploring Engineering, 2019
Fuel injection system is an indispensible part of the present day automobiles. The depletion of t... more Fuel injection system is an indispensible part of the present day automobiles. The depletion of the fuels along with continuous surge in the fuel prices has made it imperative to use fuel economically and restricting the wastage to a minimum. Contrary to the carburetor, using predefined amount of fuel irrespective of the environment, Fuel Injection System uses just the required amount of fuel based on the operating conditions as sensed by the Engine Control Module (ECM). Numerous parameters are required to be sensed by the ECM to achieve optimum efficiency of the engine. To handle the processing of such large number of parameters, a robust architecture is required. This paper presents the design and implementation of ECM utilized in Electronic Fuel Injection (EFI) system on a Field Programmable Gate Array. The ECM architecture discussed in the proposed system is computationally efficient enough to fulfill ever-increasing functionalities of the ECM. The main objective of this researc...
Journal of King Saud University - Engineering Sciences, 2018
Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for s... more Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security features is proposed in this work. Abysmal analysis of the AES algorithm implies that the security of AES lies in the S-box operations. This paper presents a new approach for generating S-box values (modified S-box) and initial key required for encryption/encryption (improved key generation) using PN Sequence Generator. The AES algorithm with proposed modifications shows significant improvement in the encryption quality as compared to traditional AES algorithm. The traditional AES algorithm equipped with proposed novel modified S-box technique and improved key generation technique gives an avalanche effect of 60% making it invulnerable to attacks. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and compared to the existing designs resulting in significant improvement in throughput. The proposed design is implemented on Spartan6 FPGA device.
2016 International Conference on Inventive Computation Technologies (ICICT), 2016
Information Security is a major issue worldwide. Various steps are being taken to improve and upg... more Information Security is a major issue worldwide. Various steps are being taken to improve and upgrade security measures. Border crossings across countries have become one of them. Therefore the use of traditional passports has lead to an improvement in the name of E-passports. E-passports are a more secured and are denoted by a symbol. E-passports contain a small chip which stores the data of passport holder. To protect this data Cryptography is widely used. This paper shows the comparison of modular multiplication methods used for RSA algorithm for 1024 bit key length. Xilinx ISE 14.3 platform is used to perform this encryption and decryption process targeting Virtex-5 FPGA board.
2012 12th International Conference on Hybrid Intelligent Systems (HIS), 2012
With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose... more With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose hardware for computationally intensive applications has now become possible. Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. This paper presents the design for Hardware implementation of Data Encryption Standard (DES) cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Iterative and Loop unrolled DES architecture are implemented. The aim of this work is to make cryptanalysis faster and better.
International Journal on Cryptography and Information Security, 2013
Cryptanalysis of block ciphers involves massive computations which are independent of each other ... more Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.
2014 International Conference on Embedded Systems (ICES), 2014
In a country like India, patients are monitored in their recovery period, so the cost of hospital... more In a country like India, patients are monitored in their recovery period, so the cost of hospitalization is also increasing day by day. The physiological parameters like body temperature, heart beat rate are monitored during recovery period of patients. This is done using a “Smart Non-Invasive Wireless Physiological Monitoring System”, where patients are monitored remotely. Impact sensors are used, which detects the fall of patients, so that immediate help is provided to them. In this paper the temperature, heart beat rate and impact sensors are used to measure physiological parameters which are then analysed and transmitted to PC through ZIGBEE wirelessly. Using GUI, parameters are monitored on PC by medical professionals. The high fluctuations in the parameters will be reported to doctors as a critical condition through GSM.
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