European Solid-State Circuits Conference, Sep 1, 1990
This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. W... more This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p, ROM based methods become unattractive for integration due to excessive memory requirements. Two new methods are discussed and compared to ROM implementations with regard to their speed/complexity behaviour. The first method is based on a (n + 1) x (n + 1) bit array multiplier, the second on carry-save addition, both of which allow very high throughputs in pipelined implementations. While the former is very convenient for CAD environments providing a pipelined multiplier macro cell generator, the latter is well-suited to full custom implementation.
CMOS circuits have been the workhorse of ICT for 40 years. Due to the unique scaling property of ... more CMOS circuits have been the workhorse of ICT for 40 years. Due to the unique scaling property of this technology, energy efficiency has enormously improved during that time, notably by lowering the supply voltage from the long-time standard of 5 to 1 V and less. As the era of “happy scaling” has come to an end, progress becomes increasingly difficult and techniques beyond 2D size reductions have come into play. A superior and viable alternative to CMOS has yet to be found.
European Solid-State Circuits Conference, Sep 1, 1990
This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. W... more This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p, ROM based methods become unattractive for integration due to excessive memory requirements. Two new methods are discussed and compared to ROM implementations with regard to their speed/complexity behaviour. The first method is based on a (n + 1) x (n + 1) bit array multiplier, the second on carry-save addition, both of which allow very high throughputs in pipelined implementations. While the former is very convenient for CAD environments providing a pipelined multiplier macro cell generator, the latter is well-suited to full custom implementation.
CMOS circuits have been the workhorse of ICT for 40 years. Due to the unique scaling property of ... more CMOS circuits have been the workhorse of ICT for 40 years. Due to the unique scaling property of this technology, energy efficiency has enormously improved during that time, notably by lowering the supply voltage from the long-time standard of 5 to 1 V and less. As the era of “happy scaling” has come to an end, progress becomes increasingly difficult and techniques beyond 2D size reductions have come into play. A superior and viable alternative to CMOS has yet to be found.
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Papers by Hubert Kaeslin