In this paper, the mechanisms of the suppression of Zr-silicide formation in poly-Si/ZrON/interfa... more In this paper, the mechanisms of the suppression of Zr-silicide formation in poly-Si/ZrON/interfacial-layer/Si structure at 1000°C annealing are discussed in detail. It was demonstrated that gaseous SiO desorption, which played a dominant role in the silicide formation in the case of the ZrO2/SiO2/Si, was completely inhibited in the ZrON/interfacial-layer/Si structure. In addition, we have found that an ultrathin interfacial SiON layer between poly-Si and ZrON stabilized the interface. Consequently, we concluded that the effective nitrogen incorporation into top/bottom interfacial SiON layers with our process was responsible for the superior thermal stability of the stack.
ABSTRACTWhisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly ... more ABSTRACTWhisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly observed for the first time. Short points between gate electrodes and poly-Si plugs in the test structure were identified by emission microscope and cross-sectional TEM samples of those points were made by using focused ion beam (FIB).Whiskers are formed during high-temperature processing such as LP-CVD SiN. We have proposed that NH3 de-oxidation step inserted in the SiN deposition sequence is effective for suppressing whisker growth. [1] In this study it was also confirmed that 600°C NH 3 pre-flow improved leakage current between gate electrode and contact plugs.
A defect-free diffusion layer is found to be formed by the cryogenic ion implantation technique f... more A defect-free diffusion layer is found to be formed by the cryogenic ion implantation technique for arsenic dopants. The following thermal annealing completely recrystallizes amorphous layers through solid-phase growth, eliminating dislocation growth. Furthermore, substrate cooling drastically suppresses the melting of the substrate surface. It is considered that, owing to the ability to absorb thermal energy brought about by cooling the substrate, the number of local microvoids formed by vacancy clusters is reduced and interstitial clusters are not easily enlarged, leading to surface roughness reduction. The substrate-cooling technique is very effective for suppressing recrystallization bought about by the self-annealing effect, and it is a very effective technology not only for reducing the defect density but also for improving the Si/SiO2 interface state density.
Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow... more Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow junctions. Boron ions were implanted in (100) Si substrates cooled using liquid nitrogen, with temperature controlled at -160 °C or lower during ion implantation. It was found that an amorphous layer was formed by boron implantation and that the amorphous layer completely recovered to single crystals after annealing at 900 °C for 30 s. No dislocation was observed in the implanted layer. It was also found that the thermal diffusion of boron was suppressed by cryo implantation. Furthermore, cryo implantation was found to be very effective in reducing the density of defects, and P–N junction leakage was reduced by one order of magnitude compared with that in the case of room temperature implantation. These results suggest that the transient enhanced diffusion of boron can be reduced by suppressing vacancy migration toward the surface during implantation. Moreover, the substrate-cooling eff...
We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very... more We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology ,the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).
2007 International Workshop on Junction Technology, 2007
A novel technique has been developed that can provide activated dopant profiling of USJ structure... more A novel technique has been developed that can provide activated dopant profiling of USJ structures without complicated Poisson based corrections. The technique has been demonstrated on USJ layers as thin as 25 nm. The value of this measurement technique is that it removes any consideration of mobility variation and allows one to focus on the electrically activated dopant. As the shape of the profile can affect device performance, this measurement will allow for optimal process development.
In this paper, the mechanisms of the suppression of Zr-silicide formation in poly-Si/ZrON/interfa... more In this paper, the mechanisms of the suppression of Zr-silicide formation in poly-Si/ZrON/interfacial-layer/Si structure at 1000°C annealing are discussed in detail. It was demonstrated that gaseous SiO desorption, which played a dominant role in the silicide formation in the case of the ZrO2/SiO2/Si, was completely inhibited in the ZrON/interfacial-layer/Si structure. In addition, we have found that an ultrathin interfacial SiON layer between poly-Si and ZrON stabilized the interface. Consequently, we concluded that the effective nitrogen incorporation into top/bottom interfacial SiON layers with our process was responsible for the superior thermal stability of the stack.
ABSTRACTWhisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly ... more ABSTRACTWhisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly observed for the first time. Short points between gate electrodes and poly-Si plugs in the test structure were identified by emission microscope and cross-sectional TEM samples of those points were made by using focused ion beam (FIB).Whiskers are formed during high-temperature processing such as LP-CVD SiN. We have proposed that NH3 de-oxidation step inserted in the SiN deposition sequence is effective for suppressing whisker growth. [1] In this study it was also confirmed that 600°C NH 3 pre-flow improved leakage current between gate electrode and contact plugs.
A defect-free diffusion layer is found to be formed by the cryogenic ion implantation technique f... more A defect-free diffusion layer is found to be formed by the cryogenic ion implantation technique for arsenic dopants. The following thermal annealing completely recrystallizes amorphous layers through solid-phase growth, eliminating dislocation growth. Furthermore, substrate cooling drastically suppresses the melting of the substrate surface. It is considered that, owing to the ability to absorb thermal energy brought about by cooling the substrate, the number of local microvoids formed by vacancy clusters is reduced and interstitial clusters are not easily enlarged, leading to surface roughness reduction. The substrate-cooling technique is very effective for suppressing recrystallization bought about by the self-annealing effect, and it is a very effective technology not only for reducing the defect density but also for improving the Si/SiO2 interface state density.
Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow... more Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow junctions. Boron ions were implanted in (100) Si substrates cooled using liquid nitrogen, with temperature controlled at -160 °C or lower during ion implantation. It was found that an amorphous layer was formed by boron implantation and that the amorphous layer completely recovered to single crystals after annealing at 900 °C for 30 s. No dislocation was observed in the implanted layer. It was also found that the thermal diffusion of boron was suppressed by cryo implantation. Furthermore, cryo implantation was found to be very effective in reducing the density of defects, and P–N junction leakage was reduced by one order of magnitude compared with that in the case of room temperature implantation. These results suggest that the transient enhanced diffusion of boron can be reduced by suppressing vacancy migration toward the surface during implantation. Moreover, the substrate-cooling eff...
We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very... more We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology ,the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).
2007 International Workshop on Junction Technology, 2007
A novel technique has been developed that can provide activated dopant profiling of USJ structure... more A novel technique has been developed that can provide activated dopant profiling of USJ structures without complicated Poisson based corrections. The technique has been demonstrated on USJ layers as thin as 25 nm. The value of this measurement technique is that it removes any consideration of mobility variation and allows one to focus on the electrically activated dopant. As the shape of the profile can affect device performance, this measurement will allow for optimal process development.
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Papers by Kyoichi Suguro