2019 IEEE International Conference on System, Computation, Automation and Networking (ICSCAN), 2019
Future 5G wireless applications require improved data rate, low delay, efficient usage of spectru... more Future 5G wireless applications require improved data rate, low delay, efficient usage of spectrum, reduced out of band emissions (OOB) and implementation complexities. Generalized Frequency Division Multiplexing (GFDM) is one of the new 5G carrier waveform candidate which meets the 5G applications requirements nicely when matched with Orthogonal Frequency Division Multiplexing (OFDM). However, the GFDM has some disadvantages such as Inter-Symbol Interference (ISI), Inter-Carrier Interference (ICI) and implementation complexities. It’s not possible to obtain a reliable communication with GFDM signal which has more severe effects on interferences and noises. To eliminate interference in communication system local DGT algorithms were used with proposed new type of prototype filtering. The proposed filtering will have separate filters for odd subcarriers and even subcarriers respectively. It introduces the orthogonality conditions which will be used to get rid of interferences in the communication systems. Simulation results shows that the suggested GFDM system has better BER performance when compared to the traditional GFDM system. In future we can directly apply some channel estimation algorithms and different MIMO antenna configurations in the modified GFDM system for improved performances.
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Papers by P. Dananjayan
System on Chip (SoC). Network on Chip (NoC) has the new architecture to deal overheads of communication.
The aim of the work is to increases the performance of the Chip Multiprocessor (CMP).
For the NoC to work reasonably, an Arbiter is required, and the performance of arbiter will affect
the system performance. A huge survey has been required for analyzing the high performance NoC
system with different proposed architectures. In the literature, different techniques are proposed for
the Arbiter module. An enhanced model intended for the arbiter from the literature study, Parallel
Distributed Round Robin Arbiter (PDRRA) has been proposed and implemented for the NoC switch.
PDRRA is the most required component for improving the CMP in terms of interconnecting the SoC.
The round robin scheduling algorithm is modified according to this work. The Arbiter is designed
with five input and five output ports and evaluated up to 65 applications. The input port is designed
with a controller which controls the buffer and a crossbar for transferring the data packets. The proposed
work includes switch architecture with new techniques for crossbar switch and bi-directional
ports. The NoC switch with PDRRA has been simulated and synthesized in Xilinx Vertex-6(V-6). For
analysis of results, the verilog code is used and Xilinx 14.7 for synthesizing the chip area utilization,
delay and power consumption. PDRRA has shown better performance when compared with new
arbiter techniques. While compared with DRRA, the PDRRA has improved the clock frequency by
13% and area overhead by 8%. Thus, the proposed work has shown improved results than recent
works of NoC interconnect system.
System on Chip (SoC). Network on Chip (NoC) has the new architecture to deal overheads of communication.
The aim of the work is to increases the performance of the Chip Multiprocessor (CMP).
For the NoC to work reasonably, an Arbiter is required, and the performance of arbiter will affect
the system performance. A huge survey has been required for analyzing the high performance NoC
system with different proposed architectures. In the literature, different techniques are proposed for
the Arbiter module. An enhanced model intended for the arbiter from the literature study, Parallel
Distributed Round Robin Arbiter (PDRRA) has been proposed and implemented for the NoC switch.
PDRRA is the most required component for improving the CMP in terms of interconnecting the SoC.
The round robin scheduling algorithm is modified according to this work. The Arbiter is designed
with five input and five output ports and evaluated up to 65 applications. The input port is designed
with a controller which controls the buffer and a crossbar for transferring the data packets. The proposed
work includes switch architecture with new techniques for crossbar switch and bi-directional
ports. The NoC switch with PDRRA has been simulated and synthesized in Xilinx Vertex-6(V-6). For
analysis of results, the verilog code is used and Xilinx 14.7 for synthesizing the chip area utilization,
delay and power consumption. PDRRA has shown better performance when compared with new
arbiter techniques. While compared with DRRA, the PDRRA has improved the clock frequency by
13% and area overhead by 8%. Thus, the proposed work has shown improved results than recent
works of NoC interconnect system.