2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009
Based on the characteristic current on the stub series terminated logic (SSTL) topology, three de... more Based on the characteristic current on the stub series terminated logic (SSTL) topology, three design parameters, the effective power and ground inductance and the signal loop inductance, are proposed to evaluate on the performance of signal integrity (SI) and power integrity (PI) for the memory circuits. From these three parameters, a design flow systematically describes how to design the layout of package for the designers is presented. Using this design flow, an improved package, which refines from a real package substrate, are shown to have better performance of SI and PI under the condition of identical layout area. Finally, the chip-package co-simulation at time domain verified the validity of the design ideas.
2008 Electrical Design of Advanced Packaging and Systems Symposium, 2008
The modeling methodology of power distribution system (PDS) in three different levels, chip, pack... more The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS cosimulation of chip-package-PCB is important for the DDR3 circuit design.
The modeling methodology of power distribution system (PDS) in three different levels, chip, pack... more The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS cosimulation of chip-package-PCB is important for the DDR3 circuit design.
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009
Based on the characteristic current on the stub series terminated logic (SSTL) topology, three de... more Based on the characteristic current on the stub series terminated logic (SSTL) topology, three design parameters, the effective power and ground inductance and the signal loop inductance, are proposed to evaluate on the performance of signal integrity (SI) and power integrity (PI) for the memory circuits. From these three parameters, a design flow systematically describes how to design the layout of package for the designers is presented. Using this design flow, an improved package, which refines from a real package substrate, are shown to have better performance of SI and PI under the condition of identical layout area. Finally, the chip-package co-simulation at time domain verified the validity of the design ideas.
2008 Electrical Design of Advanced Packaging and Systems Symposium, 2008
The modeling methodology of power distribution system (PDS) in three different levels, chip, pack... more The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS cosimulation of chip-package-PCB is important for the DDR3 circuit design.
The modeling methodology of power distribution system (PDS) in three different levels, chip, pack... more The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS cosimulation of chip-package-PCB is important for the DDR3 circuit design.
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Papers by Raphael Huang