Papers by Subhasis Bhattacharjee
A Distributed Algorithm for Constructing an Independent Dominating Set
Lecture Notes in Computer Science, 2022
Asia South Pacific Design Automation Conference (ASPDAC)
FPGA placement using space-filling curves
ACM Transactions on Embedded Computing Systems, 2009
Research in VLSI placement, an NP-hard problem, has branched in two different directions. The fir... more Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality. The other one considers placement as a graph-embedding problem and designs approximation algorithms with provable bounds on the quality of the solution. In this article, we aim at unifying the above two directions. First, we extend the existing approximation algorithms for graph embedding in 1D and 2D grid to those for hypergraphs, which typically model circuits to be placed on a FPGA. We prove an approximation bound of O ( d ālog n log log n ) for 1D, that is, linear arrangement and O ( d log n log log n ) for the 2D grid, where d is the maximum degree of hyperedges and n , the number of vertices in the hypergraph. Next, we propose an efficient method based on linear arrangement of the CLBs and the notion of space-filling curves for placin...
Test pattern generation for power supply droop faults
Proceedings of the IEEE International Conference on VLSI Design, 2006
AbstractĀ In deep sub-micron VLSI chips, when several tran-sistors in physical proximity switch s... more AbstractĀ In deep sub-micron VLSI chips, when several tran-sistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow ...
In WSN, each sensor is responsible for sensing environmental conditions and sending them to the o... more In WSN, each sensor is responsible for sensing environmental conditions and sending them to the one or more base stations. Battery-operated sensors are severely constrained by the amount of energy that can be spend for transmitting these sensed data. However, aggregation of data (including removal of redundant data) at intermediate sensors and forwarding of aggregate data reduce overall energy consumptions in WSN. In general, data gathering refers to the process of periodic collection of sensed data from various sensors to one or more base stations (BS). Energy efficient data gathering scheduling is essential for improving the lifetime of WSN. In this paper, we propose a distributed algorithm to compute data-gathering schedule that aim to improve the lifetime of WSN by suitably selecting energy-efficient data-flow paths from various sensors to the base station. For a multihop WSN with n sensors, the proposed algorithm first computes a schedule in O(n^2) time steps, and then this sch...
In the map labeling problem, we are given a set P = {p1, p2, . . . , pn} of point sites distribut... more In the map labeling problem, we are given a set P = {p1, p2, . . . , pn} of point sites distributed on a 2D map. The label of a point pi is an axis-parallel rectangle of specified size. The objective is to label maximum number of points on the map so that the placed labels are mutually non-overlapping. Here, we investigate a special class of map labeling problem where (i) the height of the label of each point is the same but its length may be different from the others, (ii) the label of a point pi touches the point at one of its four corners and (iii) it does not obscure any other point in P . We describe an efficient heuristic algorithm for this problem which runs in O(n ā n) time in the worst case. We run our algorithm as well as the algorithm proposed in [14] on the available benchmarks [13]. The results produced by our algorithm is same as that of [14] in most of the cases, and is one less in few cases. But the time taken by our algorithm is much less than [14].
In WSN, each sensor is responsible for sensing environmental conditions and sending them to the o... more In WSN, each sensor is responsible for sensing environmental conditions and sending them to the one or more base stations. Battery-operated sensors are severely constrained by the amount of energy that can be spend for transmitting these sensed data. However, aggregation of data (including removal of redundant data) at intermediate sensors and forwarding of aggregate data reduce overall energy consumptions in WSN. In general, data gathering refers to the process of periodic collection of sensed data from various sensors to one or more base stations (BS). Energy efficient data gathering scheduling is essential for improving the lifetime of WSN. In this paper, we propose a distributed algorithm to compute data-gathering schedule that aim to improve the lifetime of WSN by suitably selecting energy-efficient data-flow paths from various sensors to the base station. For a multihop WSN with $n$ sensors, the proposed algorithm first computes a schedule in $O(n^2)$ time steps, and then this...
Distributed Algorithm forPowerAwareConnected Dominating SetforEf(Eient Routing inMobile Ad HocNetworks
changes frequently andunpredictably. Limitation ofbattery powerofeachnodegenerates achallenge for... more changes frequently andunpredictably. Limitation ofbattery powerofeachnodegenerates achallenge forpoweraware Eftfiet rutig i adhocmoblenvionmntithanco design. Incaseofdominating setbasedapproach, routing nomicuseofbattery powerisanimportant problem and .i . . .' information iSexchanged only between thedominating nodes, conventional routing protocols areunsuitable there dueto .d static choice ofrouting paths without consideration ofremainresulting inareduced trafiE. So,total energyconsumption overagiven time, that dependents onnetwork traf(E, isalso ingbalttery powerofthenodes. Inthis palper, weproposeredce . Reore likchne adit sas sdmr a simple andefEiient distributed algorithm forcalculating efucen. powerawareconnected dominating setforAdhocwireless networks. Toenhance thelifetime ofeachnode, whichwill in aIn this paper, we assumethatallnodes, distributed over aregion, haveanequal maximumtransmission range say, r.
A Fast Parallel Genetic Algorithm Based Approach for Community Detection in Large Networks
2019 11th International Conference on Communication Systems & Networks (COMSNETS)
For large scale networks, under various formulations, the community detection problem is known to... more For large scale networks, under various formulations, the community detection problem is known to be NP-hard. Several genetic algorithm based community detection methods have been reported in the literature so far. But most of them exhibit a very slow convergence and hence not scalable. To achieve faster convergence, in this paper, we propose a parallel genetic algorithm for community detection based on diameter of the communities. To the best of our knowledge, so far, ours is the first work where the diameter of the community has been considered as a key parameter for community detection. This new concept expedites the convergence of the proposed genetic algorithm significantly without sacrificing the quality of the solution. Implementation of the algorithm on GP-GPU platform finds good quality community structures with near optimal modularity value with significantly less number of generations. Experiments show that it achieves 3 to 5 times speedup on synthetically created LFR (LancichinettiāFortunatoāRadicchi) benchmark networks compared to the existing sequential genetic algorithm. Simulation on well-known real-world benchmark networks with up to 58 K nodes and 428 K edges results speedup of 4.27 at maximum.
Instantaneous Mean-Time-To-Failure (MTTF) estimation for checkpoint interval computation at run time
Microelectronics Reliability
An Energy-Efficient Distributed Algorithm for Bluetooth Scatternet Formation
Adaptive Checkpoint Interval Algorithm Considering Task Deadline and Lifetime Reliability for Real-Time System
Procedia Computer Science, 2015
Abstract Checkpointing mechanism is used to tolerate the impact of transient faults by rollback o... more Abstract Checkpointing mechanism is used to tolerate the impact of transient faults by rollback operation. Recently, it has also been used as a mechanism to enhance system's lifetime by identifying and tolerating permanent fault 5,19,10,12. However, equidistant checkpoint interval may cause task deadline violation in the system. Here, we propose an adaptive checkpoint interval placement algorithm (ADeLiRACI) that meets all tasks deadline. The checkpoint intervals are adjusted to minimize the impact of stresses and permanent faults on the running hosts. This novel mechanism allows greater applicability in real time systems with hard deadline such as weather prediction, financial transactions etc. We compare the estimated completion time for increasing fault-rate in the system against five existing algorithms. For all applications, ADeLiRACI is able to meet the hard deadline along with enhancing lifetime reliability of the system.
Certificate-based encoding of gate level description for secure transmission
International Journal of Electronic Security and Digital Forensics, 2015
Modern system-on-chip design strongly depends on secure exchange of intellectual properties among... more Modern system-on-chip design strongly depends on secure exchange of intellectual properties among various authorities. Since it involves large amount of data, the conventional message encryption techniques need improvised use. We propose a novel obfuscation technique for synthesised digital circuits that facilitates secure transmission. It does not need traditional cryptographic data encryption of the whole circuit, and thus requires significantly less time compared to RSA-based encryption. The encoding/decoding of the circuit is guided by a certificate generated specially for the circuit itself. The encoded description hides the functionality of the original circuit. The inbuilt integrity checking at the receiver enables in identifying any intentional modification. We propose two distinct approaches for certificate generation that allow a greater trade-off between the volume of data and the protection. Experimental results show that the proposed technique can withstand a variety of attacks from intruders.
Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System
ABSTRACT Due to continued technology scaling, reliability of today's integrated circuits ... more ABSTRACT Due to continued technology scaling, reliability of today's integrated circuits (IC) is an emerging design challenge especially in varied range of operating environment. The lifetime reliability of modern system has been severely limited by higher wear-out and stress effects. Checkpointing has been extensively used as an effective method in fault-tolerant system design. Traditionally, it is used to tolerate the impact of transient faults through saving the intermediate results at predefined time and rolling-back to appropriate previously saved state whenever needed. In this paper, we proposed a new checkpointing mechanism for a duplex real-time system that achieves fault-tolerant against transient and permanent faults, and also provides a fault avoidance mechanism by migrating task from an unhealthy (perhaps near-to-die) host to a spare host. We developed a mathematical model for evaluating the performance of the proposed methodology in presence of various faults and task migration. The combination of checkpointing and task migration enhances the lifetime reliability of the system by tolerating faults and wear-out. Since checkpointing imposes additional overhead, energy consumption and ability to meet the task deadline are very crucial for any real-time system. The Expected-Execution-Time (EET) of a task is an important performance metric in respect to task completion. Similarly, the Average-Energy-Consumption (AEC) reflects the energy usage of a checkpointing mechanism under various faults. Under probabilistic distribution of various faults, we evaluate EET and AEC for our proposed checkpointing mechanism. We also investigated the deadline estimation for our proposed algorithm. We found that the proposed algorithm is able to meet the deadline even when the fault rate is as high as 10ā3. Our simulation result shows that the proposed checkpointing mechanism can meet task deadline with only 12.57% time overhead.
In wireless sensor networks (WSN), each sensor is responsible for sensing environmental condition... more In wireless sensor networks (WSN), each sensor is responsible for sensing environmental conditions and sending them to the one or more base stations. Battery-operated sensors are severely constrained by the amount of energy that can be spend for transmitting these sensed data. However, aggregation of data (including removal of redundant data) at intermediate sensors and forwarding of aggregate data reduce overall energy consumptions in WSN. In general, data gathering refers to the process of periodic collection of sensed data from various sensors to one or more base stations (BS). Energy efficient data gathering scheduling is essential for improving the lifetime of WSN. In this paper, we propose a distributed algorithm to compute data-gathering schedule that aim to improve the lifetime of WSN by suitably selecting energy-efficient data-flow paths from various sensors to the base station. For a multihop WSN with n sensors, the proposed algorithm first computes a schedule in O(n 2) time steps, and then this schedule is periodically updated based the residual energy and the feedback received from the BS. The system performs approximately log(L) schedule updates where L is the expected lifetime of the system in number of data-gathering rounds. Moreover, each updation process uses the existing active schedule (data-flow path)-thus consuming only a small fraction of a single data gathering round activity. Such an algorithm thus could precisely incorporate the energy consumptions due to updates and related activities. Moreover, our algorithm does not assume any global knowledge of the topology or the positions of various sensors. Through simulation study, we found that our proposed algorithm achieves significantly higher network lifetime compared to existing data-flow schedules based on the Minimum Spanning Tree (MST), the Shortest Path Tree (SPT), the Weighted Rooted Tree (WRT) [3].
Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis
2013 International Symposium on Electronic System Design, 2013
ABSTRACT Check pointing mechanism is used to tolerate the impact of transient faults through roll... more ABSTRACT Check pointing mechanism is used to tolerate the impact of transient faults through roll-back operation to a previously saved system state. In this paper, we propose a novel check pointing mechanism that considers fault tolerance in a duplex system in the presence of both transient and permanent faults. The main objective of our proposed mechanism is to extend the lifetime reliability of the duplex system by avoiding or even tolerating permanent faults in microprocessors. In addition, we also propose to migrate tasks from a 'near-to-die' processor to a spare processor under a condition where the current Mean-Time-To-Failure (MTTF) value is less or equal to a pre-determined threshold MTTF value. We validate our proposed mechanism and perform overhead analysis using various case studies. Later, we compare it with one of the most popular existing check pointing mechanism, namely the roll-forward check pointing scheme [9]. We show that unlike roll-back or roll-forward mechanisms, our proposed mechanism gives significantly higher lifetime reliability with reasonable system overheads.
IEEE Transactions on CAD, 2004
To date all the proposals for low power designs of RAMs essentially focus on circuit level soluti... more To date all the proposals for low power designs of RAMs essentially focus on circuit level solutions. What we propose here is a novel architecture (high) level solution. Our methodology provides a systematic tradeoff between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance improvements while simultaneously reducing power. In this respect it stands apart from other approaches where the conventional wisdom is reducing power reduces speed. The basic approach here divides the RAM into modules, interconnecting these modules in a binary tree where the tree can be reconfigured dynamically during normal operation and during test mode. Furthermore, during test mode, most of the RAM can be switched off-providing major power reduction, while test application time is reduced. The aspect ratio of the modules is allowed to vary as a design parameter. The chosen aspect ratio for module impacts power/access time/area trade offs. Such novel features make the proposed methodology of potential practical significance. Also a design tool is developed which inputs various parameters, such as desired power/performance, giving outputs basic design parameters such as the needed number of modules, area overhead and resulting test speed-up.
To date all the proposal for low power designs of RAMs essentially focus on circuit level solutio... more To date all the proposal for low power designs of RAMs essentially focus on circuit level solutions. What we propose here is a novel architecture level solution. Our methodology provides a systematic trade off between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance improvements while reducing power. In this respect it stands apart from other approaches where the conventional wisdom of reducing power reduces speed.
Article 12 (23 pages): FPGA Placement Using Space-Filling Curves: Theory Meets Practice
To date, all of the proposals for low-power designs of RAMs essentially focus on circuit-level so... more To date, all of the proposals for low-power designs of RAMs essentially focus on circuit-level solutions. What we propose here is a novel architecture (high) level solution. Our methodology provides a systematic tradeoff between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance improvements while simultaneously reducing power. In this respect, it stands apart from other approaches where power reduction results in speed reduction. The basic approach here divides the RAM into modules, interconnecting these modules in a binary tree where the tree can be reconfigured dynamically during normal operation and during test mode. Furthermore, during test mode, most of the RAM can be switched off, which provides major power reduction, while test-application time is reduced. The aspect ratio of the modules is allowed to vary as a design parameter. The chosen aspect ratio for module impacts power/access time/area tradeoffs. Such novel features make the proposed methodology of potential practical significance. Also, a design tool is developed which inputs various parameters, such as desired power/performance, giving outputs basic design parameters, such as the needed number of modules, area overhead, and resulting test speed-up. Index Terms-Embedded RAM, leakage power, low power, lowpower RAM (LPRAM), low-power testing, memory architecture, RAM, testable RAM. I. INTRODUCTION F URTHER progress in low-power very large scale integration (VLSI) technology, including low-power RAM designs, is crucial for the semiconductor industry. Additionally, the success of future system-on-a-chip (SOC) depends heavily on innovations in low-power embedded RAM design. All previous works on RAM focus on circuit-level solutions. There are mainly three directions in which research has targeted design of low-power RAM [2], [3], [7], [8]. Specifically, these are reduction in 1) charging capacitance; 2) operating voltage; and 3) static current. Proposed methodology here departs radically from all these and provides an architectural high-level solution. This does not preclude application of the lower circuit-level techniques for low-power design, in addition. Therefore, any existing circuit-level techniques can also be applied to our proposed methodology to achieve further power savings. However, a unique feature of our design that cannot be accomplished through the circuit approach is that power reduction is achieved with potential performance and test improvements.
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Papers by Subhasis Bhattacharjee