Papers by Balaji Vaidyanathan
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9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003.
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Hot Carrier Degradation in Semiconductor Devices, 2014
The increase in CMOS hot carrier lifetime due to Deuterium anneals motivates a straightforward ph... more The increase in CMOS hot carrier lifetime due to Deuterium anneals motivates a straightforward physical picture for hot carrier degradation. The various possible isotope effects provide context for a discussion of some qualitative aspects of the physics. Typical industry DC hot carrier stress models and their application to AC circuit models are described and motivated in that context.
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IEEE Transactions on Device and Materials Reliability, 2012
The impact of negative bias temperature instability (NBTI) on circuit reliability is typically as... more The impact of negative bias temperature instability (NBTI) on circuit reliability is typically assessed without accounting for the variability associated with the manufacturing process. With technology progression, manufacturing process variability scales more aggressively than transistor NBTI lifetime. Hence, a clear link between transistor and circuit reliability that takes variability into account is imperative to analyze circuit reliability. We propose a figure of merit termed fall-out to describe the proportion of circuits whose frequencies would exceed the initial manufacturing distribution. We use fall-out to assess NBTI and process variability in tandem, and we show that the fall-out of circuit frequency (or timing delay) peaks and diminishes as technology scales. We propose that the fall-out of a ring oscillator can be used as a worst-case indicator of circuit reliability in any given technology.
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IEEE Transactions on Dependable and Secure Computing, 2011
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Control circuit in an asynchronous design is comprised mostly of Muller C-elements. Previous work... more Control circuit in an asynchronous design is comprised mostly of Muller C-elements. Previous work has concentrated on power, performance, and area issues of various CMOS implementations of the C-element. In this paper we carried out a thorough soft error analysis of four popular CMOS implementations of the Muller C-element. It shows that SIL implementation has the best soft error resilience. Optimization techniques to improve the soft error resilience of C-elements are proposed. Results show 2x improvements in critical charge by using our techniques. Finally, analysis of power, performance, and area tradeoff is carried out for the optimized C-element.
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2016 IEEE 8th International Memory Workshop (IMW), 2016
Industry-standard Circuit Reliability simulation Tools (ICRT) to simulate Channel Hot Carrier (CH... more Industry-standard Circuit Reliability simulation Tools (ICRT) to simulate Channel Hot Carrier (CHC) is either not possible at the full-chip level consisting of few million transistors or time consuming and prone to abrupt termination of simulation due to resource usage anomalies at reasonable large sub-block level. We have proposed a hierarchical design-in-reliability methodology to identify CHC aging of critical transistors accurately at full-chip level in 10x faster time than required by ICRT. Accurate reliability simulation and design mitigation is later carried out at much smaller and critical sub-block level using ICRT. We have demonstrated our methodology in screening critical blocks in a NAND flash memory and the results are provided thus enabling reliable and faster time to tape-out.
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Code compression techniques have been proposed to mitigate the problem of limited memory resource... more Code compression techniques have been proposed to mitigate the problem of limited memory resources in embedded systems. As technology scales, reducing on-chip bus energy consumption is becoming important for embedded system designers. In this paper, we propose a crosstalk-aware energy-efcient code compression scheme, which can reduce inter-wire coupling transition induced instruction bus energy consumption, without sacricing compression ratio. The experimental
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Describes the intricacies of hot carrier degradation in modern semiconductor technologies Covers ... more Describes the intricacies of hot carrier degradation in modern semiconductor technologies Covers the entire hot carrier degradation phenomenon, including topics such as characterization, carrier transport, carrier-defect interaction, technological impact, circuit impact, etc Enables detailed understanding of carrier transport, interaction of the carrier ensemble with the defect precursors, and an accurate assessment of how the newly created defects impact the device performance Covers modeling issues starting from detailed physics-based TCAD approaches up to efficient SPICE-compatible compact models
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Reliability Physics Symposium ( …
Time-dependent performance degradation due to Negative Bias Temperature Instability (NBTI) and Ho... more Time-dependent performance degradation due to Negative Bias Temperature Instability (NBTI) and Hot-Carrier Injection (HCI) are major hurdle for product reliability assurance in current and future technologies. As we reach the sub-40nm regime, transistor reliability ...
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Reliability Physics Symposium, …
Abstract—Embedded DRAM has been widely used in System on Chip (SOC) systems due to its higher den... more Abstract—Embedded DRAM has been widely used in System on Chip (SOC) systems due to its higher density than SRAM. Embedded DRAM soft error rate (SER) has become an important subject since more embedded dynamic random access memories (DRAM) are now ...
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Papers by Balaji Vaidyanathan