Papers by sayan Chatterjee
Indian Journal of Medical and Paediatric Oncology, 2008
... Indian J Med Paediatr Oncol 2008;29:23-5. How to cite this URL: Kundu S, Chatterjee S,Mondol ... more ... Indian J Med Paediatr Oncol 2008;29:23-5. How to cite this URL: Kundu S, Chatterjee S,Mondol D, Dastidar AG, Roy A. Myoepithelial carcinoma in infratemporal fossa. ... A commentary on the 2nd Ed. Cancer 1992;70:379-85. Back to cited text no. 2. ...
Indian Journal of Medical and Paediatric Oncology, 2008
Indian Journal of Medical and Paediatric Oncology, 2008
... Indian J Med Paediatr Oncol 2008;29:23-5. How to cite this URL: Kundu S, Chatterjee S,Mondol ... more ... Indian J Med Paediatr Oncol 2008;29:23-5. How to cite this URL: Kundu S, Chatterjee S,Mondol D, Dastidar AG, Roy A. Myoepithelial carcinoma in infratemporal fossa. ... A commentary on the 2nd Ed. Cancer 1992;70:379-85. Back to cited text no. 2. ...
Lecture Notes in Computer Science, 2012
In this paper, we have modified a low-voltage, low-power V T (Threshold Voltage) extractor circui... more In this paper, we have modified a low-voltage, low-power V T (Threshold Voltage) extractor circuit, and by doing this we have obtained results with greater accuracy. At the same time, the output generated from this circuit is found to be robust enough against supply voltage variations. This scheme is based on the most popular extraction algorithm which essentially starts with I d versus V GS characteristics of any MOS transistor operating in saturation. Here the V T extractor block is followed by an offset generator and a feedback block. Now, for the purpose of modification, we have mainly changed the architecture of the offset generator block, keeping rest of the basic blocks unaltered. While doing this we have achieved more accurate results at low supply voltage ranging from 1.2 to 1.8V. In this range, for almost all the cases we found results with excellent accuracy. Whereas, considering the worst case scenario, the maximum deviation from the SPICE-V T value is found to be only 2.9%. Low power consumption, self-compensation for any second-order effect etc. are the key features for this modified architecture. The paper describes the V T extraction scheme, as well as, illustrates the techniques and circuit architecture required for the purpose. The results are supported by SPICE simulations.
Lecture Notes in Computer Science, 2012
In this paper, we have modified a low-voltage, low-power V T (Threshold Voltage) extractor circui... more In this paper, we have modified a low-voltage, low-power V T (Threshold Voltage) extractor circuit, and by doing this we have obtained results with greater accuracy. At the same time, the output generated from this circuit is found to be robust enough against supply voltage variations. This scheme is based on the most popular extraction algorithm which essentially starts with I d versus V GS characteristics of any MOS transistor operating in saturation. Here the V T extractor block is followed by an offset generator and a feedback block. Now, for the purpose of modification, we have mainly changed the architecture of the offset generator block, keeping rest of the basic blocks unaltered. While doing this we have achieved more accurate results at low supply voltage ranging from 1.2 to 1.8V. In this range, for almost all the cases we found results with excellent accuracy. Whereas, considering the worst case scenario, the maximum deviation from the SPICE-V T value is found to be only 2.9%. Low power consumption, self-compensation for any second-order effect etc. are the key features for this modified architecture. The paper describes the V T extraction scheme, as well as, illustrates the techniques and circuit architecture required for the purpose. The results are supported by SPICE simulations.
Advances in Electrical Engineering, 2014
ABSTRACT Subthreshold circuit designs are very much popular for some of the ultra-low power appli... more ABSTRACT Subthreshold circuit designs are very much popular for some of the ultra-low power applications, where the minimum energy consumption is the primary concern. But, due to the weak driving current, these circuits generally suffer from huge performance degradation. Therefore, in this paper, we primarily targeted analyzing the performance of a near-threshold circuit (NTC), which retains the excellent energy efficiency of the subthreshold design, while improving the performance to a certain extent. A modified row-based dual Vdd 4-operand carry save adder (CSA) design has been reported in the present work using 45 nm technology. Moreover, to find out the effectiveness of the near-threshold operation of the 4-operand CSA design, it has been compared with the other design styles. From the simulation results, obtained for the frequency of 20 MHz, we found that the proposed scheme of CSA design consumes 3.009x 10^(-7) Watt of average power (Pavg), which is almost 90.9% lesser than that of the conventional CSA design, whereas, looking at the perspective of maximum delay at output, the proposed scheme of CSA design provides a fair 44.37% improvement, compared to that of the subthreshold CSA design.
Advances in Electrical Engineering, 2014
ABSTRACT Subthreshold circuit designs are very much popular for some of the ultra-low power appli... more ABSTRACT Subthreshold circuit designs are very much popular for some of the ultra-low power applications, where the minimum energy consumption is the primary concern. But, due to the weak driving current, these circuits generally suffer from huge performance degradation. Therefore, in this paper, we primarily targeted analyzing the performance of a near-threshold circuit (NTC), which retains the excellent energy efficiency of the subthreshold design, while improving the performance to a certain extent. A modified row-based dual Vdd 4-operand carry save adder (CSA) design has been reported in the present work using 45 nm technology. Moreover, to find out the effectiveness of the near-threshold operation of the 4-operand CSA design, it has been compared with the other design styles. From the simulation results, obtained for the frequency of 20 MHz, we found that the proposed scheme of CSA design consumes 3.009x 10^(-7) Watt of average power (Pavg), which is almost 90.9% lesser than that of the conventional CSA design, whereas, looking at the perspective of maximum delay at output, the proposed scheme of CSA design provides a fair 44.37% improvement, compared to that of the subthreshold CSA design.
Proceedings of the 2014 IEEE Students' Technology Symposium, 2014
This paper proposes the design of an energy efficient, high speed and low power full subtractor u... more This paper proposes the design of an energy efficient, high speed and low power full subtractor using Gate Diffusion Input (GDI) technique. The entire design has been performed in 150nm technology and on comparison with a full subtractor employing the conventional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), respectively it has been found that there is a considerable amount of reduction in Average Power consumption (P avg ), delay time as well as Power Delay Product (PDP). P avg is as low as 13.96nW while the delay time is found to be 18.02pico second thereby giving a PDP as low as 2.51x10 -19 Joule for 1 volt power supply. In addition to this there is a significant reduction in transistor count compared to traditional full subtractor employing CMOS transistors, transmission gates and CPL, accordingly implying minimization of area. The simulation of the proposed design has been carried out in Tanner SPICE and the layout has been designed in Microwind.
Proceedings of the 2014 IEEE Students' Technology Symposium, 2014
This paper proposes the design of an energy efficient, high speed and low power full subtractor u... more This paper proposes the design of an energy efficient, high speed and low power full subtractor using Gate Diffusion Input (GDI) technique. The entire design has been performed in 150nm technology and on comparison with a full subtractor employing the conventional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), respectively it has been found that there is a considerable amount of reduction in Average Power consumption (P avg ), delay time as well as Power Delay Product (PDP). P avg is as low as 13.96nW while the delay time is found to be 18.02pico second thereby giving a PDP as low as 2.51x10 -19 Joule for 1 volt power supply. In addition to this there is a significant reduction in transistor count compared to traditional full subtractor employing CMOS transistors, transmission gates and CPL, accordingly implying minimization of area. The simulation of the proposed design has been carried out in Tanner SPICE and the layout has been designed in Microwind.
2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT), 2013
This paper introduces a Low Power 3-bit flash type ADC (Analog-to-Digital Converter) where the co... more This paper introduces a Low Power 3-bit flash type ADC (Analog-to-Digital Converter) where the conventional comparators have been replaced with the CMOS inverter based comparator designs. The reported structure of the ADC is designed using 180nm technology and it consumes 130.9 IlWatt of average power while operating with an input frequency (fIN) of 30MHz, and a supply voltage of 1.8 Volt. Moreover, with the aim of increasing the design efficiency, an optimized analog layout,
2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT), 2013
This paper introduces a Low Power 3-bit flash type ADC (Analog-to-Digital Converter) where the co... more This paper introduces a Low Power 3-bit flash type ADC (Analog-to-Digital Converter) where the conventional comparators have been replaced with the CMOS inverter based comparator designs. The reported structure of the ADC is designed using 180nm technology and it consumes 130.9 IlWatt of average power while operating with an input frequency (fIN) of 30MHz, and a supply voltage of 1.8 Volt. Moreover, with the aim of increasing the design efficiency, an optimized analog layout,
Smart Innovation, Systems and Technologies, 2014
Journal of Communications Technology and Electronics, 2014
In this article, a new method of pattern synthesis of centre fed, equal distance linear array hav... more In this article, a new method of pattern synthesis of centre fed, equal distance linear array having single and multiple synthesis objectives has been proposed and statistically investigated. Single objective of reduced side lobe level (SLL) and first null beamwidth (FNBW) has been considered separately. Conse quently, multiple objectives of beamwidth and side lobe level have been investigated. Synthesis of linear array for suitable objectives has been investigated on Taylor one parameter distribution with equal progressive phase. Excitation amplitude of each array element is taken as optimization parameter where distribution has been optimized using Particle Swarm Optimization (PSO) for achieving low SLL. Later the same has been incorporated for obtaining suitable FNBW. In our optimization algorithm conventional PSO has been mod ified with a restricted search PSO (RSPSO) where search space has been predefined within excitation ampli tude range. PSO within the defined range searches for optimum excitation amplitude to achieve the desired objectives. In order to illustrate the effectiveness of the proposed RSPSO, simulation results of three signifi cant instances of linear array have been presented for both even and odd number of element. The design results obtained using RSPSO have improved result than those obtained using other state of the art evolution ary algorithms like differential evolution (DE), invasive weeds optimization (IWO) and Conventional particle Swarm optimization (CPSO) in a statistically significant way.
IEEE Transactions on Antennas and Propagation, 2014
ABSTRACT A wide band iris excited fractal slotted array has been realized and experimentally veri... more ABSTRACT A wide band iris excited fractal slotted array has been realized and experimentally verified at X band. The design starts with a centered plus shaped slot in the broadwall of a rectangular waveguide and the same has been used in second iteration for fractal configuration, which exhibits dual resonance. The fractal unit cell is optimized for bandwidth by carrying out parametric study of slot-iris combinations and 2.4 GHz bandwidth is achieved for both radiation pattern and impedance response. An empirical expression for conductance of the unit cell has been developed to facilitate design of antenna array using the unit cell as an element. The optimized unit cell has been used for designing a four element array, which exhibits a pattern bandwidth of 1.4 GHz and impedance bandwidth of 2 GHz. The array is simulated in commercial fullwave 3D FEM simulator. The designed array has been fabricated and measured response has been compared with simulated data.
Manufacturing and Industrial Engineering, 2014
2013 International Conference on Microwave and Photonics (ICMAP), 2013
International Conference on Electronics, Communication and Instrumentation (ICECI), 2014
In this paper, a novel method for null placements in beam steered linear array with unequal excit... more In this paper, a novel method for null placements in beam steered linear array with unequal excitation amplitude and uniform inter-element spacing has been presented. The proposed method has been developed using Taylor one parameter distribution for linear array and particle swarm optimization (PSO). The beam steering has been achieved by maintaining a constant phase difference between two consecutive elements of the array. In order to place nulls in the desired direction excitation amplitude perturbation method using PSO has been considered. Search space of PSO has been defined using Taylor one parameter distribution for linear array. Within the defined search space PSO with the null placement objective. The proposed method has been tested for both single and wide null objectives. As example 12 elements linear array has been considered, for both single and wide null placement objective. Results show that, null level in the desired directions lies within 89% to 100% of desired null level of -60 dB, which in turn proves the effectiveness of the proposed method.
International Journal of Electronics, 2014
In this article, non-uniformly excited linear arrays are optimised using Taylor distribution and ... more In this article, non-uniformly excited linear arrays are optimised using Taylor distribution and classical particle swarm optimisation (CPSO) algorithm for obtaining desired equal side lobe level (SLL). Elements of the array are considered to be isotropic in nature with uniform interelement spacing. Excitation amplitudes of each element are taken as optimisation parameters. Taylor distribution defines the range of excitation amplitude in which CPSO algorithm searches for the optimum value of excitation amplitude, with the objective of obtaining desired equal SLL. The proposed method eliminates the initial randomness of defining search space for CPSO algorithm. Comparison with other methods has been made whenever possible. The results reveal that the proposed method can be used to obtain the desired SLL.
Electromagnetics, 2009
In this work we investigated the bandwidth characteristics of waveguide-fed planar slot arrays. E... more In this work we investigated the bandwidth characteristics of waveguide-fed planar slot arrays. Elliott's technique was used to design a number of end-fed and center-fed planar arrays with different aperture distributions and different amounts overloading in terms of conductances of radiating slots and resistances of coupling slots. Subsequently these arrays were analyzed by employing a full wave method of moments to solve for the coupled integral equations for the slot aperture electric field. Results of a study of radiation pattern and return loss as a function of frequency for different amounts of overloading are presented.
Strategy & Leadership, 2007
Purpose – When a merger or an acquisition fails, usually integration problems or overpayment gets... more Purpose – When a merger or an acquisition fails, usually integration problems or overpayment gets the blame. The authors illustrate that a common cause of failure is the traditional notion of synergy that exacerbates the overpayment and integration problems. This synergy usually leads to the failure of many mergers, yet synergy remains one of the most common justifications that management
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Papers by sayan Chatterjee