IBM Scalable POWERparallel

Scalable POWERparallel or SP is an IBM supercomputer platform. The nodes are based on the RS/6000 with clustering software called PSSP which is mainly written in Perl. Some of the technologies developed include the High Performance Switch (HPS) for internode communication.

Nodes

POWER1-based

Model	# of CPUs	CPU	CPU MHz	Cache	Memory	Introduced	Discontinued
SP1	1	POWER1++	62.5	None	64 to 256 MB	1993-02-02	1994-12-16

POWER2-based

Model	# of CPUs	CPU	CPU MHz	L2 Cache	Memory	Introduced	Discontinued
Thin 1	1	POWER2	66	?	64 to 512 MB	1995-08-22	1996-12-20
Thin 2				?	?		1997-06-27
Wide 1				?	64 MB to 2 GB		1996-12-20
Wide 2			77	?	?		1997-06-27

PowerPC 604-based

Model	# of CPUs	CPU	CPU MHz	Cache	Memory	Introduced	Discontinued
High 1	2, 4, 6, 8	PowerPC 604	112	?	?	1996-07-23	1998-01-08
High 2		PowerPC 604e	200	?	?	1997-08-26	1998-04-21
332 Thin	2, 4		332	?	?	1998-04-21	2000-12-29
332 Wide				?	?

P2SC-based

Model	# of CPUs	CPU	CPU MHz	Cache	Memory	Introduced	Discontinued
160 Thin	1	P2SC	160	?	?	1997-10-06	1998-04-21
Thin P2SC			120	?	?	1996-10-08
Wide P2SC			135	?	?

POWER3-based

Model	# of CPUs	CPU	CPU MHz	L2 Cache	Memory	Introduced	Discontinued
POWER3 High	2, 4, 6, 8	POWER3	222	?	?	1999-09-13	2000-12-29
POWER3 High		POWER3-II	375	?	?	2000-07-18	2002-12-27
POWER3 Thin	1, 2	POWER3	200	?	?	1999-09-01	2000-06-30
POWER3 Thin		POWER3-II	375	?	?	2000-02-07	2003-04-08
POWER3 Thin			450	?	?	2002-01-22
POWER3 Wide	1, 2	POWER3	200	?	?	1999-02-01	2000-06-30
POWER3 Wide	2, 4	POWER3-II	375	?	?	2000-02-07	2003-04-08
POWER3 Wide	2, 4		450	?	?	2002-01-22

See also

• IBM POWER microprocessors
• RS/6000
• POWER1
• POWER2
• POWER3
• PowerPC 604

External links

Architecture overview