Papers by Siddhartha Nath
ACM Transactions on Design Automation of Electronic Systems
Modern electronic design automation (EDA) flows depend on both implementation and signoff tools t... more Modern electronic design automation (EDA) flows depend on both implementation and signoff tools to perform timing-constrained power optimization (TCPO) through Engineering Change Orders (ECOs), which involve gate sizing and threshold-voltage ( V th )-assignment of standard cells. However, the signoff ECO optimization is highly time-consuming, and the power improvement is hard to predict in advance. Ever since the industrial benchmarks released by the ISPD-2012 gate-sizing contest, active research has been conducted extensively to improve the optimization process. Nonetheless, previous works were mostly based on heuristics or analytical methods whose timing models were oversimplified and lacked of formal validations from commercial signoff tools. In this paper, we propose ECO-GNN, a transferable graph-learning-based framework, which harnesses graph neural networks (GNNs) to perform commercial-quality signoff power optimization through discrete V th -assignment. One of the highlights ...
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Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
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Proceedings of the 28th Asia and South Pacific Design Automation Conference
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Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
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Author(s): Nath, Siddhartha | Advisor(s): Kahng, Andrew B. | Abstract: In today's leading-edg... more Author(s): Nath, Siddhartha | Advisor(s): Kahng, Andrew B. | Abstract: In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation products. One root cause of this difficulty is the increased margins that are used in the design process to guardband for (i) variability and aging, as well as (ii) analysis inaccuracies. Currently, these margins incur huge costs to design companies, because the benefits of deploying the next technology node are only approximately 20% in circuit performance, power and density. To reduce margins, fast and accurate pathfinding of architecture, technology and constraints choices are essential. A second root cause is the high cost (and, therefore, limited supply) of electronic design automation tool licenses, accompanied by the lack of any systematic methodology to optimize the use of available tools within long-duratio...
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Proceedings of the 59th ACM/IEEE Design Automation Conference
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Abstract—In modern SOC implementations, multi-mode design is commonly used to achieve better circ... more Abstract—In modern SOC implementations, multi-mode design is commonly used to achieve better circuit performance and power across voltage-scaling, “turbo ” and other operating modes. Although there are many tools for multi-mode circuit implementation, to our knowledge there is no available systematic analysis or methodology for the selection of associated signoff modes. We observe that the selection of signoff modes has significant impact on circuit area, power and performance. For example, incorrect choice of signoff voltages for required overdrive frequencies can result in a netlist with 15% suboptimality in power or 21 % in area. In this paper, we propose a concept of mode dominance which can be used as a guideline for signoff mode selection. Further, we also propose efficient circuit implementation flows to optimize the selection of signoff modes within several distinct use cases. Our results show that our proposed methodology provides 5-7 % improvement in performance compared t...
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2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021
Reinforcement learning (RL) has gained attention recently as an optimization algorithm for chip d... more Reinforcement learning (RL) has gained attention recently as an optimization algorithm for chip design. This method treats many chip design problems as Markov decision problems (MDPs), where design optimization objectives are converted into rewards given by the environment and design variables are converted into actions provided to the environment. Some recent examples include applications of RL to macro placement and standard cell layout routing. We believe RL can be applied to nearly all aspects of VLSI implementation flows, since many VLSI implementation problems are often NP-complete and state-of-art algorithms cannot be guaranteed to be optimal. With enough training data, it is possible to achieve better results with RL. In this paper we review recent advances in applying RL to VLSI implementation problems such as cell layout, synthesis, placement, routing and parameter tuning. We discuss the challenges of applying RL to VLSI implementation flows and propose future research directions for overcoming these challenges.
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2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021
Reinforcement learning (RL) has gained attention recently as an optimization algorithm for chip d... more Reinforcement learning (RL) has gained attention recently as an optimization algorithm for chip design. This method treats many chip design problems as Markov decision problems (MDPs), where design optimization objectives are converted into rewards given by the environment and design variables are converted into actions provided to the environment. Some recent examples include applications of RL to macro placement and standard cell layout routing. We believe RL can be applied to nearly all aspects of VLSI implementation flows, since many VLSI implementation problems are often NP-complete and state-of-art algorithms cannot be guaranteed to be optimal. With enough training data, it is possible to achieve better results with RL. In this paper we review recent advances in applying RL to VLSI implementation problems such as cell layout, synthesis, placement, routing and parameter tuning. We discuss the challenges of applying RL to VLSI implementation flows and propose future research directions for overcoming these challenges.
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Proceedings of the 2021 International Symposium on Physical Design, 2021
Relentless pursuit of high-frequency low-power designs at advanced nodes necessitate achieving si... more Relentless pursuit of high-frequency low-power designs at advanced nodes necessitate achieving signoff-quality timing and power during digital implementation to minimize any over-design. With growing design sizes (1--10M instances), full flow runtime is an equally important metric and commercial implementation tools use graph-based timing analysis (GBA) to gain runtime over path-based timing analysis (PBA), at the cost of pessimism in timing. Last mile timing and power closure is then achieved through expensive PBA-driven engineering change order (ECO) loops in signoff stage. In this work, we explore "on-the-fly'' machine learning (ML) models to predict PBA timing based on GBA features, to drive digital implementation flow. Our ML model reduces the GBA vs. PBA pessimism with minimal runtime overhead, resulting in improved area/power without compromising on signoff timing closure. Experimental results obtained by integrating our technique in a commercial digital implementation tool show improvement of up to 0.92% in area, 11.7% and 1.16% in power in leakage- and total power-centric designs, respectively. Our method has a runtime overhead of $\sim$3% across a suite of 5--16nm industrial designs.
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Proceedings of the 2021 International Symposium on Physical Design, 2021
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Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 [18] is a wide... more Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 [18] is a widely adopted NoC power and area estimation tool that is based on circuit-level templates, which use specific logic structures to model implementation of different router components. ORION2.0 estimation models can have large errors (up to 185%) versus actual implementation, often due to a mismatch between the actual router RTL and the templates assumed, as well as the effects of optimization tools in modern design flows. In this work, we propose comprehensive parametric and non-parametric modeling methodologies that fundamentally differ from logic template based approaches in that the estimation models are derived from actual physical implementation data. Specifically, we propose a new parametric modeling methodology as well as improvements to previous work on non-parametric modeling. Our work on parametric modeling proposes (1) ORION NEW models, developed using a new methodology that does ...
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Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 [18] is a wide... more Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 [18] is a widely adopted NoC power and area estimation tool that is based on circuit-level templates, which use specific logic structures to model implementation of different router components. ORION2.0 estimation models can have large errors (up to 185%) versus actual implementation, often due to a mismatch between the actual router RTL and the templates assumed, as well as the effects of optimization tools in modern design flows. In this work, we propose comprehensive parametric and non-parametric modeling methodologies that fundamentally differ from logic template based approaches in that the estimation models are derived from actual physical implementation data. Specifically, we propose a new parametric modeling methodology as well as improvements to previous work on non-parametric modeling. Our work on parametric modeling proposes (1) ORION NEW models, developed using a new methodology that does ...
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2021 58th ACM/IEEE Design Automation Conference (DAC), 2021
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Proceedings of the 39th International Conference on Computer-Aided Design, 2020
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2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013
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......The GreenDroid mobile application processor is a 45-nm multicore research prototype that ta... more ......The GreenDroid mobile application processor is a 45-nm multicore research prototype that targets the Android mobile-phone software stack and can execute general-purpose mobile programs with 11 times less energy than today’s most energy-efficient designs, at similar or better performance levels. It does this through the use of a hundred or so automatically generated, highly specialized, energy-reducing cores, called conservation cores. Our research attacks a key technological problem for microprocessor architects, which we call the utilization wall. 1 The utilization wall says that, with each process generation
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......The GreenDroid mobile application processor is a 45-nm multicore research prototype that ta... more ......The GreenDroid mobile application processor is a 45-nm multicore research prototype that targets the Android mobile-phone software stack and can execute general-purpose mobile programs with 11 times less energy than today’s most energy-efficient designs, at similar or better performance levels. It does this through the use of a hundred or so automatically generated, highly specialized, energy-reducing cores, called conservation cores. Our research attacks a key technological problem for microprocessor architects, which we call the utilization wall. 1 The utilization wall says that, with each process generation
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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015
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Papers by Siddhartha Nath