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Juha Plosila

University of Turku, Department of Computing, Faculty Member

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Dr. Juha Plosila is a Professor in the field of Autonomous Systems and Robotics at the University of Turku (UTU), Department of Computing, Finland. He received a PhD degree in Electronics and Communication Technology from UTU in 1999. He leads the Autonomous Systems Lab research group and Smart Systems unit at UTU. He is the head of the EIT Digital Master Programme in Embedded Systems at the EIT Digital Master School (European Institute of Innovation and Technology), and is a member (representing UTU) in the Node Strategy Committee of the EIT Digital Finland node. His current research interests include adaptive multi-processing systems and platforms, intelligent multi-agent monitoring and control architectures, machine learning and optimization approaches, as well as application of heterogeneous energy efficient architectures to new computational challenges in the cyber-physical systems and internet-of-things domains, with a recent focus on fog/edge computing (edge intelligence) and autonomous multi-robot systems.
Phone: +358503839453
Address: University of Turku, Department of Computing, Vesilinnantie 5, FI-20014 Turku, Finland

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Papers by Juha Plosila

Energy-Efficient Navigation of an Autonomous Swarm with Adaptive Consciousness

Remote Sensing

The focus of this work is to analyze the behavior of an autonomous swarm, in which only the leade... more The focus of this work is to analyze the behavior of an autonomous swarm, in which only the leader or a dedicated set of agents can take intelligent decisions with other agents just reacting to the information that is received by those dedicated agents, when the swarm comes across stationary or dynamic obstacles. An energy-aware information management algorithm is proposed to avoid over-sensation in order to optimize the sensing energy based on the amount of information obtained from the environment. The information that is needed from each agent is determined by the swarm’s self-awareness in the space domain, i.e., its self-localization characteristics. A swarm of drones as a multi-agent system is considered to be a distributed wireless sensor network that is able to share information inside the swarm and make decisions accordingly. The proposed algorithm reduces the power that is consumed by individual agents due to the use of ranging sensors for observing the environment for safe...

Embedded Multi-Core Systems

An Asynchronous Linear Predictive Analyzer

Linear predictive analysis is a standard technique in modern digital speech processing. This make... more Linear predictive analysis is a standard technique in modern digital speech processing. This makes it an interesting implementation area for asynchronous design. We present an asynchronous speed-independent circuit implementation of a linear predictive analysis system. The implementation is built around a program ROM into which the algorithm is encoded. The design process is carried out using the action systems formalism as the development tool. As the result we get an efficient and logically highly reliable system with a potential for low power consumption. We present various block diagrams of the resulting composition and show the details of a set of selected controllers.

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

Very Large Scale Integration Systems Ieee Transactions on, Apr 1, 2010

Abstract We present a self-contained adaptive system for detecting and bypassing permanent errors... more Abstract We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT ...

An Efficient Dynamic Multicast Routing Protocol for Distributing Traffic in NOCs

Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems

Dual-level fault-tolerance is presented on many-core systems, provided by the software-based syst... more Dual-level fault-tolerance is presented on many-core systems, provided by the software-based system agent and hardware-based local agents. The system agent performs fault-triggered energy-aware remapping with bandwidth constraints, addressing coarse-grained processor failures. The local agents achieve fine-grained link-level fault tolerance against transient and permanent errors. The paper concisely presents the architecture, dual-level fault-tolerant techniques and experiment results.

Design of Synchronous Action Systems

The action systems framework has recently been applied to the area of synchronous VLSI design. In... more The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchronous hardware, using synchronous action systems. These explicitly model synchronous two-phase behavior. They are developed using the refinement calculus in a usual manner. The fundamental idea of synchronous action systems is to make a formal description transparent in the sense that its hardware implementation can be obtained by direct mapping. The presented design methodology also allows a postponed decision on the final implementation aspects regarding the architecture (synchronous / asynchronous

Synchronization of Action Systems

On fault tolerance techniques towards nanoscale circuits and systems

The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shr... more The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shrink, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process, for instance the concentration of dopants, the thickness of the gate and the insulation oxides, the width and thickness of metal wires, etc. This results in decreased yield which increases the costs per functioning chip. Electromigration causes intermittent and permanent failures after some period of operation, which means that these faults cannot be observed in the manufacture test. The problem of electromigration increases when going further to nanometer regime because of the decreasing width and increasing deviation of wires. Lowering the supply voltages make the circuits more vulnerable to noise and background radiation resulting in a higher soft error rate. The only reasonable way to cope with these reliability problems is to build the circuits fault tolerant. Therefore, the yield can be maintained at an acceptable level by admitting some amount of faults in a chip. Electromigration problems can be overcome by the use of built-in redundancy and dynamically reconfigurable circuit structure. The soft errors can be handled by using static redundancy methods like hardware, information and time redundancy. This report discusses fault tolerance techniques for nanoscale structures. It begins with a study of phenomena that the move towards nano introduces. A gategorization for fault types is presented and the different impacts of scaling into nano regime are connected to these types. Later in the report a number of fault tolerance techniques are examined and their suitability for nanoscale circuits and systems is evaluated. Each technique is connected to one or several fault types according to their properties for fault tolerance perspective. Finally it is concluded that no single technique is enough for tolerating all the types of faults in nanosacle circuits and systems. Therefore a combination of two or more techniques is needed. The optimal mixture is design specific according to its usage purpose and proneness to different defect sources.

Synchronous Design Aspects Using Action Systems

The action systems framework has recently been applied to the area of synchronous VLSI design. In... more The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchronous hardware, using synchronous action systems. These explicitly model synchronous two-phase behavior. They are developed using the re nement calculus in a usual manner. The fundamental idea of synchronous action systems is to make a formal description transparent in the sense that its hardware implementation can be obtained by direct mapping. The presented design methodology also allows a postponed decision on the nal implementation aspects regarding the architecture (synchronous / asynchronous)

A novel hardware acceleration scheme for java method calls

2008 Ieee International Symposium on Circuits and Systems, May 18, 2008

Abstract This paper presents a novel strategy for accelerating the method calls in the REALJava c... more Abstract This paper presents a novel strategy for accelerating the method calls in the REALJava co-processor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is realized as an FPGA prototype. It allows measurements of real life performance increase, and validates the concept. The system is intended to be used in embedded environments, limiting the CPU performance and memory available to the virtual machine. The co-processor is designed ...

Hierarchical Agent-Based Architecture for Resource Management in Cloud Data Centers

2014 Ieee 7th International Conference on Cloud Computing, Jun 1, 2014

ABSTRACT In order to resource management in a large-scale data center, we present a hierarchical ... more ABSTRACT In order to resource management in a large-scale data center, we present a hierarchical agent-based architecture. In this architecture, multi agents cooperate together to minimize the number of active physical machines according to the current resource requirements. We proposed a local agent in each physical machine (PM) to determine the PM’s status and a global agent to optimizes VM placement based on PM’s status. Experimental results show the proposed architecture can minimize energy consumption while maintaining an acceptable QoS.

Toward Self-Placing Applications on 2D and 3D NoCs

Embedded Multi-Core Systems, 2011

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015

Power management of NoC-based manycore systems with runtime application mapping becomes more chal... more Power management of NoC-based manycore systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on network-on-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.

Formal Power Analysis of On-Chip Communication

MD: Minimal path-based fault-tolerant routing in on-Chip Networks

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 Inte... more

Fault Tolerance Analysis of Distributed Algorithms for Mesh Networks-on-Chip

Introducing Action Systems Class Hierarchy to SystemC Modelling

Abstract ActionC is an integration of SystemC, an informal design language for embedded systems, ... more Abstract ActionC is an integration of SystemC, an informal design language for embedded systems, and Action Systems, a formal modelling language that supports verifica- tion and stepwise correctness-preserving refinement of sys tem models. In the Ac- tionC approach Action Systems sets a formal foundation for SystemC modelling providing a possibility to verify the design as early as duri ng the construction of the first transaction level model. This report provides an im plementation for the ActionC language structures that concern Action Systems type system verifica- tion with invariants. The implementation,introduced here will be a part of a larger modelling framework,that will be elaborated in the future. Keywords: SystemC, Action Systems, ActionC, Formal methods, System mod-

Dark Silicon and Congestion Aware Power Management for Manycore Systems under Dynamic Workloads

Distributed BIST Approach for Power Constrained Many-Core Systems

—Dark Silicon is a phenomenon where a large portion of a chip&#39;s silicon area must remain ... more —Dark Silicon is a phenomenon where a large portion of a chip&#39;s silicon area must remain mostly passive to stay within the chip&#39;s power budget due to the thermal and power delivery issues. On the other hand, by reducing the transistor size, susceptibility to internal defects increases and large range of defects such as aging or transient faults will be more frequently shown up. In this paper, a dark silicon aware distributed built-in-self-test (BIST) approach for many-core systems is presented. The approach also benefits from dynamic voltage and frequency scaling in the online BIST process to maximize the number of tested cores with a negligible negative impact on the system performance.

Energy-Efficient Navigation of an Autonomous Swarm with Adaptive Consciousness

Remote Sensing

The focus of this work is to analyze the behavior of an autonomous swarm, in which only the leade... more The focus of this work is to analyze the behavior of an autonomous swarm, in which only the leader or a dedicated set of agents can take intelligent decisions with other agents just reacting to the information that is received by those dedicated agents, when the swarm comes across stationary or dynamic obstacles. An energy-aware information management algorithm is proposed to avoid over-sensation in order to optimize the sensing energy based on the amount of information obtained from the environment. The information that is needed from each agent is determined by the swarm’s self-awareness in the space domain, i.e., its self-localization characteristics. A swarm of drones as a multi-agent system is considered to be a distributed wireless sensor network that is able to share information inside the swarm and make decisions accordingly. The proposed algorithm reduces the power that is consumed by individual agents due to the use of ranging sensors for observing the environment for safe...

Embedded Multi-Core Systems

An Asynchronous Linear Predictive Analyzer

Linear predictive analysis is a standard technique in modern digital speech processing. This make... more Linear predictive analysis is a standard technique in modern digital speech processing. This makes it an interesting implementation area for asynchronous design. We present an asynchronous speed-independent circuit implementation of a linear predictive analysis system. The implementation is built around a program ROM into which the algorithm is encoded. The design process is carried out using the action systems formalism as the development tool. As the result we get an efficient and logically highly reliable system with a potential for low power consumption. We present various block diagrams of the resulting composition and show the details of a set of selected controllers.

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

Very Large Scale Integration Systems Ieee Transactions on, Apr 1, 2010

Abstract We present a self-contained adaptive system for detecting and bypassing permanent errors... more Abstract We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT ...

An Efficient Dynamic Multicast Routing Protocol for Distributing Traffic in NOCs

Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems

Dual-level fault-tolerance is presented on many-core systems, provided by the software-based syst... more Dual-level fault-tolerance is presented on many-core systems, provided by the software-based system agent and hardware-based local agents. The system agent performs fault-triggered energy-aware remapping with bandwidth constraints, addressing coarse-grained processor failures. The local agents achieve fine-grained link-level fault tolerance against transient and permanent errors. The paper concisely presents the architecture, dual-level fault-tolerant techniques and experiment results.

Design of Synchronous Action Systems

The action systems framework has recently been applied to the area of synchronous VLSI design. In... more The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchronous hardware, using synchronous action systems. These explicitly model synchronous two-phase behavior. They are developed using the refinement calculus in a usual manner. The fundamental idea of synchronous action systems is to make a formal description transparent in the sense that its hardware implementation can be obtained by direct mapping. The presented design methodology also allows a postponed decision on the final implementation aspects regarding the architecture (synchronous / asynchronous

Synchronization of Action Systems

On fault tolerance techniques towards nanoscale circuits and systems

The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shr... more The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shrink, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process, for instance the concentration of dopants, the thickness of the gate and the insulation oxides, the width and thickness of metal wires, etc. This results in decreased yield which increases the costs per functioning chip. Electromigration causes intermittent and permanent failures after some period of operation, which means that these faults cannot be observed in the manufacture test. The problem of electromigration increases when going further to nanometer regime because of the decreasing width and increasing deviation of wires. Lowering the supply voltages make the circuits more vulnerable to noise and background radiation resulting in a higher soft error rate. The only reasonable way to cope with these reliability problems is to build the circuits fault tolerant. Therefore, the yield can be maintained at an acceptable level by admitting some amount of faults in a chip. Electromigration problems can be overcome by the use of built-in redundancy and dynamically reconfigurable circuit structure. The soft errors can be handled by using static redundancy methods like hardware, information and time redundancy. This report discusses fault tolerance techniques for nanoscale structures. It begins with a study of phenomena that the move towards nano introduces. A gategorization for fault types is presented and the different impacts of scaling into nano regime are connected to these types. Later in the report a number of fault tolerance techniques are examined and their suitability for nanoscale circuits and systems is evaluated. Each technique is connected to one or several fault types according to their properties for fault tolerance perspective. Finally it is concluded that no single technique is enough for tolerating all the types of faults in nanosacle circuits and systems. Therefore a combination of two or more techniques is needed. The optimal mixture is design specific according to its usage purpose and proneness to different defect sources.

Synchronous Design Aspects Using Action Systems

The action systems framework has recently been applied to the area of synchronous VLSI design. In... more The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchronous hardware, using synchronous action systems. These explicitly model synchronous two-phase behavior. They are developed using the re nement calculus in a usual manner. The fundamental idea of synchronous action systems is to make a formal description transparent in the sense that its hardware implementation can be obtained by direct mapping. The presented design methodology also allows a postponed decision on the nal implementation aspects regarding the architecture (synchronous / asynchronous)

A novel hardware acceleration scheme for java method calls

2008 Ieee International Symposium on Circuits and Systems, May 18, 2008

Abstract This paper presents a novel strategy for accelerating the method calls in the REALJava c... more Abstract This paper presents a novel strategy for accelerating the method calls in the REALJava co-processor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is realized as an FPGA prototype. It allows measurements of real life performance increase, and validates the concept. The system is intended to be used in embedded environments, limiting the CPU performance and memory available to the virtual machine. The co-processor is designed ...

Hierarchical Agent-Based Architecture for Resource Management in Cloud Data Centers

2014 Ieee 7th International Conference on Cloud Computing, Jun 1, 2014

ABSTRACT In order to resource management in a large-scale data center, we present a hierarchical ... more ABSTRACT In order to resource management in a large-scale data center, we present a hierarchical agent-based architecture. In this architecture, multi agents cooperate together to minimize the number of active physical machines according to the current resource requirements. We proposed a local agent in each physical machine (PM) to determine the PM’s status and a global agent to optimizes VM placement based on PM’s status. Experimental results show the proposed architecture can minimize energy consumption while maintaining an acceptable QoS.

Toward Self-Placing Applications on 2D and 3D NoCs

Embedded Multi-Core Systems, 2011

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015

Power management of NoC-based manycore systems with runtime application mapping becomes more chal... more Power management of NoC-based manycore systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on network-on-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.

Formal Power Analysis of On-Chip Communication

MD: Minimal path-based fault-tolerant routing in on-Chip Networks

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 Inte... more

Fault Tolerance Analysis of Distributed Algorithms for Mesh Networks-on-Chip

Introducing Action Systems Class Hierarchy to SystemC Modelling

Abstract ActionC is an integration of SystemC, an informal design language for embedded systems, ... more Abstract ActionC is an integration of SystemC, an informal design language for embedded systems, and Action Systems, a formal modelling language that supports verifica- tion and stepwise correctness-preserving refinement of sys tem models. In the Ac- tionC approach Action Systems sets a formal foundation for SystemC modelling providing a possibility to verify the design as early as duri ng the construction of the first transaction level model. This report provides an im plementation for the ActionC language structures that concern Action Systems type system verifica- tion with invariants. The implementation,introduced here will be a part of a larger modelling framework,that will be elaborated in the future. Keywords: SystemC, Action Systems, ActionC, Formal methods, System mod-

Dark Silicon and Congestion Aware Power Management for Manycore Systems under Dynamic Workloads

Distributed BIST Approach for Power Constrained Many-Core Systems

—Dark Silicon is a phenomenon where a large portion of a chip&#39;s silicon area must remain ... more —Dark Silicon is a phenomenon where a large portion of a chip&#39;s silicon area must remain mostly passive to stay within the chip&#39;s power budget due to the thermal and power delivery issues. On the other hand, by reducing the transistor size, susceptibility to internal defects increases and large range of defects such as aging or transient faults will be more frequently shown up. In this paper, a dark silicon aware distributed built-in-self-test (BIST) approach for many-core systems is presented. The approach also benefits from dynamic voltage and frequency scaling in the online BIST process to maximize the number of tested cores with a negligible negative impact on the system performance.