Effect of oxide breakdown on RS latches

Microelectronics Reliability 47 (2007) 581–584 www.elsevier.com/locate/microrel Effect of oxide breakdown on RS latches R. Fernández a a,b,* , R. Rodrı́guez a, M. Nafrı́a a, X. Aymerich a Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain b Departament d’Educació Generalitat de Catalunya, IES Castellarnau, 08206 Sabadell, Spain Available online 20 February 2007 Abstract In this work, the influence of the oxide breakdown on RS latches performance has been analysed. The NAND and NOR RS latch topologies have been compared in terms of noise margin and switching times for different broken down transistors. Moreover, the influence of the additional current path due to BD and of the variation of the MOSFET parameters on the circuit functionality have been separately evaluated. The results show that RS latches do not lose functionality after BD. However, reductions on noise margin and variations on switching times are observed, which depend on the damaged transistor. The performance degradation of the circuit is mainly due to the additional post-BD gate current whereas the variation of the BD MOSFET parameters has only a small influence. Ó 2007 Elsevier Ltd. All rights reserved. 1. Introduction The impact of dielectric breakdown (BD) on MOS devices and circuits is one of the most critical issues of present CMOS reliability that can limit the IC dimensions reduction. Regarding to this problem, some authors have claimed for a relaxation of the dielectric reliability specifications, showing that even after BD certain digital circuits can still remain functional [1,2]. In order to clarify the problem, further analysis of the dielectric breakdown effect on the circuit performance must be done. In this sense, an accurate description of the post-BD device behaviour, which could be included in circuit simulators, is needed. At device level, it has been shown that BD not only has associated an additional current through the gate but also a variation of the MOSFET SPICE parameters [3]. However, generally, when studying the circuit reliability, only the BD gate current is considered. In this work, the impact of each of these BD effects on the post-BD functionality of simple digital circuits is analysed. As an example, basic RS latches have been studied, since they are key components of * Corresponding author. Address: Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain. Tel.: +34 93 581 4803; fax: +34 93 581 26 00. E-mail address: Raul.Fernandez@uab.es (R. Fernández). 0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.01.021 frequency dividers, which are becoming very interesting for RF applications [4]. To perform this analysis, the experimental broken down transistor output characteristics have been modeled and included in a circuit simulator. Noise margin and switching times in two different topologies of RS latches, NAND and NOR RS, have been studied. 2. Experimental The samples used in this work were nMOSFETs fabricated with 1.5 V bulk technology, SiON as gate dielectric (EOT of 1.6 nm) and draw aspect ratio 350 nm/130 nm. Constant voltage stresses (3 V) were applied to the gate with the other terminals grounded to provoke oxide hard breakdown (HBD). For the considered samples, the similar ID an IG currents as a function of the gate voltage (inset of Fig. 1) shows that BD has been produced close to the drain [5]. For the studied circuits (Fig. 3), this case would be the worst one, since for breakdown close to the source in most of the cases, the additional current through the gate would flow to ground, having little influence in the circuit performance. The experimental broken down transistor output characteristics have been described using a model that separately considers the additional BD gate current and the variation of the MOSFET SPICE parameters. In this description, BSIM4 model is combined with a network of 582 R. Fernández et al. / Microelectronics Reliability 47 (2007) 581–584 200 HBD 200 180 150 160 140 100 120 80 50 ID (uA) 1E-3 D I uA 100 0 abs(I) (A) 1E-4 -50 1E-5 40 20 0 1E-6 IGHBD IDHBD ISHBD modellDHBD modelISHBD 1E-7 1E-8 1E-9 -1.5 60 -1.0 -0.5 0.0 0.5 1.0 1.5 -100 V (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1G 1.2 1.3 1.4 1.5 V (V) D -20 -40 -60 -80 -100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VDS (V) Fig. 1. Experimental ID–VDS characteristics (symbols) and fittings (continuous lines) for fresh (top curves) and HBD MOSFETs (bottom curves) for VG = 1.20 V, 1.35 V, 1.5 V. Inset: Post-BD currents in all the device terminals vs VG. These curves show that the HBD path is located close to the drain. diodes and resistances [6] to account for all the BD effects in the post-BD ID–VD curves. Fresh and damaged transistor SPICE parameters have been extracted with Aurora software [7] and included in a circuit simulator to observe the influence of oxide HBD on RS latch functionality. Fig. 2. Experimental ID–VD curves measured before BD (up triangles) and after BD (down triangles). The fittings of the curves are shown in dotted lines. Calculated post-BD ID–VD curves when only the variation of BSIM4 parameters (open squares) or the BD gate current (open circles) is considered. The gate voltage was 1.5 V in all cases. The BSIM parameters extracted from these curves are used for the simulations shown in Figs. 4 and 6. Table 1 Summary of the four cases simulated to separately evaluate the influence of the BD gate current and the BSIM parameter variation in the degradation of the latch performance 3. Results ID–VDS characteristics of the transistors for different gate voltages (VG) have been measured before and after HBD. Typical curves measured on the devices are shown in Fig. 1 (symbols). After BD, negative values of the ID current for very low VDS voltages and a decrease of the saturation current due to oxide damage are observed [8]. To fit the experimental data both the BD gate current and the variation of the MOSFET parameters must be considered [3]. Continuous lines in Fig. 1 show these fittings. The impact of the BD gate current and the variation of MOSFET parameters on the measured post-BD ID–VD curves is shown in Fig. 2 for VG = 1.5 V . The experimental ID–VD curves measured on fresh and on BD MOSFET have been plotted using up and down triangles, respectively. The BSIM4 model has been used to fit the fresh curves (dotted line). As indicated before, to describe the experimental post-BD ID–VD curves (down triangles), BSIM4 model and the contribution of the post-BD IG to ID (inset in Fig. 1) are needed (dotted line). The post-BD BSIM4 model parameters are obtained from the ID–VG and ID–VD curves, once the contribution to ID of the BD gate current has been subtracted (open squared line). This curve will be used to get the BSIM parameters of case D in Table 1. When only the additional current due to BD is considered (i.e., the post-BD BSIM parameters variations is neglected), the open circles curve in Fig. 2 is obtained Fresh BSIM parameters Post-BD BSIM parameters Without additional BD current With additional BD current A D B C BD was considered in transistor M3, for NAND and NOR topologies. (this curve will be used to study case B in Table 1). Note that it is not enough to consider the BD gate current to reproduce the experimental post-BD device behavior. The contribution of the BD gate current to ID current is considered by adding a network of diodes and resistances connected between gate and drain (since only drain BD is considered in this work) whose values are obtained from the post-BD ID–VG curves (inset in Fig. 1). To analyse the impact of a drain HBD nMOSFET in the performance of a RS latch, the post-BD MOSFET model has been included in a circuit simulator. NOR and NAND topologies (Fig. 3) have been considered and compared. Additionally, the BD gate current and the variation of the MOSFET parameters have been separately considered. For PMOS devices, the fresh BSIM parameters have been used for all the simulations. Fig. 4 (middle) shows the NAND RS latch response considering different broken down transistors, for all allowed Reset and Set combinations (Fig. 4 top). Both BD gate current and variation of BSIM4 parameters are simultaneously considered. Differences in the outputs, depending on the broken down transistor (M1, M2, M3 583 R. Fernández et al. / Microelectronics Reliability 47 (2007) 581–584 VCC /Out P1 /R Out P2 P3 M1 P4 /S M3 M2 M4 Q+ Q 1 0 - S 0 1 0 1 VCC P1 P3 /Out Out P2 R M1 P4 M2 M3 M4 S Fig. 3. Schematics of RS latches based on NAND gates (top) and NOR gates (bottom). Logic 1 (0) corresponds to 1.5 V (0 V). Additional capacitances of 100 fF have been also included in order to consider load effects. Input (V) 1.6 R S 1.2 0.8 0.4 NOR Output (V) NAND Output (V) 0.0 1.6 1.2 0.8 0.4 0.0 1.6 1000 1.2 800 0.8 Fresh M1 M2 M3 M4 0.4 0.0 0 20 40 60 80 time (ns) Fig. 4. Responses of the RS latches based on NAND gates (middle) and NOR gates (bottom). BD gate current and variation of the BSIM4 parameters are considered. The input signal is shown in the top figure. tpLHNAND tpHLNAND tpLHNOR tpHLNOR 600 400 delay ps R 0 0 1 1 mainly during the storage stage, is produced. Moreover, if HBD takes place in transistor M3 (down triangles) or M4 (diamonds) the low level increases to 0.6 V and 0.4 V, respectively, and no remarkable variations are produced on the high state. However, in any case the latch loses the functionality. For NOR RS (Fig. 4 bottom), the low level is less affected after HBD than in the NAND latch case. In the worst case, oxide HBD in transistor M2 (up triangles) during the storage stage (R = S = 0), values of 0.4 V are obtained for the low output. However, the output high level for NOR topology is much affected than for the NAND one. A 0.2 V reduction of the high level, when the latch is storing, is observed in case of HBD on transistor M1 (circles), M2 (up triangles) or M3 (down triangles). Therefore, concerning the noise margin, NOR structure is more robust than NAND one. On the other hand, it is interesting to observe, from Fig. 4 results, that the low to high (tpLH) and high to low (tpHL) switching times of the RS latch are also affected by BD. Fig. 5 shows the increment of tpLH and tpHL, with respect to the fresh latch, depending on the broken down MOSFET and latch structure. In case of NAND structure the delay times are reduced in hundreds of picoseconds for all broken down MOSFET, except for tpHL on transistor M3 or M4. However, for NOR structure the swithching times increase in case of HBD on M1 or M4 and decrease in case of M2 or M3. The variation of these times can be attributed to the additional current path due to HBD, which supplies current to the load capacitance during tpLH and helps to discharge the capacitance for tpHL. Figs. 4 and 5 show a degradation of the RS latches performance after BD. In order to clarify which of the BD device effects (additional gate current or variation of the MOSFET parameters) produce this performance variation, both latches topologies have been simulated in case of BD on transistor M3 (which is one of the worst cases in both topologies). Four different cases have been simulated: fresh device (case A), fresh BSIM parameters plus additional 200 0 -200 -400 -600 -800 and M4) can be observed. If the damaged transistor is M1 (circles), only a small reduction of the high level output, when the latch is storing (R = S = 0), is observed. In case of oxide HBD in M2 (up triangles), an increase of the low level output and a reduction on high level output, M1 M2 M3 M4 BD MOSFET Fig. 5. Switching times variation after BD for different BD MOSFET and different RS latch topologies. 584 R. Fernández et al. / Microelectronics Reliability 47 (2007) 581–584 Input (V) 1.6 1.2 0.8 R S 0.4 NOR Output (V) NAND Output (V) 0.0 1.6 1.2 0.8 0.4 0.0 4. Conclusions 1.6 The effects of BD on RS latch have been analyzed taking into account the RS structure, the broken down MOSFET and the different effects that the BD has on MOSFET (additional current and SPICE parameter variation). The results show that after BD the RS latches do not lose their functionality. However, depending on the broken down transistor and the latch structure the noise margin and switching times of the latch are affected. In terms of noise margin, NOR structure appears more robust to BD. The switching time variation depends on the damaged transistor but NAND structure seems to be more robust to BD. Moreover, the degradation of the RS latch performance is mainly due to the additional BD gate current, whereas the MOSFET parameter variation after BD has only a small effect in the behavior of these digital circuits. 1.2 case A case B case C case D 0.8 0.4 0.0 0 20 40 60 80 time (ns) Fig. 6. Responses of the NAND (middle) and NOR (bottom) RS latches, when the additional current path and the MOSFET parameters variation after BD are separately considered (see text). current due to BD (case B), post-BD BSIM parameters plus additional BD current (case C) and only post-BD BSIM parameters (case D), which are resumed in Table 1. The BSIM parameters for each of these cases have been extracted from the curves shown in Fig. 2. Fig. 6 shows the simulation results for the four considered cases (Table 1) for all possible input combinations (Fig. 6 top). In case of NAND topology (Fig. 6 middle), for cases A (fresh device) and D (only BSIM parameters variation) the latch shows a similar behaviour. On the other hand, the latch performance for cases B and C is also similar, but a 0.15 V better noise margin is obtained for case B. The NOR simulation (Fig. 6 bottom) shows similar tendencies, although in this topology the outputs for cases B and C are practically identical. Fig. 7 shows the variation of the switching times in cases B to D from those measured in case 1000 800 600 delta tp (ps) 400 200 0 Case B Case C Case D -200 -400 -600 A (fresh device). Note that only one of the considered times (tpHL for the NAND topology) changes when the gate current is ommited (case D) whereas all of them suffer important modifications when the gate current is included in the simulations (cases B and C). The results in Figs. 6 and 7 indicate that, for RS latches, the main effect that affects the circuit behaviour is the additional gate current due to breakdown and that the MOSFET parameters variation has a negligible effect on the post-BD latch performance. tpLHNAND tpHLNAND tpLHNOR tpHLNOR -800 Fig. 7. Switching times variation (from the fresh device case) for NAND and NOR topologies when the additional BD gate current and/or the BD MOSFET parameters variation are considered. Acknowledgements The authors would like to thank to Javier Martı́n Martı́nez for the extraction of BSIM4 parameters and to IMEC for sample provision. Also to the Spanish MEC (project TEC2004-00798), to DURSI of the Generalitat de Catalunya (2005SGR-00061) and to European Commission (Marie Curie Actions, APROTHIN Project). References [1] Rodrı́guez R, Stathis JH, Linder BP, Kowalczyk S, Chuang CT, Joshi RV, et al. The impact of gate oxide breakdown on SRAM stability. IEEE EDL 2002;23(9):559–61. [2] Kaczer B, Degraeve R, Rasras M, de Mieroop KV, Roussel PJ, Groeseneken G. Impact MOSFET gate oxide breakdown on digital circuit operation and reliability. IEEE TED 2002;49(3):500–6. [3] Fernández R, Rodrı́guez R, Nafrı́a M, Aymerich X. DC BD MOSFET model for circuit reliability simulation. EL 2005;41(6):368–70. [4] Boon CC, Do MA, Yeo KS, Ma JG. Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. 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