SISTEM DIGITAL

Konversi Antar Sistem Bilangan

Desimal ke Biner

Setiap unit bilangan biner merupakan kelipatan 2.

n

……. 2 6 2 5 2 4 2 3 2 2 2 1 2 0

Untuk melakukan konversi bilangan decimal ke biner dapat dilakukan dengan cara sebagai berikut .

Contoh : 25 desimal

Operasi Penjumlahan

Ada beberapa hal umum yang harus diketahui dalam penjumlahan bilangan biner yaitu sebagai berikut :

Contoh penjumlahan dalam bilangan biner

Bilangan Bertanda

Sebagian besar komputer digital menangani bilangan negative sebagai bilangan positif, sehinga diperlukan sign (tanda) bilangan + atau -. Tanda tersebut diwakili oleh satu bit yang disebut sebagai sign bit. Dimana 0 merupakan tanda positif dan 1 merupakan tanda negative. Bit tanda ini menempati posisi bit paling kiri atau pada bagian MSB seperti pada gambar 2.1 dibawah.

Gambar 2.1 Bilangan bertanda 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10  0 + carry 1 ditempatkan pada posisi berikutnya 1 + 1 + 1 = 11  1 + carry 1 ditempatkan pada posisi berikutnya

Case V: Equal and Opposite Numbers

Contoh : +9 dan -9

Langkah 1 : mencari nilai complemen 2 dari -9 +9 1 0 0 1 C'1 0 1 1 0 1 C'2 0 1 1 1

TABEL KEBENARAN

Tabel kebenaran merupakan gambaran bagaimana sebuah output dari rangkaian logika bergantung kepada logic level yang ada pada rangkaian inputnya, Tabel kebenaran ini berisi kombinasi dari logic level yang ada pada input. untuk jumlah kombinasi input adalah 2 n .

Untuk 2 input maka kombinasinya adalah 2 n = 2 2 yaitu 4 kombinasi input.

Tabel Kebenaran 2 input Tabel Kebenaran 3 input

SUM-OF-PRODUCTS FORM

Metoda penyederhanaan rangkaian logika salah satunya adalah SOP (sum of products).

Contoh:

Setiap pernyataan dalam bentuk sum of products terdiri dari dua atau lebih operasi AND yang semuanya di OR kan.

PRODUCTS OF SUM FORM

Bentuk persamaan logika juga menggunakan POS (products of sum). Terdiri dari 2 atau lebih operasi OR yang kemudian di AND kan.

ALGEBRAIC SIMPLIFICATION

Sebuah pernyataan Boolean dapat kita sederhanakan bentuknya dengan menggunakan banyak cara, pernyataan yang baru digunakan untuk mengimplementasikan sebuah rangkaian yang sama dengan rangkaian asli, tetapi memiliki gerbang dan koneksi yang lebih sedikit.

Contoh

Hasil penyederhanaan

NAND GATE LATCH

Rangkaian dasar FF dapat dibangun dari 2 gerbang NAND atau 2 gerbang NOR.

Versi gerbang NAND disebut sebagai NAND gate latch atau secara sederhana latch (Gambar 6.3a). 2 gerbang NAND di cross-coupled sehingga output NAND-1 dihubungkan ke salah satu input dari NAND-2 dan sebaliknya. Output gerbang diberi label dan disebut dengan latch out put. Pada kondisi normal, output akan selalu di invers dengan yang lain. Ada 2 latch input : SET input yaitu input set Q sama dengan state 1; RESET input akan resets Q ke 0 state.

Versi kedua gerbang NAND (Gambar 6.3b). , dimana 1 0. HIGH dari gerbang NAND-1 menghasilkan LOW pada output NAND-2, dan output NAND-1 tetap HIGH. Ada 2 kemungkinan output yaitu SET = RESET = 1.

Gambar 6.3 NAND Latch Simbol

CLOCK SIGNALS AND CLOCKED FLIP-FLOPS

System digital dapat beroperasi secara asinkron atau sinkron. Pada system asinkron, output rangkaian logika dapat merubah state setiap saat satu atau lebih input berubah. Pada system sinkron, waktu setiap output dapat merubah state ditentukan oleh sebuah sinyal yang disebut dengan clock. Sinyal clock merupakan sebuah pulsa segiempat seperti pada Gambar 6.7 berikut.

Gambar 6.7 Sinyal Clock

Sinyal clock didistribusikan ke semua bagian system, dan sebagian (if not all) output system dapat merubah state hanya pada saat clock membuat transisi. Transisi disebut sebagai edges.

Pada saat clock berubah dari 0 ke 1, maka disebut sebagai positive-going transition (PGT); pada saat clock berubah dari 1 ke 0, maka disebut sebagai negative-going transition (NGT).

Sebagiian system digital merupakan sinkron karena rangkaian sinkron lebih mudah untuk melakukan perancangan dan troubleshoot. Hal ini disebabkan rangkaian output dapat berubah hanya pada waktu spesifik atau disinkronkan dengan transisi clock-signal.

Sinkronisasi dari sinyal clock juga digunakan pada clocked flip-flops yang digunakan untuk merubah states pada satu atau lebih clock's transitions.

T FLIP FLOP

The T type flip-flop is a single input device: T (trigger). Two outputs: Q and Q' (where Q' is the inverse of Q).

The operation of the T type flip-flop is as follows: A '0' input to 'T' will make the next state the same as the present state (i.e. T = 0 present state = 0 therefore next state = 0). However a '1' input to 'T' will change the next state to the inverse of the present state (i.e. T = 1 present state = 0 therefore next state = 1).

Knowing the above, we can now formalise the operating characteristics and the state change

JK FLIP FLOP

The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are again two outputs Q and Q' (where Q' is the reverse of Q).

A. When J=K=0, the current output will carry through to the next state. e.g. Current state Q = Next state Q B. When J=0 and K=1, the next state output will be put to 0. This happens regardless of the present state output.

C. When J=1 and K=0, the next state output will be asserted (put to 1). This happens regardless of the present state output.

D. When J=K=1, the next state output will be the inverse of the current state output. e.g.

Current state Q' = Next state Q.

Knowing the above we can now construct the state change There actually exists two operating characteristics that satisfy every possible output combination. This means there should be some 'don't care' terms with each output combination (as our diagram shows). In the list below we shall see how each of the terms i. Two conditions exist so that the next state is 0 while the present state is also 0. From the operating characteristics diagram, we can see that condition A and B would both satisfy this scenerio. The common term to make this scenerio true is J=0. We dont care about K, as K=1 or K=0 while J=0 will work. Hence the 'don't care' term is K,

ii.

Operating characteristics C and D both satisfy this scenerio. The common term is again J, as the situation is solved by J=1 and either K=0 or K=1, therefore the 'don't care' term is K as shown on the state change table.

iii. When the output goes from 1 to 0, there are two characteristics that will allow this to happen; B and D. K=1 and J can be equal to 1 or 0. Therefore in this case, J is the 'don't care' term.

iv.

When the JK flip-flop remains at logic, it means that either A or C of the four operating characteristics have been applied. K must equal 0 in either case, but J could have been equal to 1 (A) or 0 (C). Because of this, J is the 'don't care' term.

The

Paralel data Transfer

Terdiri dari serangkaian memori 1 bit yang dapat ditulis atau dibaca secara bersamaan.

Digunakan untuk menyimpan data.

ALU

All arithmetic operations take place in the arithmetic/logic unit (ALU) of a computer. Figure 9-1 is a block diagram showing the major elements included in a typical ALU. The main purpose of the ALU is to accept binary data that are stored in the memory and to execute arithmetic and logic operations on these data according to instructions from the control unit. 1. The control unit receives an instruction (from the memory unit) specifying that a number stored in a particular memory location (address) is to be added to the number presently stored in the accumulator register.

2. The number to be added is transferred from memory to the B register.

3. The number in the B register and the number in the accumulator register are added together in the logic circuits (upon command from the control unit).The resulting sum is then sent to the accumulator to be stored.

Aritmatika Biner

Operasi aritmatika binari, merupakan operasi aritmatika yang melandasi tentang proses aritmatika dan logika pada sistem digital dan komputer modern. Namun pada kenyataannya, operasi aritmatika tersebut tidak dapat diwakili oleh operasi yang terdapat pada gerbang dasar, walaupun secara prinsipnya, tiap-tiap gerbang mewakili satu operasi aritmatika, terutama adalah operasi-operasi dasar penjumlahan dan pengurangan.

Contoh :

Pada saat kita akan menjumlahkan dua bilangan biner 1+1, bila diwakilkan dengan operasi penjumlahan pada Gerbang OR, akan menghasilkan keluaran yang berbeda dengan hasil operasi aritmatika yang sesungguhnya, dimana jika diperasikan dengan Gerbang OR, akan diperoleh keluaran 1 2 +1 2 = 1 2 , sedangkan pada operasi aritmatika idealnya output yang diperoleh adalah 1+1 = 10 2 , bagaimana mengimplementasikan operasi ini pada sistem komputer digital ? Maka untuk menjawab pertanyaan ini dibutuhkan sebuah rangkaian aritmatika yang dapat mewakili operasi aritmatika yang sesungguhnya.

Operasi penjumlahan aritmatika :

Pusat Bahan Ajar dan eLearning Tim Dosen http://www.mercubuana.ac.id

Rangkaian Penjumlah Tak lengkap (Half Adder)

Penjumlah tak lengkap (half adder) menjumlahkan 2 angka biner pada satu operasi, yang akan menghasilkan keluaran dua digit biner, yaitu biner hasil jumlah dan biner limpahan.

Rangkaian half adder (HA) ini mewakili operasi aritmatika penjumlahan dua bilangan biner, yang tidak bisa diwakili oleh operasi penjumlahan dengan gerbang OR. Sebuah HA, dapat digambarkan fungsinya seperti pada Gambar 9.2 berikut :

Gambar 9.2 Block Diagram, rangkaian dan table kebenaran half Adder Untuk melakukan operasi penjumlahan dengan HA ini, diwakili oleh dua buah gerbang logika, yaitu gerbang EXOR dan AND, dengan bentuk rangkaian seperti pada Gambar 9. Sehingga dengan rangkaian HA ini, kita dapat melakukan operasi penjumlahan biner dengan rangkaian logika, sehingga dengan demikian, akan dapat kita peroleh : 0+0 = 0, 0+1 = 1, 1+0=1 dan 1+1 = 10.

Kekurangan

Penjumlahan dengan HA ini hanya dapat melakukan operasi penjumlahan dua biner terhadap LSB (least significant binary)-nya saja, tetapi untuk nilai biner yang lebih berbobot, rangkaian ini tidak dapat melakukannya.

Rangkaian Penjumlah Lengkap (Full Adder)

Kelemahan yang dimiliki oleh rangkaian penjumlah tak penuh (HA), yang hanya dapat melakukan operasi penjumlahn terhadap 2 bilangan biner pada sisi LSB, diatasi dengan membangun rangkaian penjumlah yang lebih lengkap yang disebut dengan rangkaian penjumlah lengkap (Full Adder).

Rangkaian Full Adder (FA), merupakan sebuah rangkaian penjumlah yang mempunyai tiga input, termasuk masukan bawaan (input carry) dan menghasilkan keluaran hasil jumlah (sum) dan hasil bawaan (output carry).

Dalam menjumlahkan dua bilangan biner, mungkin terdapat bawaan dari satu kolom ke kolom berikutnya, contoh :

n-bit Carry Ripple Adder

An n-bit adder used to add two n-bit binary numbers can be built by connecting n full adders in series. Each full adder represents a bit position j (from 0 to n-1).

Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at higher position j+1. The output of a full adder at position j is given by: Sj=

Xj

Yj Cj

Cj+1 = Xj . Yj + Xj . Cj + Y . Cj

In the expression of the sum Cj must be generated by the full adder at lower position j. The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately:

Total Propagation delay = 2 nD

4-bit Carry Ripple Adder

Adds two 4-bit numbers:

producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3

Total Propagation delay = 2 nD = 8D or 8 gate delays

Larger Adder

Example: 16-bit adder using 4 4-bit adders. Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from the most The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that are added because the carry signals have to propagate from one full-adder to the next. For large values of N, the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate the calculation of the carry bits. This solution involves a "look-ahead carry generator" which is a block that simultaneously calculates all the carry bits involved. Once these bits are available to the rest of the circuit, each individual three-bit addition (X i +Y i +carry-in i ) is implemented by a simple 3-input XOR gate. The design of the look-ahead carry generator involves two Boolean functions named Generate and Propagate.

For each input bits pair these functions are defined as:

The carry bit c-out(i) generated when adding two bits Xi and Yi is '1' if the corresponding function Gi is '1' or if the c-out(i-1)='1' and the function Pi = '1' simultaneously. In the first case, the carry bit is activated by the local conditions (the values of Xi and Yi). In the second, the carry bit is received from the less significant elementary addition and is propagated further to the more significant elementary addition. Therefore, the carry_out bit corresponding to a pair of bits Xi and Yi is calculated according to the equation:

For a four-bit adder the carry-outs are calculated as follows carry_out0 = G 0 + P 0 . carry_in 0 carry_out1 = G 1 + P 1 . carry_out 0 = G 1 + P 1 G 0 + P 1 P 0 . carry_in 0 carry_out2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 . carry_in 0 carry_out3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 . carry_in 0

The set of equations above are implemented by the circuit below and a complete adder with a look-ahead carry generator is next. The input signals need to propagate through a maximum of 4 logic gate in such an adder as opposed to 8 and 12 logic gates in its counterparts illustrated earlier. sum_out 0 = X 0 Y 0 carry_out 0 sum_out 1 = X 1 Y 1 carry_out 1 sum_out 2 = X 2 Y 2 carry_out 2 sum_out 3 = X 3 Y 3 carry_out 3

BCD Adder

BCD addition is the same as binary addition with a bit of variation: whenever a sum is greater than 1001, it is not a valid BCD number, so we add 0110 to it, to do the correction.

This will produce a carry, which is added to the next BCD position.

 Add the two 4-bit BCD code inputs. A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD decoders.

Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word.

Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Figure below shows the pseudo block of a decoder

Basic Binary Decoder

AND gate can be used as the basic decoding element, because its output is HIGH only when all its inputs are HIGH. For example, if the input binary number is 0110, then, to make all the inputs to the AND gate HIGH, the two outer bits must be inverted using two inverters as shown in figure below

Binary n-to-2 n Decoders

A binary decoder has n inputs and 2 n outputs. Only one output is active at any one time, corresponding to the input value. Figure below shows a representation of Binary n-to-2 n decoder

Example -2-to-4 Binary Decoder

A 2 to 4 decoder consists of two inputs and four outputs, truth table and symbols of which is shown below.

Truth Table X To minimize the above truth table we may use kmap, but doing that you will realize that it is a waste of time. One can directly write down the function for each of the outputs. Thus we can draw the circuit as shown in figure below.

Note: Each output is a 2-variable minterm (X'Y', X'Y, XY', XY)

Circuit

Contoh 3-8 binary decoder

A 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of which is shown below.

Truth Table X Y Z F0 F1 F2 F3 F4 F5 F6

Implementing Functions Using Decoders

 Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2 n decoder to generate the minterms, and an OR gate to form the sum.

o The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.

 Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates.

 Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

Example -Full adder

Equation

S(x, y, z) = (1,2,4,7)

C(x, y, z) = (3,5,6,7)

Truth Table X An encoder is a combinational circuit that performs the inverse operation of a decoder. If a device output code has fewer bits than the input code has, the device is usually called an encoder. e.g. 2 n -to-n, priority encoders.

The simplest encoder is a 2 n -to-n binary encoder, where it has only one of 2 n inputs = 1 and the output is the n-bit binary number corresponding to the active input.

Example -Octal-to-Binary Encoder

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3to-8 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of an Octal-to-binary encoder.

Truth Table I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:

Based on the above equations, we can draw the circuit as shown below

Example -Decimal-to-Binary Encoder

Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what the 4-to-10 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of a Decimal-to-binary encoder.

Truth Table I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1

Priority Encoder

If we look carefully at the Encoder circuits that we got, we see the following limitations. If more then two inputs are active simultaneously, the output is unpredictable or rather it is not what we expect it to be.

This ambiguity is resolved if priority is established so that only one input is encoded, no matter how many inputs are active at a given point of time.

The priority encoder includes a priority function. The operation of the priority encoder is such that if two or more inputs are active at the same time, the input having the highest priority will take precedence.

Example -4to3 Priority Encoder

The truth table of a 4-input priority encoder is as shown below. The input D3 has the highest priority, D2 has next highest priority, D0 has the lowest priority. This means output Y2 and Y1 are 0 only when none of the inputs D1, D2, D3 are high and only D0 is high.

A 4 to 3 encoder consists of four inputs and three outputs, truth table and symbols of which is shown below.

Truth

Now that we have the truth table, we can draw the Kmaps as shown below.

Kmaps

From the Kmap we can draw the circuit as shown below. For Y2, we connect directly to D3.

We can apply the same logic to get higher order priority encoders. MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs controls the input source that will be switched on to the output as shown in the figure below. At any given point of time only one input gets selected and is connected to output, based on the select input signal.

Mechanical Equivalent of a Multiplexer

The operation of a multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the inputs, which is connected to the output. As you can see at any given point of time only one input gets transferred to output.

Example -2x1 MUX

Design of a 2:1 Mux

To derive the gate level implementation of 2:1 mux we need to have truth table as shown in figure. And once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is equal to '1'.

Combining the two 1' as shown in figure, we can drive the output y as shown below Y = A.S' + B.S Table B

Demultiplexers

They are digital switches which connect data from one input source to one of n outputs.

Usually implemented by using n-to-2 n binary decoders where the decoder enable line is used for data input of the de-multiplexer.

The figure below shows a de-multiplexer block diagram which has got s-bits-wide select input, one b-bits-wide data input and n b-bits-wide outputs.

Mechanical Equivalent of a De-Multiplexer

The operation of a de-multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the outputs, which

COMPARATOR

Comparators can compare either a variable number X (xn xn-1 ... x3 x2 x1) with a predefined constant C (cn cn-1 ... c3 c2 c1) or two variable numbers X and Y. In the first case the implementation reduces to a series of cascaded AND and OR logic gates. If the comparator answers the question 'X>C?' then its hardware implementation is designed according to the following rules:

 The number X has two types of binary figures: bits corresponding to '1' in the predefined constant and bits corresponding to '0' in the predefined constant.

 The bits of the number X corresponding to '1' are supplied to AND gates  The bits corresponding to '0' are supplied to OR logic gates  If the least significant bits of the predefined constant are '10' then bit X0 is supplied to the same AND gate as bit X1.

If the least significant bits of the constant are all '1' then the corresponding bits of the number X are not included in the hardware implementation. All other relations between X and C can be transformed in equivalent ones that use the operator '>' and the NOT logic operator as shown in the table below. The comparison process of two positive numbers X and Y is performed in a bit-by-bit manner starting with the most significant bit:

Initial relationship to be tested

 If the most significant bits are Xn='1' and Yn='0' then number X is larger than Y.

 If Xn='0' and Yn='1' then number X is smaller than Y.

 If Xn=Yn then no decision can be taken about X and Y based only on these two bits.

If the most significant bits are equal then the result of the comparison is determined by the less significant bits Xn-1 and Yn-1. If these bits are equal as well, the process continues with the next pair of bits. If all bits are equal then the two numbers are equal.

MULTIPLIER

Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier. An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n-bit adders where each adder is shifted by one position. For each adder one input is the shifted multiplicand multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits.

Dividers

The

Full Subtracter

A full subtracter is a combinational circuit that performs subtraction involving three bits, namely minuend, subtrahend, and borrow-in. The logic symbol and truth table are shown below.

Symbol

Truth Table X From the above expression, we can draw the circuit below. If you look carefully, you will see that a full-subtracter circuit is more or less same as a full-adder with slight modification.

Parallel Binary Subtracter

Parallel binary subtracter can be implemented by cascading several full-subtracters.

Implementation and associated problems are those of a parallel binary adder, seen before in parallel binary adder section.

Below is the block level representation of a 4-bit parallel binary subtracter, which subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit difference output D3D2D1D0 with borrow output Bout.

Serial Binary Subtracter

A serial subtracter can be obtained by converting the serial adder using the 2's complement system. The subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend stored in the X register.

The circuit for a 4-bit serial subtracter using full-adder is shown in the figure below. Table table fungsi. Keuntungan dari ROM adalah data atau program permanen didalam main memory dan tidak perlu di load dari sebuah perangkat pernyimpanan eksternal. ROM merupakan sebuah chip dengan rangaian terintegrasi, dimana data dialirkan ke chip sebagai bagian dari proses pabrikasi. Ada 2 masalah terkait hal ini :

1. Langkah untuk memasukkan data memerlukan biaya besar.

2. Tidak boleh ada error, jika satu bit salah, maka keseluruhan proses ROM harus diulang.

Programmable ROM

PROM bersifat nonvolatile dan hanya ditulis satu kali. Proses penulisan dilakukan secara eletrik dan dapat dilakukan oleh supplier atau pelanggan pada waktu berikutnya selain dari chip yang asli pabrik. Diperlukan sebuah perangkan khusus untuk proses menulis atau "programming". PROM lebih fleksibel dan nyaman.

Read Mostly Memory

Berfungsi untuk aplikasi dimana operasi read jauh lebih sering daripada operasi write, tetapi diperlukan penyimpanan yang bersifat nonvolatile. Ada 3 bentuk umum dari read mostly

ERROR CORRECTING

System memory semikonduktor merupakan subjek untuk terjadinya error. Error yang terjadi dikategorikan sebagai hard failure dan soft error.

Hard failure merupakan kerusakan fisik permanen sehingga cell memory tidak reliable menyimpan data karena menjadi stuck pada 0 atau 1 atau switch tak menentu antara 0 dan 1. Hard error dapat disebabkan oleh penyalahgunaaan, proses pabrikasi dan penggunaan.

Soft error merupakan kejadian kejadian yang menyebabkan perubahan isi salah satu atau banyak cell memory tanpa merusak memory. Error ini dapat disebabkan karena masalah sumber daya atau partikel alpha. Partikel ini merupakan hasil dari kerusakan radioaktif.

Sebagian besar system memory memiliki logic untuk mendeteksi dan mengoreksi error tersebut.

Hamming Code

Error correcting code paling sederhana adalah hamming code yang ditemukan oleh Richard

Hamming pada Bell Laboratories.

Tabel 6.2 , perbandingan jumlah cek bit dengan bit data CONTOH 8 bit data + 4 cek bit, total word adalah 12 data, sehingga posisi nya adalah sebagai berikut: 1. Memisahkan data dan cek bit untuk data yang baru di ambil 2. Melakukan proses perhitungan cek bit untuk data yang baru diambil 3. Melakukan proses perbandingan terhadap cek bit data yang tersimpan dan cek data yang baru dijemput dengan operasi X-OR Hasilnya adalah 0110 (6), maka bit posisi 6 error.