Coupling effects and channels separation in FinFETs

Solid-State Electronics 48 (2004) 535–542 www.elsevier.com/locate/sse Coupling effects and channels separation in FinFETs F. Dauge a,* a , J. Pretet a,c , S. Cristoloveanu a, A. Vandooren b, L. Mathew b, J. Jomaah a, B.-Y. Nguyen b IMEP (UMR CNRS/INPG/UJF), ENSERG BP 257, 38016 Grenoble Cedex 1, France b Motorola, Digital DNA Lab., 3501 Ed Bluestein Blvd, Austin, TX 78721, USA c STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France Received 27 May 2003; received in revised form 14 July 2003; accepted 18 September 2003 Abstract Double-gate devices are best candidates for the MOSFET scaling down to the deca-nanometer range. The motivation of this work is to investigate the coupling effects in FinFETs and to extract the carrier mobility in each of the four possible channels. The coupling of the lateral, front and back interfaces is analyzed based on experimental results in FinFETs with various geometries. The influence of the substrate bias on the front and lateral surface potentials is especially emphasized. The back-gate action is minimized in ultra-narrow fins. Finally, the transport properties at each interface are presented and compared. The electron and hole mobilities are significantly lower on the fin edges than at the top and bottom interfaces.
2003 Elsevier Ltd. All rights reserved. Keywords: SOI; MOSFETs; FinFETs; Mobility; SCEs 1. Introduction In order to achieve high performance circuits, CMOS is being pushed toward channel lengths down to 10 nm. Several technological approaches have been proposed to overcome the scaling limits imposed by fundamental aspects such as very high doping, inversion layer capacitance, low carrier mobility, etc. SOI technology with ultrathin body and multiple gate architectures is an attractive solution for down scaling [1]. The most promising transistor is the double-gate (DG) SOI MOSFET, which exhibits excellent performances and consistently outperforms single-gate devices [2,3]: near ideal subthreshold slope, high transconductance, minimized short-channel effects (drain-induced barrier lowering, fringing field, charge sharing). The complexity of the DG fabrication process, in particular the fabrication of the bottom gate and its * Corresponding author. Fax: +33-4-76856070. E-mail address: dauge@enserg.fr (F. Dauge). alignment with the top gate, is still a serious limitation for the industrial development of planar DG technology. To avoid this technological barrier, Hisamoto et al. introduced the Delta [4] and FinFET [4,5] structures with lateral gates. The FinFET technology is very attractive because the process flow is easier to implement with existing processing techniques. The technology consists of preparing a narrow silicon island (fin) by etching the silicon film. After the gate oxide growth, the polysilicon gate is then deposited in a single step, which naturally enables perfect self-alignment of the two lateral gates. In a FinFET, the gate actually covers the three sides of the body (Figs. 1 and 2): the top channel as well as the two lateral channels. The top channel is more or less deactivated, by using a thicker oxide or nitride [6], such as to focus on the lateral control of the channels. However the top-channel conduction can also be used to enhance the performance. For example, Intel proposed the ‘‘tri-gate transistor’’ which allows achieving 20% enhancement for the drain current [7]. The name is misleading because there is actually one gate 0038-1101/$ - see front matter
2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.09.033 536 F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 Section 3. Next, systematic measurements are presented which demonstrate that the front channel as well as the two lateral channels are modulated by the back gate. Reciprocally, we show that the back-channel characteristics are modulated by the top gate, enabling differed activation of the four channels. Basically, the transistor can be operated with two, three and even four active channels. The amount of volume inversion depends on the top gate and the substrate bias [8]. Finally, in Section 5, the contributions of the different channels in terms of carrier mobility are separated by deactivating either the film–BOX interface or the front and lateral interfaces. A simple characterisation method for FinFETs with variable aspect ratio is proposed and validated experimentally. Fig. 1. TEM cross-section of the FinFET. 2. Device processing Fig. 2. 3D configuration of the FinFET architecture. and three channels. The lateral sections control most of the inversion layer if the fin is narrow enough. We will demonstrate that for higher aspect ratios (i.e., fin width exceeding the Si film thickness), the top channel can provide an extra current exceeding by far 20%. As for conventional SOI devices, the body is in contact with the buried oxide (BOX) and a back channel can be activated by appropriate substrate (back gate) biasing. The FinFET will then convert into a 4-channel transistor controlled by two gates (front and back). The back-gate action is also responsible for interesting coupling effects affecting the front and lateral channels. In this paper, we address for the first time several critical issues of the FinFET: the effect of the fin size, the influence of the substrate bias, and the transport properties of the different channels. The device architecture and technological parameters are first described in Section 2. Short-channel effects are briefly discussed in The devices were fabricated at Motorola, APRDL, using SOI Unibond starting wafers featuring 110 nm thick silicon film and 200 nm thick buried oxide. The silicon channel was left undoped with a background boron concentration of 1015 cm
3 . The devices feature a  lateral gate oxide with an additional nitride layer 30 A (9 nm equivalent oxide thickness) for the top gate. N-channel and P-channel FinFETs have a symmetrical gate configuration with dual N+/P+ polysilicon gate material. The fin was defined by optical lithography. A special trim process, used for further thinning (50 nm) of the fins, leads to well-controlled profiles of Ôtall’ silicon fins. A polysilicon gate electrode etch process was developed for avoiding polysilicon stringer formation due to the large topography. Copper metallization and tungsten plugs for interlevel connections were used, as well as a cobalt silicidation process for the gate and source–drain terminals. Transmission electron microscope (TEM) cross-sectional view of the FinFETs is shown in Fig. 1, with the current flowing in the perpendicular direction. Fig. 2 schematically shows the corresponding 3D structure. The dimensions of the devices are defined as follows: • Hfin is the height of the Si film (width of a lateral channel), kept constant (Hfin  100 nm). • Tfin is the fin thickness (distance between the two lateral gates), varying from 0.18 to 10 lm. • Lfin is the gate length of the FinFET (varying from 0.12 to 10 lm). Distinction must be made between the vertical thickness of the film (Hfin ) and the lateral thickness of the fin (Tfin ). For simplicity, in the following we will refer to the fin thickness defined by lithography. Note that the real fin thickness, achieved after trimming process, is about 50 nm smaller. F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 3. Classical dimensional effects The subthreshold characteristics depend on channel length and fin thickness. Fig. 3 shows the variation of drain current versus gate voltage for different channel lengths. 0.6 and 0.3 lm long FinFETs behave as longchannel devices, with constant threshold voltage and excellent subthreshold swing (60 mV/decade at 300 K). Below 0.18 lm, we observe conventional short-channel effects: as the length Lfin decreases, the threshold voltage is lowered and the subthreshold slope degrades due to charge sharing. A key advantage of SOI devices is the reduction of the short-channel effects when the body thickness decreases [1,9,10]. This also applies to FinFETs as illustrated in Fig. 4. The characteristics of devices with very short channels (Lfin ¼ 0:15 lm) and variable fin thickness are compared. A clear improvement is observed as the FinFET thickness is reduced: VT increases and the subthreshold slope becomes steeper. The increase in VT 1.E-05 TFin = 0.21 µm VD = 10 mV Drain current [A] 1.E-06 for thinner FinFETs is not due to quantum effects that are expected only for fins thinner than 10 nm [9]. In our case, the double gate control of the body potential is reinforced by the use of thinner fins. The charge sharing effect is reduced, hence the threshold voltage lowering in short channels is attenuated. This gives rise to an apparent VT increase. Similar trends are observed for P-channel FinFETs. Another important aspect is that our devices offer a direct comparison of short-channel effects in single-gate and double-gate transistors. Indeed, thin FinFETs behave as quasi-double gate MOSFETs because the role of the top section of the gate is negligible. By contrast, very thick FinFETs, where the lateral gates play a marginal role, can be considered as quasi-single-gate MOSFETs. Increasing the fin thickness, the double-gate action is relaxed being relayed by the single-gate control. We have seen that this causes a degradation in short-channel effects (although the film thickness is comparable with the minimum value of the fin thickness). This degradation is confirmed by the extreme case of 10 lm thick fin. It is concluded that our measurements fully support theoretical predictions [11,12] which show the superiority of double-gate transistors in controlling the shortchannel effects. 1.E-07 LFin = 0.135, 0.18, 0.3 and 0.6 µm 1.E-08 4. Coupling effects 1.E-09 4.1. Front conduction modulated by the back gate 1.E-10 1.E-11 -1 -0.8 -0.6 -0.4 -0.2 0 Gate voltage [V] 0.2 0.4 Fig. 3. Drain current versus top-gate voltage in N-channel FinFETs with different channel lengths and fixed fin thickness (Lfin ¼ 0:135, 0.18, 0.3, 0.6 lm, Tfin ¼ 0:21 lm, Hfin ¼ 100 nm, VD ¼ 10 mV). 1.E-05 LFin = 0.15 µm VD = 10 mV 1.E-06 Drain current [A] 537 1.E-07 TFin = 0.27, 0.24 and 0.18 µm 1.E-08 1.E-09 1.E-10 1.E-11 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 Gate voltage [V] Fig. 4. Drain current versus top gate voltage in short Nchannel with variable channel thicknesses and fixed Lfin (Tfin ¼ 0:18, 0.24, 0.27 lm, Lfin ¼ 0:15 lm, Hfin ¼ 100 nm, VD ¼ 10 mV). The coupling between the front and back gates is a well known phenomena in fully depleted SOI MOSFETs [13] that allows to study the properties of the two interfaces. The coupling effect is also visible in FinFETs, where the critical parameter is the fin thickness. A FinFET can be operated with two, three and even four channels when the substrate is biased in inversion. In Figs. 5–7, we see the evolution of the drain current and the transconductance of top gate for different fin thickness and back-gate bias (from )60 to +60 V with 10 V step). In these results, it is difficult to decorrelate the front and lateral conduction because they both coexist. But, we note the clear influence of the back gate: lateral shift of the characteristics and hump on gm due to the gradual activation of the back channel. In thick devices (Fig. 5), the coupling between front and back channels is strong and a back channel conduction appears (Fig. 5a). The degradation of the transconductance peak, when the back interface is driven into accumulation (Fig. 5b), is a natural effect resulting from the increase of the vertical field [1]. As the fin thickness decreases, the back conduction and coupling effect are reduced: more limited lateral shift (Fig. 6a) and transconductance hump (Fig. 6b). For the thinnest FinFET (Fig. 7a and b), the coupling 538 F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 8.E-08 1.E-07 TFin = 0.21 µm VD = 10 mV Transconductance [S] 1.E-08 Drain current [A] TFin = 0.21 µm VD = 10 mV 7.E-08 VG2 -60V -> 60 V step 10 V 1.E-09 1.E-10 VG2 -60V -> 60 V step 10 V 6.E-08 5.E-08 4.E-08 3.E-08 2.E-08 1.E-08 1.E-11 0.E+00 -1 (a) -0.5 0 Gate voltage [V] 0.5 1 -1 -0.5 (b) 0 Gate voltage [V] 0.5 1 Fig. 5. Drain current (a) and transconductance (b) versus top-gate voltage in a relatively thick N-channel FinFET for variable backgate bias (Tfin ¼ 0:21 lm, Lfin ¼ 10 lm, VD ¼ 10 mV, VG2 ¼
60 to 60 V with step 10 V). Coupling effects are strong. 8.E-08 1.E-07 TFin = 0.195 µm VD = 10 mV Transconductance [S] 7.E-08 Drain current [A] 1.E-08 VG2 -60V -> 60 V step 10 V 1.E-09 1.E-10 TFin = 0.195 µm VD = 10 mV VG2 -60V -> 60 V step 10 V 6.E-08 5.E-08 4.E-08 3.E-08 2.E-08 1.E-08 1.E-11 (a) 0.E+00 -1 -0.5 0 Gate voltage [V] 0.5 1 (b) -1 -0.5 0 Gate voltage [V] 0.5 1 Fig. 6. Drain current (a) and transconductance (b) versus top-gate voltage in N-channel FinFET for variable back-gate bias (Tfin ¼ 0:195 lm, Lfin ¼ 10 lm, VD ¼ 10 mV, VG2 ¼
60 to +60 V with step 10 V). Coupling effects are lower than in Fig. 5. 8.E-08 1.E-07 1.E-08 VG2 -60V -> 60 V step 10 V 1.E-09 1.E-10 VG2 -60V -> 60 V step 10 V TFin = 0.18 µm VD = 10 mV 7.E-08 Transconductance [S] Drain current [A] TFin = 0.18 µm VD = 10 mV 6.E-08 5.E-08 4.E-08 3.E-08 2.E-08 1.E-08 1.E-11 (a) 0.E+00 -1 -0.5 0 Gate voltage [V] 0.5 1 (b) -1 -0.5 0 Gate voltage [V] 0.5 1 Fig. 7. Drain current (a) and transconductance (b) versus top-gate voltage in a relatively thin N-channel FinFET for different backgate bias (Tfin ¼ 0:18 lm, Lfin ¼ 10 lm, VD ¼ 10 mV, VG2 ¼
60 to 60 V with step 10 V). Coupling effects are vanishing. almost disappears and only the main conductions, lateral and front channels, coexist mixing together. The impact of back-gate bias is strongly lowered due to the reduction of the aspect ratio (fin thickness Tfin versus film thickness Hfin ). The back channel is suppressed (Fig. 7a) and the modulation of the transconductance peak (Fig. 7b) is limited to 10–15%. These results imply that, in very thin fins, the back gate loses the control of the potential at the film–BOX interface. There are two main reasons: • The back surface potential tends indeed to be governed by fringing fields penetrating from the bottom of the lateral gates into the body and BOX. 539 F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 • The lateral interfaces being very close to each other, their mutual coupling becomes stronger than the vertical coupling. Hence, the lateral conduction appears earlier and controls the front and back surface potentials, which tend to decorrelate. Threshold voltage [V] 1 The coupling effects are summarized by VT ðVG2 Þ curves shown in Fig. 9 for various fin thickness. The linear decrease in threshold voltage with increasing back-gate bias is typical for fully depleted SOI MOSFETs. In very thick fins the slope can be modeled by the classical coupling relation formulated by Lim and Fossum [13]: TOX1 DVT ¼
 DVG2 TOX2 TFin = 0.18, 0.195, 0.21, 0.225, 0.3, 0.6 and 10 µm 0 -0.5 -1 -1.5 -60 ð1Þ 60 In this section, we discuss the reverse coupling effect, that is the influence of the top gate on the back channel. Back conduction is activated by substrate biasing and obviously is very notorious in thick FinFETs (Fig. 10a and b). Reverse coupling is responsible for the distortion of these characteristics according to the top gate bias. For positive VG , we observe an apparent leakage current (Fig. 10a) which is nothing but the current flowing in the top and laterals channels. For negative VG , the transconductance peak is degraded (Fig. 10b). The lateral shift of these characteristics is more limited than in Fig. 5 because the reverse coupling coefficient is weaker. A more unusual feature is visible on the transconductance curves (Fig. 10b) which exhibits two or three distinct peaks due to the differed activation of the various channels. We use the double derivative method [14] 1.E-06 1E-07 Drain current [A] VG2 = 0V VG2 -60V -> 60 V step 10 V 1.E-08 1.E-09 TFin = 10 µm VD = 10 mV 1E-08 1E-09 1E-10 VG2 -30V -> 40 V step 5 V 1E-11 TFin = 10 µm VD = -10 mV 1E-12 1E-13 1.E-11 (a) 40 4.2. Back conduction modulated by top gate 1E-06 1.E-10 -20 0 20 Back-gate voltage [V] corresponds to the fin aspect ratio (Tfin =Hfin ). The top channel can provide much more than the 20% additional current reported in [7]. 1.E-05 1.E-07 -40 Fig. 9. Top gate threshold voltage versus back-gate bias in Nchannel SOI FinFETs with various fin thickness (L ¼ 10 lm). The coupling effect increases in thicker fins. Thinner FinFETs do not obey this law as a consequence of charge sharing between the top and lateral channels. Basically, the one-dimensional vertical control transforms into a two-dimensional control (vertical and lateral). Moreover, the slope falls rapidly to virtually zero in very thin fins, where only the lateral control subsists. The message here is that the lateral channels are rather immune to back-gate influence. Same results and conclusions are obtained for Pchannel FinFETs. A major difference however appears in wide fins (Fig. 8a and b). In N-channels, 1-D coupling effect develops normally (Fig. 8a). In P-channels, the characteristics exhibit several humps (Fig. 8b) reflecting the successive activation of the different channels. For simplicity, we consider the case of back channel in accumulation (VG2 ¼ þ40 V). It is clear that the lateral channels open first and reach strong inversion before the top channel becomes prevailing (VG 
0:8 V). The delayed activation of the top channel is due to a higher threshold voltage resulting from a lower gate doping and a higher effective oxide thickness. Note that the difference in strong inversion currents flowing in top and lateral channels exceeds one order of magnitude and well Drain current [A] 0.5 -1 -0.5 0 Gate voltage [V] 0.5 1 (b) -1 -0.5 0 Gate voltage [V] 0.5 1 Fig. 8. Drain current versus top-gate voltage in wide and long FinFETs for different back-gate bias: (a) N-channel (Tfin ¼ 10 lm, Lfin ¼ 10 lm, VG2 ¼
60 to 60 V with step 10 V), (b) P-channel (Tfin ¼ 10 lm, Lfin ¼ 10 lm, VD ¼
10 mV, VG2 ¼
30 to 40 V with step 5 V). 540 F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 2.0E-07 1.E-05 VG1 -1V -> 0.2 V step 0.2 V VG1 -1V -> 1 V step 0.2 V 1.E-07 1.E-08 1.E-09 Transconductance [S] Drain current [A] 1.E-06 TFin = 10 µm VD = 10 mV VG1 = 0V TFin = 10 µm VD = 10 mV 1.5E-07 1.0E-07 5.0E-08 1.E-10 0.0E+00 1.E-11 -30 -10 10 30 Back-gate voltage [V] (a) -30 50 -20 (b) -10 0 10 20 30 40 Back-gate voltage [V] Fig. 10. Drain current (a) and transconductance (b) versus back-gate voltage in a large N-channel FinFET for different front gate bias (Tfin ¼ 10 lm, Lfin ¼ 10 lm, VD ¼ 10 mV, VG2 ¼
1 to 1 V with step 0.1 V). to discriminate the different conductions and in particular to determine the corresponding threshold voltages. In this method, the threshold voltage is defined as the gate voltage for which the derivative of transconductance is maximum. This method is very useful because it is not affected by device degradation mechanisms such as series resistance and surface roughness mobility degradation. For example, Fig. 11a and b shows the transconductance and second derivative of current for a long and thick FinFET (Lfin ¼ 10 lm and Tfin ¼ 0:6 lm) with different top gate bias. The transconductance exhibits two clear peaks as well as the onset of a third peak on the left (for VG ¼ 0 V). The second derivative offers a better resolution for identifying the three different peaks. The first peak (VG2 
8 V) reflects the activation of the laterals channels which are ‘‘closer’’ to the back interface and so more sensitive to coupling. The second peak (VG2 
3 V) corresponds to front-channel threshold voltage and, finally, the main peak (VG2 > 0 V) is due to the back conduction. It is worth noting that substrate depletion underneath the BOX can lead to an even more complex transconductance behaviour. Total Front Lateral gm;Max ¼ gm;Max þ gm;Max Lateral gm;Max ¼2 2.0E-09 TFin = 0.6 µm VD = 10 mV hFin eox 1  Lateral  VD  lLateral ¼  lLateral A LFin TOX ð3Þ TFin = 0.6 µm VD = 10 mV G1 1.5E-09 VG1 -1V -> 0 V step 0.1 V 1.0E-09 D 4.E-09 3.E-09 2.E-09 VG1 -1V -> 0 V step 0.1 V 1.E-09 0.E+00 5.0E-10 0.0E+00 -5.0E-10 -1.0E-09 -30 (a) ð2Þ Front is the maximum transconductance for the where gm;Max Lateral front channel and gm;Max the maximum transconductance for the lateral channels. First order approximation yields: Second derivative I vs V Transconductance [S] 5.E-09 The experiment has shown that often the lateral conduction and front conduction are mixed which masks their individual properties. Here we present a simple method that allows separating the contributions of different channels in terms of carrier mobilities. For mobility decorrelation, we use FinFETs with variable width and appropriate voltages for the different gates. When back channel conduction is negligible and the front/lateral channels are simultaneously Total activated, the total transconductance peak gm;Max is given by [S/V] 6.E-09 5. Channel separation and transport properties -20 -10 0 10 20 Back-gate voltage [V] 30 40 -15 (b) -10 -5 0 5 Back-gate voltage [V] 10 15 Fig. 11. Transconductance (a) and second derivative of drain current (b) versus back-gate voltage in a long N-channel FinFET for different front gate bias (Tfin ¼ 0:6 lm, Lfin ¼ 10 lm, VD ¼ 10 mV, VG2 ¼
1 to 0 V with step 0.1 V). Different peaks correspond to distinct channels. 541 F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 and Front ¼ gm;Max tFin eox  Front  VD  lFront LFin TOX ð4Þ Multiplying Eq. (2) by the coefficient A, we have A Total gm;Max Lateral ¼l T Lateral lFront  tFin þ oxFront  2  hFin TOX ð5Þ 1400 y = 1284.1x + 196.35 [ L = 0.2 m and Tox = 3nm ] Mobility function Agm,max [cm2/Vs] Total In other words, plotting the experimental value A  gm;Max versus fin thickness results in a straight line. The intercept with the vertical axis corresponds to the lateral mobility on the fin edges and the slope yields the front channel mobility lFront . The method is illustrated in Fig. 12. Taking into consideration an additional trimming of the fin thickness by 50 nm in the lateral direction and using linear regression, we obtain lLateral ¼196 cm2 /V s and n Front 2 ln ¼ 677 cm /V s for N-channel FinFETs. The difference between oxide thickness on the film edges and surface is accounted for in Fig. 5 and therefore, does not affect the accuracy of the extracted mobility values. The back channel mobility, lBack ¼ 682 cm2 /V s, is n determined from the back-channel transconductance peak measured for a front-gate bias adjusted such as to suppress the front and lateral channels. In P-channels, the front and lateral conductions still mix together but are activated for different threshold voltages. Although Eq. (2) is no longer perfectly accurate, it can still be applied. The hole mobility at the back channel again is found from the transconductance peak. For wide fin, where fringing fields are negligible, we obtain lBack ¼ 150 cm2 /V s. The various mobilities for p N- and P-channels are summarized in Table 1. Another possibility for evaluating the mobilities of the lateral and the front channels separately is to accumulate the back interface and use devices with particular geometry. For example, in 10 lm thick fins, where the lateral conduction is mostly negligible, we monitor the front-channel mobility. To determine the lateral mobil- 1200 tFin = 10 µm 1000 800 600 400 µlateral 200 0 0 0.2 0.4 0.6 0.8 1 Fin thickness tFin (m) Fig. 12. Normate mobility versus real thickness for different Nchannel devices with Tfin ¼ 10 lm (Wnorm ¼ 10 lm, TOXnorm ¼ 3 nm, VD ¼
10 mV). Table 1 Extracted values of electron and hole mobility for the various FinFET channels Mobility (cm2 /V s) N-channel FinFETs P-channel FinFETs Lateral interfaces Front interface Back interface 196 677 682 96 163 150 ity, we select instead the thinnest FinFETs (0.18 lm) where the front-channel contribution is negligible due to the aspect ratio and higher threshold voltage. Note that accumulation at one interface degrades the mobility in the opposite channel because the vertical field is higher and the series resistances can increase too. On the other hand, a compensating mechanism may lead to overestimate the back-channel mobility. Indeed, the back-gate bias acts at the wafer scale, inducing not only inversion at the back channel but also accumulation in the terminals, so reducing the series resistance. However, the above effects are not likely to alter the key messages delivered by Table 1: • The carrier mobility in the lateral channels is relatively poor. This is primarily due to the sidewall degradation during the fin thinning. A different crystal orientation on the fin sidewalls can also be claimed. • The front and back channel mobilities are excellent, comparable with values reported for conventional single-gate SOI MOSFETs. This implies that fin trimming does not affect the quality of the top and bottom interfaces of the film. 6. Conclusions The coupling effects and the transport properties of SOI FinFETs have been experimentally studied. The influence of the fin thickness on short channel and coupling effects has been emphasized. We have shown that classical front and back interface coupling effects still occur in thick FinFETs. In thin devices, the specific architecture of FinFETs can result in the suppression of the back-gate influence. We have demonstrated that the contributions of the various channels can be separated. A novel method for mobility segregation has been proposed and validated experimentally. The front-gate and back-gate mobilities are significantly higher than the lateral-channel mobility. This difference is presumably due to a different crystallographic orientation and to a degradation of the interface on the sidewalls. Finally, the transport properties of the various channels can be combined in order to obtain high performance FinFETs with increased current. To reach optimum trade-off between performance, short-channel effects and integration density, a 542 F. Dauge et al. / Solid-State Electronics 48 (2004) 535–542 well-defined balance between front/back and lateral dimensions will be necessary. Acknowledgements Part of this work has been performed at the Center for Projects in Advanced Microelectronics (CPMA), which is a multi-project institute operated by CNRS, LETI, and Universities, France. Thanks are due to Motorola team for competent device processing. References [1] Cristoloveanu S, Li SS. Characterization of Silicon-OnInsulator Materials and Devices. Boston: Kluwer Academic Publishers; 1995. p. 381. [2] Franck D, Laux S, Fischetti M. IEDM Tech Dig 1992:553. [3] Wong H-S, Frank DJ, Solomon P. IEDM Tech Dig 1998:407–10. [4] Hisamoto D, Kaga T, Takeda E. Trans Electron Dev 1991;38:1419. [5] Hisomoto D, Lee W-C, Kedzierski J, Anderson E, Takeuchi H, Asano K, et al. IEDM Tech Dig 1998:1032–4. [6] Huang X, Lee WC, Kuo C, Hisamoto D, Chang L, Kedzierski J, et al. IEEE Trans Electron Dev 2001;48: 880. [7] Chau Robert, Doyle Brian, Kavalieros Jack, Barlage Doug, Murthy Anand, Doczy Mark, Arghavani Reza, Datta Suman. ISSDMC Nagoya Japan 68, 17 September, 2002. [8] Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T. IEEE Electron Dev Lett 1987;ED-8:410–2. [9] Celler GK, Cristoloveanu S. Frontiers of silicon-on-insulator. J Appl Phys 2003;93(9):4955–78. [10] Pretet J, Dieudonne F, Allibert F, Bresson N, Matsumoto T, Ohata A, et al. Electrochemical Society Proceedings; 2003. p. 476–87 (invited paper). [11] Yan RH, Ouzmard A, Lee KF. IEEE Trans Electron Dev 1992;39:1704. [12] Allibert F, Ernst T, Pretet J, Hefyene N, Perret C, Zaslavsky A, et al. Solid-State Electron 2001;45:559–66. [13] Lim H-K, Fossum JG. IEEE Trans Electron Dev 1983; 30:1244. [14] Wong H-S. Solid-State Electron 1987;30:953–68.