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The RatCAP Front-End ASIC

2008, IEEE Transactions on Nuclear Science

We report on the design and characterization of a new ASIC for the RatCAP, a head-mounted miniature PET scanner intended for neurological and behavioral studies of an awake rat. The ASIC is composed of 32 channels, each consisting of a charge sensitive preamplifier, a 5-bit programmable gain in the pole-zero network, a 3 rd order bipolar semi-Gaussian shaper (peaking time of 80 ns), and a timing and energy discriminator. The energy discriminator in each channel is used to arm the zero-crossing discriminator and can be programmed to use either a low energy threshold or an energy gating window. A 32-to-1 serial encoder is embedded to multiplex into a single output the timing information and channel address of every event. Finally, LVDS I/O were integrated on chip to minimize the digital noise on the read-out PCB.

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 5, OCTOBER 2008 2727 The RatCAP Front-End ASIC Jean-Francois Pratte, Student Member, IEEE, Sachin Junnarkar, Student Member, IEEE, Grzegorz Deptuch, Member, IEEE, Jack Fried, Paul O’Connor, Member, IEEE, Veljko Radeka, Member, IEEE, Paul Vaska, Member, IEEE, Craig Woody, Member, IEEE, David Schlyer, Member, IEEE, Sean Stoll, Member, IEEE, Sri Harsha Maramraju, Student Member, IEEE, Srilalan Krishnamoorthy, Student Member, IEEE, Roger Lecomte, Member, IEEE, and Rejean Fontaine, Member, IEEE Abstract—We report on the design and characterization of a new ASIC for the RatCAP, a head-mounted miniature PET scanner intended for neurological and behavioral studies of an awake rat. The ASIC is composed of 32 channels, each consisting of a charge sensitive preamplifier, a 5-bit programmable gain in the pole-zero network, a 3rd order bipolar semi-Gaussian shaper (peaking time of 80 ns), and a timing and energy discriminator. The energy discriminator in each channel is used to arm the zero-crossing discriminator and can be programmed to use either a low energy threshold or an energy gating window. A 32-to-1 serial encoder is embedded to multiplex into a single output the timing information and channel address of every event. Finally, LVDS I/O were integrated on chip to minimize the digital noise on the read-out PCB. technology, has a size The ASIC was realized in the TSMC 0.18 of 3.3 mm 4.5 mm and a power consumption of 117 mW. The gate length of the N-channel MOSFET input device of the charge sensitive preamplifier was increased to minimize 1/f noise. This led to a factor improvement of the ENC with respect to the first version of the ASIC [1]. An ENC of 650 e-rms was measured with the APD biased at the input. In order to predict the achievable timing resolution, a model was derived to estimate the photon noise contribution to the timing resolution. Measurements were performed to validate the model, which agreed within 12%. The coincidence timing resolution between two typical LSO-APD-ASIC modules was measured using a 68 source. Applying a threshold at 420 keV, a timing resolution of 6.7 ns FWHM was measured. An energy resolution of 18.7% FWHM at 511 keV was measured for a 68 source. m 15 Ge Ge Index Terms—ASIC, CMOS, PET, PET/MR, photon noise, RatCAP, timing resolution. I. INTRODUCTION ASED on our experience with previous designs, a new ASIC for the RatCAP head-mounted miniature Positron Emission Tomography (PET) scanner was realized [1]–[3]. This ASIC was specifically designed for the RatCAP project, but will also be used in the BNL PET Wrist Scanner [4], a simultaneous dual-modality PET/MRI scanner [5], and a coded B Manuscript received May 13, 2008; revised July 30, 2008. Current version published December 04, 2008. This work was supported by the Office of Basic Sciences of the U.S. Department of Energy and has been authored by employees of Brookhaven Science Associates, LLC under Contract DE-AC02-98CH10886 with the U.S. Department of Energy. J.-F. Pratte, S. Junnarkar, G. Deptuch, J. Fried, P. O’Connor, V. Radeka, P. Vaska, C. Woody, D. Schlyer, and S. Stoll are with the Brookhaven National Laboratory, Broohaven, NY 11973 USA (e-mail: jfpratte@bnl.gov). S. H. Maramraju and S. Krishnamoorthy are with Stony Brook University, Stony Brook, NY 11794 USA. R. Lecomte and R. Fontaine are with the Université de Sherbrooke, Sherbrooke J1K 2R1, Canada. Digital Object Identifier 10.1109/TNS.2008.2004275 Fig. 1. Drawing of the RatCAP camera. Each detector block is composed of an LSO crystal, APD and custom ASIC. aperture gamma-ray imager for homeland security applications. Significant improvements were made on this ASIC to lower the electronic and common mode noise, to add programmable gain, to lower the random input offset voltage of the timing discriminator, to add an energy gating discriminator and finally to add Low-Voltage Differential Signaling (LVDS) transceivers for communication with the Data Acquisition system (DAQ). In Section II, the ASIC will be presented along with the design considerations. Also described is an overview of the readout system which was specifically designed for the RatCAP. Then, the measurements will be presented. Finally, the ASIC performance will be discussed, along with the validation of a model elaborated to evaluate the contribution to the timing resolution of the statistical fluctuations in the light emitted by the Lutetium Oxyorthosilicate (LSO) scintillator and the photoelectron statistics. II. THE RATCAP ASIC The RatCAP camera is composed of twelve modules of LSO and Avalanche Photodiode (APD) array coupled to the read-out ASIC, as presented in Fig. 1. The LSO array is composed of coupled one to one to a 4 8 crystals of avalanche photodiode array from Hamamatsu (S8550). Each pixel of the APD has a capacitance of 10 pF and a leakage current of 1.5 nA. The main design objectives for the front-end electronics are the following. First, it should have minimal power dissipation in 0018-9499/$25.00 © 2008 IEEE Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. 2728 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 5, OCTOBER 2008 Fig. 2. Block diagram of a channel. order not to affect the animal’s behavior or affect the avalanche photodiode (APD) gain which is sensitive to temperature. Second, all the front-end electronics must be small enough to fit on the back of the detector. Third, the number of interconnections between the chips and the DAQ should be minimized in order to maximize the animal’s mobility, allowing for awake animal behavioral studies. Finally, the electronics must be optimized for the detector characteristics in order to achieve the best possible timing resolution. The mixed-signal ASIC has 32 channels. Each channel is composed of a Charge Sensitive Preamplifier (CSP), a polezero network with 32 programmable gain settings, a 3 order bipolar Gaussian shaper, a zero-crossing discriminator (ZCD) used to pick off the timing information of every event and a programmable energy discriminator. Fig. 2 presents a block diagram of one channel. A serial encoder (not shown in Fig. 2) multiplexes through a single output the digital stamp of each event occurrence and the 5-bit corresponding channel address. A 1088-bit serial programming interface (SPI) was integrated to program the gain and the energy discrimination mode of each channel as well as the analog multiplexers of the ASIC. The 100 MHz system clock of the RatCAP camera is daisy chained through the 12 ASICs. The ASIC’s clock input, clock output and the serial encoder output use integrated LVDS transceivers. Two analog multiplexers, one per sixteen channels, are integrated to help in calibration and diagnosis of the analog chain. The ASIC was realized in TSMC technology, has a size of 3.3 mm 4.5 mm and has a 0.18 power consumption of 117 mW. Fig. 3 presents a microphotograph of the ASIC. A. Analog Front-End The CSP amplifier is based on a modified telescopic cascode architecture [1]. The N-channel MOSFET input device has been optimized with respect to the technology parameters and the detector characteristics at its operating point (capacitance, leakage current and gain), using the EKV transistor model [6], to minimize the Equivalent Noise Charge (ENC) [7], [8]. , twice the minimum feature The gate length was set to 0.4 size, to minimize the 1/f noise contribution. With a gate width of 1760 and biased with 600 , the device is operated in weak inversion, and leads to a calculated ENC of 453 e-rms at a shaper’s peaking time of 80 ns (neglecting the stray capacitance at the input). The input device has a transconductance of 13 mS and a gate capacitance of 5.8 pF. All other transistor dimensions of the CSP are optimized for minimum white series and 1/f noise contribution to the overall ENC, mainly set by the input device. The feedback capacitor is 200 fF, which gives the CSP a gain of 5 mV/fC. The pole-zero network following the CSP is used to eliminate in the amplifier’s the non-linearity of the reset transistor feedback [9]. It also provides a gain N, as seen in the transfer represents the function of the analog front-end (1), where and reset transistor in the number of pairs of capacitor pole-zero cancellation network: (1) where , and are expressed by: (2) (3) (4) On a per channel basis, the factor N can be programmed between 18 to 49 in unit steps, to vary the overall front-end gain by a factor 2.7, between 21.5 and 58.5 mV/fC. A minimum of 18 pairs in the zero are required to minimize the shaper’s noise contribution relative to the CSP input. This add-on was driven by the ratio of 2.5 between the pixel with the greatest charge collection to the pixel with the lowest charge collection within an LSO-APD detector module. This spread comes mainly from the light collection efficiency and APD gain variation between pixels. This leads to a wide signal dynamic range in the analog front-end which creates a considerable time dispersion in the ZCD, leading to a deterioration of the timing resolution. Also, as a single energy threshold is used for all channels, the programmable gain allows for a more uniform discrimination between the Compton scatters and the photopeak events within a detector module. It can be demonstrated that the original spread of 2.5 in the charge collection efficiency is reduced to an average of 0.033 after gain correction. Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. PRATTE et al.: THE RATCAP FRONT-END ASIC 2729 to calculate the photon noise and the overall achievable timing resolution. Subsequently, this model will be validated in the Experimental Result section of this paper. The timing resolution is the noise divided by the slope of the signal at the discrimination point. In a scintillator based system, the timing resolution can be expressed as, (5) where the total noise is the sum of the electronic and . The electronic time dependent photon noise noise can be calculated using [7], and it is presented in [1], [2] for this specific system. The slope at the discrimination point can be obtained by the convolution of the system’s input signal from the LSO-APD response, with the impulse function of the system, expressed by (1) in this case. As a first order approximation, neglecting the finite rising edge of the APD-LSO response due to the total capacitance at the input and the effective input impedance of the preamplifier, the input signal is modeled by: (6) is the total number of primary photoelectrons multiwhere is the LSO decay time constant. plied by the APD gain, and Regarding the photon noise calculation relative to the CSP input, [14] presented the following expression: Fig. 3. Microphotograph of the RatCAP ASIC. The 32 channel ASIC was realized in TSMC 0.18  technology, has a size of 3.3 mm 4.5 mm and has a power consumption of 117 mW. m 2 The third-order bipolar semi-Gaussian shaper has a peaking time of 80 ns. It is realized in two stages: a first-order low-pass filter and a second-order bandpass filter implemented with a biquadratic architecture [10]–[12]. Both amplifiers used in the shaper are a scaled down version of the CSP amplifier, where every transistor was optimized to minimize its electronic noise contribution. B. Timing Resolution and Photon Noise Model The number of electron-hole pairs created as a function of time in the photodetector varies statistically from one event to another. This is due to the statistical nature of the process in which a scintillator emits visible light following the absorption of a gamma photon. The quantity and the time distribution of the emitted photons vary. Also, the photoelectron statistics in the APD, where there are the lowest quantity of information carriers [13], will affect the number of electron-hole pairs created from one event to another. This photon noise is non-stationary (time dependent) and directly affects the achievable timing resolution, one of the main figure of merit of the LSO-APD-ASIC detector module. A model of the photon noise is essential to predict a scintillator based system’s performance and to validate the measurement results. Below, a procedure is presented (7) with , the excess noise factor [15], defined as: (8) and being the electron charge, the APD gain, the effective ionization ratio, the LSO-APD photoelecthe weighting function of the analog tron current (6) and is the factor by which the front-end (1)[7], [16]. Note that statistical noise on the APD current (equal to the multiplied photocurrent plus the multiplied APD bulk dark current) exceeds that which would be expected from a noiseless multiplier on the basis of shot noise alone [17]. The 12 LSO-APD detector modules used in the RatCAP camera have an average APD gain of 46.8 and average of 5200 photoelectrons per MeV. For this APD gain and number of photoelectrons, the calculated slope at the zero-crossing of the bipolar shaper is 713 electrons per nanosecond. As previously mentioned the modeled ENC is 453 e-rms. Assuming an APD effective ionization ratio of 0.04, it leads to an excess noise factor F of 3.77 and a photon noise relative to the input of 1211 e-rms. Hence the average predicted timing resolution of the RatCAP camera is 1.8 ns rms for 511 keV gamma photons. Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. 2730 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 5, OCTOBER 2008 C. Energy and Zero-Crossing Discriminators This mixed-signal circuit is composed of two comparators for energy discrimination, one comparator for generating a trigger on the zero-crossing of the shaper’s bipolar signal, which represents the timing information of each event, and a logic block, as seen in Fig. 2. The comparators used for energy discrimination are identical and have a power consumption of 67.5 each. For better noise trigger immunity, internal positive feedback is used to create an hysteresis of 15 mV, which corresponds roughly to six sigma of the noise. There are two main design criteria for the comparator used to trigger on the zero-crossing of the shaper’s bipolar signal. First, the sensitivity of the comparator had to be high enough to minimize the energy dependent time walk for the desired input charge dynamic range, while keeping the power consumption to the minimum feasible. This is crucial, as the signal amplitude is not sent to the DAQ for post-processing of the time stamp and correction for the time walk. Second, the input stage of the comparator had to be designed to minimize input random offset voltage. Input random offset voltage acts like an offset on the reference baseline, varying from one channel to another due to its random nature. The effective consequence of having nonnegligible random input offset voltage is that the comparator will not trigger at the zero-crossing of the bipolar signal, but either below or above the baseline, creating a considerable dispersion of the timing trigger as a function of energy. To minimize the random input offset voltage of the comparator, one has to take great care to match the threshold voltage and the drain current of the differential pair devices [18]. Those two parameters are functions of the input devices, but also of the load of the differential pair. For a MOSFET, the threshold voltage mismatch can be expressed as: (9) where is the voltage threshold mismatch coefficient, and are the which is constant for a given technology, and transistor gate width and length. The drain current mismatch for a device in weak inversion is expressed as: (10) where is the electron charge, the Boltzmann’s constant, the temperature and the subthreshold slope factor [19]. In is expressed strong inversion, drain current mismatch as: (11) with is the gate source voltage, the threshold voltage, where the carrier mobility mismatch coefficient and the device oxide mismatch coefficient. Fig. 4 presents the schematic of the comparator used to trigger on the zero-crossing of the shaper’s bipolar signal. It is a differential amplifier used in open-loop, consisting of a differential input pair M1-M2 with diode connected MOSFET load M5-M6 which mirror the output signal to a push-pull output stage M8-M10. In order to improve matching between the differential input pair M1-M2, which directly affects the input random offset voltage through the variation of their threshold voltage, the gate length was set to eight times the minimum gate size. Diode connected transistors M5 -M6 are used to load the differential pair, as a lower impedance helps matching of the output current, hence the variation of the Vgs of M1-M2. It also has the benefit of lowering the voltage swing at the output of M1-M2, improving the propagation delay in the first stage. Again, the gate length of M5-M6 is bigger than the minimum size to improve their matching. To counter the loss of gain from the lower impedance of the load, current sources M3-M4 are added to increase the transconductance of the differential pair. The transistor M11 is used to cascode M8 to reduce the kick back, from the digital output stage M12-M13 through the gate to drain parasitic capacitance of M8, to the output of the differential pair. Hysteresis is not desired in the comparator to allow triggering at the zero-crossing of the bipolar signal. But still, immunity to noise triggering is essential. Hence, by driving the gate of transistor M17 to a logic low state, the comparator can be disabled by clamping one side of the differential output stage to the power supply rail, preventing any triggers from the shaper’s baseline noise. To enable the comparator, the gate of M17 is pulled to a logic high state. When the comparator is enabled, the transistor M17 has minimal influence on the comparator’s characteristics. Each channel can be programmed independently to discriminate the signal’s amplitude based on a low threshold, or to satisfy an energy gating window. In both energy gating modes, when a signal with an amplitude greater than the lower energy threshold is detected, the zero-crossing comparator is enabled by controlling the gate of M17 through some logic. When the energy gating window mode is enabled, the zero-crossing discriminator’s trigger will be gated if the shaper signal’s amplitude is greater than the upper energy threshold. Hence, to obtain the timing information of a detected event in the energy gating window mode, the shaper signal’s amplitude has to be greater than the lower energy threshold, and lower than the upper energy threshold. In simulation, it is clear that there is enough time to enable the zero-crossing comparator, when the low energy condition is met, before the zero-crossing occurs. When the zero-crossing of the bipolar signal is detected, the comparator of Fig. 4 triggers. Following this trigger, all logics are reset, in order to be ready for the next event. As the digital part of the circuit is completely asynchronous, monostable circuits are used to ensure proper reset time. D. Timing and Address Serial Encoder (12) One of the main design criteria of the RatCAP camera is to minimize the number of interconnections with the DAQ in order Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. PRATTE et al.: THE RATCAP FRONT-END ASIC 2731 Fig. 4. Schematic of the comparator used to trigger on the zero-crossing of the shaper’s bipolar signal. It is implemented using a differential amplifier in open-loop. To prevent noise triggers, the transistor M17 is used to enable the comparator only when the amplitude of the shaper’s signal is greater than the low energy threshold. Fig. 5. Block diagram of the chip encoder. Each of the 32 channels are connected to a 32 input Wired-NOR, where the detected time of arrival of an event triggers the Control Signal Generator (CSG). The CSG will transmit the timing edge, asynchronously with respect to the 100 MHz system clock, through the single ASIC output. Each channel is also tied to a 32 to 5 priority encoder which generates the address of the channel that fired. The address is then serialized through the same output as the timing edge. to optimize the animal’s mobility, which justified the implementation of a timing and address serial encoder. Fig. 5 presents a block diagram of the encoder. It consists of a wired-NOR, a Control Signal Generator (CSG), a 32-to-5 priority encoder, a serializer and an output OR gate. The encoder’s output consists of a leading edge created from a wired-NOR of all 32 ZCD outputs which is asynchronous with the clock, followed by at least one clock cycle, a stop bit and then the 5 bit address of the channel that fired. Fig. 6 shows an oscilloscope capture of Fig. 6. Oscilloscope capture of the pulse generator trigger used to inject the charge in the ASIC (top), along with the shaper’s bipolar signal (middle) and the encoder’s digital output (bottom). The leading edge of the encoder’s digital output represents the time of occurrence of a detected event, which is followed by the 5-bit address of the channel that fired. the encoder’s output, along with the shaper’s bipolar signal and the trigger of the pulse generator used to inject charge in the channel. The 32 ZCD outputs are interconnected to the wired-NOR. Hence, when a timing trigger is generated in a channel, the wired-NOR output triggers the CSG which feeds back a blocking signal to all channels in order to prevent corruption of the chip output if another event is detected while the current event is being processed. After the last address bit has been transmitted, the CSG unblocks every channel to allow a new event to be transmitted. Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. 2732 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 5, OCTOBER 2008 Fig. 8. ENC as a function of input capacitance. The marker represents the measured ENC of 650 e-rms with the APD biased at a gain of 45. which also performs a timing offset calibration to correct for time dispersions between the 384 channels [21]. Fig. 7. Picture of the readout rigid-flex PCB of the RatCAP PET camera before being cut from the panel. The 32 ZCD outputs are also interconnected to the 32-to-5 priority encoder. Hence, when a channel fires, the priority encoder will generate the 5 bit address which is latched in the serializer. Under the control of the CSG, the serializer will then transmit synchronously with the clock, the address to the output OR gate, starting with the LSB. In the case where more than one channel triggers the encoder before the blocking signal is broadcast, for instance in the case of a Compton scatter within the LSO scintillator array, the encoder will give priority to the higher channel address. The synchronous part of the encoder works with a clock of 100 MHz, therefore the length of the blocking period is between 70 and 80 ns. Assuming a singles rate of about 3,125 cps per channel, a minimum efficiency of 99.3% is predictable. E. System Readout The Printed Circuit Board (PCB) of the RatCAP PET camera is a ten layer rigid-flex, coated with an organic solderability preservative. Fig. 7 presents a picture of the PCB. All magnetic material was removed, allowing for dual-modality PET/MR applications. Each of the twelve blocks consists of an LSO-APD array and ASIC. To minimize any common mode noise, LVDS communication protocol is being used. Each ASIC has two LVDS transmitters and one LVDS receiver embedded. The LVDS transmitter has a power consumption of 16 mW, while the receiver has a power consumption of 3.25 mW. To minimize the number of traces on the PCB, the 100 MHz system clock and the SPI are daisy chained throughout. The twelve ASICs are programmed and readout through the Timestamp and Signal Processing Module (TSPM), an FPGA-based custom DAQ system [20]. The TSPM generates a 64-bit word per detected event, which contains the absolute time stamp of the detected photon as well as the address of the channel that fired. An average 1.2 million events per second are expected for the RatCAP, and the maximum rate capability of the DAQ is 80 MB per second. The data is acquired in list mode, and coincidence matching is performed offline using a software III. EXPERIMENTAL RESULTS The ASIC has been thoroughly tested and is fully functional. Out of 35 packaged ASICs of 32 channels each, a total of 4 channels were not responding, leading to a yield of 99.6%. A. Equivalent Noise Charge The ENC of the front-end was measured for various capacitances at the input, and is reported in Fig. 8. The ENC was also measured with the Hamamatsu APD S8550 biased at a high voltage of 353 V to obtain the noise figure at the nominal operating gain of 45. An ENC of 650 e-rms was measured. The measurements were performed with the ASIC on a test PCB with the 100 MHz LVDS system clock, the serial programming interface and the digital output of the ASIC operational in order to obtain realistic results. By extrapolating the curve to the abscissa, a total capacitance at the input of 15.5 pF is deduced, where the gate capacitance of the input NMOS of the CSP is 5.8 pF, the input pad is 500 fF and the feedback capacitor of the CSP is 200 fF. Hence a stray capacitance at the input of about 9 pF is estimated. By comparison, the calculated ENC taking into account the stray capacitance and the APD noise figure, considering solely the noise of the input device and neglecting the noise from the shaper and any digital activity, leads to a value of 645 e-rms, which is in good agreement with the measurement. This calculated ENC of 645 e-rms differs from the 453 e-rms presented in Section II-A, as the stray capacitance was originally neglected. To evaluate the contribution from the digital activities in the ASIC and on the PCB to the ENC, it was measured again but this time with only the analog front-end enabled. A negligible improvement was noticed, meaning that the digital activities had negligible effect. It is expected that the digital noise may have a greater impact on the rigid-flex PCB designed for the RatCAP camera caused by the higher density of digital traces near the via interconnecting the detector anodes to the ASIC input, due to the limited real estate. B. Energy Resolution Energy spectra for all channels can be obtained simultaneously in the system by taking the derivative of the measured Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. PRATTE et al.: THE RATCAP FRONT-END ASIC 2733 Fig. 10. Electronic timing jitter at the encoder’s output. The error bars represent the rms deviation of all the channels measured. Also plotted, the minimum and maximum measured jitter as a function of input charge. Ge Fig. 9. Energy spectra of an LSO-APD-ASIC detector module using a source. An energy resolution of 18.7% E : FWHM is measured. (1 = 95 5keV) output trigger rate as a function of the energy threshold. For example, Fig. 9 displays such a spectrum, where the trigger rate data, the fit of the trigger rate data and its derivative as a function of the energy threshold is displayed. An energy resolution FWHM is measured for a typof 18.7% ical channel connected to an APD-LSO detector using a source. C. Timing Jitter and Time Walk The electronic timing jitter and time walk were measured. A voltage pulse from a Tektronix AFG3251 function generator is fed to the test input of the ASIC, where an integrated analog multiplexer allows one to choose which channel to stimulate. A Tektronix TDS6804B oscilloscope is used to histogram the leading edge of the ASIC’s encoder output relative to the function generator trigger signal. The mean and the distribution width of the histogram represent the time walk and the timing jitter, respectively, for a given amount of charge injected in the channel. The measurements were performed without a load at the input, having solely the stray capacitance of 9 pF. Fig. 10 presents the mean, standard deviation, minimum and maximum timing jitter of all the channels measured. Considering the ratio of 2.5 between the photopeak position of the pixel with the greatest charge output to the pixel with the lowest charge output, and assuming an average energy resolution of 20% FWHM, the effective dynamic range is from 5.4 fC to 22.8 fC. Hence a maximum electronic jitter of 1.8 ns rms is expected. An average time walk of 0.7 ns is measured for a shaper signal amplitude between 310 mV and 520 mV, the effective dynamic range where all photopeaks will be aligned using the programmable gain of each channel. D. Timing Resolution and Scintillator Photon Noise Model Validation The photon noise model was validated for two arbitrary channels. Table I presents the measured number of photoelectrons, APD gain and ENC for both channel. To validate this model, the timing resolution due to the photon was measured indirectly by subtracting the noise TABLE I MEASURED CHARACTERISTICS OF THE TWO CHANNELS USED IN THE TIMING RESOLUTION MODEL. THE NUMBER OF PHOTOELECTRONS, APD GAIN AND EQUIVALENT NOISE CHARGE ARE PRESENTED TABLE II COMPARISON OF THE MODEL WITH THE MEASUREMENTS OF THE TIMING RESOLUTION FOR THE TWO CHANNELS UNDER TEST. THE TOTAL TIMING RESOLUTION, ALONG WITH THE CONTRIBUTION FROM THE ELECTRONIC NOISE AND PHOTON NOISE ARE PRESENTED. (ALL RESULTS IN NS RMS). timing resolution due to the electronic noise : the overall measured timing resolution from (13) It is important to note that the timing resolution contribution from the electronic noise has to be measured for an ideal LSO-APD input signal, and not for the delta response of the system. This can be achieved by applying the following voltage pulse using a waveform generator to an injection capacitor tied to the front-end input: (14) where is the total amount of charge injected. The total of the LSO-APD-ASIC module was timing resolution measured with an energy window of 15.5 keV centered on the 511 keV photopeak, in coincidence with a -PMT detector. Table II presents the calculated and measured timing resolution, along with the respective contribution from the electronic noise and photon noise. Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. 2734 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 5, OCTOBER 2008 to the Canadian Microelectronics Corporation for support in the fabrication of previous revisions of the ASIC. REFERENCES [1] J.-F. Pratte, S. Robert, G. D. Geronimo, P. O’Connor, S. Stoll, C. P. R. Fontaine, and R. Lecomte, “Design and performance of 0.18  CMOS charge preamplifier for APD-based PET scanners,” IEEE Trans. Nucl. Sci., vol. 51, no. 5, pp. 1979–1985, Oct. 2004. [2] J.-F. Pratte, G. D. Geronimo, S. Junnarkar, P. O’Connor, B. Yu, S. R. V. Radeka, C. Woody, S. Stoll, P. Vaska, A. Kandasamy, and R. L. Fontaine, “Front-end electronics for the RatCAP mobile animal PET scanner,” IEEE Trans. Nucl. Sci., vol. 51, no. 4, pp. 1318–1323, Aug. 2004. [3] P. Vaska, C. L. Woody, D. J. Schlyer, S. Shokouhi, S. P. Stoll, J.-F. P. P. O’Connor, S. Junnarkar, S. Rescia, B. Yu, M. Purschke, A. K. A. Villanueva, A. Kriplani, V. Radeka, N. Volkow, R. Lecomte, and R. Fontaine, “RatCAP: Miniaturized head-mounted PET for conscious rodent brain imaging,” IEEE Trans. Nucl. Sci., vol. 51, no. 5, pp. 2718–2722, Oct. 2004. [4] A. Kriplani, D. J. Schlyer, P. Vaska, S. P. Stoll, S. Southekal, S. J. P. C. Woody, S. Junnarkar, and J.-F. Pratte, “Non-invasive and selective measurement of the arterial input function using a PET wrist scanner,” in Proc. IEEE Nuclear Science Symp. andMedical Imaging Conf. Rec., San Diego, CA, 2006, vol. 6, pp. 3266–3270. [5] D. Schlyer, P. Vaska, D. Tomasi, C. Woody, S. Solis-Najera, W. Rooney, J.-F. Pratte, S. Junnarkar, S. Stoll, M. Purschke, S.-J. Park, Z. M. S. Southekal, S.-H. Maramraju, S. Krishnamoorthy, A. Kriplani, and P. O’Connor, “Preliminary studies of a simultaneous PET/MRI scanner based on the RatCAP small animal tomograph,” in Proc. IEEE Nuclear Science Symp. and Medical Imaging Conf. Rec., San Diego, CA, 2006, vol. 4, pp. 2340–2344. [6] C. Enz, F. Krummenacher, and E. Vittoz, “An analytical mos transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” J. Analog Integr. Circuits Signal Process., pp. 83–114, 1995. [7] V. Radeka, “Low-noise techniques in detectors,” Annu. Rev. Nucl. Part. Sci., vol. 38, pp. 217–77, 1988. [8] G. D. Geronimo and P. O’Connor, “MOSFET optimization in deep submicron technology for charge amplifiers,” IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 3223–3232, Dec. 2005. [9] G. DeGeronimo and P. O’Connor, “A CMOS fully compensated continuous reset system,” IEEE Trans. Nucl. Sci., vol. 47, no. 4, pp. 1458–1462, Aug. 2000. [10] S. Ohkawa, M. Yoshizawa, and K. Husimi, “Direct synthesis of the gaussian filter for nuclear pulse amplifiers,” Nucl. Instrum. Methods, vol. 138, pp. 85–92, 1976. [11] W.-K. Chen, Passive and Active Filters Theory and Implementations, 1st ed. New York: Wiley, 1986. [12] J.-F. Pratte, C. Pepin, D. Rouleau, O. Menard, J. Mouine, and R. Lecomte, “Design of a fast shaping amplifier for PET/CT APD detectors with depth-of-interaction,” IEEE Trans. Nucl. Sci., vol. 49, no. 5, pp. 2448–2454, Oct. 2002. [13] , G. Knoll, Ed., Radiation Detection and Measurement, 3rd ed. New York: Wiley, 1999. [14] M. Casey, C. Reynolds, D. Binkley, and J. Rochelle, “Analysis of timing performance for an APD-LSO scintillation detector,” Nucl. Instrum. Methods Phys. Res. A, vol. A504, pp. 143–148, 2003. [15] P. Webb, R. McIntyre, and J. Conradi, “Properties of avalanche photodiodes,” RCA Rev., vol. 35, pp. 235–278, 1974. [16] V. Radeka, “Optimum signal-processing for pulse-amplitude spectrometry in the presence of high-rate effects and noise,” IEEE Trans. Nucl. Sci., vol. NS-15, pp. 455–470, 1968. [17] “Avalanche Photodiode: A User Guide, Understanding Avalanche Photodiode for Improving System Performance,” PerkinElmer, Waltham, MA, 2006. [18] M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433–1440, 1989. [19] C. Enz and E. Vittoz, “MOS transistor modeling for low-voltage and low-power analog IC design,” Microelectron. Eng., vol. 39, pp. 59–76, 1997. [20] S. Junnarkar, J. Fried, S. Southekal, J.-F. Pratte, P. O’Connor, V. R. P. Vaska, M. Purschke, D. Tomasi, C. Woody, and R. Fontaine, “Next generation of real time data acquisition, calibration and control system for the RatCAP scanner,” IEEE Trans. Nucl. Sci., vol. 55, no. 1, pp. 220–224, Feb. 2008. m Fig. 11. Coincidence timing resolution between two APD-LSO-ASIC detector modules. Energy threshold was set at 420 keV. The first conclusion is that the model is valid, predicting within 12% the photon noise contribution. Second, it is interesting to notice that the zero-crossing discriminator’s timing resolution is dominated by the photon noise. This is due to the fact that the timing measurement is achieved at the zero-crossing of the shaper’s bipolar signal roughly 280 ns after the first photon being emitted by the scintillator, hence suffering from a large integration of the photons fluctuation and photoelectron statistics from one event to another. The coincidence timing resolution between the two previous LSO-APD-ASIC detector modules was measured for a source, with an energy threshold set at 420 keV. Fig. 11 shows the spectrum, where a coincidence timing resolution of 6.7 ns FWHM was obtained from the fit, which is also in good agreement with the model. The measured coincidence timing resolution, one of the main figures of merit of the LSO-APD-ASIC detector module, is comparable to performance achieved with other LSO-APD based-PET systems in the field [22], [23]. IV. CONCLUSION The ASIC for the RatCAP small animal PET camera was presented. The ASIC is fully functional and is currently used in the BNL RatCAP project, dual-modality PET/MRI, Wrist scanner apparatus, and finally in a coded-aperture gamma-ray imager for Homeland Security applications. The implementation of this new ASIC was justified by the improved performance where the ENC was lowered significantly, programmable gain was embedded to compensate for the light collection and APD gain variations, the timing and energy discriminator were improved, and finally LVDS transceivers were integrated to minimize the digital noise on the readout PCB. A future revision of the ASIC is being discussed, where the timing discriminator would be replaced by an architecture in which the photon noise would be minimized. Also, global and trimming digital to analog converters would be integrated to have independent energy thresholds in each channel. ACKNOWLEDGMENT The authors would like to acknowledge J. Triolo, D. Pinelli, K. Wolniewicz, P. Rehak, S. Rescia, and A. Kandasamy for their contributions and precious advice. The authors are also grateful Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply. PRATTE et al.: THE RATCAP FRONT-END ASIC [21] S.-J. Park, S. Southekal, M. Purschke, S. Junnarkar, J.-F. Pratte, S. Stoll, C. Woody, D. Schlyer, and P. Vaska, “Digital coincidence processing for the RatCAP conscious rat brain PET scanner,” IEEE Trans. Nucl. Sci., vol. 55, no. 1, pp. 510–515, Feb. 2008. [22] M. Bergeron, J. Cadorette, J.-F. Beaudoin, J. Rousseau, M. Dumoulin, M. Lepage, G. Robert, V. Selivanov, M.-A. Tétrault, N. Viscogliosi, T. Dumouchel, S. Thorn, J. DaSilva, R. deKemp, J. Norenberg, R. Fontaine, and R. Lecomte, “Performance evaluation of the labPET APD-based digital PET scanner,” in Proc. IEEE Nuclear Science Symp. and Medical Imaging Conf. Rec., Honolulu, HI, 2007, vol. 6, pp. 4185–4191. 2735 [23] V. Spanoudaki, D. McElroy, and S. Ziegler, “An analog signal processing ASIC for a small animal LSO–APD PET tomograph,” Nucl. Instrum. Methods Phys. Res. A, vol. A564, pp. 451–462, 2006. Authorized licensed use limited to: Brookhaven National Laboratory. Downloaded on January 30, 2009 at 14:50 from IEEE Xplore. Restrictions apply.