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An investigation on steep-slope and low-power nanowire FETs

An investigation on steep-slope and low-power nanowire FETs

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011
Abstract
In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAs- InAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/µm at a supply voltage of 400 mV.

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