IBM System/360 Model 50

IBM System/360 Model 50 console and CPU with front panel

The IBM System/360 Model 50 is a member of the IBM System/360 family of computers. The Model 50 was announced in April 1964 with the other initial models of the family, and first shipped in August 1965 to the Bank of America.

The system has a CPU cycle time of 500 nanoseconds, 25% faster than the Model 40 and 40% slower than the Model 65. Processor storage is magnetic core memory that transfers four bytes per 2 microsecond cycle. It has "protected" and "local" core storage for registers and internal buffers with cycle times of 200 and 500 nanoseconds respectively.

Read-only control storage for microcode employs "balanced capacitor technology" (BCROS) with cycle time of 500 nanoseconds, designed by Anthony Proudman in IBM's Hursley laboratory and implemented by Fernando "Fred" Neves. This technology uses two capacitors to represent each bit.

Features

The Model 50 implements the complete System/360 "universal instruction set" architecture, including floating-point, decimal, and character operations as standard features. The "direct control" instructions are an optional feature. Optional microcode providing compatibility with either the IBM 1410/7010 or 7070/7074 systems is available.

The system comes with four sizes of core memory. The F50, or 2050F is equipped with 65,536 bytes, the G50 has 131,072 bytes, the H50 262,144 bytes, and the I50 524,288 bytes. The system can also attach IBM 2361 Large Capacity Storage (LCS) modules which provide up to 8,388,608 bytes of additional storage, however with a greatly increased memory cycle time of 8 microseconds compared to the 2 microseconds of processor storage.

An IBM 1052 printer/keyboard for use as an operator's console is optional. The I/O options include one channel-to-channel adapter (CTCA) and up to three selector channels. A multiplexer channel for attachment of slow-speed devices is standard on all models. The F50 has 64 subchannels, that is it can attach up to 64 slow-speed devices. The other models have 128 subchannels. This can optionally increase to 256 subchannels on the H50 and I50.

Microcode

The Model 50 uses a 90 bit (or 85 bit, depending on definition) "horizontal microcode" instruction format, with each word containing 15 (or 25) separate fields. There are 2816 words of microcode storage.