DATA SHEET

Part No. Package Code No.

MN2PS00003RF
UBGA433-P-1313A

Publication date: April 2009

SDB00174AEM

MN2PS00003RF Contents
Overview 3 Features 3 Applications 3 Pin Assignments 4 Pin Descriptions 5 Absolute Maximum Ratings . 10 Power Supply Sequence . 12 Recommended Operating Range . 13 Input / Output Capacitance. 14 Electrical Characteristics . 14 Analog Electrical Characteristics 41 DA Converter (3-ch. 10 bit) Characteristics 41 AD Converter (10 bit) Characteristics . 41 42 Clock Generator (PLL) Characteristics 42 Analog Comparator (Analog schmidt ) Characteristics

SDB00174AEM

MN2PS00003RF

MN2PS00003RF
Network Camera System LSI with HD
Overview
High image quality camera signal processing / encoding and network data transmission functions are integrated on a single chip.

Features
HD-Movie function / High quality image processing / High speed signal processing technology Multi-stream (4-ch.) MPEG-4, H.264 Data transmission at 20 Mbps with an on-chip Ethernet MAC Security camera functions (motion detector support, image masking, and bidirectional sound)

Applications
Network camera Security camera

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Pin Assignments

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Pin Descriptions
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 B1 B2 B3 B4 B5 B6 B7 B8 B B B B B B B B B B B B B B B B B B B B B B O B B I/O VSS VSS GPIO74 GPIO76 VDDI GPIO81 CPUAD15 CPUAD18 CPUAD21 CPUAD9 CPUAD12 FR_ALE CPUD22 CPUD19 CPUREB CPUWAIT CPUAD2 CPUD28 CPUD30 CPUD29 FR_BLOCK DRA0 VSS VSS VSS VSS GPIO70 GPIO72 GPIO77 GPIO80 GPIO83 CPUAD17 Pin Name Pin No. B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 B B B B B B B B B O B O O B B B B B B B I/O B B Pin Name CPUAD20 CPUAD7 VDDI FR_RB FR_WP CPUD20 CPUD17 VDDI CPUAD1 CPUAD4 CPUD31 VDDI DRCASB DRA1 VSS VSS LCDCLK LCDOUI7 VSS VSS VSS VSS VSS GPIO79 CPUAD16 CPUAD19 CPUAD8 CPUAD11 FROM_CS CPUD21 CPUD18 CPUWE3B
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Pin No. C17 C18 C19 C20 C21 C22 C23 C24 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24

I/O B B O B

Pin Name CPUAD3 CPUD25 DRWEB CPUD27 VSS VSS

O O B B B

DRA3 DRA4 LCDVD LCDOUT6 LCDOUT3 VSS

B B B B B

GPIO68 GPIO71 GPIO75 GPIO78 CPUAD14 VDD_CPU2

B B B

CPUAD6 CPUAD13 FR_CLE VDD_CPU0_0

B B B B B

CPUD16 CPUWE2B CPUAD5 CPUD24 CPUD26 VSS VSS VSS

O O

DRA7 DRA8 5

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Pin Descriptions (continued)
Pin No. E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 F1 F2 F3 F4 F5 F6 F7 F8 O O B B B O B B O I B B B B B I/O B B B Pin Name LCDOUT1 GPIO28 LCDOUT5 VSS VSS GPIO69 GPIO73 VDD_GPIO0 VDD_GPIO0 GPIO82 VDD_CPU1 CPUAD10 CPUD23 VSS VSS CPUAD0 FR_CYC DRRASB FROM_SEL VSS DRA2 VSS DRA9 DRA11 GPIO26 GPIO25 LCDOUT2 VDD_LCD VSS VSS VSS VSS Pin No. F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 G1 G2 G3 G4 G5 G6 G7 G19 G20 G21 G22 G23 G24 H1 H2 H3 O O I I I O B B B B O B O O I/O VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DRA5 DRA10 VSS VDDI DRA12 GPIO23 VDDI GPIO27 LCDOUT0 LCDHD VSS VSS VDDQ DRA6 DRD25 VSS DRBA0 DRBA1 CCD0 CCD1 CCD2
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Pin Name

Pin No. H4 H5 H6 H19 H20 H21 H22 H23 H24 J1 J2 J3 J4 J5 J6 J19 J20 J21 J22 J23 J24 K1 K2 K3 K4 K5 K6 K19 K20 K21 K22 K23

I/O B B

Pin Name GPIO24 LCDOUT4 VSS VDDQ

B B O B B I I I I

DRD24 DRD26 DRA13 DRDQS2 DRD16 CCD4 CCD5 CCD3 CCD6 VDD2_0 VSS VDDQ

B O B B B I I I I I

DRD27 DRDQM2 DRD28 DRD17 DRD19 CCD8 CCD9 CCD11 CCD10 CCD7 VSS VDDQ

B B B

DRD29 DRD18 DRD30 VDDI 6

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Pin Descriptions (continued)
Pin No. K24 L1 L2 L3 L4 L5 L6 L19 L20 L21 L22 L23 L24 M1 M2 M3 M4 M5 M6 M19 M20 M21 M22 M23 M24 N1 N2 N3 N4 N5 N6 N19 O B B B B B B O B B B B B B B B B B I/O B Pin Name DRAMFCK VDDI GPIO2 GPIO1 GPIO0 VDD_LVDS0 VSS VDDQ DRDQS3 DRD20 DRD31 VDDI DRAMFCKX GPIO3 GPIO6 GPIO5 GPIO4 VDD_LVDS1 VSS VDDQ VDDQ DRDQM3 DRD21 DRD23 DRD22 GPIO7 AFE_SCK AFE_SDO VDD_CCD_0 VSS_LVDS0 VSS VDDQ Pin No. N20 N21 N22 N23 N24 P1 P2 P3 P4 P5 P6 P19 P20 P21 P22 P23 P24 R1 R2 R3 R4 R5 R6 R19 R20 R21 R22 R23 R24 T1 T2 T3 B B B B B B B B B B B B B B B I/O O B B B O B B B B XDCS DRD1 DRD0 DRDQS1 DRDQM1 AFE_CS FCK CCDVD CCDHD VSS_LVDS1 VSS VDDQ DRD4 DRD2 DRD8 DRD9 VDDI VDDI GPIO67 GPIO15 VDD1_0 GPIO66 VSS VDDQ DRD7 DRD5 DRD3 DRD11 DRD10 GPIO12 GPIO9 GPIO65
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Pin Name

Pin No. T4 T5 T6 T19 T20 T21 T22 T23 T24 U1 U2 U3 U4 U5 U6 U19 U20 U21 U22 U23 U24 V1 V2 V3 V4 V5 V6 V19 V20 V21 V22 V23

I/O B

Pin Name GPIO10 VSS VSS VDDQ

B O B B B B B B B B

GPIO58 DRDQM0 DRD6 DRD13 DRD12 GPIO14 GPIO8 GPIO55 GPIO61 GPIO60 VSS VDD0_0

I B B B B B B B B B

TEST0 GPIO21 DRDQS0 DRD15 DRD14 GPIO54 GPIO52 GPIO13 GPIO11 GPIO59 VSS VDD0_1

I B B

PLLBYPASS GPIO19 GPIO57 VDDI 7

MN2PS00003RF
Pin Descriptions (continued)
Pin No. V24 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 Y1 Y2 Y3 Y4 Y5 Y6 Y7 B B B I B I B B B B I/O O B Pin Name DRCKE GPIO56 VDDI VSS GPIO63 GPIO62 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GPIO22 TRACEON GPIO17 CPUSEL GPIO53 GPIO51 VSS GPIO49 VSS VSS GPIO46 Pin No. Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 I B B B B B B B I I I I I B B I/O B Pin Name GPIO43 VSS GPIO39 GPIP29 AVSS_AD0 LENADC8 LENADC2 ADC10 AVSS_AD2 ADC0 VREF_DA PLLVDD1 VSS VSS VSS GPIO20 GPIO18 GPIO16 RSTB VSS VSS VSS GPIO47 GPIO45 VDD_GPIO1_0 GPIO37 GPIO33 USBPVDD USBAVSS2 USBAVSS1 LENADC4 AVDD_AD1
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Pin No. AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23

I/O I I ADC6 ADC4

Pin Name

AVDD_DA PLLVSS1 VSS VSS VSS B O B B B DBGD MCK24O GPIO64 GPIO50 GPIO48 VSS VSS B B GPIO36 GPIO35 VDD_GPIO1_1 USBVSS USBPVSS USBAVDD2 I I I I I O LENADC10 LENADC6 LENADC0 ADC8 ADC2 HD_PBOUT AVSS_DA PLLVDD2 PLLVDD3 VSS VSS I DBGCK 8

MN2PS00003RF
Pin Descriptions (continued)
Pin No. AB24 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 I I I I I I B B B B I/O I Pin Name MCK24I VSS VSS VSS GPIO42 GPIO40 GPIO32 GPIO30 USBVDD RREFEXT USBAVDD1 VDDI LENADC9 LENADC5 LENADC1 ADC11 ADC7 Pin No. AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 B B B B B I O I/O I ADC3 AVDD_AD0 VIDEOOUT IREF_DA PLLTESTIO PLLVSS3 VSS VSS VSS VSS GPIO44 GPIO41 GPIO38 GPIO34 GPIO31 VDDI GPANAIO Pin Name Pin No. AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 O I I I I I I/O B B Pin Name USBSIGDM USBSIGDP AVDD_AD2 LENADC7 LENADC3 AVSS_AD1 ADC9 ADC5 ADC1 VDDI COMP_DA HD_PROUT PLLVSS2 VSS VSS

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Absolute Maximum Ratings
VSS = AVSS_AD = AVSS_DA = PLLVSS = USBAVSS = USBPVSS = USBVSS = VSS _LVDS = 0 V Parameter A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 External supply voltage for GPIO External supply voltage for LCD External supply voltage for CCD External supply voltage for ADC External supply voltage for DAC External supply voltage for PLL External supply voltage for USB External supply voltage for LVDS Internal supply voltage Internal supply voltage for USB External supply voltage for CPU External supply voltage for DRAM External supply voltage Symbol VDD0 VDD1 VDD2 VDD_Q VDD_CPU0 VDD_CPU1 VDD_CPU2 VDD_GP0 VDD_GP1 VDD_LCD VDD_CCD AVDD_AD AVDD_DA PLLVDD USBAVDD USBPVDD VDD_LVDS VDDI USBVDD Rating 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +4.6 0.3 to +1.7 0.3 to +1.7 V V V V V V V V V V *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 *1, 2 V *1, 2 V *1, 2 V *1, 2 Unit Notes

Notes)*1: When outside power supply or the inside power supply voltage does OFF, a penetration electric current flows, and the output is in a condition of the uncertainty. But please do ON at the same time as much as possible. *2: The table show a power supply terminal name corresponding to the sign in the production standards. Symbol VDD0 VDD1 VDD2 VDD_Q VDD_CPU0 VDD_CPU1 VDD_CPU2 VDD_GP0 VDD_GP1 Supply Pin Name VDD0_0, VDD0_1 VDD1_0 VDD2_0 VDDQ VDD_CPU0_0 VDD_CPU1 VDD_CPU2 VDD_GPIO0 VDD_GPIO1_0, VDD_GPIO1_1 Symbol VDD_LCD VDD_CCD AVDD_AD AVDD_DA PLLVDD Supply Pin Name VDD_LCD VDD_CCD_0 AVDD_AD0, AVDD_AD1, AVDD_AD2 AVDD_DA PLLVDD1, PLLVDD2, PLLVDD3 Symbol VSS AVSS_AD AVSS_DA PLLVSS VSS AVSS_AD0, AVSS_ADI, AVSS_AD2 AVSS_DA PLLVSS1, PLLVSS2, PLLVSS3 Supply Pin Name

USBAVSS USBAVSS1, USBAVSS2 USBPVSS USBPVSS USBVSS VSS_LVDS USBVSS VSS_LVDS0, VSS_LVDS1

USBAVDD USBAVDD1, USBAVDD2 USBPVDD USBPVDD VDD_LVDS VDDI USBVDD VDD_LVDS0, VDD_LVDS1 VDDI USBVDD
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Absolute Maximum Ratings (continued)
VSS = AVSS_AD = AVSS_DA = PLLVSS = USBAVSS = USBPVSS = USBVSS = VSS _LVDS = 0 V Parameter A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 Input voltage Output voltage Output current (TYPE-HL4) Output current (TYPE-HL8) Output current (TYPE-HL12) Output current (TYPE-HL60) Input current power supply Power dissipation Operating temperature Storage temperature IV PD Topr Tstg IO Symbol VI VO Rating 0.3 to VDD + 0.3 (max. 4.6) 0.3 to VDD + 0.3 (max. 4.6) 12 24 36 60 60 / pin 960 30 to +85 50 to +150 Unit V V mA mA mA mA mA mW C C Notes

Notes) 1. TYPE-HL4 pin : FCK, CPUD16 to 31, DBGD, GPIO0 to 22, GPIO29 to 67, CCDHD,CCDVD,CPUAD0 to 21, CPUWE2B to 3B, FR_RB, FR_WP, AFE_CS, CPUREB, FR_ALE, FR_CLE, FR_CYC, AFE_SCK, AFE_SD0, CPUWAIT, FROM_CS, FR_BLOCK TYPE-HL8 pin : GPIO23 to 28, GPIO68 to 83, LCDHD, LCDVD, LCDCLK, LCDOUT0 to 7 TYPE-HL12 pin : DRA0 to 13, DRD0 to 31, DRBA0 to 1, XDCS, DRCKE, DRDQM0 to 3, DRDQS0 to 3, DRWEB, DRCASB, DRRASB TYPE-HL60 pin : DRAMFCK, DRAMFCKX 2. The absolute maximum ratings are the limit values beyond which the LSI may be damaged and proper operation is not assured. 3. Please connect all power supply terminals to each power supply directly outside. 4. Please connect the TESTO terminal and PLLTESTIO terminal to VSS directly outside. 5. Please make the PLLBYPASS terminal OPEN or VSS fixation.

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Power Supply Sequence
Parameter Time difference between rising time and falling time Reset signal pulse width Symbol tr1, tf1 tr2, tf2 trsb Conditions VDD 90% VDD 90% VDD 90%, RSTB 70% Min 125 125 (*1) Typ Max 125 125 Unit ms ms ms

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Recommended Operating Range
VSS = AVSS_AD = AVSS_DA = PLLVSS = USBAVSS = USBPVSS = USBVSS = VSS _LVDS = 0 V Parameter B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 Internal supply voltage Ambient temperature Input rise time Input fall time Oscillation frequency Recommended external capacitance Recommended external feedback resistance External supply voltage Symbol VDD0 VDD1 VDD2 VDD_Q VDD_CPU0 VDD_CPU1 VDD_CPU2 VDD_GP0 VDD_GP1 VDD_LCD VDD_CCD AVDD_AD AVDD_DA PLLVDD USBAVDD USBPVDD VDD_LVDS VDDI USBVDD Ta tr tf fOSC1 CXI7 CXO7 Rf7 24 MHz Xtal VDD0 = 3.0 V External feedback resistor VI = VDD or VSS , VDD0 = 3.0 V 24 Conditions Limits Min 3.0 1.65 3.0 1.7 1.65 1.65 1.65 1.65 3.0 1.65 1.65 3.0 3.0 3.0 3.0 3.0 3.0 1.08 1.08 30 Typ 3.3 1.8 3.3 1.8 1.8 1.8 1.8 1.8 3.3 1.8 1.8 3.3 3.3 3.3 3.3 3.3 3.3 1.2 1.2 Max 3.6 3.6 3.6 1.9 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 1.32 1.32 85 30 30 Unit V V V V V V V V V V V V V V V V V V V C ns ns MHz pF k Notes *1 *1,2

Notes) *1: The oscillation characteristics differ according to the conditions, i.e., type of oscillator or external capacitors' values. Select the appropriate conditions specified by the oscillator manufacturer. *2: VDD shows all IO power without VDD0 supplies. MCK24O MCK24I

Rf7
Note) Consult the manufacturer to use oscillator, value of CXI7 , CXO7 , Rf7

Oscillator

CXI7

CXO7

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Input / Output Capacitance
Parameter C1 C2 C3 Input terminal Output terminal I/O terminal Symbol CIN COUT CI/O VDD = VI = 0 V, f = 1 MHz, Ta = 25C Conditions Limits Min Typ 2.5 2.5 2.5 Max 4 4 4 Unit pF pF pF Notes *1 *1 *1

Notes) 1. Capacitance values reflect I/O cell capacitance only (excluding analog and oscillation cells, and NOT including package capacitance). 2. *1: VDD shows all IO power supplies.

Electrical Characteristics
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Static supply current (@25C) IDDS D2 Static supply current (@85C) External power supply operating supply current Analog power supply operating supply current Internal power supply operating supply current Symbol Conditions VI (pull-up) = OPEN, VI (pull-down) = OPEN, VI (XI) = VDD0 *1 Input pins and bi-directional pins in the Hi-Z state are simultaneously connected to either VDD input levels. VI = VDD or VSS , f = 216 MHz, VDD18V = 1.8 V *2 AVDD33V = 3.3 V *3 VDD_LVDS = 3.3 V VDD_GP1 = 3.3 V VDD0 , 2 = 3.3 V VDDI = 1.2 V USBVDD = 1.2 V output open Limits Min Typ 7 Max 70 Unit

D1

mA

20

360

mA

D3

IDDO

20

39

mA

D4

IADDO

42

84

mA

D5

IDDIO

120

530

mA

Notes) *1: VDD0, which is applied to the XI pin, must be different from the power supply for measuring IDDS. *2: VDD18V = VDD_Q , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD, VDD_CCD, VDDI *3: AVDD33V = AVDD_AD, AVDD_DA, PLLVDD, USBAVDD, USBPVDD, VDD_LVDS

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Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input LVCMOS level with pull-up resistor (controllable) : ADC0 to 11, LENADC0 to 10 D6 D7 D8 D9 Input voltage high level Input voltage low level Pull-up resistor Input leakage current VIH VIL RIH ILI VI = 0.0 V VI = AVDD_AD or VSS pull-up resistor = OFF AVDD_AD 0.7 0 10 30 AVDD_AD AVDD_AD 0.3 90 5 V V k A

Input LVCMOS level with pull-down resistor (controllable) : CCD0 to 11 D10 D11 D12 D13 Input voltage high level Input voltage low level Pull-down resistor Input leakage current VIH VIL RIL ILI VI = VDD_CCD VDD_CCD = 3.0 V to 3.6 V VI = VDD_CCD or VSS pull-down resistor = OFF VDD_CCD 0.7 0 10 30 VDD_CCD VDD_CCD 0.3 90 5 V V k A

Input LVCMOS level : FROM_SEL D14 D15 D16 Input voltage high level Input voltage low level Input leakage current VIH VIL ILI VI = VDD_CPU0 or VSS VDD_CPU0 0.7 0 VDD_CPU0 VDD_CPU0 0.3 5 V V A

Input LVCMOS level with pull-down resistor : CPUSEL D17 D18 D19 D20 Input voltage high level Input voltage low level Pull-down resistor Input leakage current VIH VIL RIL ILI VI = VDD0 VDD0 = 3.0 V to 3.6 V VI = VDD0 or VSS pull-down resistor = OFF VDD0 0.7 0 10 30 VDD0 VDD0 0.3 90 5 V V k A

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Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input LVCMOS level with pull-down resistor : TRACEON, PLLBYPASS D21 D22 D23 D24 Input voltage high level Input voltage low level Pull-down resistor Input leakage current VIH VIL RIL ILI VI = VDD0 VDD0 = 3.0 V to 3.6 V VI = VDD0 or VSS pull-down resistor = OFF VDD0 0.7 0 10 30 VDD0 VDD0 0.3 90 5 V V k A

Input LVCMOS level schmidt : RSTB D25 D26 Input threshold voltage * Input leakage current VT+ VT ILI VDD1 = 3.0 V to 3.6 V VI = VDD1 or VSS 1.85 VDD1 0.3 1.45 5 VDD1 0.7 V A

Input LVCMOS level schmidt with pull-up resistor : DBGCK D27 Input threshold voltage * VT+ VT RIH ILI VDD0 = 3.0 V to 3.6 V VI = 0.0 V VDD0 = 3.0 V to 3.6 V VI = VDD0 or VSS pull-up resistor = OFF 1.85 VDD0 0.3 10 1.45 30 90 5 VDD0 0.7 V

D28 D29

Pull-up resistor Input leakage current

k A

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level : CPUREB, FROM_CS D30 D31 D32 D33 D34 D35 D36 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CPU0 or VSS IOL = 0.7 mA, VI = VDD_CPU0 or VSS IOH = 0.8 mA, VI = VDD_CPU0 or VSS IOL = 1.4 mA, VI = VDD_CPU0 or VSS VO = VDD_CPU0 or VSS VDD_CPU0 0.8 0.3 5 VDD_CPU0 0.7 0 VDD_CPU0 0.8 0.3 VDD_CPU0 VDD_CPU0 0.3 V V V V V V A

Input/output LVCMOS level with pull-up resistor (controllable) : AFE_CS, AFE_SCK, AFE_SD0 VT+ D37 Input threshold voltage * VT D38 D39 D40 D41 D42 D43 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VOH VOL VOH VOL RIH ILO IOH = 0.4 mA, VI = VDD_CCD or VSS IOL = 0.7 mA, VI = VDD_CCD or VSS IOH = 0.8 mA, VI = VDD_CCD or VSS IOL = 1.4 mA, VI = VDD_CCD or VSS VI = 0.0 V VDD_CCD = 3.0 V to 3.6 V VO = VDD_CCD or VSS pull-up resistor = OFF 10 30 VDD_CCD 0.8 0.3 90 5 VDD_CCD = 3.0 V to 3.6 V VDD_CCD 0.3 VDD_CCD 0.8 0.3 1.85 1.45 V V V V k A VDD_CCD 0.7

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt : CCDHD, CCDVD VT+ D44 Input threshold voltage * VT D45 D46 D47 D48 D49 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CCD or VSS IOL = 0.7 mA, VI = VDD_CCD or VSS IOH = 0.8 mA, VI = VDD_CCD or VSS IOL = 1.4 mA, VI = VDD_CCD or VSS VO = VDD_CCD or VSS VDD_CCD 0.8 0.3 5 VDD_CCD = 3.0 V to 3.6 V VDD_CCD 0.3 VDD_CCD 0.8 0.3 1.85 1.45 V V V V A VDD_CCD 0.7

Output LVCMOS level : LCDCLK D50 D51 D52 D53 Output voltage high level Output voltage low level Output voltage high level Output voltage low level VOH VOL VOH VOL IOH = 0.8 mA, VI = VDD_LCD or VSS IOL = 1.4 mA, VI = VDD_LCD or VSS IOH = 1.6 mA, VI = VDD_LCD or VSS IOL = 2.8 mA, VI = VDD_LCD or VSS VO = Hi-Z VI = VDD_LCD or VSS VO = VDD_LCD or VSS VDD_LCD 0.8 0.3 VDD_LCD 0.8 0.3 V V V V

D54

Output leakage current

ILO

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

SDB00174AEM

18

MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-down resistor (controllable) : LCDHD, LCDVD, LCDOUT4 to 5 D55 D56 D57 D58 D59 D60 D61 D62 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current VIH VIL VOH VOL VOH VOL RIL ILO IOH = 0.8 mA, VI = VDD_LCD or VSS IOL = 1.4 mA, VI = VDD_LCD or VSS IOH = 1.6 mA, VI = VDD_LCD or VSS IOL = 2.8 mA, VI = VDD_LCD or VSS VI = VDD_LCD or VSS VDD_LCD = 3.0 V to 3.6 V VO = VDD_LCD or VSS pull-down resistor = OFF 10 30 VDD_LCD 0.8 0.3 90 5 VDD_LCD 0.7 0 VDD_LCD 0.8 0.3 VDD_LCD VDD_LCD 0.3 V V V V V V k A

Input/output LVCMOS level : LCDOUT0 to 3, LCDOUT6 to 7 D63 D64 D65 D66 D67 D68 D69 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.8 mA, VI = VDD_LCD or VSS IOL = 1.4 mA, VI = VDD_LCD or VSS IOH = 1.6 mA, VI = VDD_LCD or VSS IOL = 2.8 mA, VI = VDD_LCD or VSS VO = VDD_LCD or VSS VDD_LCD 0.8 0.3 5 VDD_LCD 0.7 0 VDD_LCD 0.8 0.3 VDD_LCD VDD_LCD 0.3 V V V V V V A

SDB00174AEM

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level : GPIO23 to 28 D70 D71 D72 D73 D74 D75 D76 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 4.0 mA, VI = VDD2 or VSS IOL = 4.0 mA, VI = VDD2 or VSS IOH = 8.0 mA, VI = VDD2 or VSS IOL = 8.0 mA, VI = VDD2 or VSS VO = VDD2 or VSS VDD2 0.8 0.3 5 VDD2 0.7 0 VDD2 0.8 0.3 VDD2 VDD2 0.3 V V V V V V A

Input/output LVCMOS level :GPIO78 to 83 D77 D78 D79 D80 D81 D82 D83 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.8 mA, VI = VDD_GP0 or VSS IOL = 1.4 mA, VI = VDD_GP0 or VSS IOH = 1.6 mA, VI = VDD_GP0 or VSS IOL = 2.8 mA, VI = VDD_GP0 or VSS VO = VDD_GP0 or VSS VDD_GP0 0.8 0.3 5 VDD_GP0 0.7 0 VDD_GP0 0.8 0.3 VDD_GP0 VDD_GP0 0.3 V V V V V V A

SDB00174AEM

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-up resistor : FR_RB D84 D85 D86 D87 D88 D89 D90 D91 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VIH VIL VOH VOL VOH VOL RIH ILO IOH = 0.4 mA, VI = VDD_CPU0 or VSS IOL = 0.7 mA, VI = VDD_CPU0 or VSS IOH = 0.8 mA, VI = VDD_CPU0 or VSS IOL = 1.4 mA, VI = VDD_CPU0 or VSS VI = 0.0 V VDD_CPU0 = 3.0 V to 3.6 V VO = VDD_CPU0 or VSS pull-up resistor = OFF 10 30 VDD_CPU0 0.8 0.3 90 5 VDD_CPU0 0.7 0 VDD_CPU0 0.8 0.3 VDD_CPU0 VDD_CPU0 0.3 V V V V V V k A

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-up resistor (controllable) : CPUWAIT D92 D93 D94 D95 D96 D97 D98 D99 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VIH VIL VOH VOL VOH VOL RIH ILO IOH = 0.4 mA, VI = VDD_CPU0 or VSS IOL = 0.7 mA, VI = VDD_CPU0 or VSS IOH = 0.8 mA, VI = VDD_CPU0 or VSS IOL = 1.4 mA, VI = VDD_CPU0 or VSS VI = 0.0 V VDD_CPU0 = 3.0 V to 3.6 V VO = VDD_CPU0 or VSS pull-up resistor = OFF 10 30 VDD_CPU0 0.8 0.3 90 5 VDD_CPU0 0.7 0 VDD_CPU0 0.8 0.3 VDD_CPU0 VDD_CPU0 0.3 V V V V V V k A

SDB00174AEM

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-up resistor (controllable) : GPIO19, GPIO22, GPIO57 to 58 D100 D101 D102 D103 D104 D105 D106 D107 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VIH VIL VOH VOL VOH VOL RIH ILO IOH = 2.0 mA, VI = VDD0 or VSS IOL = 2.0 mA, VI = VDD0 or VSS IOH = 4.0 mA, VI = VDD0 or VSS IOL = 4.0 mA, VI = VDD0 or VSS VI = 0.0 V VDD0 = 3.0 V to 3.6 V VO = VDD0 or VSS pull-up resistor = OFF 10 30 VDD0 0.8 0.3 90 5 VDD0 0.7 0 VDD0 0.8 0.3 VDD0 VDD0 0.3 V V V V V V k A

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-down resistor (controllable) : GPIO17, GPIO21 D108 Input threshold voltage * VT+ VT VOH VOL VOH VOL RIL ILO VDD0 = 3.0 V to 3.6 V IOH = 2.0 mA, VI = VDD0 or VSS IOL = 2.0 mA, VI = VDD0 or VSS IOH = 4.0 mA, VI = VDD0 or VSS IOL = 4.0 mA, VI = VDD0 or VSS VI = VDD0 VDD0 = 3.0 V to 3.6 V VO = VDD0 or VSS pull-down resistor = OFF 10 30 VDD0 0.8 0.3 90 5 1.85 VDD0 0.3 VDD0 0.8 0.3 1.45 VDD0 0.7 V

D109 D110 D111 D112 D113 D114

Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current

V V V V k A

Input/output LVCMOS level with pull-down resistor (controllable) : GPIO56 D115 D116 D117 D118 D119 D120 D121 D122 Input voltage high level Input voltage low level Output voltage low level Output voltage high level Output voltage low level Output voltage high level Pull-down resistor Output leakage current VIH VIL VOH VOL VOH VOL RIL ILO IOH = 3.9 mA, VI = VDD1 or VSS IOL = 5.3 mA, VI = VDD1 or VSS IOH = 5.8 mA, VI = VDD1 or VSS IOL = 6.6 mA, VI = VDD1 or VSS VI = VDD1 VDD1 = 3.0 V to 3.6 V VO = VDD1 or VSS pull-down resistor = OFF 33 100 VDD1 0.8 0.3 300 5 VDD1 0.7 0 VDD1 0.8 0.3 VDD1 VDD1 0.3 V V V V V V k A

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.
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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-up resistor (controllable) : GPIO70, GPIO73, GPIO76 to 58 D123 D124 D125 D126 D127 D128 D129 D130 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VIH VIL VOH VOL VOH VOL RIH ILO IOH = 0.8 mA, VI = VDD_GP0 or VSS IOL = 1.4 mA, VI = VDD_GP0 or VSS IOH = 1.6 mA, VI = VDD_GP0 or VSS IOL = 2.8 mA, VI = VDD_GP0 or VSS VI = 0.0 V VDD_GP0 = 3.0 V to 3.6 V VO = VDD_GP0 or VSS pull-up resistor = OFF 10 30 VDD_GP0 0.8 0.3 90 5 VDD_GP0 0.7 0 VDD_GP0 0.8 0.3 VDD_GP0 VDD_GP0 0.3 V V V V V V k A

Input/output LVCMOS level with pull-up resistor (controllable) : GPIO59 to 61 D131 D132 D133 D134 D135 D136 D137 D138 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VIH VIL VOH VOL VOH VOL RIH ILO IOH = 0.4 mA, VI = VDD1 or VSS IOL = 0.7 mA, VI = VDD1 or VSS IOH = 0.8 mA, VI = VDD1 or VSS IOL = 1.4 mA, VI = VDD1 or VSS VI = 0.0 V VDD1 = 3.0 V to 3.6 V VO = VDD1 or VSS pull-up resistor = OFF
SDB00174AEM

VDD1 0.7 0 VDD1 0.8

VDD1 VDD1 0.3

V V V

0.3 VDD1 0.8 0.3 10 30 90 5

V V V k A 25

MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-up resistor (controllable) : GPIO34 to 35, GPIO44 to 45 D139 D140 D141 D142 D143 D144 D145 D146 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VIH VIL VOH VOL VOH VOL RIH ILO IOH = 2 mA, VI = VDD_GP1 or VSS IOL = 2 mA, VI = VDD_GP1 or VSS IOH = 4 mA, VI = VDD_GP1 or VSS IOL = 4 mA, VI = VDD_GP1 or VSS VI = 0.0 V VDD_GP1 = 3.0 V to 3.6 V VO = VDD_GP1 or VSS pull-up resistor = OFF 10 30 VDD_GP1 0.8 0.3 90 5 VDD_GP1 0.7 0 VDD_GP1 0.8 0.3 VDD_GP1 VDD_GP1 0.3 V V V V V V k A

Input/output LVCMOS level : CPUWE2B, CPUWE3B D147 D148 D149 D150 D151 D152 D153 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CPU0 or VSS IOL = 0.7 mA, VI = VDD_CPU0 or VSS IOH = 0.8 mA, VI = VDD_CPU0 or VSS IOL = 1.4 mA, VI = VDD_CPU0 or VSS VO = VDD_CPU0 or VSS VDD_CPU0 0.8 0.3 5 VDD_CPU0 0.7 0 VDD_CPU0 0.8 0.3 VDD_CPU0 VDD_CPU0 0.3 V V V V V V A

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level : CPUD16 to 31, CPUAD0 to 5, FR_WP, FR_ALE, FR_CLE D154 D155 D156 D157 D158 D159 D160 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CPU0 or VSS IOL = 0.7 mA, VI = VDD_CPU0 or VSS IOH = 0.8 mA, VI = VDD_CPU0 or VSS IOL = 1.4 mA, VI = VDD_CPU0 or VSS VO = VDD_CPU0 or VSS VDD_CPU0 0.8 0.3 5 VDD_CPU0 0.7 0 VDD_CPU0 0.8 0.3 VDD_CPU0 VDD_CPU0 0.3 V V V V V V A

Input/output LVCMOS level : CPUAD6 to 13 D161 D162 D163 D164 D165 D166 D167 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CPU1 or VSS IOL = 0.7 mA, VI = VDD_CPU1 or VSS IOH = 0.8 mA, VI = VDD_CPU1 or VSS IOL = 1.4 mA, VI = VDD_CPU1 or VSS VO = VDD_CPU1 or VSS VDD_CPU1 0.8 0.3 5 VDD_CPU1 0.7 0 VDD_CPU1 0.8 0.3 VDD_CPU1 VDD_CPU1 0.3 V V V V V V A

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level : CPUAD14 to 21 D168 D169 D170 D171 D172 D173 D174 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VIH VIL VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CPU2 or VSS IOL = 0.7 mA, VI = VDD_CPU2 or VSS IOH = 0.8 mA, VI = VDD_CPU2 or VSS IOL = 1.4 mA, VI = VDD_CPU2 or VSS VO = VDD_CPU2 or VSS VDD_CPU2 0.8 0.3 5 VDD_CPU2 0.7 0 VDD_CPU2 0.8 0.3 VDD_CPU2 VDD_CPU2 0.3 V V V V V V A

Input/output LVCMOS level with pull-down resistor (controllable) : GPIO66 to 67 D175 D176 D177 D178 D179 D180 D181 D182 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current VIH VIL VOH VOL VOH VOL RIL ILO IOH = 0.4 mA, VI = VDD1 or VSS IOL = 0.7 mA, VI = VDD1 or VSS IOH = 0.8 mA, VI = VDD1 or VSS IOL = 1.4 mA, VI = VDD1 or VSS VI = VDD1 VDD1 = 3.0 V to 3.6 V VO = VDD1 or VSS pull-down resistor = OFF 10 30 VDD1 0.8 0.3 90 5 VDD1 0.7 0 VDD1 0.8 0.3 VDD1 VDD1 0.3 V V V V V V k A

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-down resistor (controllable) : GPIO29, GPIO36 to 39, GPIO40, GPIO63 to 64 D183 D184 D185 D186 D187 D188 D189 D190 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current VIH VIL VOH VOL VOH VOL RIL ILO IOH = 2 mA, VI = VDD_GP1 or VSS IOL = 2 mA, VI = VDD_GP1 or VSS IOH = 4 mA, VI = VDD_GP1 or VSS IOL = 4 mA, VI = VDD_GP1 or VSS VI = VDD_GP1 VDD_GP1 = 3.0 V to 3.6 V VO = VDD_GP1 or VSS pull-down resistor = OFF 10 30 VDD_GP1 0.8 0.3 90 5 VDD_GP1 0.7 0 VDD_GP1 0.8 0.3 VDD_GP1 VDD_GP1 0.3 V V V V V V k A

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-down resistor (controllable) : FR_CYC, FR_BLOCK D191 D192 D193 D194 D195 D196 D197 D198 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current VIH VIL VOH VOL VOH VOL RIL ILO IOH = 0.4 mA, VI = VDD_CPU0 or VSS IOL = 0.7 mA, VI = VDD_CPU0 or VSS IOH = 0.8 mA, VI = VDD_CPU0 or VSS IOL = 1.4 mA, VI = VDD_CPU0 or VSS VI = VDD_CPU0 VDD_CPU0 = 3.0 V to 3.6 V VO = VDD_CPU0 or VSS pull-down resistor = OFF 10 30 VDD_CPU0 0.8 0.3 90 5 VDD_CPU0 0.7 0 VDD_CPU0 0.8 0.3 VDD_CPU0 VDD_CPU0 0.3 V V V V V V k A

Input/output LVCMOS level schmidt : FCK VT+ D199 Input threshold voltage * VT D200 D201 D202 D203 D204 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VOH VOL VOH VOL ILO IOH = 0.4 mA, VI = VDD_CCD or VSS IOL = 0.7 mA, VI = VDD_CCD or VSS IOH = 0.8 mA, VI = VDD_CCD or VSS IOL = 1.4 mA, VI = VDD_CCD or VSS VO = VDD_CCD or VSS VDD_CCD 0.8 0.3 5 VDD_CCD = 3.0 V to 3.6 V VDD_CCD 0.3 VDD_CCD 0.8 0.3 1.85 1.45 V V V V A VDD_CCD 0.7

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.
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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-up resistor (controllable) : DBGD D205 Input threshold voltage * VT+ VT VOH VOL RIH ILO VDD0 = 3.0 V to 3.6 V IOH = 4.0 mA, VI = VDD0 or VSS IOL = 4.0 mA, VI = VDD0 or VSS VI = 0.0 V VDD0 = 3.0 V to 3.6 V VO = VDD0 or VSS pull-up resistor = OFF 10 30 1.85 VDD0 0.3 VDD0 0.8 0.3 90 5 1.45 VDD0 0.7 V

D206 D207 D208 D209

Output voltage high level Output voltage low level Pull-up resistor Output leakage current

V V k A

Input/output LVCMOS level schmidt with pull-up resistor (controllable) : GPIO9, GPIO12 to 13 D210 Input threshold voltage * VT+ VT VOH VOL VOH VOL RIH ILO VDD1 = 3.0 V to 3.6 V IOH = 0.4 mA, VI = VDD1 or VSS IOL = 0.7 mA, VI = VDD1 or VSS IOH = 0.8 mA, VI = VDD1 or VSS IOL = 1.4 mA, VI = VDD1 or VSS VI = 0.0 V VDD1 = 3.0 V to 3.6 V VO = VDD1 or VSS pull-up resistor = OFF 10 30 VDD1 0.8 0.3 90 5 1.85 VDD1 0.3 VDD1 0.8 0.3 1.45 VDD1 0.7 V

D211 D212 D213 D214 D215 D216

Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current

V V V V k A

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-up resistor (controllable) : GPIO18, GPIO20 D217 Input threshold voltage * VT+ VT VOH VOL VOH VOL RIH ILO VDD0 = 3.0 V to 3.6 V IOH = 2.0 mA, VI = VDD0 or VSS IOL = 2.0 mA, VI = VDD0 or VSS IOH = 4.0 mA, VI = VDD0 or VSS IOL = 4.0 mA, VI = VDD0 or VSS VI = 0.0 V VDD0 = 3.0 V to 3.6 V VO = VDD0 or VSS pull-up resistor = OFF 10 30 VDD0 0.8 0.3 90 5 1.85 VDD0 0.3 VDD0 0.8 0.3 1.45 VDD0 0.7 V

D218 D219 D220 D221 D222 D223

Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current

V V V V k A

Input/output LVCMOS level schmidt with pull-up resistor (controllable) : GPIO51, GPIO62, GPIO65 D224 Input threshold voltage * VT+ VT VOH VOL VOH VOL RIH ILO VDD1 = 3.0 V to 3.6 V IOH = 0.4 mA, VI = VDD1 or VSS IOL = 0.7 mA, VI = VDD1 or VSS IOH = 0.8 mA, VI = VDD1 or VSS IOL = 1.4 mA, VI = VDD1 or VSS VI = 0.0 V VDD1 = 3.0 V to 3.6 V VO = VDD1 or VSS pull-up resistor = OFF 10 30 VDD1 0.8 0.3 90 5 1.85 VDD1 0.3 VDD1 0.8 0.3 1.45 VDD1 0.7 V

D225 D226 D227 D228 D229 D230

Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current

V V V V k A

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-up resistor (controllable) : GPIO68 to 69, GPIO71 to 72, GPIO74 to 75 VT+ D231 Input threshold voltage * VT D232 D233 D234 D235 D236 D237 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VOH VOL VOH VOL RIH ILO IOH = 0.8 mA, VI = VDD_GP0 or VSS IOL = 1.4 mA, VI = VDD_GP0 or VSS IOH = 1.6 mA, VI = VDD_GP0 or VSS IOL = 2.8 mA, VI = VDD_GP0 or VSS VI = 0.0 V VDD_GP0 = 3.0 V to 3.6 V VO = VDD_GP0 or VSS pull-up resistor = OFF 10 30 VDD_GP0 0.8 0.3 90 5 VDD_GP0 = 3.0 V to 3.6 V VDD_GP0 0.3 VDD_GP0 0.8 0.3 1.85 1.45 V V V V k A VDD_GP0 0.7

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-up resistor (controllable) : GPIO32 to 33, GPIO41 to 43 VT+ D238 Input threshold voltage * VT D239 D240 D241 D242 D243 D244 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-up resistor Output leakage current VOH VOL VOH VOL RIH ILO IOH = 2 mA, VI = VDD_GP1 or VSS IOL = 2 mA, VI = VDD_GP1 or VSS IOH = 4 mA, VI = VDD_GP1 or VSS IOL = 4 mA, VI = VDD_GP1 or VSS VI = 0.0 V VDD_GP1 = 3.0 V to 3.6 V VO = VDD_GP1 or VSS pull-up resistor = OFF 10 30 VDD_GP1 0.8 0.3 90 5 VDD_GP1 = 3.0 V to 3.6 V VDD_GP1 0.3 VDD_GP1 0.8 0.3 1.85 1.45 V V V V k A VDD_GP1 0.7

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-down resistor (controllable) : GPIO0 to 7 VT+ D245 Input threshold voltage * VT D246 D247 D248 D249 D250 D251 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current VOH VOL VOH VOL RIL ILO IOH = 0.4 mA, VI = VDD_CCD or VSS IOL = 0.7 mA, VI = VDD_CCD or VSS IOH = 0.8 mA, VI = VDD_CCD or VSS IOL = 1.4 mA, VI = VDD_CCD or VSS VI = VDD_CCD VDD_CCD = 3.0 V to 3.6 V VO = VDD_CCD or VSS pull-down resistor = OFF 10 30 VDD_CCD 0.8 0.3 90 5 VDD_CCD = 3.0 V to 3.6 V VDD_CCD 0.3 VDD_CCD 0.8 0.3 1.85 1.45 V V V V k A VDD_CCD 0.7

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-down resistor (controllable) : GPIO8, GPIO10 to 11, GPIO14 to 16, GPIO52 to 55 D252 Input threshold voltage * VT+ VT VOH VOL VOH VOL RIL ILO VDD1 = 3.0 V to 3.6 V IOH = 0.4 mA, VI = VDD1 or VSS IOL = 0.7 mA, VI = VDD1 or VSS IOH = 0.8 mA, VI = VDD1 or VSS IOL = 1.4 mA, VI = VDD1 or VSS VI = VDD1 VDD1 = 3.0 V to 3.6 V VO = VDD1 or VSS pull-down resistor = OFF 10 30 VDD1 0.8 0.3 90 5 1.85 VDD1 0.3 VDD1 0.8 0.3 1.45 VDD1 0.7 V

D253 D254 D255 D256 D257 D258

Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current

V V V V k A

Note) *: I/O Cell0.4 V

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level schmidt with pull-down resistor (controllable) : GPIO30 to 31, GPIO46 to 50 VT+ D259 Input threshold voltage * VDD_GP1 = 3.0 V to 3.6 V VT VOH VOL VOH VOL RIL ILO IOH = 2 mA, VI = VDD_GP1 or VSS IOL = 2 mA, VI = VDD_GP1 or VSS IOH = 4 mA, VI = VDD_GP1 or VSS IOL = 4 mA, VI = VDD_GP1 or VSS VI = VDD_GP1 VDD_GP1 = 3.0 V to 3.6 V VO = VDD_GP1 or VSS pull-down resistor = OFF 10 30 VDD_GP1 0.8 0.3 90 5 VDD_GP1 0.3 VDD_GP1 0.8 0.3 1.85 1.45 V V V V k A VDD_GP1 0.7

D260 D261 D262 D263 D264 D265

Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Output LVCMOS level schmidt : DRAMFCK VT+ D266 Input threshold voltage * VT D267 D268 D269 D270 D271 D272 D273 D274 D275 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output leakage current VOH VOL VOH VOL VOH VOL VOH VOL ILO IOH = 4.6 mA, VI = VDD_Q or VSS IOL = 5.8 mA, VI = VDD_Q or VSS IOH = 6.5 mA, VI = VDD_Q or VSS IOL = 8.1 mA, VI = VDD_Q or VSS IOH = 7.4 mA, VI = VDD_Q or VSS IOL = 9.3 mA, VI = VDD_Q or VSS IOH = 9.3 mA, VI = VDD_Q or VSS IOL = 11.6 mA, VI = VDD_Q or VSS VO = VDD_Q or VSS VDD_Q 0.8 0.3 5 VDD_Q 0.8 0.3 VDD_Q 0.8 0.3 VDD_Q = 2.7 V to 3.3 V VDD_Q 0.3 VDD_Q 0.8 0.3 1.85 1.45 V V V V V V V V A VDD_Q 0.7

Note) *: Hysteresis width 0.4 V of input/output cell is a design value. It is not inspected the schmidt width.

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Output LVCMOS level schmidt : DRAMFCKX D276 D277 D278 D279 D280 D281 D282 D283 Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level VOH VOL VOH VOL VOH VOL VOH VOL IOH = 4.6 mA, VI = VDD_Q or VSS IOL = 5.8 mA, VI = VDD_Q or VSS IOH = 6.5 mA, VI = VDD_Q or VSS IOL = 8.1 mA, VI = VDD_Q or VSS IOH = 7.4 mA, VI = VDD_Q or VSS IOL = 9.3 mA, VI = VDD_Q or VSS IOH = 9.3 mA, VI = VDD_Q or VSS IOL = 11.6 mA, VI = VDD_Q or VSS VO = Hi-Z VI = VDD_Q or VSS VO = VDD_Q or VSS VDD_Q 0.8 0.3 VDD_Q 0.8 0.3 VDD_Q 0.8 0.3 VDD_Q 0.8 0.3 V V V V V V V V

D284

Output leakage current

ILO

Output LVCMOS level schmidt : DRA0 to 13, DRBA0 to 1, XDCS, DRCKE, DRDQM0 to 3 D285 D286 D287 D288 Output voltage high level Output voltage low level Output voltage high level Output voltage low level VOH VOL VOH VOL IOH = 3.9 mA, VI = VDD_Q or VSS IOL = 5.3 mA, VI = VDD_Q or VSS IOH = 5.8 mA, VI = VDD_Q or VSS IOL = 6.6 mA, VI = VDD_Q or VSS VO = Hi-Z VI = VDD_Q or VSS VO = VDD_Q or VSS VDD_Q 0.8 0.3 VDD_Q 0.8 0.3 V V V V

D289

Output leakage current

ILO

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MN2PS00003RF
Electrical Characteristics (continued)
VDD1 , VDD_CPU0 , 1 , 2 , VDD_GP0 , VDD_LCD , VDD_CCD =1.65 V to 3.6 V VDD_Q = 1.7 V to 1.95 V VDDI , USBVDD = 1.08 V to 1.32 V VDD0 , VDD2 , VDD_GP1 , AVDD_AD , AVDD_DA , PLLVDD , USBAVDD , USBPVDD , VDD_LVDS = 3.0 V to 3.6 V VSS , AVSS_AD , AVSS_DA , PLLVSS , USBAVSS , USBPVSS , USBVSS , VSS_LVDS = 0 V fTEST = 216 MHz, Ta = 30C to +85C Parameter Symbol Conditions Limits Min Typ Max Unit

Input/output LVCMOS level with pull-down resistor (controllable) : DRDQS0 to 3 D290 D291 D292 D293 D294 D295 D296 D297 Input voltage high level Input voltage low level Output voltage high level Output voltage low level Output voltage high level Output voltage low level Pull-down resistor Output leakage current VIH VIL VOH VOL VOH VOL RIL ILO IOH = 3.9 mA, VI = VDDQ or VSS IOL = 5.3 mA, VI = VDDQ or VSS IOH = 5.8 mA, VI = VDDQ or VSS IOL = 6.6 mA, VI = VDDQ or VSS VI = VDDQ VDDQ = 3.0 V 3.6 V VO = VDDQ or VSS pull-down resistor = OFF 33 100 VDDQ 0.8 0.3 300 5 VDDQ 0.7 0 VDDQ 0.8 0.3 VDDQ VDDQ 0.3 V V V V V V k A

Output LVCMOS level : DRWEB, DRCASB, DRRASB D298 D299 D300 D301 Output voltage high level Output voltage low level Output voltage high level Output voltage low level VOH VOL VOH VOL IOH = 3.9 mA, VI = VDDQ or VSS IOL = 5.3 mA, VI = VDDQ or VSS IOH = 5.8 mA, VI = VDDQ or VSS IOL = 6.6 mA, VI = VDDQ or VSS VO = Hi-Z VI = VDDQ or VSS VO = VDDQ or VSS VDDQ 0.8 0.3 VDDQ 0.8 0.3 V V V V

D302

Output leakage current

ILO

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MN2PS00003RF
Analog Electrical Characteristics DA Converter (3-ch. 10 bit) Characteristics
AVDD_DA = 3.3 V, VDD1 = 1.2 V, AVSS_DA = 0.0 V, Ta = 25C Parameter Symbol Conditions Limits Min Typ Max Unit

COMP_DA, IREF_DA, VREF_DA, HD_PBOUT, HD_PROUT, VIDEOOUT E1 E2 E3 E4 Full scale output current Non linearity Differential non linearity Sampling clock IFS INLE DNLE fDACK VREF = 0.92 V, RIREF = 9 k fDACK = 54 MHz, VREF = 0.92 V, RIREF = 9 k, RL = 75 fDACK = 54 MHz, VREF = 0.92 V, RIREF = 9 k, RL = 75 CL = 10 pF, VREF = 0.92 V, RIREF = 9 k, RL = 75 11.9 13.3 14.7 3 3 54 mA LSB LSB MHz

AD Converter (10 bit) Characteristics

AVDD_AD = 3.3 V, VDD1 = 1.2 V, AVSS_AD = 0.0 V, Ta = 25C Parameter ADC0 to 11 E5 Non linearity INLE fADCK = 12 MHz fADST = 1.5 MHz VREFL/H = 0.0 V / 3.3 V fADCK = 12 MHz fADST = 1.5 MHz VREFL/H = 0.0 V / 3.3 V 3 LSB Symbol Conditions Limits Min Typ Max Unit

E6 E7

Differential non linearity Clock frequency

DNLE fADCK

3 12.0

LSB MHz

LENADC0 to 6 E8 Non linearity INLE fADCK = 18 MHz fADST = 1.5 MHz VREFL/H = 0.0 V / 3.3 V fADCK = 18 MHz fADST = 1.5 MHz VREFL/H = 0.0 V / 3.3 V 3 LSB

E9 E10

Differential non linearity Clock frequency

DNLE fADCK

3 18.0

LSB MHz

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MN2PS00003RF
Analog Electrical Characteristics (continued) AD Converter (10 bit) Characteristics (continued)
AVDD_AD = 3.3 V, VDD1 = 1.2 V, AVSS_AD = 0.0 V, Ta = 25C Parameter LENADC7 to 10 E11 Non linearity INLE fADCK = 18 MHz fADST = 1.5 MHz VREFL/H = 0.0 V / 3.3 V fADCK = 18 MHz fADST = 1.5 MHz VREFL/H = 0.0 V / 3.3 V 3 LSB Symbol Conditions Limits Min Typ Max Unit

E12 E13

Differential non linearity Clock frequency

DNLE fADCK

3 18.0

LSB MHz

Clock Generator (PLL) Characteristics

PLLVDD = 3.3 V, VDD1 = 1.2 V, PLLVSS = 0.0 V, Ta = 25C Parameter Symbol Conditions Limits Min Typ Max Unit

Clock generator 1 (PLL) : PLLTESTIO

E14 E15 Input frequency Output frequency fIN fOUT Multiply by 44 12 528 MHz MHz

Clock generator 2 (PLL) : PLLTESTIO

E16 E17 Input frequency Output frequency fIN fOUT Multiply by 27 12 324 MHz MHz

Clock generator 3 (PLL) : PLLTESTIO

E18 E19 Input frequency Output frequency fIN fOUT Multiply by 99 3 297 MHz MHz

Analog Comparator (Analog schmidt ) Characteristics

Parameter Symbol Conditions Limits Min Typ Max Unit

DBGCK, DBGD, GPIO20 to 21, GPIO50, GPIO17 to 18, GPIO30 to 31, GPIO41 to 43 E34 Hysteresis width VT VDD0 = 3.0 V to 3.6 V VDD_GP1 = 3.0 V to 3.6 V 0.6 V

FCK, GPIO51 to 55, GPIO62, GPIO65, GPIO68 to 69, GPIO71 to 72, GPIO74 to 75, AFE_CS, AFE_SCK E35 Hysteresis width VT VDD_CCD = 1.65 V to 3.6 V VDD1 = 1.65 V to 3.6 V VDD_GP0 = 1.65 V to 3.6 V
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Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805