Zero Resonant

Voltage Power

Switching Conversion

Bill Andreycak
Abstract The technique of zero voltage switching in modern power conversion is explored. Several ZVS topologies and applications, limitations of the ZVS technique, and a generalized design procedure are featured. Two design examples are presented: a 50 Watt DC/DC converter, and an off-line 300 Watt multiple output power supply. This topic concludes with a performance comparison of ZVS converters to their square wave counterparts, and a summary of typical applications. Introduction Advances in resonant and quasi-resonant power conversion technology propose alternative solutions to a conflicting set of square wave conversion design goals; obtaining high efficiency operation at a high switching frequency from a high voltage source. Currently, the conventional approaches are by far, still in the production mainstream. However, an increasing challenge can be witnessed by the emerging resonant technologies, primarily due to their lossless switching merits. The intent of this presentation is to umavel the details of zero voltage switching via a comprehensive analysis of the timing intervals and relevant voltage and current waveforms. The concept of quasi-resonant, "lossless" switching is not new, most noticeably patented by one individual [1] and publicized by another at various power conferences [2,3]. Numerous efforts focusing on zero current switching ensued, fIrst perceived as the likely candidate for tomorrow's generation of high frequency power converters [4,5,6,7,8]. In theory, the onoff transitions occur at a time in the resonant cycle where the switch current is zero, facilitating zero current, hence zero power switching. And while true, two obvious concerns can in1pede the quest for high efficiency operation with high voltage inputs. By nature of the resonant tank and zero current switching limitation, the peak switch current is significantly higher than its square wave counterpart. In fact, the peak of the full load switch current is a minimum of twice that of its square wave kin. In its off state, the switch returns to a blocking a high voltage every cycle. When activated by the next drive pulse, the MOSFET output capacitance ( Coss) is discharged by the FET, contributing a significant power loss at high frequencies and high voltages. Instead, both of these losses are avoided by implementing a zero voltage switching technique [9,10]. Zero Voltage Switching Overview Zero voltage switching can best be defined as conventional square wave power conversion during the switch's on-time with "resonant" switching transitions. For the most part, it can be considered as square wave power utilizing a constant off-time control which varies the conversion frequency, or on-time to maintain regulation of the output voltage. For a given unit of tin1e, this method is similar to fIXed frequency conversion which uses an adjustable duty cycle, as shown in Fig. 1. Regulation of the output voltage is accomplished by adjusting the effective duty cycle, performed by varying the conversion frequency , changing the effective on-time in a ZVS design. The foundation of this conversion is sin1ply the volt-second product equating of the input and output. It is virtually identical to that of square wave power conversion, and vastly el

Zero Voltage Switching

Resonant Conversion

1-1

SQUARE WAVE

v
R
0

Topp ~ ..XXBD -J FREQ

k zvs

v
0

Fig. 1- Zero Voltage Switching vs. Conventional

Square Wave

unlike the energy transfer system of its electrical dual, the zero current switched converter . During the ZVS switch off-time, the L-C tank circuit resonates. This traverses the volt age across the switch from zero to its peak, and back down again to zero. At this point the switch can be reactivated, and lossless zero voltage switching facilitated. Since the output capacitance of the MOSFET switch (Coss) has been discharged by the resonant tank, it does not contribute to power loss or dissipation in the switch. Therefore, the MOSFET transition losses go to zero -regardless of operating frequency and input voltage. This could represent a significant savings in power, and result in a substantial improvement in efficiency. obviously, this attribute makes zero voltage switching a suitable candidate for high frequency, high voltage converter designs. Additionally, the gate drive requirements are somewhat reduced in a ZVS design due to the lack of the gate to drain (Miller) charge, which is deleted when VDSequals zero. The technique of zero voltage switching is applicable to all switching topologies; the buck regulator and its derivatives (forward, half and full bridge), the flyback, and boost converters, to name a few. This presentation will focus on the continuous output current, buck derived topologies, however a list of references describing the others has been included in the appendix.

Fig. 2 -Resonant
SWITCH
acTIvATIoB

Switch Implementation
I 0. I OPP r-;;;OB

~ 0. OPP

VIWVO1- IOVCR -

i I I I I

i I I I I

o Fig. 3Genera/ Wavefonns

zvs Benefits .Zero power " Lossless" switching transitions EMI / RFI at transitions

.Reduced .No

power loss due to discharging Coss

.No higher peak currents, (ie. ZCS) same as square wave systems .High efficiency with high voltage inputs at

any frequency .Can incorporate parasitic circuit and componentL&C

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.Reduced "Miller" .Short

gate drive effects)

requirements

(no

circuit tolerant

zvs Differences: .Variable .Higher frequency operation (in general)

off-state voltages in single switch,

unclamped topologies .Relatively new technology -users must climb the learning curve .Conversion frequency is inversely proportional to load current .A more sophisticated control circuit may be required Design Equations A zero voltage switched Buck regulator will be used to develop the design equations for the various voltages, currents and time intervals associated with each of the conversion periods which occur during one complete switching cycle. The circuit schematic, component references, and relevant polarities are shown in Fig. 4. Typical design procedure guidelines and "shortcuts" will be employed during the analysis' for the purpose of brevity. At the onset, all components will be treated as though they were ideal which simplifies the generation of the basic equations and relationships. As this section progresses, losses and non-ideal characteristics of the components will be added to the formulas. The timing summary will expound upon the equations for a precise analysis. Another valid assumption is that the output ZVS

fIlter section consisting of output inductor Lo and capacitor Co has a time constant several orders of magnitude larger than any power conversion period. The fIlter inductance is large in comparison to that of the resonant inductor's value LR and the magnetizing current MLo as well as the inductor's DC resistance is negligible. In addition, both the input voltage VlN and output voltage Vo are purely DC, and do not vary during a given conversion cycle. Last, the converter is operating in a closed loop configuration which regulates the output voltage Vo . Initial Conditions: Time interval < to Before analyzing the individual time intervals, the initial conditions of the circuit must be deflDed. The analysis will begin with switch Ql on, conducting a drain current ID equal to the output current Io, and VDs = VCR = O (ideal). In series with the switch Ql is the resonant inductor LR and the output inductor Lo which also conduct the output current Io .It has been established that the output inductance Lo is large in comparison to the resonant inductor LR and all components are ideal. Therefore, the voltage across the output inductor VLo equals the input to output voltage differential; VLo = VlN -Vo .The output filter section catch diode Do is not conducting and sees a reverse voltage equal to the input voltage; VDo = Vl, observing the polarity shown in Figure 4. Table I. INITIAL
COMP. STATUS 01 Do LA Lo ON OFF

CONDITIONS
CIRCUIT VALUES ID=ILR=ILO=lo IDO=O

VDS=VCR=O; VDO=VIN; ILR=IO

; VLR=O ; ILO=O

V, r)=VIN-VO

Vo

Fig. 4 -Zero

Voltage Switched Buck Regulator

Capacitor Charging State: to -t 1 The conversion period is initiated at time to when switch QI is turned OFF. Since the current through resonant inductor LR and output inductor Lo cannot change instantaneously, and no drain current flows in QI while

Zero Voltage Switching

Resonant Conversion

1-3

Table II -CAPACITOR

CHARGING: to -tl

COMP.STATUS CIRCUIT VALUES 01 CR LR DO

Fig. 5 -Simplified Model

OFF

ID=O; VDS(t)=VCR(t)

Charging ICR=O ; VCR(t) RISES UNEARLY VCR(tO)=O; VCR(t1)=VIN OFF ILR(t)=IO;VLR=O VDO(tO)=VIN ; VOQ(t1)=O ; DECREASES UNEARLY VLQ(tO)=VIN-VO ; VLO(t1)=-VO DECREASES UNEARLY ; ILO=lo

Lo

tOl

CRV1N 10

IcR

= /0

for

(0

Fig. 6- Resonant

Capacitor

Wavefonns

it is off, the current is diverted around the switch through the resonant capacitor CR. The constant output current will linearly increase the voltage across the resonant capacitor until it reaches the input voltage (V CR= v IN). Since the current is not changing, neither is the voltage across resonant inductor LR. At time to the switch current ID "instantly" drops from 10 to zero. Simultaneously, the resonant capacitor current IcR snaps from zero to 10, while the resonant inductor current ILR and output inductor current ILO are constant and also equal to 10 during interval tOr.Voltage across output inductor Lo and output catch diode D o linearly decreases during this interval due to the linearly increasing voltage across resonant capacitor CR. At time t1' VCRequals VIN' and Do starts to conduct.

Resonant State: tl -t2 The resonant portion of the conversion cycle begins at t1 when the voltage across resonant capacitor VCRequals the input voltage VIN' and the output catch diode begins conducting- At t I, current through the resonant components IcR and ILR equals the output current 10. The stimulus for this series resonant L-C circuit is output current 10 flowing through the resonant inductor prior to time ti. The ensuing resonant tank current follows a cosine function beginning at time ti' and ending at time t2- At the natural resonant frequency "'R, each of the L-G tank components exhibit an impedance equal to the tank impedance, ZR- Therefore, the peak voltage across GR and switch Ql are a function of ZR and 10. The instantaneous voltage across GR and Ql can be evaluated over the resonant time interval using the following relationships: /0

ZR

l/U)RCR

CR(rl)

V1N

:.

v CR(t)= V'N+loZR sin[c.> R(t-tJ]:~

Of greater importance is the ability to solve the equations for the precise off-time of the switch. This off-time will vary with line and load changes and the control circuit must respond in order to facilitate true zero voltage switching. While some allowance does exist for a fIXed off time technique, the degree of lati-

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tude is insufficient to accommodate typical input and output variations. The exact time is obtained by solving the resonant capacitor voltage equations for the condition when zero voltage is attained. Let V CR(t)= 0 ; IoZR SIN(.> R(t-tJ) = -V1N

LINE

CHANGES

The equation can be further simplified by extracting the half cycle (180 degrees) of conduction which is a constant for a given resonant frequency, and equal to 1\" /CUR .
,'2
t 12 = -+ 1\" 1 -arcsm .

C.>R

C.>R

~z -'0 RJr1

V1N

The resonant component current (IcR = ILR) is a cosine function between time t1 and t2' described as: ICR(I) = Iocos[U) R(t-tJ]:~ The absolute maximum duration for this interval occurs when 270 degrees (311" /2UJ~ of resonant operation is required to intersect the zero voltage axis. This corresponds to the limit of resonance as minimum load and maximum line voltage are approached. Contributions of line and load influences on the resonant time interval t]2 can be analyzed individually as shown in Figs. 7 and 8. Prior to time tl' the catch diode Do was not conducting. Its voltage, V00' was linearly decreasing from VIN at time to to zero at ti while input source VIN was supplying full output current, Io. At time tl' however, this situation changes as the resonant capacitor initiates resonance, diverting the resonant inductor current away from the output filter section. Instantly, the output diode voltage, V00' changes polarity as it begins to conduct, supplementing the decreasing resonant inductor current with diode current loo. extracted from stored energy in output inductor Loo The diode current waveshape follows a cosine function during this interval, equalling Io minus IcR(t). Also occurring at time tl' the output fIlter inductor Lo releases the stored energy required

Fig. 8 -Resonant Capacitor Voltage vs. Load to maintain a constant output current 10. Its reverse voltage is clamped to the output voltage Vo minus the diode voltage drop VDO by the convention followed by Figure 4. Table III -RESONANT
COMP. STATUS 01 CA OFF Resonant

INTERV AL: tl .~

CIRCUIT VALUES VOS(t)=VCA(t) VCA(t) =VIN + (loZAsin(IJA(t-t1))) IcA(t) = IOcos(wA(t-t1)) VLA(t) = [loZAsin(wA(t-t1)) ILA(t) = ICA(t) IOQ(t)= IO-ILA(t) VLO=-(VO+VOO(fwd))

LA

Resonant

Do Lo

ON Discharge

Zero Voltage Switching

Resonant Conversion

1-5

Inductor Charging State: t2 -t3 To facilitate zero voltage switching, switch Ql is activated once the voltage VDSacross Ql and resonant capacitor VCRhas reached zero, occurring at time t2. During this inductor charging interval tv resonant inductor current I LR is linearly returned from its negative peak of minus 10 to its positive level of plus 10. The output catch diode D 0 conducts during the t2J interval- It continues to freewheel the full output current 10, clamping one end of the resonant inductor to ground through D 0- There is a constant voltage, VlN -V DO, across the resonant inductor. As a result, ILR rises linearly, 100 decreases lineatly. Energy stored in output inductor Lo continues to be delivered to the load during this time period. A noteworthy peculiarity during this timespan can be seen in the switch drain current waveform. At time t2' when the switch is turned on, current is actually returning from the resonant tank to the input source, VlN- This indicates the requirement for a reverse polarity diode across the switch to accommodate the bidirectional current. An interesting result is that the switch can be turned on at any time during the first half of the t2Jinterval without affecting normal operation. A separate time interval could be used to identify this region if desired.
~=~ dl
; dl = dIRLR /V/N

Table IV .INDUCTOR
COMP. STATUS 01 CA LA Do Lo the conversion Charging ON ON

CHARGING:

t2 -t3

CIRCUIT VALUES lo(t)=-lo+((VIN+VOO)/LA)t VCA=O VLA=VIN+VOO ILA(t) = -10+ (VLA/LA) (t-t2) IOO(t)= 10-ILA(t) ILO=IO; VLO=-(VO+VOO) period, DC most of the pertinent

waveforms Assuming the input the output -V 0. The current tive Catch In voltage essentially during operation the on-time tions. the

approach ideal source filter switch

conditions. with QJ closed, and VlN

components, supplies output voltage

current, V LO equals

inductor current equal

and resonant to 10, and their

inductor respec-

are both voltage diode closed is

drops voltage loop in

are operation

zero

(VDs=VLR=O). VlN, and lDO=O. the output circuit switch

V DO equals

where the

regulation, the interval. the

control of the

varies tJ4

on-time

Variable result duration, of and by line

frequency modulating load condior lowering effect as

is actually as dictated

Increasing

the time frequency duty cycle For to

the conversion widening wave voltage increased decrease period. the

has the same in a traditional example, in if the

square output to an

converter. were load, in

drop

response frequency the loads effective where capacitor,

the conversion to raise

would ON little the the tJ4 frequenis to

LR LR6.IR V1N

order

Conversely, is drawn circuit summary, proportional from would the

at light

energy control duration cy. In

the output adjust

(23

to minimize

by increasing

the conversion conversion to the power

where tJ.IR = -10 to +10 = 210

frequency delivered

inversely

2LRlo VlN

and varies with V1N and Vo

the load.
Vo = V1N (34 tO1 +(12+ (23 + (34 = ~N 134

Power Transfer State: 13 -14 Once the resonant inductor current I LR has reached 10 at time tj, the zero voltage switched converter resembles a conventional square wave power processor. During the remainder of

Im+134

(34 = ~

VOt03

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Table V-

POWER

TRANSFER:
CIRCUIT VALUES

t] -t4

COMP. STATUS 01 CR ~ Do Lo OFF Charging ON

VOS = IoRoS(ON) VCR=O ILR=lo; VOo=VIN VLO=VIN-Vo; VLR=O

; 10 = 10

ILO=lo

~N=18V Vo = 5 V 10 = 5 A

Fig. 9 --ZVS

Buck Regulator

Wavefonns

Zero Voltage Switching

Resonant Conversion

1-7

zvs Converter Limitations: In a ZVS converter operating under ideal conditions, the on-time of the switch (23+(34) approaches zero, and the converter will operate at maximum frequency and deliver zero output voltage. In a practical design , however, the switch on-time cannot go to zero for several reasons. First of all, the resonant tank components are selected based on the maximum input voltage ~Nmox and minimum output current IOmin for the circuit to remain resonant over all operating conditions of line and load. If the circuit is to remain zero voltage switched, then the resonant tank current cannot be allowed to go to zero. It can, however, reach 10min . There is a finite switch on-time associated with the inductor charging interval (23where the resonant inductor current linearly increases from -10 to + 10. As the on-time in the power transfer interval (J4approaches zero, so will the converter output voltage. Therefore, the minimum on-time and the maximum conversion frequency can be calculated based upon the limitation of 10min and zero output voltage. The limits of the four zero voltage switched time intervals will be analyzed when 10 goes to 10 minimum. Each solution will be retained in terms of the resonant tank frequency CUR for generalization.

:. 123 =

2LRlomin ~Nmar
t34min = 0

2 C.>R

Maximum

Off-Time: tOl+t12min =

1+1.51\" = CUR

0.909 fR

The maximum conversion frequency corresponds to the minimum conversion period, TCONVmi" , which is the sum of the minimum ontime and maximum off-time: T CONVmi,,:

tl2max

311' 2(,,)R

1.511" t.)R

F CONVmax

LR =

ZR WR

~Nmax Iominw R

KTmax

= f R /1.227 ~

0.815

fR

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conversion period where (34equals zero. Topology coefficient KT will be incorporated to defme the ratio of the maximum conversion frequency (minimum conversion period) to that of the resonant tank frequency, WR. ~N = POTCONV ' Where TCONV = ~
WR
7.71 R -2U>

WIN

p Omin-;:;-

V/~Iomin R VINmax

p Omin = VOlomin

ViNlomin 2(7.71)V1Nmax

Fig. 10-- WaVefonnSatFCONV= Kr.fR In a realistic application, the output voltage of the power supply is held in regulation at Vo which stipulates that the on-time in the power processing state, t34, cannot go to zero as in the example above. The volt-second product requirements of the output must be satisfied during this period, just as in any square wave converter design. Analogous to minimum duty cycle, the minimum on-time for a given design will be a function of V1N,Vo and the resonant tank frequency, UJR. Although small, a specific amount of energy is transferred from the input to the output during the capacitor charging interval tOI. The voltage into the output fIlter section linearly decreases from V1N at time to to zero at tl' equal to an average value of V1N/2. In addition, a constant current equal to the output current /0 was being supplied from the input source. The average energy transferred during this interval is defined as:
2
WIN = 1 -ViNIotOt = ViNIo --= CR ViN ViNCR -

p Omin

0.065

V/Nmaxlomin

:::: 6.5%

PINmin

2 The equation CR and "'R as:

10

2 in terms of

Under normal circumstances the circuit will be operating far above this minimum requirement, In most applications, the amount of power transferred during the capacitor charging interval tOl can be neglected as it represents less than seven percent (7% ) of the minimum input power, This corresponds to less than one percent of the total input power assuming a lO:lload range, ZVS Effective Duty Cycles: A valid assumption is that a negligible amount of power is delivered to the load during the capacitor charging interval tol' Also, no power is transferred during the resonant period from tn' Although the switch is on during period t2J, it is only recharging the

can be reorganized

~N

V/~Iomin

2U)RV/Nmax

This minimum energy can be equated to minimum output watts by dividing it by its

Zero Voltage Switching

Resonant Conversion

1-9

resonant and output inductors to maintain the minimum output current, 10..-". In summary, NO output power is derived from ~N during interval tm. The power required to support Vo at its current of 10 is obtained from the input source during the power transfer period t34.Therefore, an effective "duty cycle" can be used to describe the power transfer interval t34 to that of the entire switching period, t04' or T CONV . ZVS .Effective Duty Cycle Calculations:

could optionally be evaluated. A computer program to calculate the numerous time intervals and conversion frequencies as a function of line and load can simplify the design process, if not prove to be indispensable. Listed in the Appendix of this section is a BASIC language program which can be used to initiate the design procedure. To summarize: When the switch is on, replace V1N with (V1N-VDS(011) = (V1N-Io.RDS(oll). When the free-wheeling diode is on, replace V o with (V 0+ VF). t 01
-CR (~N-IoRDS(oll

V t "Duty Cycle" = -.. = ~ V1N t()4

"Duty Cycle" =
134

10
tO1 +t12+t23 +t34 And can be analyzed over line and load ranges using previous equations for each interval. Accommodating wsses in the Design

Equations: Equations for zero voltage switching using ideal components and circuit parameters have been generated, primarily to understand each of the intervals in addition to computer modeling purposes. The next logical progression is to modify the equations to accommodate voltage drops across the components due to series impedance, like RDS(oll)'and the catch diode forward voltage drop. These two represent the most significant loss contributions in the buck regulator model. Later, the same equations will be adapted for the buck derived topologies which incorporate a transformer in the power stage. The procedure to modify the equations is straightforward. Wherever VrN appears in the equations while the switch is on it will be replaced by VrN- VDS(oll) , the latter being a function of the load current /0. The equations can be further adjusted to accept changes of RDS(011) and VF , etc. with the device junction temperatures. Resonant component initial tolerances, and temperature variations likewise

ZR

VINIlItU-

---

ROS(on)IOmin

IOmin Transformer Coupled Circuit Equa-

tions: The general design equations for the Buck topology also apply for its derivates; namely the forward, half-bridge, full-bridge and push-pull converters. Listed below are the modifications and circuit specifics to apply the previous equations to transformer coupled circuits. General Transformer Coupled Circuits. MaiDtaiDing the resonant tank components on the primary side of the transformer isolation boundary is probably the most common and simplest of configurations. The design procedure begins by transforming the output voltage and current to the primary side through the turns ratio, N. The prime (') designator will be used to signify the translated variables as seen by the primary side circuitry.

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N=

Primary Secondary Vo'=Vo.N

Turns Turns ; and Zo'=Zo.N2

Io'=Io/N;

To satisfy the condition

for resonance, IR<Io'

The resonant tank component equations now become:

L R = ZR =
(NR
V1N1IWX N

Determining Transformer Turns Ratio (N): The transformer turns ratio is derived from the equations used to derme the power transfer interval t34 in addition to the maximum offtime, t03. While this may rust seem like an iterative process, it simplifies to the volt-second product relationship described. The general equations are listed below. The turns ratio N is derived by substituting N. Vo for the output voltage Vo in the power transfer interval t34 equation. Solving for N results in the relationship: NVO/V1N = t34/(tOl+t12+t23+t3J

Iominw

Note: the calculated resonant inductance value does not include any series inductance, typical of the transformer leakage and wiring inductances.
CR = -;;--

N=

V1Nmin t34 VOt04

Iomin NV1NmaxC.>R

The transformer magnetizing and leakage inductance is part of the resonant inductance. This requires adjustment of the resonant inductor value, or both the resonant tank impedance ZR and frequency (J)Rwill be off-target. One

Note: the calculated resonant capacitor value does not include any parallel capacitance, typical of a MOSFET output capacitance, Coss, in shunt. Multi-transistor variations of the buck topology should accommodate all switch capacitances in the analysis. Timing Equations (including N):
CRV1NN 10
1 11" U}R + -arcsm (J) R .V1NN [ IoZR ] 12

11

2LRlo ~
NVO(tOl+tI2+t23) VJN-NVO
T CONY = /Ol +/12+/23+/34

option is to design the transformer inductance to be exactly the required resonant inductance, thus eliminating one component. For precision applications, the transformer inductance should be made slightly smaller than required, and "shimmed" up with a small inductor.

Zero Voltage Switching

Resonant Conversion

1.11

Expanding

zvs

to Other

Topologies

ZVS Forward Converter -Single Ended: The single ended forward converter can easily be configured for zero voltage switching with the addition of a resonant capacitor across the switch. Like the buck regulator, there is a high voltage excursion in the off state due to resonance, the amplitude of which varies with line and load. The transformer can be designed so that its magnetizing and leakage inductance equals the required resonant inductance. This simplifies transformer reset and eliminates one component. A general circuit diagram is shown in Fig. 12 below. The associated waveforms for when LpRI equals LR are shown in Fig. 13.
LSHIM

Fig. 13 -Forward

Convelter

Wavefonns

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zvs

Clamped Configurations

00 Half and

Full Bridge Topologies: Zero voltage switching can be extended to multiple switch topologies for higher power levels, specifically the half and full bridge configurations. While the basic operation of each time interval remains similar, there is a difference in the resonant t12interval. While single switch converters have high off state voltage, the bridge circuits clamp the switch peak voltages to the DC input rails, reducing the switch voltage stress. This alters the duration of the off segment of the resonant interval, since the opposite switch(es) must be activated long before the resonant cycle is completed. In fact, the opposite switch( es) should be turned on immediately after their voltage is clamped to the rails, where their drain to source voltage equals zero. If not, the resonant tank will continue to ring and return the switch voltage to its starting point, the opposite rail. Additionally, this off period varies with line and load changes. Examples of this are demonstrated in Figs. 14 and 15. To guarantee true zero voltage switching, it is recommended that the necessary sense circuitry be incorporated.

Fig. 15 --C/amped ZVS Wavefonns

Zero Voltage Switching

Resonant Conversion

1-13

zvs Half Bridge: The same turns ratio, N, relationship applies to the half bridge topology when V1Nin the previous equations is considered to be one-half of the bulk rail-torail voltage. ~N is the voltage across the transformer primary when either switch is on. Refer to the circuit and waveforms of Figs. 14 and 15. CR, the resonant capacitor becomes the parallel combination of the two resonant capacitors, the ones across each switch. Although the resonant inductor value is unaffected, all series leakage and wiring inductance must be taken into account. The off state voltages of the switches will try to exceed the input bulk voltage during the resonant stages. Automatic clamping to the input bulk rails occurs by the MOSFET body diode, which can be externally shunted with a higher performance variety. Unlike the forward converter which requires a core reset equal to the applied volt second product, the bidirectional switching of the half ( and full) bridge topology facilitate automatic core reset during consecutive switching cycles [11,12].

Fig. tO tlt2

16

--ZVS tJ t.

Half

Bridge

Circuit tO tl t2 tJ

ON OFF 0. 0" VIN VIN

2 a VIN !.!!1

2 O

10 N
0

rT!r
..-

10 N

IOUT -V Dl
t~
O

IOUT -VD2

0 ! tO tl ! ! t2

---t ! t3

t-! t( tOtl t2 Bridge t3 : : tO t. i: tl t2

'--r--. ! t3

Fig.

17 --ZVS

Ha/f

Wavefonns

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zvs Full Bridge: The equations represented for the forward topology apply equally well for one conversion cycle of the full bridge topology, including the transformer turns ratio. Since the resonant capacitors located at each switch are "in-circuit" at all times, the values should be adjusted accordingly. As with the half bridge converter, the resonant capacitors' voltage will exceed the bulk rails, and clamping via the FET body diodes or external diodes to the rails is common [13].

Fig. to tlt2

18

-ZVS tJ t.

Full

Bridge

Circuit tO tl t2 tJ

ON OFF ON orr VIN

,,--~~ , ,

\.~

J'j

" : ..~-c
VIN

v
0: !,

-n..
r-~:;;.l .~ f i ,

~".JA-

Io N
0

i :

-10 N

IOUT -V Dl

IOUT -VD2 O
.. tO tl t2 tJ

:
t4

-~:
I :

:
I :

---i

:
I :

, :

:
, :

---l--. :
I :

tO t2 t3 t.

tl

t2

t3

tOtl

Fig. 19 -ZVS

Full Bridge Wavefonns

Zero Voltage Switching

~

Resonant Conversion

1-15

zvs

Design Procedure

Buck Derived Topologies 00 Continuous Output Current: 1. List all input/output specsand ranges. ~N min & max ; Vo ; 10 min & max
Estimate unclamped V DSIOWJX = Note: possible). For clamped applications (bridges): Increase the maximum switch (buck voltages. and forward): For

8. Breadboard the circuit carefully using RF techniques wherever possible. Remember -parasitic inductances and capacitances prefer to resonate upon stimulation, and quite often, unfavorably. 9. Debug and modify the circuit as required to accommodate component parasitics, layout concerns or packaging considerations. Avoiding Parasitics Ringing of the catch diode junction capacitance with circuit inductance (and package leads) will significantly degrade the circuit performance. Probably the most common solution to this everyday occurrance in square wave converters is to shunt the diode with an R-C snubber. Although somewhat dissipative, a compromise can be established between snubber losses and parasitic overshoot caused by the ringing. Unsnubbed examples of various applicable diodes are shown in Fig. 20 below.

applications

V1NIOWJX(1 + (lolOWJX/lo",;,,) lo",;" if V DSIOWJX is too high if

V DSIOWJX= ~NIOWJX

3. Select

resonant

tank

frequency,

wR

(HINT: wR=21ffR). 4. Calculate the resonant tank impedance and component values. 5. Calculate each of the interval durations (tOI thru (34) and their ranges as a function of all line and load combinations. (See Appendix -for a sample computer program written in BASIC) Additionally, summarize the results to establish the range of conversion frequencies, peak voltages and currents, etc. 6. Analyze the results. Determine if the frequency range is suitable for the application. If not, a recommendation is to limit the load range by raising [om;" and start the design procedure again. Verify also that the design is feasible with existing technology and components. 7. Finalize the circuit specifics and details. D Derive the transformer turns ratio. (nonbuck applications) D Design the output fIlter section based upon the lowest conversion frequency and output ripple currentJo(ac). D Select applicable MOSFET etc. components; diode,

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Multiresonant ZVS Conversion Another technique to avoid the parasitic resonance involving the catch diode capacitance is to shunt it with a capacitor much larger than the junction capacitance. Labelled CD, this element introduces favorable switching characteristics for both the switch and catch diode. The general circuit diagram and associated waveforms are showm below, but will not be explored further in this presentation [14,15].

loo

VCK VDS

IDO

VDO

L-~~

-/"L
t o

~
~ ~ ~ t4

Fig. 21 --Multiresonant Current Mode Controlled

ZVS Circuit

Fig. 22 --Multiresonant

Wavefonns

ZVS Conversion Variable frequency power converters can also benefit from the use of current mode control. Two loops are used to determine the precise ON time of the power switch --an "outer" voltage feedback loop, and an "inner" current sensing loop. The advantage to this approach is making the power stage operate as a voltage controlled current source. This eliminates the two pole output inductor characteristics in addition to providing enhanced dynamic transient response. Principles or operation. Two control ICs are utilized in this design example. The UC3843A PWM performs the current mode control by providing an output pulse width determined by the two control loop inputs. This pulse width, or repetition rate is used to set the conversion period of the UC3864 ZVS resonant controller. Rather than utilize its voltage controlled oscillator to generate the conversion period, it is

determined by the UC3843A output pulse width. Zero voltage switching is performed by the UC3864 one-shot timer and zero crossing detection circuitry. When the resonant capacitor voltage crosses zero, the UC3864 output goes high. This turns ON the power switch and recyctes the UC3843A to initiate the next current mode controlled period. The UC3864 fault circuitry functions, but its error amplifier and VCO are not used.

Zero Voltage Switching

Resonant Conversion

1-17

zvs Forward Converter ..Design Example

1. List circuit specifications: VI!\, = 18 to 26 V Vo = 5.0 V; 10 = 2.5 to 10 A 2. Estimate the maximum voltage across the switch: VDSmax= VINmax(l + (IOmtU/IOmi,, =26-(1+(10/2.5 = 26-5 = 130 V 3. Select a resonant tank frequency, wR. A resonfiDt tank period frequency of SOOKHz will be used. It was selected as a compromise between high frequency operation and low parasitic effects of the components and layout. fR = SOOKHz ; ~ =3.14.106 radians/sec 4. Calculate the resonant tank impedance and component values. Resonant tank impedance, ZR > V1Nmax/IOmin To accommodate the voltage drop across the MOSFET, calculate VDS(on)min' which equals RDS(on!Omin = 0.8.2.5 = 2V ZR = (V1Nmax-VDSmin)/IOmin ZR = (26-2)/2.5 CR = l/(Z#~ = 10 O = 1/(10.3.14.106) = 32nF

Table VI .Interval
VIN=18 10=2.5 t10 t12 t23 t34 TCONV fCONV 0.217 1.29 0.93 1.39 3.83 261kHz

Durations vs. Line & Load

VIN=18 10= 10 0.055 1.06 3.72 6.68 11.51 87kHz VIN=26 10=2.5 0.314 1.49 0.64 0.78 3.23 310kHz VIN=26 10= 10 0.078 1.08 2.58 1.78 5.52 181kHz

Transistor Switch Durations: toN toFF 2.32 1.51 10.4 1.11 1.42 1.80 4.36 1.16

~ ~ r.:i ~ H ~

L1 LO 9 8 7 6 5 4 3 2 ~ 0

T.DO..A

...'"."'..,, -..A

~~-::::~I 18 I 20 I 22

--

I 2.

I 26

VrN(VOLTB) Fig. 23 -Switch Times vs. Line & Load

dfcONV/d~N 10 = df/dV Highest load. = 2.SA 6.1 (11.9 SA

vs 10 7.SA 10A 11.7 occurs avg 10.2 near full

11.211.9 kHz/V)

"gain"

LR = ZR/C.>R = 10/3.34 .106 = 3.18p.H 5. Calculate each or the interval durations (tOl thru t.u> and ranges as they vary with line and load changes. The zero voltage switched buck converter "gain" in kiloHertz per volt of ~N and kHz per amp of 10 can be evaluatated over the specified ranges. A summary of these follows:

dfcONV/dlo vs VlN VlN = df/dV 18 20 22 24 26 avg 20.4

= 23.3 22.1 20.5 18.8 17.3

Highest "gain" (23.3 kHz/A)

occurs at VlNmin.

It may be necessary to use the highest gain values to design the control loop compensation for stability over all operating conditions. While this may not optimize the loop transient response for all operating loads, it will guarantee stability over the extremes of line and load.

1.18
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A. Output Filter Section: Select Lo and Co for operation at the lowest conversion frequency and designed ripple current.
3S0K... = 300KOA >'-' 2S0~..-SA ~

= 200K !::)
O .., 1.50K

~~7..A
-

B. Heatsink Requirements: An estimate of the worst case power dissipation of the power switch and output catch diode can be made over line and load ranges. C. Control Circuit: The UC3861-64 series of controllers will be examined and programmed per the design requirements. Programming the Control Circuit One-sbot: Accommodating OIT-time Variations. The switch off-time varies with line and load by::= ::t 35% in this design example using ideal components. Accounting for initial tolerances and temperature effects results in an much wider excursion. For all practical purposes, a true fIXed off-time technique will not work. Incorporated into the UC3861 family of ZVS controllers is the ability to modulate this off-

~ ...1.00E 75E -

~--~

I 20

22 VI:N(VOLTS)

24

Fig. 24 -Conversion

Freq. vs. Line & Load

6. Analyze the results. The resonant component values, range of conversion frequencies, peak voltage and current ratings seem well within the practical limits of existing components and technology. 7. Finalize the circuit specifics and details based on the information obtained above.

rault Logic and Precision Reference

-,.
~
Bias SV and Gen

sv

8oft

fl

Gnd

NI In
1JVI.O

~
B/A Out

Vcc

Range ..la Cvco

8'..aSa, Logic

~.'1' Drivers

Out

Out

I.~o

PWE

Gnd

ac

Fig. 25 --The UC3861-64 ZVS Contollers --Block Diagram

Zero Voltage Switching

~

Resonant Conversion

1-19

VCR

lated range of conversion frequencies spans 87 to 310 kHz. These values will be used for this "fIrst cut" draft of the control circuit prograntming. Due to the numerous circuit specif ics omitted from the computer program for simplicity, the actual range of conversion frequencies will probably be somewhat wider than planned. Later, the actual timing component values can be adjusted to accommodate these differences. First, a minimum fc of 75 kHz has been selected and programmed according to the
fTOFF VARIATIONS ~

111 -CR Volts & Off-time vs. Line

111 & Load

following equation: F~Omi" = 3.6/(Rmi"C~o) The maxim um f c of 350 kHZ is programmed

by:

time. Initially, the one-shot is programmed for the maximum off-time, and modulated via the ZERO detection circuitry. The switch drainsource voltage is sensed and scaled to initiate turn-on when the precision 0.5V threshold is crossed. This offset was selected to accommodate propogation delays between the instant the threshold is sensed and the instant that the switch is actually turned on. Although brief, these delays can become significant in high frequency applications, and if left unaccounted, can cause NONZERO switching transitions. Referring to Fig. 26, in this design, the off time varies between 1.11 and 1.80 microseconds, using ideal components and neglecting temperature effects on the resonant components. Since the ZERO detect logic will facilitate "true" zero voltage switching, the off-time can be set for a much greater period, Th h th 31 bil 'ty e one-s o as a: range capa 1 and will be programmed for 2,2 uS (max), controllable down to 0.75 uS. ~ Programming of the one-shot requires a single R-C time constant, and is straightforward using the design infor- O mation and equations from the data sheet. Implementation of this feature is shown in the control circuit schematic, Programming the VCO. The calcu-

FK'Omar= 3.6/(Rmin I Rra"8")0CK'O

Numerous values of Rminand CK'O will satisfy the equations. The procedure can be simplified by letting Rminequal looK. CK'O (JJ.F) = O.O36/fmin (kHz) RRANGE (kO) = loo/(fcoNVmar/fcONVmin -1) where Rmin=looK, CK'O=470pF,RRANGE = 27K The VCO gain in frequency per volt from the error amplifier output is approximated by: dF/dV = 1/(RRANGEC\-t:'o) = 78.2 kHz/V

with an approximate 3.6 volt delta from the error amplifier .

E/A + .

VOLTAGE CONTROLLED OSCILLATOR

..

aAHGB

NIB

-=? -=-=r
Fig. 27 --E/A -VCO B/ock Diagram

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Fault Protection -Soft Start & Restart Delay: One of the unique features of the UC 3861 family of resonant mode controllers can be found in its fault management circuitry. A single pin connection interfaces with the soft start, restart delay and programmable fault mode protection circuits. In most applications, one capacitor to ground will provide full protection upon power-up and during overload conditions. Users can reprogram the timing relationships or add control features (latch off following fault, etc) with a single resistor . Selected for this application is a 1 uP softrestart capacitor value, resulting in a soft -start duration of 10 ms and a restart delay of approximately 200 ms. The preprogrammed ratio of 19:1 (restart delay to soft start) will be utilized, however the relevant equations and relationships have also been provided for other applications. Primary current will be utilized as the fault trip mechanism, indicative of an overload or short circuit current condition. A current transformer is incorporated to maximize efficiency when interfacing to the three volt fault threshold. Optional Programming of Tss and TRD: Soft Start: Tss = CsR.10K Restart Delay: TRD = CsR.l90K Timing Ratio: TRD:T ss ~ 19:1 Gate Drive: Another unique feature of the UC 3861-64 family of devices is the optimal utilization of the silicon devoted to output totem pole drivers. Each controller uses two pins for the A and B outputs which are internally configured to operate in either unison or in an alternating configuration. Typical performance for these 1 Amp peak totem pole outputs shows 30 ns rise and fall times into 1nF . Loop Compensation --General Information. The ZVS technique is similar to that of conventional voltage mode square wave conversion which utilizes a single voltage feedback loop. Unike the dual loop system of current mode control, the ZVS output fIlter section exhibits

FAULT

~f

Fig. 29 --Fault Operational Wavefonns a two pole-zero pair and is compensated accordingly. Generally, the overall loop is designed to cross zero dB at a frequency below one-tenth that of the switching frequency. In this variable frequency converter, the lowest conversion frequency will apply, corresponding to approximately 85 KHz, for a zero crossing of 8.5 KHz. Compensation should be optimized for the highest low frequency gain in addition to ample phase margin at crossover. Typical examples utilize two zeros in the error amplifier compensation at a frequency equal to that of the output filter's two pole break. An additional high frequency pole is placed in the loop to combat the zero due to the output capacitance ESR, assuming adequate error amplifier gainbandwidth. A noteworthy alternative is the use of a two loop approach which is similar to current mode control, eliminating one of the output poles. One technique known as Multi-Loop Control for Quasi-Resonant Converters [18] has been

Zero Voltage Switching

Resonant Conversion

1-21

developed. Another, called Average Current Mode Control is also a suitable candidate. fUPI = ~ 1
FP F

.fU '

ZI = ('rR D
I.flFP

1
lID R IIflnJ \C F

1
C.>Z2=

CUn

(R1P+Ra>C1
Gain at !ZI' !Z2 = RFP IIRn
R1P+Rrz

1 R;C;

Fig. 30 -EITor

Amplifier

Compensation

Summary The zero voltage switched quasi-resonant technique is applicable to most power conversion designs, but is most advantageous to those operating from a high voltage input. In these applications, losses associated with discharging of the MOSFET output capacitance can be significant at high switching frequencies, impairing efficiency. Zero voltage switching avoids this penalty by negating the drain-to-source, "off-state" voltage via the resonant tankA high peak voltage stress occurs across the switch during resonance in the buck regulator and single switch forward converters. Limiting this excursion demands limiting the useful load range of the converter as well, an unacceptable solution in certain applications. For these situations, the zero voltage switched multiresonant approach [14,15] could prove more beneficial than the quasi-resonant ZVS variety. Significant improvements in efficiency can be obtained in high voltage, half and full bridge ZVS applications when compared to their square wave design complements. Clamping of
ILa La ~II~ TI

VI. > t 1I1~

Le ~ V..T -~ +1 Cell::o = -Do 1 1

IpO

11

100 uP

.1

La

r~.,~

T2l,lOO --t:*-

~~
2.:

f-t\ 11
Ve.-VDo le.

~'11. -

Voa.

~ ~.~,.,

65~ lUpr
;J.oOK

11E

l1up
.70

-=- pP

"lO pP

Fig. 31 --Zero Voltage Switched Forward Converter

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the peak resonant voltage to the input rails avoids the high voltage overshoot concerns of the single switch converters, while transforD1er reset is accomplished by the bidirectional switching. Additionally, the series transforD1er primary and circuit inductances can beneficial, additives in the formation of the total resonant inductor value. This not only reduces size, but incorporates the detrimental parasitic generally snubbed in square wave designs, further enhancing efficiency.

A new series of control ICs has been developed specifically for the zero voltage switching techniques with a list of features to facilitate lossless switching transitions with complete fault protection. The multitude of functions and ease of programmability greatly simplify the interface to this new generation of power conversion techniques; those developed in response to the demands for increased power density and efficiency.

Zero Voltage Switching

Resonant Conversion

1-23

References [1] P. Vinciarelli, "Forward Converter Switching At Zero Current, " U.S. Patent [2] # 4,415,959 (1983) K. H. Liu and F. C. Lee, " Resonant Switches -a Unified Approach to Improved Performances of Switching Converters," 1ntemalional Telecommumicalions Energy Conference; New Orleans,1984 [3] K. H. Lieu, R. Oruganti, F. C. Lee, "Resonant Switches -Topologies and characteristics," IEEE PESC 1985 (France) M. Jovanovic, D. Hopkins, F. C. Lee, "Design Aspects For High Frequency Off-line Ouasi-resonant Converters," High Frequency Power Conference, 1987 D. Hopkins, Stephenson, Hybridized IEEE APEC M. Jovanovic, F. C. Lee, F. "Two Megahertz Off-Line Ouasi-resonant Converter," Conference, 1987

[12] R. Steigerwald, " A Comparison of HalfBridge Resonant Converter Topologies," IEEE 1987 [13] J. Sabate, F. C. Lee, "Offline Application of the Fixed Frequency Clamped Mode Series-Resonant Converter," IEEEAPEC Conference, 1989 [14] W. Tabisz, F. C. Lee, "Zero VoltageSwitching Multi-Resonant Technique -a Novel Approach to Improve Performance of High Frequency Quasi-Resonant converters," IEEE PESC, 1988 [15] W. Tabisz, F. C. Lee, " A Novel, ZeroVoltage Switched M ulti- Resonant Forward Converter," High Frequency Power Conference, 1988 [16] L. Wofford, " A New Family of Integrated Circuits Controls Resonant Mode Power Converters," Power Conversion and Intelligent Motion Conference, 1989 [17] W. Andreycak, "Controlling Zero Voltage Switched Power Supplies," High Frequency Power Conference, 1990 [18] R. B. Ridley, F. C. Lee, V. Vorperian, "Multi-Loop Control for Quasi-Resonant Converters, " High Frequency Power Conference Proceedings, 1987 Additional References:

[4]

[5]

[6]

W. M. Andreycak, "1 Megahertz 150 Watt Resonant Converter Design Review, Unitrode Power Supply Design Seminar Handbook SEM-6OOA, 1988 A. Heyman, "Low Profile High Frequency Off-line Ouasi Resonant Converter," IEEE 1987 W. M. Andreycak, "UC3860 Resonant Control IC Regulates Off-Line 150 Watt Converter Switching at 1 MHz, " High Frequency Power Conference 1989

[7]

[8]

[9]

M. Schlect, L. Casey, "Comparison of the Square-wave and Ouasi-resonant Topologies," IEEE APEC Conference, 1987

."High Frequency Resonant, Quasi-Resonant and Multi-Resonant Converters," Virginia Power Electronics Center, (Phone # 703-9614536), Edited by Dr. Fred C. Lee ."Recent Developments in Resonant Power Conversion," Inteltec Communication Press (Phone # 805-658-0933), Edited by K Kit Sum

[10] M. Jovanovic, R. Farrington, F. C. Lee, "Comparison of Half-Bridge, ZCS-ORC and ZVS-MRC For Off-Line Applications," IEEE APEC Conference, 1989 [11] M. Jovanovic, W. Tabisz, F. C. Lee, "Zero Voltage-Switching Technique in HighFrequency Off-Line Converters," IEEE PESC, 1988

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10 ' Zero Voltage Switching Calculations and Equations 20 ' Using the Continuous Current Buck Topology 30 ' in a Typical DC/DC Converter Power Supply Application 40' 50 PRINTER$ = "lptl:": ' Printer at parallel 60 , 70 ' Summary of Variables and Abbreviations 80' 90 ' Cr = Resonant lOO' 110' 120 130 140 150 160 170 180 190 200 210 220 230' 240 250 260 270 280 290 300 310 320 330 340 350 Capacitor port #1 **********

Lr = Resonant Inductor Zr = Resonant Tank Impedance ' Fres = Resonant Tank Frequency (Hz) , ' Vlmin = Minimum DC Input Voltage ' Vlmax = Maximum DC Input Voltage ' Vdson = Mosfet on Voltage = 10*Rds ' Rds = Mosfet on Resistance ' Vdsmax = Peak MOSFET off State Voltage ' Vo = DC output Voltage ' Vdo = Output Diode Voltage Drop ' 10max = Maximum Output Current ' 10min = Minimum Output Current ' Start with , ' ****Define ' (Suggestion: parameters for low voltage dc/dc buck regulator

5 Vi and 5 10 data points ranging from min to max*' With broad ranges, use logarithmic spread) : 'Vi data : '10 data

DATA 18,20,22,24,27 DATA 2.5,4,6,8,10 FRES = 500000! VO = 5! VDO = .8 RDS = .8 SAFT = .95 ,

360 FOR J = 1 TO 5: 370 FOR K = 1 TO 5: 380 390 400 410

READ VI(J): READ 10(K):

NEXT NEXT

CLS PRINT "For OUtput to screen, enter'S' or'S'," INPUT "Otherwise output will be sent to printer: ", K$ IF K$ = "5" OR K$ = "s" THEN K$ = "scrn:" ELSE K$ = PRINTER$

420 OPEN K$ FOR OUTPUT AS #1: CLS 430 PRINT #1, "================================================" 440 PRINT #1, " Zero Voltage Switching Times (uSec) vs. Vi, 10" 450 PRINT #1, 460 , "================================================"

Zero Voltage Switching

Resonant Conversion

1-A1

470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 860 870 880 890 900 910 920

' ,

=========HERE

GOES===========

VIMAX = VI(5): 10MIN ZR = (VIMAX -(RDS * WR = 6.28 CR = 1/ LR = ZR / , * (ZR WR VI FRES * WR)

= 10(1): 10MIN))

10MAX = 10(5) (IOMIN * SAFT)

FOR J = 1 TO 5: PRINT #1,

= VI(J) Input Voltage 10 later / (1 mult. -RSIN by 10-6 A 2)): 'dt12 = ###.## V"; VI

USING"

FOR K = 1 TO 5: 10 = 10(K) RSIN = (VI/ (IO * ZR)): , D(O, D(l, D(2, D(3, D(6, D(4, D(5, NEXT K , PAR$(O) PAR$(l) PAR$(2) PAR$(3) PAR$(4) PAR$(5) PAR$(6) , FOR P = 0 TO 6 PRINT #1, PAR$(P); FOR K = 1 TO 5 PRINT #1, USING" NEXT K: NEXT P PRINT NEXT J , PRINT PRINT PRINT PRINT PRINT PRINT END #1, #1. #1, #1, #1, #1, "Addit;onal "Zr(Ohms) ="; Informat;on:" INT(1000! #1, PRINT #1, = "la = "dt01 = "dt12 = "dt23 = "dt34 = "Tconv = "dt03 (A) =" =" =" =" =" =" =" K) K) K) K) K) K) K) = 10 * = (CR * = (3.14/ = (2 = D(l, = VO = D(l, * .000001: VI) '

VDSON = RDS * Compensate for

/ 10: 'dt01 WR) + (1/ WR) * 10) * / VI: K) D(6, K) 'dt23 + D(3, K)) + D(3, / + D(2,

ATN(RSIN K): VI K) ' dt03

LR * K)

+ VDO) K)

-VDSON) + D(4, K):

-(VO 'Tconv

+ VDO)):

'dt34

+ D(2,

####.###";

D(P.

K)

l000000!;

ZR)

/1000 /10 / 10 --9) A -6) 10MIN) /1000 / 1000

"wR(KRads)="; "Cr(nF) ="; "Lr(uH) ="; "Vdsmax =";

INT(WR / INT1000 INT1000 VIMAX *

1000) * CR) * LR) (1 +

10MAX /

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Zero

Voltage

Switching

Times

(uSec)

vs.

Vi,

10

10 (A) dtO1 dt12 dt23 dt34 TCOnV dtO3

Input 2.500 0.218 1.290 0.931 1.387 3.825 2.439 Input 2.500 0.242 1.339 0.838 1.150 3.569 2.419 Input 2.500 0.266 1.390 0.762 0.988 3.406 2.418 Input 2.500 0.290 1.442 0.698 0.870 3.301 2.431 Input 2.500 0.327 0.516 0.621 0.442 1.906 1.464
Information: = 10.526

Voltage 4.000 0.136 1.153 1.490 1.791 4.571 2.780 Voltage 4.000 0.151 1.175 1.341 1.406 4.074 2.667 Voltage 4.000 0.166 1.198 1.219 1.153 3.737 2.584 Voltage 4.000 0.182 1.223 1.117 0.975 3.498 2.522 Voltage 4.000 0.204 1.264 0.993 0.793 3.254 2.461

= 18.00 6.000 0.091 1.096 2.235 2.682 6.103 3.421 = 20.00 6.000 0.101 1.108 2.011 1.987 5.207 3.220 = 22.00 6.000 0.111 1.120 1.829 1.557 4.616 3.060 = 24.00 6.000 0.121 1.133 1.676 1.268 4.199 2.930 = 27.00 6.000 0.136 1.153 1.490 0.983 3.763 2.780

V 8.000 0.068 1.070 2.980 4.118 8.236 4.118 V 8.000 0.076 1.079 2.682 2.852 6.688 3.836 V 8.000 0.083 1.087 2.438 2.136 5.744 3.608 V 8.000 0.091 1.096 2.235 1.682 5.103 3.421 V 8.000 0.102 1.109 1.987 1.253 4.451 3.198

10.000 0.054 1.056 3.725 6.677 11.511 4.835

10 (A) dtO1 dt12 dt23 dt34 TCOnV dtO3

10.000 0.061 1.062 3.352 4.186 8.661 4.475

10 (A) dtO1 dt12 dt23 dt34 TCOnV dtO3

10.000 0.067 1.069 3.048 2.958 7.141 4.183

10 (A) dtO1 dt12 dt23 dt34 TCOnV dtO3

10.000 0.073 1.075 2.794 2.241 6.183 3.941

10 (A) dtO1 dt12 dt23 dt34 TCOnV dtO3 Additional Zr(Ohms)

10.000 0.082 1.085 2.483 1.604 5.254 3.650

wR(KRads)= 3140 Cr(nF) = 30.254 Lr(uH) Vdsmax = 3.352 = 135

Zero Voltage Switching

Resonant Conversion

1-A3

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