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    Verilog Systemtask

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    Sagar Shah
    verilog systemtask

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    Verilog Systemtask

    Uploaded by

    Sagar Shah
    45 views20 pages
    verilog systemtask

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    verilog systemtask

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    verilog systemtask

    Copyright:

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    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    45 views20 pages

    Verilog Systemtask

    Uploaded by

    Sagar Shah
    verilog systemtask

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    CS221:DigitalDesign

    FiniteStateMachine

    Dr.A.Sahu DeptofComp.Sc.&Engg. IndianInstituteofTechnologyGuwahati

    Out e Outline
    FiniteStateMachine
    Describethesequentialbehaviorusinga FSM ExampleofFSM Convert C tafi finite it state t t machine hi t toa Controller asequentialcircuithaving

    AregisterandCombinationallogic

    SequentialCircuit:FSM
    FS SM inp puts Combinational Circuit s1 s0 State register/ History/ Sequence n1 n0
    FS SM outp puts

    clk

    Y(t)=F(a(t),b(t),H) His History/Sequence /State

    FormallyDescribe/mathematicallyDescribe BooleanAlgebra:WorkingCombinationalCircuit FiniteStateMachine:WorkingofSequentialCircuit

    NeedBetterWaytoDesignSequentialCircuits

    Trialanderror:notagooddesign method
    Willwebeabletoguessacircuitthat worksforotherdesiredbehavior?
    Howaboutcountingupfrom1to9? Pulsinganoutputfor1cycleevery10cycles? Detecting gthesequence q 135inbinary yona 3bitinput?

    NeedaBetterWaytoDesign Sequential lCircuits


    Combinationalcircuitdesignprocesshad twoimportantthings
    1 Aformalwaytodescribedesiredcircuit 1. behavior Booleanequation, equation ortruthtable 2. Awelldefinedprocesstoconvertthat behaviortoacircuit

    Weneedthosethingsforsequence circuit i itdesign d i

    FiniteStateMachine
    FiniteStateMachine(FSM)
    Awaytodescribedesiredbehaviorof sequentialcircuit Akin k toBoolean l equationsfor f combinationalbehavior Liststates,andtransitionsamongstates

    FiniteStateMachine:Example
    Example:Makexchangetoggle(0to1,or1 to0)everyclockcycle Twostates:Off(x=0),andOn(x=1) Transition T iti from f Offt toOn, O orOn O t toOff, Off on risingclockedge Arrowwithnostartingstatepointstoinitial state(whencircuitfirststarts)

    FiniteStateMachine:Example
    Outputs: x clk^ x=0 Off clk^
    Off O On Off O On O Off On O Off On O

    x=1 On

    clk state O t t Outputs: x

    cycle 1

    cycle 2

    cycle 3

    cycle 4

    Off

    On

    Off

    On

    ControllerforOnOff
    Input CLK P RE 1 0 RE1 1
    CLK P N
    ThinkofClockEnable:onlyRisingEdge(RE) Aboveonemaynotwork:LevelSensitive RisingEdge:Clockimplicit

    Output X N 1 1 0 0
    X

    C bi ti l Combinational Logic P CLK DFF

    X N

    X N

    FSMExample:0,1,1,1,repeat
    Want0,1,1,1,0,1,1,1,...
    Eachvalueforoneclockcycle

    CandescribeasFSM:Fourstates,Transitionon gclockedge g tonextstate rising


    Outputs: x
    clk State Off On1 On2 On3 Off On1 On2 On3 Off

    x=0 clk^ x=1 clk ^ x=1 clk^ x=1 Off On1 On2 On3

    Outputs: x

    clk^

    ExtendFSMtoThreeCyclesHighLaserTimer

    Fourstates:WaitinOffstatewhileb i 0(b) is b=1 1(&risingclockedge), edge) Whenb transitiontoOn1


    SetsX=1 Onnexttwoclockedges,transitiontoOn2, thenOn3,whichalsosetx=1

    Sox=1forthreecyclesafterbutton pressed

    ExtendFSMtoThreeCyclesHighLaserTimer
    Inputs: b; Outputs: x x=0 Off b clk ^ b*clk x=1 clk^ On1
    clk Inputs: b S tate Off Output s : x

    clk^

    b*clk^ x=1 On2 clk^ x=1 On3

    Off

    Off

    Off

    Off On1 On2 On3 Off

    FSMSimplification:RisingClockEdgesImplicit
    Showingrisingclockoneverytransition:cluttered Makeimplicit assumeeveryedgehasrising clock Whatifwewantedatransitionwithout arising g edge
    AsynchronousFSMs lesscommon,andadvanced topic Weconsidersynchronous FSMs All transitiononrising gedge g

    FSMSimplification:RisingClockEdgesImplicit
    Inputs: b; Outputs: x
    x=0 Off
    ^ b *clk ^ x=1 clk ^ b b *clk ^ clk

    Inputs: b; Outputs: x x=0 Off b x=1 On1 b x=1 On2


    a

    ^ x=1 x=1 clk

    x=1 On3

    On1

    On2

    On3

    Note: Transition with no associated condition thus transistions to next state on next clock cycle

    FSMDefinition
    Set S tof fstates t t
    Ex:{Off,On1,On2,On3}

    S Set tof finputs i t & setofoutputs


    Ex:Inputs:{x},Outputs:{b}

    Inputs: b; Outputs: x x=0 Off b x=1 On1 x=1 On2 x=1 On3 b

    Initialstate
    Ex:Off

    Setoftransitions
    ib next tstates, t t E iti D Describes Ex:H Has5t transitions

    Setofactions
    Sets S t outputs t t while hil in i states t t Ex:x=0,x=1,x=1,andx=1

    We often draw FSM graphically, known as state diagram


    Can also use table (state table), or textual languages

    FSMExample: p CodeDetector
    Unlockdoor(u=1)onlywhenbuttonspressed insequence:

    start,thenred,blue,green,red
    Input I f fromeach h b button:s,r,g,b
    Also,outputa indicatesthatsomecoloredbutton pressed
    a

    Start Red Green Blue

    u r g b a

    Code

    detector

    Door lock

    FSMExample:CodeDetector
    Waitforstart(s=1)inWait, Oncestarted(Start) Ifseered,gotoRed1 Then, h if fseebl blue,goto Blue, l Then, h if fsee green,gotoGreen,Then,ifseered,goto Red2 Red2 Inthatstate,openthedoor(u=1) Wrongbutton b atanystep,returntoWait i

    FSMExample:CodeDetector
    Wait u=0 s Start u=0 ar Red1 u=0 ab a Blue u=0 ag a
    a

    Inputs: s,r,g,b,a; Outputs: u


    a

    s a

    ar ar

    ab ab

    ag ag

    ar ar

    Green u=0

    ar a

    Red2 u=1

    Q: Can you trick this FSM to open the door, without knowing the code? A: Yes, hold all buttons simultaneously

    ImproveFSMforCodeDetector
    Inputs: s,r,g,b,a; Outputs: u Wait u=0 s s Start u=0 0 a ar Red1 u=0 ab a u=0 ag Blue a u=0 Green a u=1 ar Red2 ar ab ag ar
    a

    Newtransitionconditions detectifwrongbuttonpressed,returnstoWait FSMprovidesformal,concretemeanstoaccuratelydefinedesiredbehavior

    Thanks

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