A Tutorial Introduction To Research On Analog and Mixed-Signal Circuit Testing

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO.
10, OCTOBER 1998
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A Tutorial Introduction to Research on

Analog and Mixed-Signal Circuit Testing
Linda S. Milor, Member, IEEE
Abstract Traditionally, work on analog testing has focused

on diagnosing faults in board designs. Recently, with increasing
levels of integration, not just diagnosing faults, but distinguishing
between faulty and good circuits has become a problem. Analog
blocks embedded in digital systems may not easily be separately
testable. Consequently, many papers have been recently written
proposing techniques to reduce the burden of testing analog and
mixed-signal circuits. This survey attempts to outline some of
this recent work, ranging from tools for simulation-based test
set development and optimization to built-in self-test (BIST)
circuitry.
Index Terms Analog circuits, analog system fault diagnosis,
analog system testing, built-in testing, integrated circuit testing,
mixed analogdigital integrated circuits, testing.
I. INTRODUCTION
ISTORICALLY, electronic circuits were almost exclusively analog and were designed with discrete components. The components were mounted on printed circuit
boards and tested with a bed of nails tester, allowing access
to all input and output voltages of components. Since the
components of an electronic system could be individually
tested, speed in identifying the cause of failures was more
of a problem. Testing research focused on the development of
methods to rapidly diagnose component failures and assembly
errors during eld servicing of weapons, navigation, and
communication systems.
The advent of integrated circuit (IC) technology and the
scaling of transistor sizes have allowed the development of
much larger electronic systems. Digital design techniques
have become predominant because of their reliability and
lower power consumption. However, although large electronic
systems can be constructed almost entirely with digital techniques, many systems still have analog components. This is
because signals emanating from storage media, transmission
media, and physical sensors are often fundamentally analog.
Moreover, digital systems may have to output analog signals to
actuators, displays, and transmission media. Clearly, the need
for analog interface functions like lters, analog-to-digital converters (ADCs), phase-locked loops, etc., is inherent in such
systems. The design of these interface functions as integrated
circuits has reduced their size and cost, but in turn, for testing
purposes, access to nodes is limited to primary inputs and
Manuscript received November 7, 1996; revised December 23, 1997. This
paper was recommended by Associate Editor G. W. Roberts.
The author is with the Submicron Development Center, Advance Micro
Devices, Sunnyvale, CA 94086 USA.
Publisher Item Identier S 1057-7130(98)07529-6.
Fig. 1. Test setup for a mixed-signal device [5].
outputs, making it more difcult to locate component failures

when circuit specications are not satised. Nevertheless,
algorithms aimed at diagnosing component failures on boards
can be applied to identifying faulty components in analog
ICs. And in fact, given limited accessibility to internal nodes
in analog integrated circuits, a large number of algorithms
and theoretical ndings for fault diagnosis and test signal
selection have been developed throughout the 1970s and
1980s [1], [2].
Recently, due to the exploding telecommunications market,
as well as markets for consumer and automotive electronics,
more and more mixed-signal devices are being designed,
integrating digital and analog components on a single chip
in order to improve performance and reduce board size and
cost. In the production of mixed-signal circuits, test can be
a limiting factor, contributing signicantly to manufacturing
cost [3]. A typical strategy for testing a mixed-signal chip
involves, when possible, rst testing the digital and analog
components, followed by some system tests to check the atspeed interaction among components. In this case, the digital
parts would be tested with standard methods, aided by software
for automatic test pattern generation, scan chains, and built-in
self-test (BIST), which has become mature and cost effective.
Testing the analog parts and the combined system is less well
understood, where test sets are typically based on a designers
experience and specications on a circuits functionality.
A typical test setup for testing the analog components is
shown in Fig. 1. Such a setup involves applying digital inputs
to the digital block, inputting a signal, which excites the analog
portion of the mixed-signal circuit with a dc, sinusoid, squarewave, or some random signal, having a known probability
distribution function, and measuring the response with an rms
power meter, operating over a narrow and tunable frequency
band. Sinusoidal inputs are commonly used to test linear
analog circuits, such as ampliers, data converters, and lters,
to verify the magnitude and phase of an output signal as a
function of the input frequency. Additionally, sinusoidal inputs
10577130/98$10.00 1998 IEEE
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 10, OCTOBER 1998
are also used to quantify the extent of nonlinearity in an output

signal by comparing the power contained in the harmonics or
noise to that of the fundamental signal, referred to as total
harmonic distortion [4]. As an alternative to deterministic input
signals, random inputs, with a known spectral distribution, may
be used to test an analog circuits transfer characteristic, via
analyzing the spectrum of the response.
Many factors limit the straightforward application of such
an approach to testing mixed-signal circuits. First, market
pressures require very efcient development of bug-free test
sets, which not only check the functionality of the analog
components, but also the at-speed operation of the entire
system. Especially for at-speed testing, the interactions between the digital and analog portions of the chip can be
complex and unique to the application, and as a result need to
be fully understood. This is certainly nontrivial and requires
extensive labor-intensive engineering work. It turns out that
for many mixed-signal circuits, a signicant contribution to
time-to-market comes from the time required for test program
development and debugging. Test program development often
begins after a design is complete due to limited CAD tool
support for test set development, and it usually takes many
iterations between design and test to realize a testable design
which satises specications. This contrasts strongly with
test program development for digital circuits. For digital
circuits, CAD tools are extensively used to generate test
patterns, which are then tested on prototypes of the circuit,
including register transfer level software descriptions, gatelevel software descriptions, and eld-programmable gate array
(FPGA) prototypes. This both validates the circuit design and
the test program prior to the availability of silicon. Hence, this
tutorial will begin with a discussion of recent tools that have
been developed to automate the test development cycle so that
test sets can be created concurrently with the design phase.
Then, even if mixed-signal test programs can be developed
efciently, complete testing of some analog circuit specications can be very costly. Consider, for example, measuring
the integral nonlinearity (INL) of an ADC. For a 13-bit ADC,
this would require locating 8192 (2 ) input voltages which
cause transitions in the output between codes, at multiple
temperatures. Such a large number of long tests can limit
throughput during production testing unless numerous test
stations are in simultaneous operation. And given the high
cost of high-speed mixed-signal test equipment, coupled with
the time that each device spends on a tester, testing can add
several dollars to the cost of a device. For example, locating
all codes can add more than a dollar to the cost of a 13-bit
ADC, which typically sells for $15 [6]. Therefore, in Section
III, methods for reducing the cost to production testing will be
presented. During production testing, the goal is to distinguish
good circuits from faulty ones with minimum cost, where cost
is inuenced by test time, throughput, and the cost of test
equipment. Unlike with board designs, fault location is not
a target because it is not possible to repair or replace faulty
components. On the other hand, during design characterization,
if a circuit has been identied as faulty, it is desirable to
nd the cause of failure. Hence, in Section IV, approaches
to fault location and identication are discussed. This problem
involves selecting input signals and measurements, in addition

to the decision algorithm.
Finally, the inputs to the analog components of a mixedsignal circuit may not be accessible to the tester. Moreover, it
is not feasible for a designer to bring all of the analog inputs
and outputs out to the package pins, and probe loading effects
can degrade measurements made on naked die. Consequently,
extra components are often required to access internal nodes
through primary inputs and outputs. But in this case, the
parasitics introduced when accessibility is augmented can
degrade some circuit performances. In Section V, design
techniques for improving the testability of embedded analog
components will be summarized. Specically, circuits for
increasing controllability and observability of internal signals
at analog component nodes will be presented. Additionally,
work on analog and mixed-signal BIST will be discussed.
Analog and mixed-signal BIST goes beyond simply improving
controllability and observability of internal nodes by attempting to reduce the need for high-performance test equipment
through implementing test signal generators and analyzing
test results on chip. Analog and mixed-signal BIST allows a
designer increased exibility to make the tradeoff between the
increased silicon area needed for BIST circuitry and external
tester requirements. Lastly, Section VI concludes this paper
with a summary.
II. TEST PROGRAM DEVELOPMENT
Creating the test programs to run mixed-signal testers is a
major bottleneck in the product delivery cycle for many mixedsignal circuits. Unlike digital test program development, which
is automated with the support of CAD tools for test program
generation and veried with the help of software and hardware
descriptions of the circuit prior to the availability of silicon,
analog and mixed-signal test program development is laborintensive, time-consuming, and must be done using fabricated
devices and on the tester. Hence, because the test engineer
works with prototypes of a circuit and the tester hardware and
software to develop and debug test programs, test program
development begins after a design is complete and prototypes
have been manufactured. In fact, the delays due to waiting
for prototypes and the lack of automation for mixed-signal
test program development leads to signicant increases in the
product development cycles, which can potentially be reduced
if some debugging of the tester-circuit interface (load board)
and the test program can be done prior to the availability of
rst silicon.
Recently, work on simulation tools to address this need has
begun, targeting emulating the testing of mixed-signal devices.
The idealistic goal of this work is depicted in Fig. 2. Clearly,
such an ideal situation is not possible, due to inaccuracies in
simulation models. Nevertheless, the diagram points out that
any reduction in test debug time after rst silicon directly
translates into a reduction in time-to-market. Consequently, it
is worthwhile to target such a goal. To achieve this goal, the
test engineer must create a software description of the test
program, including models of tester hardware, the test board,
code to program the tester to perform various tests in the
MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING
Fig. 2. Ideal potential time-to-market reduction due to the use of electronic

design automation (EDA) tools for test program development.
Fig. 3. The test environment.
language of the target tester, and, of course, the circuit. Under

these conditions the test engineer may then simulate the testing
process and evaluate the impact of parasitics on test results,
check the synchronization between analog and digital tester
resources, check impedance matching and transient effects,
etc., in order to evaluate the effectiveness of a test program
prior to the availability of prototypes. And, if simulation
models are reasonably accurate, signicant portions of the test
program can be debugged before rst silicon.
Writing a test program involves dening input stimuli, tester
resources, output responses, the postprocessing calculations
performed, and the load board. Tools have been proposed to
automate several components in this process. These include the
design of the load board, verication of each test, generation
of tester source code, and the complete emulation of the entire
test program.
The load board connects the device under test (DUT) to the
tester resources (Fig. 3). Designing a load board is a timeconsuming task in test program development, since a test
program combines a number of tests, each of which may
require different connections and components on the load
board. Kao and Xia have proposed a tool to automatically
synthesize the load board [8]. This tool considers connectivity
data from test schematics for the individual tests, determines
shared tester resources, inserts switches for different setups,
and generates a net list for the nal load board circuit. In
addition, a printed circuit board place and route tool is used
to automatically place and route load board components, after
which parasitic information is extracted.
Simulating a test may help identify problems with, say,
settling times, impedance matching, load board parasitics,
and instrument precision. This requires the test engineer to
evaluate the performance of a device as measured on a piece
of commercial automatic test equipment with realistic approximations to actual measurement and instrumentation techniques
used in the tester hardware. Some such models for tester
resource simulation have been implemented and are described
in [9][11]. Given tester resource models, in [9][11] the
simulation of a test is performed in an environment which
combines a traditional approach to simulation, i.e., SPICE,
for smaller analog components, with behavioral models for
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measurement instruments and larger analog blocks. If the

circuit is a mixed-signal device, mixed-signal simulation techniques are used, combining circuit-level, analog behavioral,
switch-level, gate-level logic, and behavioral logic verication
capabilities. Simulation of a test not only makes it possible to
investigate DUT-test interactions, but also makes it possible
to identify critical components through sensitivity analysis,
whose tolerances, if too large, may degrade test results.
In [12], a source code generator is proposed which automatically creates a test program in the language of the target tester
hardware. This source code generator provides tester setup
conditions and connectivity information, sets control bits, and
controls the movement and analysis of data.
Finally, a tool for checking test program synchronization is
proposed in [7] and [11]. The software tools described in [7]
and [11] are automatic test equipment (ATE) program emulators. Test program emulators are proposed to verify instrument
settings, instrument precision, measurement synchronization,
etc., using a workstation. In particular, during emulation, the
test program interacts with simulation models of the DUT, load
board, and tester resources through a communication channel,
where, as the test program executes, it sets up the virtual
instruments (simulation models of the tester resources) and
sources the test patterns. These patterns are then simulated, and
the simulation responses are collected and postprocessed. The
emulator then performs the decision-making and branching,
as is done in the real test program. Based on the results,
more test patterns are fed back to the simulator, until testing
is complete. The whole process works as if the test program
is veried on-line on real tester hardware. Consequently, both
fault-free and faulty simulation prototypes of the circuit can
be tested to verify that the test program both passes good
devices and rejects faulty ones. Given sufcient accuracy in
the simulation models, if test program and design bugs are
caught by the emulator, signicant debug time would clearly
be saved, which would otherwise have been spent using the
tester hardware, after the availability of silicon.
III. REDUCING THE COST OF PRODUCTION TEST
Some analog and mixed-signal circuits require large numbers of specications to be veried, where checking all specications can result in prohibitive testing times on expensive
automated test equipment [6], [13]. In this section the problem
of minimizing the cost of production testing is considered,
assuming that the circuit being tested has a predened set
of specications that need to be measured, with prespecied
binning limits, indicating limits for failed die and limits for
various performance grades of good die. The aim of techniques
presented in this section is to minimize testing time by
optimally ordering the tests (Section III-A) and by dropping
some specication tests without degrading fault coverage
(Section III-B). The methods presented are best suited to
large production runs where the cost of evaluating fault
coverage using a sample of circuits that are exhaustively and
nonoptimally tested can be amortized over large numbers of
circuits that are subsequently optimally tested. Therefore, these
methods can be applied without the use of fault models, since
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fault coverage of subsets of a test set can be computed based

on historical pass/fail data. Nevertheless, it may be desirable
to optimally order and/or select a best subset for production
testing for a new product prior to the availability of a large
database of historical pass/fail data. In this case, fault models
are needed to generate such a database using simulation data.
Hence, in Section III-C, fault modeling is discussed, together
with its application to evaluating the effectiveness of a test set.
A. Optimal Ordering of Tests
Typical industrial practice in production testing involves
performing groups of tests, where if any set is failed, the die
is assigned a failure bin number and testing is terminated.
The number of die in various bins provides information about
the common failure modes of the chip. The order of the
groups of tests with a common bin number often depends
on the complexity of the test. In other words, usually gross
failures, like shorts between power and ground, are checked
rst, followed by, say, tests for defects in digital components.
The last set of tests usually relates to checking the performance
of the entire system. This approach to test ordering intuitively
maximizes the information attained about failure modes.
Because testing is terminated as soon as a test is failed,
average production testing time varies depending on the order
of the tests. Specically, if tests for gross failures are performed rst and a circuit frequently fails such tests, then the
average production testing time will be shorter compared to
another circuit which mostly fails the system tests which are
performed last.
If groups of tests are ordered to maximize information about
failure modes, they may not be optimized for minimizing
production testing time. Production testing time not only
depends on the time to complete each test, but also on the
probability that a particular test will be performed on a circuit,
given its position in the test set. Consequently, if a large
number of die fail a certain system test and if this system
test also fails die with shorts between power and ground,
production test time may be less if such a test is performed
rst, at the expense of separating die with gross failures from
die that just fail a particular system test. Hence, there is
clearly a tradeoff between optimizing failure bin information
and test time, where the former is usually more important
during the early stages of production, while the latter is more
important for mature products. On the other hand, if testing
for each failure bin is terminated as soon as a test is failed,
the order of tests can certainly be optimized within the group
corresponding to each failure bin to reduce test time, while
retaining as much failure information.
Mathematically, the order of tests may be optimized as
follows. Suppose a test set has tests which are ordered from
the rst position ( ) to the last ( ), requiring test times
. The probability
that the th test is
of
performed is
where
is the yield of the test in the th position. Average
test time is then
Average Test Time
Hence, minimizing production testing time involves gathering
pass/fail data for each of the circuit specications using a
, the
sample of fabricated chips in order to calculate
position, given previous tests
yield of the test in the
to
. Then Dijkstras Algorithm can be
in positions
used to optimize the order [14]. Specically, the test selection
problem is formulated as a shortest path problem in a directed
graph, where the computational complexity is dominated by
the number of possible subsets of the test set, . In order to
cut the computational cost by avoiding the evaluation of all
subsets of the test set, two heuristic approaches to
possible
test ordering have also been proposed [15].
B. Selecting a Subset of Specication Tests
The easiest way to reduce the number of tests in a test set
is to drop the tests that are never failed. It is possible that a
test will not be failed if it is designed to detect a processing
problem that has not yet occurred. Moreover, it is likely that
some tests will never be failed when there are many more circuit specications that have to be measured than independent
sources of variability in the manufacturing process. It turns
out that the order in which tests are performed will inuence
which tests are never failed. For example, a redundant test,
placed early in a test set, may detect some faulty circuits,
which could be detected by a combination of tests performed
later. For example, a power supply short problem most certainly will be detected by a system performance test, and
therefore a test for such a short would be redundant. Hence,
as there is a tradeoff between minimizing production test time,
achieved by optimally ordering a test set, and maximizing
failure information, there is also a tradeoff between achieving
minimal production test time through eliminating tests and
maximizing failure information. Clearly, failure information
is more important early in the product cycle, while reducing
test time is more important for mature products. And, if a
group of tests is assigned a single failure bin, redundant tests
from that group can be eliminated at little cost.
In [15] and [16], an algorithm has been developed that
orders tests so that the number of tests that have no dropout
is maximized. In other words, this algorithm identies and
maximizes the number of redundant tests. It uses historical
pass/fail data to identify those tests that detect some faulty
circuits which are detected by no other test. If the sample size
is large enough, all necessary tests will detect some such faulty
circuits that are detected by no other test. In this way redundant
tests are identied. On the other hand, if the sample size is
too small, some necessary tests may be wrongly identied as
redundant, resulting in reduced fault coverage, dened as the
probability of correctly rejecting a faulty circuit. This may
occur if some process corners have not yet been exercised.
And in fact, for circuits with high yield, large sample sizes
of nonoptimally tested circuits are needed in order to achieve
SAMPLE SIZE AS
FUNCTION
OF
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TABLE I
YIELD AND FAULT COVERAGE
high fault coverages, since if large sample sizes are available,

presumably all realistic process corners have been exercised
(Table I).
A number of papers have attempted to go beyond just
dropping tests that are never failed. These papers have proposed using a limited set of measurements to predict the
results of other measurements. Supposing that the number
of measurements is much larger than the number of primary
sources of variation in the manufacturing process, the number
of primary sources of variation in the manufacturing process
limits the dimension of the set of basis vectors that span the
measurement space. In order to characterize the measurement
space, these methods rely on linear models of deviations in
circuit performances as a function of variations in parameters
characterizing the manufacturing process. These linear models
can be constructed by simulation, where the basis vectors
of the measurement space are sensitivities of measurements
to changes in process parameters [17]. Alternatively, basis
vectors for the measurement space can be found empirically
using a sample of devices coming off the production line,
assuming they manifest all of the sources of variability of the
manufacturing process [18]. Using an empirical set of basis
functions eliminates the need to simulate often very complex
circuits, which can either lead to results of limited accuracy
or can be extremely computationally intensive. But empirical
basis functions include noise, which can be minimized by
averaging repeated measurements of the same device. And
basis functions can be missed if all process corners have not
yet been exercised.
Mathematically, for the case when the span of the measurement space is characterized by simulation [17], let denote a
vector of changes in measurement responses from nominal,
changes in parameter values
and let denote a vector of
from nominal. Then, given a sensitivity matrix
Alternatively, for an empirical model, the columns of would

denote changes from nominal of the measurements for
different devices [18]. The problem addressed is to nd a set
of measurements which can be used to predict the responses of
other measurements not made. Suppose that the measurements
are divided into two sets, where
is a vector of the
measurements that are made and
is a vector of
measurements that need to be predicted. The sensitivity matrix
and ,
can correspondingly be divided into two matrices,
where
AT
95% CONFIDENCE
Then, if
and
has rank , the measurements
can be used to predict parameters deviations
where
is the transpose of . And the remaining measurements are predicted as follows:
For a circuit, the results of measurements

and the predicted
can be used to sort devices into
results for measurements
performance bins.
is
One runs into problems with this approach when
or nearly so. In this case, for any
of rank less than
cannot be inverted, and
choice of measurements ,
cannot be predicted. This would
all of the parameters
happen if sensitivities for different sources of variation in the
manufacturing process are not unique. In such a case, it would
not be possible to determine from measurements the values of
with linearly dependent sensitivities. In
those parameters
fact, such parameters, which cannot be predicted unless the
values of other parameters are known, are said to belong to
the same ambiguity group. Since the purpose of this work is to
nd a set of basis vectors that span the measurement space, the
problem of ambiguities in is solved by dropping a column
for one member of each ambiguity or approximate
of
ambiguity group. One way of identifying dependent columns
with column pivoting, where a
is QR factorization of
set of unambiguous columns is sequentially selected until
no more can be found [19]. In another approach, columns
are sequentially selected by choosing the largest element,
to
corresponding to a high sensitivity of a measurement
a parameter , so that it is possible to accurately solve for
the parameters that are selected. This process also continues
until no more columns with large sensitivities can be found
[20]. An alternative approach is to test all small subsets of
columns for dependency, sequentially eliminating ambiguous
columns [19]. The problem with this last approach is that
the number of subsets to be tested grows exponentially with
. A fourth approach to identifying ambiguity groups from
which ambiguous columns are identied begins by computing
using singular value decomposition or
the null space of
Gaussian elimination [21]. The rows of the matrix that span
the null space correspond to different ambiguity groups only if
they are orthogonal. Hence the ambiguity groups are found by
checking the rows of the null space for pairwise orthogonality,
which can be performed in polynomial time.
Once columns corresponding to ambiguity groups have
can
been pruned from , an optimal set of measurements
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be chosen, where the rank of

determines the minimum
number of measurements required. The method suggested in
[17] involves nding a set of measurements which minimizes
the average prediction variance of the model coefcients .
When the number of measurements is large, the maximum
variance is minimized with the -Optimality criterion, i.e.,
. This approach is computationally
maximizing
costly for large problems, and hence an approximate solution is
with pivoting. The
found in [17] using QR factorization of
resulting pivots correspond to the selected measurements .
In an alternative approach, the measurements are selected by
minimizing the average standard error of the predicted output
[22]. This algorithm is based on -Optimal experimental
design.
For both approaches to test selection, the minimum number
of test vectors may not be sufcient to conclusively verify
the performance specications because of the size of the
condence bounds on the predicted test results, due to measurement noise and model inaccuracies. In fact, adding more
measurements reduces the size of the condence bounds on
the predicted test results , making it possible to conclusively verify if predicted test results are inside or outside of
binning limits. In [22], the -Optimal criteria is used to select
additional tests, and in [23] the measurement with the highest
prediction variance is iteratively selected.
These approaches to test selection based on linear modeling
have been proven to be effective for ADCs [6]. Specically,
50 commercial 13-bit ADCs were exhaustively tested to
reveal that 18 measurements of code transitions out of 8192
sufced to model all randomness in the manufacturing process
for a batch of devices and to predict the remaining code
transitions. The remaining 77 devices were tested with this
reduced test set.
C. Evaluating the Effectiveness of a Test Set
How can we determine if a test set is effective for a given
circuit? Fault coverage is a good measure of the effectiveness
of a test set, i.e., the probability that a faulty circuit fails
tests. One way to evaluate the fault coverage of a test set
is to exhaustively test a sample of manufactured circuits.
This approach would require a very large sample in order
to evaluate high fault coverages (Table I). If such historical
data is not available, an alternative is to use simulation data
to determine the faults that are detectable by a given test set,
optimize the order of a test set, and eliminate redundant tests
in a test set. For this to be possible, one needs an accurate and
efcient simulation methodology and a fault model. Moreover,
an efcient statistical simulation strategy is needed because of
the very high computational cost associated with simulating
large systems and the very large number of random variables
needed to model manufacturing processes.
Faults in analog circuits can be classied into two categories: catastrophic and parametric [24]. Catastrophic faults
include open nodes, shorts between nodes, and other topological changes in a circuit. For integrated circuits, they usually
result from local defect mechanisms like particles on the wafer
surface generated by equipment during processing, particles
that block exposure of a local area during masking, oxide

defects which short out transistors, severe misalignment of
layers, etc. For printed circuits boards, catastrophic faults
can come from excess solder, resulting in bridging between
pins, lack of solder, a broken pin of a component, missing
components, improperly oriented components, or use of a
wrong component (i.e., a resistor rather than a capacitor) [11].
For integrated circuits, one way to produce a catastrophic fault
list is to mimic the defect size and frequency distribution of the
manufacturing process using a Monte Carlo defect simulator
that places missing or extra material in a given layer of a
layout and extracts the impact on circuit topology [25], [26].
Alternatively, prior to the availability of a layout, a fault
list may be generated from a schematic, i.e., broken wires,
gate-drain shorts, etc. [27], [28]. For printed circuit board
technology, a fault list may include open and shorted pins,
missing components, improperly oriented components, or use
of the wrong component [11].
Parametric faults refer to changes in a circuit that do
not affect its connectivity. Such changes may be global or
local. Global variation of parameters is due to imperfect
parametric control in IC manufacturing. Such variations affect
all transistors and capacitors on a die, and if large, result
in circuits that fail performance specications or are binned
as lower performance parts. Such variations have a large
component due to lot-to-lot uctuations, because of processing
in different equipment at different times, a smaller component
due to wafer-to-wafer uctuations, because of variations in the
performance of individual pieces of equipment as a function
of time, a smaller component due to within-wafer uctuations,
often because of temperature gradients during etching, and a
smaller component due to within-reticle uctuations, often due
to lens distortion which affects lithography [29]. For example,
transistor channel length will vary both systematically and
randomly across a die, reticle, wafer, and between wafers and
lots. In order to characterize global parametric variations, a set
of independent factors is usually identied that explain lot-tolot, wafer-to-wafer, and die-to-die variations in a process, often
by principal components methods [30], [31].
Local variations of parameters are due to local defect mechanisms, like particles, which, say, enlarge a single transistors
channel length or capacitor locally, or local variations in
parameters across a die because of imperfect process control,
for example, due to local temperature gradients during etching
or local variations in the lens of a stepper. Local variations
in parameters due to defects are often modeled as large
changes in a single device parameter, like a change in a
single resistor value. Local variations due to imperfect process
control have little effect on digital components, but result in
random differences between physically adjacent devices in
analog components, which gives rise to mismatch, to which
many analog designs are very sensitive. Modeling mismatch
entails supplementing global statistical process models with
additional variables indicating the extent of mismatch, possibly
as a function of device area and spacing [30], [32], [33].
Incidentally, the data needed to characterize mismatch is
harder to come by due to the lack of test structures on scribe
line monitors that can be used to measure mismatch.
1395
Fig. 4. The map between the parameter space and the measurement space. Parameters and measurements not in the acceptability region correspond
to faculty circuits [15].
Simulating both catastrophic and parametric faults can be

cumbersome because of the computational cost of simulating
large analog systems. A hierarchical approach to fault simulation reduces the computational cost. Hierarchical simulation
involves partitioning a system into blocks. The blocks are then
electrically simulated and their responses are stitched together
with a behavioral simulator in order to evaluate system performances. This is the approach taken in [11] and [33][37]
for catastrophic fault simulation. And if a catastrophic fault
model is used, fault coverage ( ) is typically dened as the
ratio of faults detected ( ) over faults simulated ( ) [11],
[28], [38]. If faults are weighted by their likelihood , then
Several authors use the same methodology for the simulation of parametric faults [34], [35], [39]. This corresponds
to a parametric fault model involving only local variations
in geometries due to defects. Such a fault model does not
include global parametric variations resulting from imperfect
process control. Given such a local parametric fault model,
in order to simulate a fault, a circuit parameter is set to an
out-of-tolerance value and the resulting circuit is simulated.
But how much out of tolerance should the parametric faults
be? Models of defect size frequency indicate that small defects
are much more likely than large defects [40]. And very small
defects result in only minor changes in circuit performances.
Hence, such small defects may not cause a circuit to fail
specications. Clearly, the denition of a parametric fault
needs to be related to the circuit specications, and specically
dening a parametric fault involves determining parameter
limits such that a circuit fails specications, which may or
may not coincide with parameter tolerances.
Similarly, for global parametric faults, which result from
imperfect control in manufacturing, parameters closer to nominal values are much more likely than parameters which are
far from nominal, while parameter values that are far from
nominal are much more likely to cause a circuit to fail
specications. And, as with local parametric faults, circuits
with parameter values that are close to tolerance limits may
not fail specications, and consequently may not be faulty.
Hence, also for global parametric faults, determining if a
parameter deviation results in a parametric fault involves
determining the map between the random variables describing
the manufacturing process and circuit performances [15], [16].

Typically, this is done using statistical modeling methods,
where, based on a limited set of simulations, an equation
is constructed for each circuit performance as a function of
parameters modeling global variations in the manufacturing
process and as a function of circuit parameters modeling local
variations due to defects [33], [41][46]. Given models for
each circuit performance and their corresponding specication,
the set of parameters where all specications are satised may
be determined, called the acceptability region. Conversely, the
set of parameters where at least one specication is failed
is likewise determined (Fig. 4). Moreover, if the parameters
characterizing the variations of the IC manufacturing process
are described by a probability density function, parametric
faults may similarly be characterized by a probability density
function.
What is fault coverage for parametric faults? For local
parametric faults, created by defects, a fault list can be
generated from a layout using tools similar to those designed
for creating catastrophic fault lists [25]. Such tools mimic
the defect size and frequency distribution for each layer of
a manufacturing process by placing extra or missing material
in a given layer of a layout and extracting the resulting circuit
changes. Those circuit changes that result in faults can be
identied using the map relating parameters to measurements.
Fault coverage is consequently the fraction of those circuit
changes that result in faults that can be detected by a given
test set.
Computing fault coverage for global parametric faults is
more complex. The digital/catastrophic fault coverage deni) does not apply for such faults since such faults
tion (
are characterized by a continuous distribution rather than a
discrete one. Nevertheless, the ratio of the likelihood of faults
detected over the likelihood of faults simulated is an equivalent
denition of parametric fault coverage [15], [16], [47]
where
is the probability density function of parameters
modeling the manufacturing process,
is the complement
of the acceptability region, i.e., the set of all parametric faults,
1396
and
is the set of parameters which correspond to circuits
that fail a given test set.
A straightforward way to evaluate the integrals in the above
equation is to use Monte Carlo analysis, where a sample of
parameters from the probability density function describing
the manufacturing process is simulated. At each , it is rst
, and if so,
determined if is a fault, in which case
is detected, and if so
.
it is determined if
is a fault and if it is
The evaluation of whether or not
detected may be determined directly, using circuit simulation,
or based on regression models of circuit performances, dening parametric faults. However, applying the Monte Carlo
algorithm directly by simulating a circuit with a sample of
parameters representing the manufacturing process may not
lead to accurate results. Specically, if a small sample size is
used, results will be inaccurate because of the sample size. In
fact, unless a test is highly inaccurate, it may be hard to nd a
sample of faulty parameters which is not detected by the test
and
. Alternatively, if the sample size is
set, i.e.,
large, the computational cost of simulating just the blocks, i.e.,
op amps, if not the whole system, hundreds of times, can be
very high, unless very inaccurate simulation models are used.
Importance sampling can reduce this cost of simulation [48].
Nevertheless, when applying the Monte Carlo algorithm, the
use of regression models of block performances as a function
of process parameters and a hierarchical simulation strategy
reduces the computational cost most effectively with accurate
results [33], [41], [42], [46]. In other words, a limited set
of simulations is performed to construct regression models,
and then the regression models are used to evaluate if tests
are passed or failed for the much larger random sample of
parameters representing manufacturing process variations. In
this case, the most signicant sources of inaccuracy will come
from a combination of the accuracy of circuit simulation,
which is used to construct the regression models, and the
ability of the regression models to mimic the simulator.
If all circuit specications are tested, the parametric fault
coverage may still not be 100%, due to measurement noise
[15]. Moreover, if tests other than the specication tests are
used, as proposed in [28], [39], [47], and [49], there may be
a systematic loss of fault coverage (Fig. 5). Similarly good
circuits may fail tests due to measurement noise and if tests
other than the specication tests are used. Yield coverage ( )
has been proposed as a parameter to quantify the problem of
discarding good circuits [47]
Yield coverage may be computed in the same way as fault

coverage.
Given the three denitions of fault coverage above, i.e.,
catastrophic fault coverage, local parametric fault coverage,
and global parametric fault coverage, which one should be
used when evaluating a test set? Sachdev, in [50], considered
Fig. 5. Systematic loss in fault coverage and yield coverage.
Fig. 6. Test results for the Class AB amplier and the measured performances for the three devices that failed specication tests but passed the
proposed test set for catastrophic faults [50].
generating test sets for just catastrophic faults. The test set
he proposed for a Class AB amplier was derived based on
realistic catastrophic faults and demonstrated high catastrophic
fault coverage of modeled faults by simple stimuli, i.e., simple
dc, ac, and transient stimuli. This test program was then
appended to the existing conventional (specication-based)
test program, in order to judge its effectiveness in a production
test environment. The results are shown in Fig. 6. As can
be seen from the gure, the yield of the device was very
high (99.5%), and the fault coverage of the proposed test set
was only 73%. The performances of the three devices which
passed tests for catastrophic faults but failed specication
tests are also shown in Fig. 6. Because the proposed test
set was designed to detect catastrophic faults and because
distributions of both local and global parametric faults have
higher frequencies of parameter values that correspond to
circuit performances close to specication limits, it appears
from these results that these three devices failed due to
parametric faults.
Because the sample of failed devices was so small, Sachdev
[50] followed up this experiment with a larger one using the
same Class AB amplier. The results of this second experiment
are shown in Fig. 7. It can be seen that the fault coverage
of the test set designed solely for catastrophic faults was
87%. The 433 circuits that failed the proposed test set but
had passed the conventional test set were then retested by
the conventional method. Of these 433 circuits, 51 passed
the conventional test set, indicating that measurement results
are very close to specication limits, causing the circuit
to pass or fail based on noise levels. The remaining 382
circuits mostly failed specications on the input offset voltage,
total harmonic distortion, and the signal-to-noise ratio. All of
1397
Fig. 7. Test results for the Class AB amplier.

CATASTROPHIC FAULTS
TABLE II
HIGH-PASS FILTER BLOCK [33]
FOR A
these specications are very sensitive to transistor matching

in the differential ampliers. Since poor transistor matching
is a parametric fault, it is likely that these circuits failed
for parametric faults. Clearly, it can be concluded that a
test based solely on process defects (catastrophic faults) is
not sufcient for ensuring that specications are satised,
and consequently catastrophic fault coverage is insufcient
in quantifying the quality of a test set for analog circuits.
This is likely because, unlike digital circuits, which tend to
have less tight performance requirements but more functional
complexity, optimal analog circuit performance is often only
achievable under optimal fabrication and operating conditions.
Hence, the parametric fall-out for analog circuits is likely to
be more signicant compared to digital designs.
Suppose, on the other hand, a test set is designed for
high parametric fault coverage. Would such a test set be
able to detect catastrophic faults? In [15], [16], and [33],
algorithms for selecting optimal sets of specication tests
based on parametric fault coverage have been presented.
Specically in [33], a subset of 1024 frequency measurements
and measurements of the system offset, dynamic range, and
total harmonic distortion for a bandpass lter was selected.
This bandpass lter is a switched-capacitor design, composed
of ve blocks, one high-pass lter, three biquads, and one
sum-gain amplier. For each of the blocks, local defects were
generated in the layout using VLASIC [25] in order to obtain
a fault list. Each fault was simulated in order to compute the
resulting distortion of parameters characterizing each of the
blocks, i.e., gain, offset, etc. The results for the high-pass
block are shown in Table II, where modications in block
performances could be classied in eight groups, the most

common two being low gain and xed output voltage. System
simulation using the behavioral model was then performed in
order to determine if specication tests are passed or failed. It
can be seen from Table II that almost all of the catastrophic
faults failed all of the specication tests. The 5% of the
catastrophic faults that did not fail all specications resulted
in circuits that under nominal processing conditions would
pass or almost pass all specication tests. Hence, for these
faults, the impact of these catastrophic faults is to lower yield.
And, it turned out that the specication tests needed to achieve
high parametric fault coverage were sufcient to detect these
catastrophic faults when they were combined with variations
in parameters and resulted in circuits that failed specications.
Consequently, in this example, a test set designed for high
parametric fault coverage also achieved 100% catastrophic
fault coverage.
It seems that it can be concluded that test sets should be
evaluated both in terms of parametric and catastrophic fault
coverage. Moreover, based on the limited set of experiments
that have been done to date, there seems to be some evidence
that test sets designed for high parametric fault coverage are
more likely to detect catastrophic faults compared to the ability
of test sets designed for high catastrophic fault coverage to
detect parametric faults.
IV. FAULT DIAGNOSIS
If an integrated circuit has been found to be faulty during
design characterization, before it is in high volume production,
it may be useful to diagnose the cause of the failure. If faults
1398
Fig. 8. Decision boundaries between the good circuit and three faulty circuits for measurement
are identied and located, a circuit can be redesigned to be

less sensitive to common failure mechanisms. Alternatively,
if an analog or mixed-signal system with components that
have been separately tested fails system specications, it
is also useful to nd the cause. In this case, problems in
system performance can occur due to assembly errors and
the degradation of components with time. It is therefore
desirable to have a methodology to rapidly identify component
failures. Two distinct strategies have been proposed for analog
fault diagnosis: simulation-before-test and simulation-aftertest. Simulation-before-test approaches begin with a fault list.
The faults are then simulated to determine the corresponding
responses to predetermined stimuli. Faults are consequently
diagnosed by comparing simulated and observed responses.
Simulation-after-test approaches, on the other hand, begin with
the failed responses, which are then used to estimate faulty
parameter or component values. For a comprehensive survey
of these approaches see Bandler and Salama [2]. The sections
below are intended to give a brief overview.
Fault diagnosis techniques need fault models. Simulationbefore-test techniques are better suited for detecting catastrophic faults and local parametric faults, while they may
perform less well in detecting global parametric faults, since
for such faults the separation between good performances
and faulty performances is less wide. On the other hand,
simulation-after-test techniques are better suited for detecting
problems with global parametric variations and mismatch, and
are not well suited for detecting catastrophic faults.
A. Simulation-Before-Test
Simulation-before-test algorithms are based on a fault dictionary. In particular, the most likely faults (usually catastrophic) are anticipated based on a fault model, and a set of
input stimuli and measurements are selected to detect faults.
The measurements may be dc responses [51], ac responses
at circuit outputs [52][55], ac responses at the power supply
node [56], transient responses at circuit outputs [57], [58], or
transient responses at the power supply node [59]. Then for the
set of potential faults, the circuits response for each stimulus
is evaluated for each fault with all but the faulty parameter set
to nominal values, i.e., the parameters for which the circuit was
designed. The responses for each fault are typically evaluated
using circuit simulation, except for the special case when the
circuit is linear, where efcient techniques exist for computing
the faulty responses [55], [60], [61]. In particular, in [55] a
assuming equal prior probabilities.
symbolic simulator is proposed for evaluating the impact of

faults on the frequency response of a circuit, greatly reducing
the computational cost needed to construct a fault dictionary. It
is also possible to construct a fault dictionary using measured
data, based on previously observed and diagnosed faults.
After evaluating the responses corresponding to the faults,
the faults and their corresponding responses are stored in
a dictionary. To diagnose a fault, the measurements of the
circuit being tested are compared with measurements in the
dictionary. The fault is identied by determining the closest
simulated fault using inspection [53], [58], the Euclidean norm
[51], [54], [55], pattern matching [52], fuzzy distance [62], or
a neural network [59].
If parameters are assumed to lie exactly at their nominal
values when the fault dictionary is constructed, errors in
fault identication can occur. Parameters are usually not at
nominal values because of uncontrollable uctuations in circuit
fabrication. Consequently, it is unlikely that measurements
will have values exactly equal to those stored in the fault
dictionary. Furthermore, different faults may result in exactly
the same measurement because of variations in components.
Approaches which account for distributions of parameters
[63], [64] typically begin with Monte Carlo simulations of
all anticipated faulty circuits and the good circuit. The use
of Monte Carlo analysis, although greatly increasing the
computational cost, provides estimates of the mean vectors
and covariance matrices
of the distributions for the good
and every type of faulty circuit. Maximum likelihood is taken
as the measure of distance to determine the most likely fault
be the prior probability of the th
class. Specically, let
is the likelihood of the th fault type based
fault type, i.e.,
on past data. Then for an observation , the corresponding
fault is identied as belonging to fault class if the quadratic
discrimination score is minimum
Fig. 8 shows the decision boundaries which separate fault

classes, assuming equal prior probabilities. If it is known that
the good circuit is much more likely than, say, fault 1, the
decision boundary would shift to the left, making it more likely
to identify the good circuit compared to fault 1. Moreover,
are updated, the
if during testing the prior probabilities
decision boundaries between faults would change accordingly.
Some faults may result in measurements that are very close
to each other (Fig. 8). In this case, the probability that a
fault will be wrongly diagnosed is high. Some algorithms

attempt to aggregate faults into ambiguity groups, assuming
parameters are within tolerance. Faults are said to belong to
the same ambiguity group if they cannot be distinguished by
a given set of measurements. To rigorously aggregate faults
into ambiguity groups, it is necessary to determine the set
of measurements that can result from each fault, given that
parameters are within tolerance. Specically, for the example
in Fig. 8 it would be necessary to determine the sets of
measurements which may result from, say, faults 2 and 3.
And, it can be seen from the gure that these sets clearly
overlap, and hence the faults should belong to a common
ambiguity group. Rigorous algorithms for the computation
of the sets of measurements resulting from each fault are
presented in [62] for linear circuits and in [28] for nonlinear
circuits.
The success of an algorithm in correctly diagnosing faults
depends on its choice of measurements. The best choice of
measurements should result in a maximum separation between
the good circuit and faulty circuits, and among faulty circuits,
as indexed, for example, by
and
where
and
are the mean and standard deviation for
and
are the
a measurement for the good circuit, and
means for faulty circuits. Algorithms for selecting an optimal
set of measurements have been presented in [28] and [65]. For
the special case where testing is restricted to the frequency
domain, theoretical guidelines for frequency selection exist
[52], [54]. In particular, a set of frequencies should be chosen
so that at least one is between each break point in the frequency
response, plus one before the rst breakpoint and one after the
last breakpoint.
B. Simulation-After-Test
Simulation-after-test algorithms have been designed to solve
for values of component parameters, given a set of measured
responses and knowledge of the circuit topology. In other
words, given that a simulator can be used to nd measured responses for a set of component parameter values, the
simulation-after-test problem is to determine the inverse map.
A fault is identied if one or more parameter values are found
to be outside of tolerance. Hence a fault can be diagnosed if it
is possible to uniquely solve for all parameters from the given
measurements. Clearly there need to be enough independent
measurements to identify all parameters. And, under these
conditions, faults can be diagnosed by solving a nonlinear set
of equations. However, the solution is only locally unique for
both linear [66][68] and nonlinear [69][72] circuits, except
under the special case where testing of a linear network is
performed at a single frequency [73], [74]. Nevertheless, to
identify all circuit parameters, a formidable set of nonlinear
equations has to be solved, and to reduce computation, algorithms have been developed based on the assumption that
only a few parameters are faulty, for both linear [75], [76]
and nonlinear [70], [77], [78] circuits. Solving for only a
few faulty parameters also reduces test point requirements.
1399
But since the faulty parameters are not known in advance, a

search is required. Since these algorithms solve for only a few
parameters, when searching for the set of faulty parameters,
all other parameters are assumed to be at nominal values, and
this raises the question of robustness. Because it can only
be guaranteed that good parameters are in tolerance, it is
possible that wrong faults will be identied, as can occur
with simulation-before-test algorithms if faults belong to a
common ambiguity group. Moreover, because of the amount of
computation required on-line, these algorithms are practically
restricted to small circuits (50100 components). Nevertheless,
parameter identication algorithms are equally applicable to
modules, reducing the size of the problem for large circuits,
or to detecting process control problems which result from
large variations in the global and mismatch parameters that
model variations in the manufacturing process. On the other
hand, common fault mechanisms, like catastrophic faults,
cannot easily be diagnosed without substantially increasing
the complexity of the numerical analysis. They can cause illconditioning and difculty in convergence of the numerical
solution.
Under the conditions that measurements vary approximately
linearly as a function of changes in parameters, and faults
are not catastrophic, but rather moderate changes in system
component parameter values or parameters modeling uctuations in the manufacturing process, matrix techniques can be
used to solve for parameter deviations from nominal. Solving
for parameter deviations may help identify problems with
component aging. Alternatively, if a circuit has previously
been screened for catastrophic faults, using an algorithm such
as the ones suggested in [28] and [50], solving for global
parameter values which model the manufacturing process may
help identify those parameters that are not well controlled
by the manufacturing process. In other words, such an analysis may help us identify critical mismatch parameters, for
example, as in [21].
Specically, if is an -dimensional vector of measurements, is an -dimensional vector of parameters, and is
a sensitivity matrix
If has rank , it is straightforward to solve for parameter

deviations from nominal using least squares
will have rank

if all of the sensitivity vectors are
are independent. If
unique, i.e., all of the columns of
there are dependencies or near dependencies in the sensitivity
vectors, the above equation is less solvable, and the component
values of the circuit or the process parameters are said to
be less diagnosable. In fact, small amounts of measurement
noise can induce wide variations in the computed parameter
values . The parameters that correspond to nearly dependent
columns are said to belong to ambiguity groups. This means
that these parameter deviations cannot be separately identied
without additional measurements. Algorithms for nding such
ambiguity groups have been developed in [19][21] and have
1400
been discussed in Section III-B. In addition, classications

of types of ambiguity, i.e., fault masking, fault dominance,
and fault equivalence, are presented in [79]. However, even
if all parameters can be identied, their values cannot be
precisely determined, due to measurement inaccuracies and
unmodeled variables. Specically, given variations of comwithin tolerance and
ponent or process parameter values
measurement uncertainty, the minimum parameter changes
that can be diagnosed can be determined and the corresponding
best measurements can be identied [80]. Moreover, given
measurement uncertainty, in [20] the accuracies of parameter
estimates are discussed, for both the cases where parameters
can be separately computed and where there are ambiguities
among parameters.
V. DESIGN
FOR
TESTABILITY TECHNIQUES
Fig. 9. Boundary scan chain on a board.
The increased complexity of analog circuits and the reduced

access to internal nodes has made it not only more difcult to
diagnose and locate faulty components, but also the functions
of embedded components may be difcult to measure. Designfor-testability techniques at the very least aim to improve
the controllability and observability of internal nodes, so that
embedded functions can be tested. Such techniques include
analog test busses and scan methods. Testability can also be
improved with BIST circuitry, where signal generators and
analysis circuitry are implemented on chip. A brief overview
of these techniques will be presented in the following sections.
A more detailed discussion can be found in [5] and [81].
A. Improving the Controllability and
Observability of Internal Nodes
Fig. 10. Modied boundary scan for a mixed-signal component.
Improving the testability of increasingly complex digital

designs has resulted in the widespread use of scan chains.
Scan chains involve shift registers, where data is serially
shifted in through a test data input pin and through the scan
chain to reach internal nodes. The test is performed and the
results are captured in registers. The results are then serially
shifted to the output through the registers to reach the test
data output pin. Scan chains not only make it possible to
improve fault coverage, but also make it possible to link
failures to specic circuit blocks. In addition, at the board
level, new high-density packaging technologies have made
it more difcult to identify failing components in a system.
With such packaging technologies, once a chip is attached to
a package, its pins are no longer accessible, and the ability
to remove a part reliably and without damage for testing
purposes may be limited. Boundary scan has been proposed
to address this controllability and observability problem for
system debug, where all chip pins for all components in a
system are connected in a scan chain (Fig. 9). A key advantage
of boundary scan has been its ability to detect opens and shorts
in the boards wiring, since 8090% of board failures result
from wiring problems. Hence, boundary scan cells combine
the shift registers that are used to input and output voltages to
and from the core circuitry with components that a) disconnect
the IO pin from the core, b) set the IO pin to a logic level,
and c) detect the logic level on another IO pin.
In the mixed-signal domain, Fasang [82] has proposed the

use of boundary scan for mixed-signal designs. He proposes
taking advantage of the fact that many mixed-signal designs
have ADCs and DACs on chip. These can be used to digitize
all analog outputs before they are stored in scan cell registers
and shifted to external pins and to convert digitized analog
input signals which are shifted into the scan path into analog
inputs for the analog components. The proposed modied
boundary scan path for a mixed-signal component is shown
in Fig. 10.
This conguration provides some controllability and observability of both digital and analog components. However,
this conguration does not make it possible to isolate failures
within the analog blocks. In order to enhance our ability
to diagnose failures within analog blocks, it may be desirable to separately test the components of the analog blocks,
i.e., ADCs, DACs, operational ampliers, oscillators, phaselocked loops, lters, etc. Given a partition of a complex
chip, component test requires the isolation of the blocks, the
control of component inputs, and the observation of component
outputs. In [83], a set of nodes to be accessed and component
tests to be performed, together with their test conditions, are
outlined for some common analog building blocks. Isolation
of the blocks from digital circuitry can be achieved through
1401
Fig. 13. Voltage-based scan cell.
Fig. 11.
Analog test bus architecture.
Fig. 12.
Simplied schematic of a P1149.4 test bus pin [85].
interface storage elements, i.e., parallel or serial shift registers

organized in a scan chain [84]. Isolation between analog blocks
may be achieved through buffers, controlled by digital circuitry
[84]. In addition, it may be necessary to disable feedback loops
in order to measure open-loop parameters, since feedback
reduces input controllability.
Given a set of nodes that need to be accessible in order
to test the blocks, it is generally neither feasible nor practical
to bring all of these nodes of an integrated circuit out to the
package pins. One way to enhance observability is to add a
small metal contact connected to the node. The signal can then
be measured with either buffered high-impedance micro probes
or an electron beam tester. The chip area required for such a
contact is signicantly less than what is needed for a bond, but
if many such contracts are used, the area overhead may become
signicant. Alternatively, analog inputs and outputs may be
combined by multiplexing and routed to primary inputs and
outputs. Such a conguration is called an analog test bus [85]
(Fig. 11). In this case any block input and/or output would be
externally addressable so that real-time data may be input and
observed. Even nodes which are shielded for electromagnetic
interference can be made observable. The analog test bus cell
shown in Fig. 12 has been designed as an analog boundary
scan cell, although it can also be used to access internal analog
nodes. It therefore has components designed to check board
connectivity, i.e., to a) disconnect the IO pin from the analog
macro, b) set the IO pin to a logic level, c) detect the logic
level on another pin, and d) connect the IO pin to the two-wire
analog test bus.
Clearly the design of the test bus must be done with
care. Specically, the test bus pin should not distort the
real-time signals entering and leaving the blocks. Except

for very high frequency nodes, the capacitance load added
by, as a minimum, the two test bus transmission gates, the
multiplexer/comparator, and the tri-state digital inverter is
unlikely to cause signicant distortions of internal signals
[85]. On the other hand, the bus capacitance, combined with
the high impedance of the transmission gates, may distort
the signal that is observed at or driven by the output pin,
by increasing delays and reducing bandwidth. Nevertheless,
transmission gates or buffers can be designed to allow for
higher output signal bandwidth at the expense of additional
capacitive loading and/or area [85].
For high-speed testing of many analog signals simultaneously, the two signals at a time controllability and observability
capability of the analog test bus may not be sufcient. Instead,
Wey [86], [87] and Soma [88] have proposed an entirely
analog scan path implementation. In [86], voltages are stored
in the scan cells, which are composed of sample-and-hold
circuits, each built with a switch for sampling, a capacitor
for storage, and a voltage follower for impedance buffering
between capacitors (Fig. 13). In order to minimize the inuence of the analog shift register test circuit on the node being
observed, a high input impedance and low output impedance
buffer is placed between the node and the sampling switch.
When a test is performed, data at various test points is
by closing
simultaneously loaded to the holding capacitors
. To scan out, the switch
is opened and a twoswitch
phase clock is used to scan out voltages, like for digital scan
is closed so that the voltage on
chains. Specically, rst,
is copied to . Then,
is closed to copy the voltage to
the next cell. This process continues until all voltages reach
the output.
In [87] and [88], currents, instead of voltages, are passed
through the scan chain. The shift register is composed of
current mirrors and switches. A possible implementation is
shown in Fig. 14. In this approach, if a node voltage is being
observed, it is rst converted to a current and isolated from the
test circuitry with a V/I converter. During loading, the switch
is closed, and the current ows through transistor
and sets the voltage on capacitor
to the level needed for
to support
. The transistor
is now capable of
when connected to a load. Then to scan
sinking a current
is opened and the switches
and
out the stored current,
are alternately closed. When
is closed, transistor
is connected to a load, and consequently sinks . As a result,
ows through
and charges up
, so that
will
when it is connected to a load. Then, in
ow through
1402
Fig. 14.
Current-based scan cell.
the next clock phase,

is opened and
is closed, so that
is then copied from
to
of the following cell.
As with the voltage scan chain, this process continues until
cell currents reach the output. It should be noted that in both
the current-based and the voltage-based approaches, scan chain
length is limited by accuracy requirements. For example, clock
feedthrough and mismatch in the current mirror transistors can
limit the accuracy of the scanned currents and voltages.
B. Analog Built-In Self Test
When test busses and scan circuitry are used to enhance
testability, signals have to be transmitted through long wires
and/or have to pass through transmission gates before they
can be measured. Hence, analog signals can be corrupted,
and distortion may occur before measurements are made due
to parasitic loading and coupling. BIST circuitry helps to
overcome this problem by going beyond simply controlling
and observing component inputs and outputs. Instead, signal
generators and analysis circuitry are implemented on chip, and
since signals do not have to be routed off chip, it is likely that
there will be less distortion of these signals when they are
measured. Consequently, dynamic tests can be performed at
full speed even during wafer probe and in the eld, without
external test equipment. And the only signal that needs to be
routed off chip is a pass/fail bit indicating the test results.
On the other hand, one major problem faced by BIST circuit
designs is the area overhead. Moreover, the design of highquality signal generators and analysis circuitry can be complex
and time-consuming.
The hardware overhead for BIST is minimized if the test
circuitry is used by much more than one of the analog
components. In addition, some BIST designs only attempt to
perform on-chip analysis of test results and rely on external
signal sources, thereby minimizing the hardware overhead.
These designs are mainly targeted for on-line test of high safety
systems, i.e., testing during operation. They signal errors due to
component degradation, electromagnetic interference, or heat.
Such circuits either rely on area redundancy (multiple copies
of the same hardware) or time redundancy (the same hardware
is used to carry out repeated operations).
In [89], a BIST circuit has been proposed for switchedcapacitor lters, relying on partial replication of the circuit
being tested (area redundancy). Using this technique, online testing is performed by rst decomposing the lter into
its component biquads. Multiplexing makes the input and
output terminal of each biquad accessible. The circuit relies

on a programmable biquad to implement a copy of each of
the component biquads (Fig. 15). The programmable biquad
can implement any of the basic lter types, i.e., low-pass,
bandpass, and high-pass, and many different frequency specications by changing the capacitance values for each node.
During testing, the same signal is input to the programmable
biquad as the component biquad being tested, and the resulting
continuous signals are compared in real-time using a voter
circuit. The voter circuit indicates an error if the outputs of the
two lters differ by more than a specied tolerance margin at
any time. An absolute acceptance window is implemented in
[89], but in [90] it is noted that an absolute tolerance window
can be too restrictive for signals with a large swing. Therefore,
as an alternative, a circuit signaling an error based on a relative
tolerance window has been proposed. In addition, instead of
comparing signals in the time domain, the signal of the circuit
being tested can be compared against a reference signal in
the frequency domain as well, using a gain detector, phase
detector, and a window comparator [91]. Note that for all
techniques, the programmable biquad is used by all lters on
the chip, and as a result, the area overhead is essentially limited
to the area required for the programmable biquad.
Another approach to concurrent testing relying upon area
redundancy involves using a continuous checksum [92]. In
this case a circuit must be approximately linear. As a result,
the time domain response can be described by state equations.
A check variable is dened as equal to a linear combination
of the state variables, and in this approach additional circuitry
is proposed which outputs the check variable. Consequently,
the additional circuitry produces a continuous nonzero signal
when the signals corresponding to the state variables deviate
from nominal.
Finally, in contrast to the previously mentioned approaches,
time redundancy is exploited for concurrent testing of ADCs
in [93]. Time redundancy employs a single piece of hardware
to carry out repeated operations. In order to avoid producing
the same erroneous result twice, in the repeated cycle, the
input operand is coded and the result decoded, after which a
comparison is made with the result obtained in the previous
cycle.
All of the above techniques should be effective in detecting
local catastrophic and some local parametric faults, since,
given an appropriate input signal, there should be a clear
discrepancy between the test circuits output and that of the
component being tested. On the other hand, because of the area
overhead, the yield of the die will decrease [40]. This decrease,
nevertheless, is likely to be small, if the area overhead of
the test circuit is small. Such circuitry is likely to be less
effective in detecting global parametric faults and component
degradation since component variations in the test circuitry are
likely to track those in the circuit being tested. Hence, only
major changes in component values are likely to be detected.
C. BIST for Mixed-Signal Integrated Circuits
When designing BIST circuitry for mixed-signal integrated
circuits, it is often possible to exploit existing on-chip hard-
Fig. 15.
A programmable biquad [89].
Fig. 16.
1403
An example of a mixed-signal circuit architecture.
ware and consequently reduce the area overhead needed for the
on-chip generation of test signals and analysis of test results. In
particular, such circuits have DACs and ADCs which may be
used for testing through reconguring the connections between
blocks. By taking advantage of ADCs and DACs, which are
already part of a design, mixed-signal circuits can be tested
with digital testers, components may be tested in parallel, and
testing is more easily performed in the eld.
A common architecture for a mixed-signal circuit is shown
in Fig. 16. This architecture assumes that a mixed-signal
circuit is composed of analog input components, connected to
a large digital section by an ADC, which in turn is connected to
analog output components by a DAC. Given the on-chip DAC,
a digital test stimulus may be implemented on-chip, in order
to test the analog output block. Specically, Ohletz [49] has
proposed a pseudorandom piecewise-constant input signal with
different amplitudes, generated with a linear feedback shift
register (LFSR), the DAC, and an output amplier (Fig. 17).
Alternatively, input stimuli could come from a ROM or DSP
circuitry, rather than an LFSR. All of these approaches keep
Fig. 17. An input stimulus generator [49].
the hardware overhead to a minimum by reconguring and

reusing existing circuitry on chip during the test mode.
During test mode, outputs of the analog output block may
be measured or routed to the analog input pins (Fig. 18).
The outputs of the analog input block are embedded on
chip and therefore not accessible. However, during the test
mode, these outputs may be measured after conversion of the
signal to digital by the on-chip ADC. One way to capture
the output is by built-in logic block observers (BILBO) [49],
1404
Fig. 18.
Implementation of the BIST scheme in [49].
[94], which are also used for digital test. The signals stored
in the BILBO registers may then be fed to a multiple input
signature register (MISR), which performs the task of onchip data compaction using signature analysis [49]. Hence,
the analog test results are consequently evaluated in the
digital domain, using the same techniques as used for onchip evaluation of the digital response. Nevertheless, signature
analysis is not the only way in which the digitized response
from an analog block can be analyzed. The response could
be compared against a known good response, stored in a
ROM, before compaction, or postprocessing may be done
based on the functional characteristics of the analog blocks.
Specically, in [39], given a pseudorandom piecewise-constant
input signal, circuitry for computing the auto-correlation and
cross-correlation of the impulse response is proposed.
In both [39] and [49], the effectiveness of pseudorandom
inputs in detecting catastrophic faults in analog components
has been demonstrated. However, the effectiveness of such
approaches in detecting both local and global parametric faults
still needs to be determined. Because the circuit performances
that are tested are different than the circuit specications, there
may be signicant systematic losses in fault coverage and/or
yield coverage for parametric faults.
In [95], a BIST circuit is proposed for looking at abnormal
changes in the power supply current. The proposed circuit
involves an upper limit detector, for detecting an abnormally
high power supply current, a lower limit detector, for detecting
an abnormally low power supply current, and some logic to
signal if there is a fault. The idea behind this approach is that
faults will either increase or decrease the power supply current
compared to the fault-free circuit. When using this power supply current monitor to test ADCs, the input voltage is varied,
so that all states of the ADC are exercised. A reasonable
fault coverage of catastrophic faults has been demonstrated by
simulation. Nevertheless, as with using random inputs to test
analog blocks, the effectiveness of this approach in detecting
local and global parametric faults is still unknown.
A more traditional signal generator is proposed for BIST
of ADCs in [4] and [96]. Specically, tests are designed
to measure the signal-to-noise ratio, gain tracking, and the
frequency response of a sigmadelta ADC (Fig. 19). The
stimulus is a precise multitone oscillator designed for an
uncalibrated environment [97], [98]. The design of the oscillator is fully digital, except for an imprecise low-pass
Fig. 19. BIST circuit for testing ADCs [4].
Fig. 20. Signal-to-noise ratio test using a correlator circuit [5].
lter, and it is digitally programmable for multiple amplitudes,

frequencies, and phases. Three digital methods are proposed
for analyzing test results: the fast Fourier transform, the
IEEE standard 1057, and a narrow-band digital lter. The
fast Fourier transform approach nds the signal and noise
powers using a correlator circuit, like the one shown in Fig. 20.
Hence, the on-chip computing resources that are required to
implement this approach include registers to store the samples,
plus circuitry to either compute or look-up values for the sine
and cosine functions. The IEEE Standard 1057 nds the signal
and noise powers by tting a sinusoid using regression and
requires similar on-chip resources. And lastly, the narrow-band
digital lter approach relies on on-chip bandpass and notch
lters, as shown in Fig. 21. In [4] and [96], it is argued that
the area overhead for the narrow-band digital lter is the least
of the above three methods, but the test results are biased, since
some of the noise power may be mistakenly included in the
signal power. However, the bias may be minimized through
proper design of the lter.
It is not only possible to build BIST circuitry for ADCs,
but also DACs can be tested with on-chip circuitry. In [99],
Fig. 21.
Signal-to-noise ratio test using a digital lter [4].
Fig. 22.
Mixed-signal BIST scheme [4], [5].
a BIST circuit has been designed to test offset, gain, integral

linearity, and differential linearity of DACs. For this circuit,
the input is a digital sequence generated on chip, and the output
is analyzed with sample-and-hold circuitry, various reference
voltages, and a comparator. A modied version of this circuit
has also been proposed for testing successive approximation
ADCs, since they involve DACs.
Finally, since many circuits contain both ADCs and DACs,
a sequential strategy for verifying both is proposed in [4]
(Fig. 22). First, all digital circuitry is tested, including the
digital components of the DAC, ADC, and the on-chip signal
generator. Then, the ADC is tested using the on-chip digital
oscillator. Next, the smoothing lter of the DAC is tested
using signals from the digital signal processing unit. Its output
is digitized by the ADC, and its response is analyzed by
the digital circuitry. This veries the functionality of the
smoothing lter, and the combination of the digital signal
generator and smoothing lter can now be used as a calibrated
analog signal source. This also completes the testing of the
DAC and ADC, since all other digital circuitry has been tested.
Once the DAC, ADC, and signal generator are considered
functional, the converters and the analog signal generator can
be used to test other on-chip analog functions.
The fault coverage of this approach to on-chip BIST still
needs to be veried. However, because the test methods are
very similar to traditional functional testing, it is likely that
fault coverage will be high, even for global parametric faults.
This is because, although global parametric variations in the
test circuit will track those in the circuit being tested, the
functions of the test circuit and the circuit being tested are
different, and hence process sensitivities are likely to differ. As
a result, one can expect less systematic loss in fault coverage
and yield coverage for parametric faults.
VI. SUMMARY
Recently, work on analog testing has evolved from its
early focus on diagnosing failures and degradation in analog
1405
board designs toward a focus on production test, including

CAD tools for test set design and optimization, and circuit
design techniques targeted to explore the tradeoff between
on-chip versus external testers. Clearly, diagnosing failures
is still important. Many circuits are still designed with discrete components, and failures in the eld should be quickly
corrected. Moreover, integrated circuits must be characterized
before production runs, and this involves determining any
systematic sources of yield loss, including components whose
performances may uctuate too much due to variations in
manufacturing. However, the new areas of research in analog
and mixed-signal testing are motivated by new concerns.
Specically, as analog and mixed-signal circuits become more
complex and have shorter product cycles, they frequently
cannot be tested using methods developed in the past, due
to the longer testing times needed for high precision analog
components and the lack of accessibility of analog components
embedded in large mixed-signal chips. Research addressing
these problems is still preliminary and is likely to evolve
rapidly in the coming years.
ACKNOWLEDGMENT
The author would like to thank M. Ohletz, W. Kao, and the
four reviewers for their helpful comments on this manuscript.
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Linda S. Milor (S86M90) received the Ph.D.

degree in electrical engineering from the University
of California, Berkeley, in 1992.
She is currently the Device Engineering Manager in the Yield Department in the Submicron
Development Center at Advance Micro Devices,
Sunnyvale, CA, where she has been working since
1995. Before joining Advanced Micro Devices, she
was an Assistant Professor with the Electrical Engineering Department at the University of Maryland,
College Park. She has published in the areas of yield
modeling, yield enhancement, circuit performance prediction, testing of analog
integrated circuits, and statistical modeling.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO.

10, OCTOBER 1998

A Tutorial Introduction to Research on

Abstract Traditionally, work on analog testing has focused

Fig. 1. Test setup for a mixed-signal device [5].

outputs, making it more difcult to locate component failures

10577130/98$10.00 1998 IEEE

are also used to quantify the extent of nonlinearity in an output

involves selecting input signals and measurements, in addition

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

Fig. 2. Ideal potential time-to-market reduction due to the use of electronic

Fig. 3. The test environment.

language of the target tester, and, of course, the circuit. Under

measurement instruments and larger analog blocks. If the

fault coverage of subsets of a test set can be computed based

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

high fault coverages, since if large sample sizes are available,

Alternatively, for an empirical model, the columns of would

For a circuit, the results of measurements

be chosen, where the rank of

that block exposure of a local area during masking, oxide

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

Simulating both catastrophic and parametric faults can be

the manufacturing process and circuit performances [15], [16].

Yield coverage may be computed in the same way as fault

Fig. 5. Systematic loss in fault coverage and yield coverage.

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

Fig. 7. Test results for the Class AB amplier.

these specications are very sensitive to transistor matching

performances could be classied in eight groups, the most

are identied and located, a circuit can be redesigned to be

assuming equal prior probabilities.

symbolic simulator is proposed for evaluating the impact of

Fig. 8 shows the decision boundaries which separate fault

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

fault will be wrongly diagnosed is high. Some algorithms

But since the faulty parameters are not known in advance, a

If has rank , it is straightforward to solve for parameter

will have rank

been discussed in Section III-B. In addition, classications

Fig. 9. Boundary scan chain on a board.

The increased complexity of analog circuits and the reduced

Fig. 10. Modied boundary scan for a mixed-signal component.

Improving the testability of increasingly complex digital

In the mixed-signal domain, Fasang [82] has proposed the

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

Fig. 13. Voltage-based scan cell.

Analog test bus architecture.

Simplied schematic of a P1149.4 test bus pin [85].

interface storage elements, i.e., parallel or serial shift registers

real-time signals entering and leaving the blocks. Except

Current-based scan cell.

the next clock phase,

output terminal of each biquad accessible. The circuit relies

MILOR: RESEARCH ON ANALOG AND MIXED-SIGNAL CIRCUIT TESTING

A programmable biquad [89].

An example of a mixed-signal circuit architecture.