RRUS 01 1 - Log - 1
RRUS 01 1 - Log - 1
RRUS 01 1 - Log - 1
**************
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.708] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955520 (result: true)
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 953400, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 08:04:21.708] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.708] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 08:04:21.712] trDcProc dlCtrl.cc:228 INFO:Carrier id 780, FilterBran
ch id 0 is added into reEnabledCarrierFBList
[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 08:04:21.712] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 08:04:21.712] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 08:04:21.712] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 08:04:21.712] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 780
[2015-01-13 08:04:21.712] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
dev = 7, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state RAMPING
, de off, ga on; dev: 1, txFreq: 953400, state: IN
IT; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955500, state: OFF; dev: 4, t
xFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: OFF; dev: 6, txFreq: 0, sta
te: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, tx
Freq: 0, state: OFF;
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 3, rx: 0
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 953400
[2015-01-13 08:04:21.848] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:21.848] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955520 (result: true)
[2015-01-13 08:04:21.864] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-33.43[-61.50 -8.00] dB)
[2015-01-13 08:04:21.916] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 789, event: 8
[2015-01-13 08:04:21.916] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :8
[2015-01-13 08:04:21.916] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 08:04:21.972] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 08:04:21.972] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 08:04:21.972] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 08:04:21.976] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 08:04:21.980] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 315, event :1024
[2015-01-13 08:04:21.984] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
70 [0.1ns]
[2015-01-13 08:04:21.984] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1254), hardDelay:(834)
= 5; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:22.048] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:22.052] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 08:04:22.052] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 08:04:22.052] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 08:04:22.052] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 786 ENABLE ev
ent
[2015-01-13 08:04:22.052] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 08:04:22.052] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 786
[2015-01-13 08:04:22.056] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:18, clientId:102
[2015-01-13 08:04:22.068] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:22.068] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x1
[2015-01-13 08:04:22.068] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 789
[2015-01-13 08:04:22.068] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:22.068] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 953400, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955500, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95550
0, state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OF
F; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:22.068] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:22.072] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 08:04:22.072] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 08:04:22.072] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 08:04:22.072] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 08:04:22.072] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 789 ENABLE ev
ent
[2015-01-13 08:04:22.072] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 08:04:22.072] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 789
[2015-01-13 08:04:22.076] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 08:04:22.076] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:21, clientId:102
[2015-01-13 08:04:22.212] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f861f7 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
c3ca0 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb10
c5ac pa1Adj 0x4779
[2015-01-13 08:04:22.456] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.131801, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.48[-61.50 -8.00] dB)
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x84140008, dpdStat: 0x001000
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 08:04:22.648] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 08:04:22.676] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 58 deg
[2015-01-13 08:04:22.676] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 58 deg
[2015-01-13 08:04:22.676] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24786
DL releas
DL releas
DL releas
DL releas
BfnAdvancerAtFirstCarrier:1,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:41.988] trDcProc platformXDlDelayAdjust.cc:104 INFO:BFN_ADVANC
E bfnAdvanceAdjustedDelay[0] = 30436.197917
[2015-01-13 10:18:41.988] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 259 ns
[2015-01-13 10:18:42.004] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:12, clientId:102
[2015-01-13 10:18:42.016] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:42.020] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:42.020] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.024] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=782, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.024] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=908300, carrierFreqMax=908500
[2015-01-13 10:18:42.024] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 953400 and vector width to 200
[2015-01-13 10:18:42.028] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.028] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
[2015-01-13 10:18:42.028] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30e tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:42.028] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
73 [0.1ns]
[2015-01-13 10:18:42.028] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:42.028] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.028] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
2 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:42.032] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.032] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =55
0
UL setCarr
0
[2015-01-13 10:18:43.196] trDcProc delayCommHandler.cc:312 INFO:carrier:0x310 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.196] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
4 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.196] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:2):calc_tArpToTrp:-140117[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.196] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14012,filterBranch:2
[2015-01-13 10:18:43.200] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.200] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:18:43.200] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:18:43.200] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 2, value 438
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:2 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.200] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2077 ns
[2015-01-13 10:18:43.200] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.200] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:43.200] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.200] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:43.204] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298942 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1735
[2015-01-13 10:18:43.204] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30434[ns] = salCarrierReportedDelay:298942 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:43.204] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 261 ns
[2015-01-13 10:18:43.216] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:18:43.228] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:18:43.228] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 2, CPRI port 0
[2015-01-13 10:18:43.228] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:16, clientId:102
[2015-01-13 10:18:43.248] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.248] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:43.252] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 30 iteration
[2015-01-13 10:18:43.252] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(17), fb=(6), invalidCarrierId=(128)
UL setCarr
et tVldbUl to 2095 ns
[2015-01-13 10:18:43.272] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.300] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:18:43.300] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 6, CPRI port 0
[2015-01-13 10:18:43.300] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:17, clientId:102
[2015-01-13 10:18:43.324] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 784
[2015-01-13 10:18:43.324] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:16, clientId:102
[2015-01-13 10:18:43.328] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 785
[2015-01-13 10:18:43.328] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:17, clientId:102
[2015-01-13 10:18:43.388] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=1
[2015-01-13 10:18:43.392] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:43.396] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(19), fb=(1), invalidCarrierId=(128)
UL setCarr
73 [0.1ns]
[2015-01-13 10:18:43.404] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:43.404] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.404] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:78
7 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.404] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.408] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.408] trDcProc delayCommHandler.cc:312 INFO:carrier:0x313 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.408] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
7 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.408] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:1):calc_tArpToTrp:-140117[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.408] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14012,filterBranch:1
[2015-01-13 10:18:43.412] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.412] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:18:43.412] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:18:43.412] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 1, value 438
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:1 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.412] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2077 ns
UL setCarr
UL setCarr
80)
[2015-01-13 10:18:43.592] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
0 tRuReportedDelayUl:121717[0.1 ns] = tRuUl:125390 - tInternalBfnDelay:3673
[2015-01-13 10:18:43.596] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.596] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:18:43.596] trDcProc delayCommHandler.cc:312 INFO:carrier:0x316 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:18:43.596] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
0 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.596] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:0):calc_tArpToTrp:-140117[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121717 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.600] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14012,filterBranch:0
[2015-01-13 10:18:43.600] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.600] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.600] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.600] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:18:43.600] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:18:43.600] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 0, value 438
[2015-01-13 10:18:43.600] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:0 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.604] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2077 ns
[2015-01-13 10:18:43.604] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.632] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:18:43.632] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 0, CPRI port 0
UL setCarr
rate_result_phase: 58 deg
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25780
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29866 us.
[2015-01-13 10:18:48.408] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 3 deg.
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 30399 us. IntegerDelay: 0x1d3 FracDela
y: 0x2c
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fa
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2753, currentDpdDelay[1]=1720 (0.1 ns)
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.444] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298927 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1720
[2015-01-13 10:18:48.448] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298927 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:48.912] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 258 ns
[2015-01-13 10:18:48.924] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:18, clientId:102
[2015-01-13 10:18:48.932] trDcProc powerClassCtrl.cc:487 INFO:totGsmCarrierPwrDb
m :4892 is higher than selected higherPowerClass:4780, maxPowerClass:4900 will b
e set
[2015-01-13 10:18:48.932] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4900
[2015-01-13 10:18:48.940] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:48.948] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:18:48.960] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:18:48.960] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:18:48.964] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:18:48.964] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.964] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.980] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:48.984] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.348] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.364] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.396] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:18:50.412] dlCtrlProc dlCtrl.cc:312 INFO:DlCtrl::removeReEnableCa
rrierFBIfReceived: remove the filterBranchId = 0 from the reEnabedCarrierFBList
list upon receipt of TRX_TX_ON_IND
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 10:18:50.412] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 10:18:50.476] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eea18b C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
a255a C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb0e
281d pa1Adj 0x4779
q: 955500, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, sta
te: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: ON; dev: 8
, txFreq: 0, state: OFF;
[2015-01-13 10:40:31.636] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 780
[2015-01-13 10:40:31.640] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = 0 (gainOffset:0 + gainMargin:122)
[2015-01-13 10:40:31.640] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:31.640] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:12, clientId:102
[2015-01-13 10:40:31.640] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:40:31.644] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:31.644] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:40:31.644] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:40:31.644] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:40:31.644] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 780 event :4
[2015-01-13 10:40:31.644] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x1, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x0 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:31.684] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 1, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 953400, state: OFF; dev: 2, txFreq: 0, state:
OFF; dev: 3, txFreq: 955500, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, t
xFreq: 955500, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500,
state: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:31.684] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 955500
[2015-01-13 10:40:31.748] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:31.752] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
DL releas
DL releas
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:34.504] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 7; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0,
state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955500, state: ON; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: OFF; dev: 8, txFreq
: 0, state: OFF;
[2015-01-13 10:40:34.504] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 789
[2015-01-13 10:40:34.504] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.504] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:21, clientId:102
[2015-01-13 10:40:34.508] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:40:34.508] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:34.508] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:40:34.508] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :4
[2015-01-13 10:40:34.508] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 7, txLo: 955520, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95
5500, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955500, state: O
FF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:34.508] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955500, LoFreq = 955500
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:34.576] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
DL releas
nel supervision. Read value (3) below exceptional low limit (10).
[2015-01-13 10:40:34.944] timeOutSrv channelSupervision.cc:490 INFO:"IMpa0" chan
nel supervision. Read value (-8) below exceptional low limit (500).
[2015-01-13 10:40:34.948] timeOutSrv channelSupervision.cc:490 INFO:"IDpa0" chan
nel supervision. Read value (1) below exceptional low limit (100).
[2015-01-13 10:40:34.948] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x3, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x2014 C3 0
x0, ncoC0 0x0 C1 0x0 C2 0x8008 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955500, txLo: 955520, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955500
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955520, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x718E3700, dpdIqGiPeakNew = 0x
718E3700, dpdIqGqPeakOld = 0x729ACD00, dpdIqGqPeak
New = 0x729ACD00.
[2015-01-13 10:40:35.112] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955520 (result: true)
[2015-01-13 10:40:35.112] trDcProc dlCtrl.cc:228 INFO:Carrier id 786, FilterBran
ch id 2 is added into reEnabledCarrierFBList
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:40:35.112] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 10:40:35.112] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020000, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:35.112] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 786
[2015-01-13 10:40:35.112] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:40:35.112] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;
DL releas
0
[2015-01-13 10:41:19.984] trDcProc delayCommHandler.cc:312 INFO:carrier:0x30d tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:19.984] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
1 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:19.984] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
78 [0.1ns]
[2015-01-13 10:41:19.984] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 10:41:19.984] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:19.984] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:3):calc_tArpToTrp:-140012[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:850 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:19.988] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14001,filterBranch:3
[2015-01-13 10:41:19.988] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:19.988] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:41:19.988] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:41:19.988] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 3, value 438
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:3 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:19.988] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2088 ns
[2015-01-13 10:41:19.988] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:20.016] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
UL setCarr
a =5330
[2015-01-13 10:41:21.216] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =67
0
[2015-01-13 10:41:21.216] trDcProc delayCommHandler.cc:312 INFO:carrier:0x313 tR
uUl:125390[0.1 ns] = tRuInternalUlDb:125390
[2015-01-13 10:41:21.216] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:78
7 tRuProcDelayUl:151650[0.1 ns] = tRuUl:125390 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.216] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:2):calc_tArpToTrp:-140112[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121712 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.216] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14011,filterBranch:2
[2015-01-13 10:41:21.220] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.220] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:41:21.220] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:41:21.220] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 2, value 438
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:2 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.220] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2078 ns
[2015-01-13 10:41:21.220] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.248] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:41:21.248] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 2, CPRI port 0
[2015-01-13 10:41:21.248] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:19, clientId:102
[2015-01-13 10:41:21.264] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
UL setCarr
UL setCarr
UL setCarr
UL setCarr
UL setCarr
lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.700] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30c, event :128
[2015-01-13 10:41:24.704] trDcProc dlDelayEventSubscriber.cc:783 INFO:isBfnAdvan
cerSetAtFirstCarrier: ON, rfPort 1
[2015-01-13 10:41:24.704] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.704] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.708] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.708] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298954 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInternalBfnDe
lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.708] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:0)tTrpToArp:30435[ns] = salCarrierReportedDelay:298954 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:1,setBfnAdvanceAtEveryCarrier:1
71 [0.1ns]
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
71 [0.1ns]
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1255), hardDelay:(834)
[2015-01-13 10:41:24.888] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.892] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298995 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3671 + DpdDelay:1749
[2015-01-13 10:41:24.892] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30440[ns] = salCarrierReportedDelay:298995 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:24.892] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 255 ns
[2015-01-13 10:41:24.904] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:18, clientId:102
[2015-01-13 10:41:24.912] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:41:24.920] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.920] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 2
[2015-01-13 10:41:24.920] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:41:24.920] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.920] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 789 event :8
r 1
[2015-01-13 10:41:25.592] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955500 and vector width to 6000
[2015-01-13 10:41:25.596] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :1024
[2015-01-13 10:41:25.596] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.596] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.596] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.600] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298999 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInternalBfnDe
lay:3675 + DpdDelay:1749
[2015-01-13 10:41:25.600] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 30f, event :128
[2015-01-13 10:41:25.600] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a1e, rfPort 1
[2015-01-13 10:41:25.600] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:25.600] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.600] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.600] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.604] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
75 [0.1ns]
[2015-01-13 10:41:25.604] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(37
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:25.604] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.720] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.724] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298928 = tRuInternalDlDb:292940 + tDlFreqCompDelay:594 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:41:26.724] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30433[ns] = salCarrierReportedDelay:298928 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.724] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.736] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3673 [0.1ns]
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(37), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.768] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298969 = tRuInternalDlDb:292940 + tDlFreqCompDelay:635 + tInter
nalBfnDelay:3673 + DpdDelay:1721
[2015-01-13 10:41:26.772] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30437[ns] = salCarrierReportedDelay:298969 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.772] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 258 ns
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 10:41:26.784] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 10:41:26.872] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0x0 pa1Adj 0x4779
[2015-01-13 10:41:27.876] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x20630a1 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8d
8c8fd C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1f96 C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8350 C1 0x8008 C2 0x8008 C3 0x8008, pmPa1 0xb0c