Imac 27 k75f PDF

8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
TABLE_TABLEOFCONTENTS_HEAD
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04/14/2010
Table of Contents
K75F_MLB
System Block Diagram
K75F_MLB
Power Block Diagram
(.csa)
TABLE_TABLEOFCONTENTS_HEAD
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
K75F_MLB
BOM Configuration
K75F_MLB
PROTO 0 DEBUG LEDS
K75F_MLB
Power Conn / Alias
K75F_MLB
Holes
K75F_MLB
UNUSED SIGNAL ALIAS
K75F_MLB
Signal Aliases
K75F_MLB
CPU DMI/PEG/FDI/RSVD
K75F_MLB
CPU CLOCK/MISC/JTAG
K75F_MLB
CPU DDR3 INTERFACES
K75F_MLB
CPU POWER
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
K75F_MLB
CPU GROUNDS
K75F_MLB
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
K75F_MLB
CPU NON-GFX DECOUPLING
K75F_MLB
CPU/PCH GFX DECOUPLING
K75F_MLB
PCH SATA/PCIE/CLK/LPC/SPI
K75F_MLB
PCH DMI/FDI/GRAPHICS
K75F_MLB
PCH PCI/FLASHCACHE/USB
K75F_MLB
PCH MISC
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
K75F_MLB
PCH POWER
K75F_MLB
PCH GROUNDS
K75F_MLB
PCH DECOUPLING
K75F_MLB
EXTENDED DEBUG PORT(XDP)
K75F_MLB
CLOCK (CK505)
K75F_MLB
CHIPSET SUPPORT
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
K75F_MLB
DDR3 VREF MARGINING
K75F_MLB
MEMORY CAPS
K75F_MLB
DDR3 SO-DIMMs 0 & 2
K75F_MLB
DDR3 SO-DIMM CONNECTOR B
K75F_MLB
DDR3 SUPPORT AND BITSWAPS
K75F_MLB
PCI-E Wireless Connector
K75F_MLB
USB HUB 1
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
K75F_MLB
USB HUB 2
K75F_MLB
ETHERNET (CAESAR II)
K75F_MLB
CAESAR II SUPPORT
K75F_MLB
ETHERNET CONNECTOR
K75F_MLB
FireWire LLC/PHY (XIO2213B)
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
K75F_MLB
FW: 1394B MISC
K75F_MLB
FIREWIRE CONNECTOR
K75F_MLB
SATA Connectors
K75F_MLB
EXTERNAL USB CONNECTORS
K75F_MLB
Internal USB Connections
K75F_MLB
SMC
K75F_MLB
SMC Support
K75F_MLB
LPC+SPI Debug Connector
K75F_MLB
SMBus Connections
K75F_MLB
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
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105
106
107
109
110
REV
ECN
DESCRIPTION OF REVISION
0000892544
CK
APPD
DATE
LAST_MODIFIED=Thu Apr 15 11:21:16 2010

Contents
Sync
Page
Contents
Page
K75F MLB_MEMSWAP
(.csa)
PRODUCTION RELEASED
2010-04-15
Date
Sync
04/14/2010
CPU POWER SENSE
K75F_MLB
GRAPHICS / DIMM POWER SENSE
K75F_MLB
Thermal Sensors
K75F_MLB
HD AND OD FAN
K75F_MLB
CPU FAN
K75F_MLB
SPI ROM
K75F_MLB
AUDIO: CODEC/REGULATOR
K75F_MLB
AUDIO: FILTER/BUFFER
K75F_MLB
AUDIO: Tweeter Amp 1
K75F_MLB
AUDIO: Woofer Amp
K75F_MLB
Audio: MLB to I/O Conn.
K75F_MLB
AUDIO: Detects/Grounding
K75F_MLB
AUDIO: Mikey
K75F_MLB
POWER SEQUENCING ENABLES
K75F_MLB
POWER SEQUENCING PGOOD
K75F_MLB
VREG: PPVCORE_S0_CPU
K75F_MLB
VREG: CPU CORE - PHASES 1-3
K75F_MLB
VREG: CPU CORE - PHASE 4
K75F_MLB
CPU VTT REGULATOR
K75F_MLB
IBEX PEAK CORE
K75F_MLB
5V_S3 / 3V3_S5 VREGS
K75F_MLB
1.5V / 1.8V VREGS
K75F_MLB
1.05 S5 SUPPLY
K75F_MLB
S3+S0 FETS
K75F_MLB
MXM PCIe, DP & Power
K75F_MLB
MXM I/O
K75F_MLB
MXM PCIE CAPS
K75F_MLB
Display: Aliases
K75F_MLB
Display: Int DP Connector
K75F_MLB
Display: BiDiVi Mux1
K75F_MLB
BIDIVI DP MUX2
K75F_MLB
Display: Ext DP Connector
K75F_MLB
Display: BiDiVi Support
K75F_MLB
K60/K61 RULE DEFINITIONS
K75F_MLB
Memory Constraints
K75F_MLB
PCIE/DMI/FDI/SATA CONSTRAINTS
K75F_MLB
IBEX PEAK CONSTRAINTS
K75F_MLB
ENET/FIREWIRE CONSTRAINTS
K75F_MLB
GRAPHICS CONSTRAINTS
K75F_MLB
SMC Constraints
K75F_MLB
POWER CONSTRAINTS
K75F_MLB
PM RESETS ENABLES PGOOD CONST
K75F_MLB
K22/K23 ICT/FCT
K75F_MLB
04/14/2010
04/14/2010
04/14/2010
04/14/2010
04/14/2010
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04/14/2010
DRAWING TITLE
SCH,K75F,MLB_MEMSWAP
DRAWING NUMBER
Apple Inc.
051-8600
REVISION
A.0.0
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
DRAWING
IV ALL RIGHTS RESERVED
DRAWING
TITLE=K22
ABBREV=DRAWING
LAST_MODIFIED=Thu Apr 15 11:21:16 2010
BRANCH
PAGE
1 OF 110
SHEET
1 OF 92
SIZE
2 SO-DIMMS
DISPLAY PORT
J9400
CONN
U93XX
X4 BIDIRECTIONAL DP LINK
PG 94
INTERNAL DISP
J9002
X4 DP
PG 90
PG 10
U1000
X4 DP
BIDIVI
HW
SUPPORT
MXM CONNECTOR
SO-DIMMS
CHA
INTEL CPU
X16 PCI-E GEN2

X4 DP
PG 31
2 SO-DIMMS
PG 84
DDR3 1333
POWER PGSENSE
53
J3100, J3100
DDR3 1333
J8400
J3200, J3200
CHB
POWER SUPPLY
SO-DIMMS
PG 93
PG 32
LGA1156 - CLARKDALE/LYNNFIELD
TEMP, CURRENT SENSE
XDP
CONN
PG 25
J2500
X4 DMI
FDI LINK
CONTROL LOGIC FROM SMC
PG 13
GPIOs
PG 19
PG 19
XDP
CONN
PG 25
PG 19
Misc
CLK
USB 96MHZ/PCIE 100MHZ/SATA 100MHZ/BCLK 133MHZ.
PG 26
U2510
PG 55
PG 19
SYNTH
U6100
J5600, J5601, J5700
FAN CONN AND CONTROL
SPI
Boot ROM
SPI
PG 18
J4530
SATA CONN
SSD
SATA 2.0 3GHZ.
PG 45
SATA-A2
IBEX PEAK
LPC
PWR
RGB OUT
(PORT A)
HDMI/DVI/DP
(PORT C)
HDMI/DVI/DP
(UP TO 14 DEVICES)
(PORT D)
USB 2.0
PG 19
X1 PCIE GEN1 LANE 2.5GBITPS
BCM5764M
PG 39
PG 39
PG 38
PCI-E GEN2
UP TO 8 LANES3
GB E-NET
CONTROLLER
AND PHY
SD CARD
J4620
EXT
PORT1
PORT3
PG 46
PG 46
J4700
CAMERA
PG 47
J4780
J4610
IR
J4630
EXT
EXT
PORT0
PORT2
PG 47
PG 46
USB HUB 2
USB HUB 1
USX2061
USX2061
PG 36
PG 46
PG 35
SMB
J4620
EXT
PG 47
0 1 2 3 4 5 6 7 8 9 10 11 12 13
PG 20
HDMI/DVI/DP
DIGITAL VIDEO OUTPUT
E-NET
MAGNETICS
J4750
BLUETOOTH
PG 47
(PORT B)
U3800
J4720
CTRL
E-NET
CONNECTOR
Ser
Prt
PG 49
PG 18
ANALOG VIDEO OUTPUT
T3900
Fan
U1800
PG 18
J3900
B,0 BSB
SMC
TO BIDIVI HW
6 SATA 2.O PORTS
ADC
PG 45
SATA
PG 51
U4900
SATA 2.0 3GHZ.
SATA-A1
SATA CONN
ODD
LPC+SPI CONN
Port80,serial
PG 18
INTEL
PG 45
J4520
SATA 2.0 3GHZ.
J5100
SATA CONN
HD
SATA-A0
J4510
PG 56,57
PG 61
CK505
XDP
INTERFACE
DMI INTERFACE
U2600
FDI INTERFACE
TEMP SENSORS
MXM - GPU DIE
CPU HEATSINK
GPU HEATSINK
AMBIENT INTAKE
CPU DIE-PECI
HARD DRIVE
OPTICAL DRIVE
LCD TEMP
SKIN TEMP
MIDBUS PROBE
DIMMs

PG 18
PG 18
HDA
PCI
(SUPPORTED UPTO 4 REQ/GNT)

PG 20
U6806
MIKEY
PG 18
U4100
U6201
TI 1394B
XIO2211
Audio
Codec
PG 41
HEADPHONES
INTERNAL/EXTERNAL
MICROPHONES
LINE INPUT
SPEAKER AMPS
U6400, U6500
SYNC_MASTER=K75F_MLB
SYNC_DATE=04/14/2010
PAGE TITLE
System Block Diagram

DRAWING NUMBER
J4300
FireWire
Conn
Mini PCI-E
AirPort
PG 43
PG 34
Apple Inc.
Audio
Conns
J3400

A.0.0
J6600,J6601,J6602,J6603
051-8600
REVISION
BRANCH
PAGE
2 OF 110
SHEET
2 OF 92
SIZE
AC/DC POWER SUPPLY
CONTROL
DCM/FCM
12V_S5
SMBUS
TEMP SENSOR
PM_SLP_S3_OD
PP12V_S0_HDD
PPLED_PWR
PP12V_S0
PP12V_G3H:
LCD PANEL
HARD DRIVE
MXM
FANS
AUDIO
PP12V_S5:
PM_SMC_G2_EN
PP12V_G3H
PP12V_S0:
PP12V_S5
PP5V_S3_REG
FET (10.3A)
PAGE 74
USB
CAMERA
IR
CARD READER
WM
PPVCORE_CPU
P5VS0_EN
SMC
PP3V42_G3H_REG
PP3V3_S5_AVREF_SMC
REG
PAGE 79
PPVTT_S0
PP5V_S0
12V S5 FET
FET (6.9A)
PAGE 80
PP3V3_S5_REG
( 7A )
3.3V @ 6.2A
PAGE 76
CRITICAL
AUDIO
IBEX PEAK
OPTICAL
MXM
HDD
PP1V05_S5
BOOT ROM
IBEX PEAK
PP1V8_S0_REG
SW (1A)
PAGE 78
CPU UNCORE
1.1V @ 30A
PAGE 76
SMC VREF
REG
PAGE 50
CPU_CORE
.65-1.5V @ 90A
PAGE 71-72
CPU PLL
PP1V05_S0
IBEX PEAK
1.05V @ 3A
PAGE 76
VCCME, PCH
1.05V @ 0.4A
PAGE 79
Q8040
FDS4465_G
P3V3S3_EN
SOI-HF
=PP12V_G3H_S5_FET
S3
S2
S1
D4
D3
D2
D1
PP3V3_S3
7
6
PP12V_S5_FET
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
GATE
4
R8040
10K
P12V_S5_EN_D
R8041
1
10K
P12V_S5_EN_G
5%
1/16W
MF-LF
2 402
ETHERNET
BT
AP
PP1V95_S3
FW
1.0V @ 0.08A
PAGE 42
P3V3S0_EN
C8040
PP3V3_S0
0.47UF
10%
FET (2.8A)
PAGE 80
2 16V
X7R
805
LCD PANEL
IBEX PEAK
AUDIO
MXM
BIDIVI
FIREWIRE
5%
1/16W
MF-LF
402
PPDDR_S3_REG
R8045
MAIN MEMORY
13A (S3 & S0)

PAGE 75
10K
P12V_S5_EN_R
3.3V @ 2.8A
PAGE 80
5%
1/16W
MF-LF
2 402
PM_SLP_S3
PP1V5_S0
1.5V @ 4.9A
PAGE 78
CPU MEM
AUDIO
FIREWIRE
Q8041
PP0V75_S0
45
IN
SMC_PM_G2_EN
SOT23-HF1
MEM_VTT
0.75V @ 0.6A
PAGE 75
2N7002
R8042
100K
PP1V2_S3
ENET
1.2V @ 0.2A
PAGE 38
5%
1/16W
MF-LF
2 402
PAGE TITLE
Power Block Diagram

DRAWING NUMBER
P12VS0_EN
PP12V_S3
Apple Inc.
WM

A.0.0
12V @ 0.2A
PAGE 80
051-8600
REVISION
BRANCH
PAGE
3 OF 110
SHEET
3 OF 92
SIZE
BOM Variants
BOM NAME
BOM OPTIONS
085-1609
PCBA,MLB,DEV,K75F
DEVELOPMENT,DEV_GROUP
COMMON
TABLE_BOMGROUP_HEAD
BOM NUMBER
TABLE_5_HEAD
PART#
TABLE_BOMGROUP_ITEM
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
639-1103
PCBA,MLB,K75F,3.20GHZ,CKD
K75F,3P20GHZ_CKD_CPU,BASIC,CPUPOC_IMAX_100_120
639-1105
PCBA,MLB,K75F,3.60GHZ,CKD
K75F,3P60GHZ_CKD_CPU,BASIC,CPUPOC_IMAX_100_120
337S3828
IC,IBEX PEAK B3 PRQ,DESKTOP,FCBGA,P425
U1800
CRITICAL
359S0157
IC,SLG2AP108,CLK GEN,CK505,QFN3
U2600
CRITICAL
341T0230
IC,EFI BOOTROM,K74/K75
U6100
CRITICAL
338S0765
IC,XIO2211ZAY,1394B_PCIE,PHY/LINK
U4100
CRITICAL
343S0485
IC,BCM5764M,68PIN QFN
U3700
CRITICAL
341T0269
ENET 1MBIT FLASH,CII,K74/K75F
U3701
CRITICAL
825-7122
MLB LABEL,48.0X4.8
X14
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
BUF_CLK
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
639-1104
PCBA,MLB,K75F,2.66GHZ,LFD
K75F,2P66GHZ_LFD_CPU,BASIC,CPUPOC_IMAX_100_120
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
639-1106
PCBA,MLB,K75F,2.93GHZ,LFD
K75F,2P93GHZ_LFD_CPU,BASIC,CPUPOC_IMAX_100_120
TABLE_5_ITEM
TABLE_5_ITEM
RAW: 335S0663
TABLE_5_ITEM
BOM GROUPS
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
BASIC
COMMON,ALTERNATE,XDP,BETTER,MXM,XDP_CPU_BPM,INT_VREF,PCH_VRM,BUF_CLK,PRODUCTION
DEV_GROUP
XDP_CONN,LPCPLUS,MOJOMUX,CPU_TDIODE
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CPUS
CPU SOCKET & ILM SUB-BOMS
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
TABLE_5_ITEM
BOM OPTION
337S3911
CKD,SLBUD,PRQ,3.20,73W,1333,K0,4M,LGA
CPU
CRITICAL
3P20GHZ_CKD_CPU
337S3910
CKD,SLBTM,PRQ,3.60,73W,1333,K0,4M,LGA
CPU
CRITICAL
3P60GHZ_CKD_CPU
337S3810
LFD,SLBLC,PRQ,2.66,95W,1333,B1,8M,LGA
CPU
CRITICAL
2P66GHZ_LFD_CPU
337S3861
LFD,SLBJG,PRQ,2.93,95W,1333,B1,8M,LGA
CPU
CRITICAL
2P93GHZ_LFD_CPU
TABLE_5_ITEM
511S0063
SOCKET,LGA1156,CPU-LF
U1000
CRITICAL
TABLE_5_ITEM
MOLEX_SOCKET
TABLE_5_ITEM
604-0942
ASSY,PURCHASED,ILM,MOLEX,K75
ILM
CRITICAL
TABLE_5_ITEM
MOLEX_SOCKET
TABLE_5_ITEM
511S0069
SOCKET,LGA1156,CPU-LF
604-0988
ASSY,PURCHASED,ILM,FOXCONN,K75
U1000
CRITICAL
FOXCONN_SOCKET
ILM
CRITICAL
FOXCONN_SOCKET
TABLE_5_ITEM
TABLE_5_ITEM
ALTERNATE SOCKET VENDORS MUST USE MATCHING ILM

TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
607-6876
SUB ASSY,CPU SOCKET,K75F,MOLEX
MOLEX_SOCKET
607-6877
SUB ASSY,CPU SOCKET,K75F,FOXCONN
FOXCONN_SOCKET
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
SKT_ILM
CRITICAL
BOM OPTION
TABLE_5_ITEM
607-6876
MOLEX CPU SOCKET AND ILM
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
607-6877
607-6876
BOM OPTION
REF DES
COMMENTS:
SKT_ILM
FOXCONN ALTERNATIVE
TABLE_ALT_ITEM
ALTERNATES
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
128S0298
128S0293
C7460,C7461,C7462,C7463
518S0811
518S0685
J9002
TABLE_ALT_ITEM
TABLE_ALT_ITEM
K75F PARTS
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
BOARD STACK-UP
051-8600
SCH,K75F,MLB_MEMSWAP
SCH1
K75F
820-2901
PCBF,K75F,MLB_MEMSWAP
MLB1
K75F
(338S0489 - BLNK) 341T0273
IC,SMC,K75F
TABLE_5_ITEM
TABLE_5_ITEM
TOP
2
3
4
5
6
7
BOTTOM
SIGNAL
GROUND
SIGNAL
POWER
POWER
SIGNAL
GROUND
SIGNAL
U4900
CRITICAL
K75F
SYNC_MASTER=MASTER
PAGE TITLE
SYNC_DATE=N/A
BOM Configuration
DRAWING NUMBER
Apple Inc.
051-8600
REVISION
A.0.0

BRANCH
PAGE
4 OF 110
SHEET
4 OF 92
SIZE
CAN DELETE THESE FOR PROTO1 AND BEYOND

63 62 6 5
=PP3V3_S5_PWRCTL
DEVELOPMENT
63 62 6 5
R500
R530
5%
1/10W
MF-LF
2 603
3.3K
5%
1/10W
MF-LF
2 603
PM_LED_S4
SILK_PART=SLP_S4
DEVELOPMENT
NOSTUFF
PM_LED_DDRREG
R531
LED500
K
=PP3V3_S5_PWRCTL
DEVELOPMENT
3.3K
3.3K
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
LED530
5%
1/10W
MF-LF
2 603
SILKSCREEN:2
PM_LED1_S4
SILK_PART=DDR_PGOOD
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:2
PM_LED1_DDRREG
DEVELOPMENT
91 19
IN
PM_SLP_S4_3_L
Q500
2N7002DW-X-G
DEVELOPMENT
Q520
SOT-363
91 70 62
IN
PM_PGOOD_DDRREG_S3
2N7002DW-X-G
SOT-363
63 62 6 5
=PP3V3_S5_PWRCTL
DEVELOPMENT
72 63 62 6 5
R510
=PP3V3_S0_PWRCTL
DEVELOPMENT
3.3K
3.3K
5%
1/10W
MF-LF
2 603
PM_LED_S3
SILK_PART=SLP_S3
PM_LED_PCHCORE
DEVELOPMENT
LED510
K
SILK_PART=PCHCORE_PGOOD
GREEN-3.6MCD
2.0X1.25MM-SM
IN
PM_SLP_S3_L
DEVELOPMENT
Q500
DEVELOPMENT
2N7002DW-X-G
Q540
SOT-363
91 68 63 62
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:4
PM_LED1_PCHCORE
91 63 62 46 37 33 32 19
DEVELOPMENT
LED540
SILKSCREEN:4
PM_LED1_S3
R540
5%
1/10W
MF-LF
2 603
IN
PCHCORE_REG_PGOOD
2N7002DW-X-G
SOT-363
63 62 6 5
72 63 62 6 5
=PP3V3_S5_PWRCTL
DEVELOPMENT
=PP3V3_S0_PWRCTL
DEVELOPMENT
R550
R520
5%
1/10W
MF-LF
2 603
5%
1/10W
MF-LF
2 603
PM_LED_PVCORE
PM_LED_SM
SILK_PART=SLP_M
DEVELOPMENT
SILK_PART=VCORE_PGOOD
LED520
K
91 62 19
IN
PM_SLP_M_L
DEVELOPMENT
2N7002DW-X-G
91 64 63 26
IN
PM_PGOOD_PVCORE_CPU
Q540
2N7002DW-X-G
Manageability
SMC_PM_G2_ENABLE
PM_S4_STATE_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_M_L
N/A
Sleep (S3/M1)
On
Soft-Off (S5/M1)
On
Sleep (S3/M-Off)
Off
Soft-Off (S5/M-Off)
Off
Battery Off (G3Hot)
N/A
Run (S0/M0)
DEVELOPMENT
SOT-363
State
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:2
PM_LED1_PVCORE
Q520
DEVELOPMENT
LED550
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:4
PM_LED1_SM
3.3K
3.3K
SOT-363
PAGE TITLE
PROTO 0 DEBUG LEDS

DRAWING NUMBER
Apple Inc.
051-8600
REVISION
A.0.0

BRANCH
PAGE
5 OF 110
SHEET
5 OF 92
SIZE
518-0352
CRITICAL
J600
EMC: C600,C626,C627,C628,C629,C630,C631
48
42 6
89 71 6
M-RT-TH
=SMB_ACDC_SCL
=PP5V_S0_SATA
PP12V_G3H
77
10
11
12
C623
10UF
C631
0.001UF
20%
10V
2 X5R
805
10%
50V
2 X7R
402
C627
0.001UF
48
89
PPVTT_S0_DDR
MAKE_BASE=TRUE
VOLTAGE=0.75V
6 63 89
LCD_BKL_ON 77
14
89
C626
0.001UF
10%
50V
2 X7R
402
C630
0.001UF
10%
50V
2 X7R
402
10%
50V
2 X7R
402
C624
89 49
PPVCORE_S0_CPU
MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
PPVTT_S0_CPU
10UF
10%
16V
2 X5R-CERM
1210
89
2N7002
46 45
PM_SLPS3_BUF2_L
IN
SOT23-HF1
PPVCORE_S0_CPU_REG
=PPVCORE_S0_CPU
=PPVTT_S0_CPU
PPVTT_S0
MAKE_BASE=TRUE
VOLTAGE=1.1V
PPVTT_S0_CPU_REG
=PPVTT_S0_PCH_VCC_DMI
=PPVTT_S0_XDP
=PPVTT_S0_PCH_VCCP_CPU
32
ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5

89
PP1V05_S0
MAKE_BASE=TRUE
VOLTAGE=1.05V
31
30
64 65 66
13 16
11 13 16 46 64
49 67
89
PP1V05_SM_PCH_LAN
0.001UF
10%
50V
X7R
402
89 49
89
PP1V5_CPU_MEM
=PP1V5_CPU_MEM
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V5_S0
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP1V05_SM_PCH_VCC_LAN
68
17
89
PP1V05_S5
22 24
24
72
25
89
22 24
13 16 29
49 72
PP0V75_S0
MAKE_BASE=TRUE
VOLTAGE=0.75V
PP12V_S0
MAKE_BASE=TRUE
VOLTAGE=12V
55
39
26
PPVTT_S0_DDR_LDO
=PP0V75_S0_MEM_VTT_S0FET
=PP12V_S0_FAN
=PP12V_S0_AUDIO_SPKRAMP
=PP12V_S0_VRD
=PPV_S0_MXM_PWR
=PP12V_S0_LCD
=PP12V_S0_PCH_CORE_VREG
=PP12V_S0_CPU_VTT_VREG
=PP12V_S0_PWRCTL
C
92 89 6
PP3V3_S3
PP1V8_S0_CPU
MAKE_BASE=TRUE
VOLTAGE=1.8V
DEVELOPMENT
R600
89
PP1V8_S0
MAKE_BASE=TRUE
VOLTAGE=1.5V
1K
5%
1/16W
MF-LF
2 402
89
PPVAXG_S0_CPU
22 24
22 24
26
GREEN-3.6MCD
2.0X1.25MM-SM
89 6
92 89 6
PP3V3_S5_REG
PP3V3_S0
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_S3
R602
R601
1K
1K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
CORE_VOLTAGES_ON_R
ITS_PLUGGED_IN
A
A
LED602
LED601
K
GREEN-3.6MCD
2.0X1.25MM-SM
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:2
CORE_VOLTAGES_ON
SILKSCREEN:1
3
D
91 63 32 25
IN
ALL_SYS_PWRGD_R 5
Q602
2N7002DW-X-G
SOT-363
89 6
PP1V8_S0_REG
=PP3V3R1V8_S0_PCH_VCCPNAND
=PP1V8R1V5_S0_PCH_VCCVRM
PP3V3_S0
MXM
R604
1K
5%
1/16W
MF-LF
2 402
89 6
GPU_PRESENT_R
PP3V3_S0
R603
1K
MXM
5%
1/16W
MF-LF
2 402
LED604
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:3
GPU_PRESENT_DRAIN
32
=PPVAXG_S0_CPU
LCD_SHOULD_ON_R
PP3V3_S0_FET
=PP3V3_S0_PCH
=PP3V3_S0_FAN
=PP3V3_S0_PCH_VCCADAC
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_VRD
=PP3V3_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP3V3_S0_SMBUS
=PP3V3_S0_SMC_LS
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_MGMT
=PP3V3_S0_DPCONN
=PP3V3_S0_TSENS
=PP3V3_S0_MXM
=PP3V3_S0_XDP
=PP3V3_S0_ODD
=PP3V3_S0_SATALED
=PP3V3_S0_SMC
=PP3V3_S0_PWRCTL
=PP3V3_S0_PCH_VCC3_3_CORE
=PP3V3_S0_VIDEO
=PP3V3_FW_FWPHY
=PP3V3_FWRS0_FWXIO
=PP3V3_S0_DP
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_CK505
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_STRAPS
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_RSTBUF
=PP3V3_S0_ME
=PP3V3_S0_ENET
=PP3V3_S0_PCH_PM
=PP3V3_S0_SMBUS_SMC_BSA
18 21 24 68
21
IN
Q602
92 89
LED603
2N7002DW-X-G
SOT-363
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:4
VIDEO_ON_L
PP5V_S0
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM
PP5V_S0_FET
=PP5V_S0_AUDIO
=PP5V_S0_SATA
=PP5V_S0_MXM
=PP5V_S0_VRD
72
72
71
72
15
11
25
32
47
77
67
63
PP5V_S5
PP5V_S5_LDO
=PP5V_S5_PCH
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.4 MM
PP1V5_S3_REG
=PP1V5_S3_MEMRESET
=PPDDR_S3_S0FET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
69
24
PP12V_S5
PP12V_S5_FET
=PP12V_S5_DDR_VREG
=PP12V_S5_P3V3S5_VREG
=PP12V_S5_P5VS3_VREG
=PP12V_S5_S3_FET
=PP12V_S5_PWRCTL
=PP12V_S5_FW
MAKE_BASE=TRUE
VOLTAGE=12V
3
70
69
69
72
63 72
41
49 50 70
32
72
"G3H" RAILS
28 29 30
28 29 31
ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC
52 53
17
G3H: ALIASES
30 46
31
89
64
55 57 58 59 60 61
89
PP12V_S3
MAKE_BASE=TRUE
VOLTAGE=12V
22 24
48
46 51
48
92 89 6
PP3V3_S3
MAKE_BASE=TRUE
VOLTAGE=3.3V
48
48
80
51
63 73 74
25
42
18 42
46 49 50
5 62 63 72
22 24
77
39 40 41
39
PP12V_S3_FET
=PP12V_S3_WM
72
44
PP3V3_S3_FET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_BT
=PP3V3_S3_SDCARD
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_MINI
=PP3V3_S3_PWRCTL
=PP3V3_S3_WM
=PP3V3_S3_SMBUS
=PP3V3_S3_MEMRESET
=PP3V3_S3_BRCRYPT
=PP3V3_S3_ENET
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
PP3V42_G3H
PP3V42_G3H_REG
=PP3V3_S5_RTC_D
=PP3V3_G3H_SMC
=PP3V3_G3H_SMCUSBMUX
=PP3V42_G3H_AVREF
=PP3V3_G3H_LPCPLUS
MAKE_BASE=TRUE
VOLTAGE=3.42V
71
27
45 46
43
46
47
72
28
44
15
44
48
33
63 72
89 71 6
PP12V_G3H
=PP12V_G3H_S5_FET
MAKE_BASE=TRUE
VOLTAGE=12V
44
48
32
44
37
GND RAILS
34 35
34
77 78 79 81
GND
VOLTAGE=0V
NET_SPACING_TYPE=GND
22 24
26
89
20
15
22 24
PP5V_S3
MAKE_BASE=TRUE
VOLTAGE=5V
27
72
36
27
48
72
55 61
PP3V3_S0M
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP5V_S3_REG
=PP5V_S3_USB
=PP5V_S3_S0FET
=PP5V_S3_CAMERA
=PP5V_S3_IR
=PP5V_S3_VREFMRGN
=PP5V_S3_PWRCTL
=PP5V_S3_MEMRESET
=PP5V_S3_DDR_VREG
=PP5V_S3_BRAY
PP3V3_SM_FET
=PP3V3_SM_PCH_VCC_ME
=PP3V3_SM_PWRCTL
69 92
MAKE_BASE=TRUE
MAX_NECK_LENGTH=4.1 MM
43
72
44
44
28
62
32
70
44
72
22 24
63 72
PAGE TITLE
6 42
Power Conn / Alias

DRAWING NUMBER
73
Apple Inc.
64
77
=PP5V_S0_ISENSE
=PP5V_S0_P1V8_VREG
=PP5V_S0_PCH
=PP5V_S0_LPCPLUS
22 24
5 62 63
68
13 17
72
47 54
50
24
MAKE_BASE=TRUE
VOLTAGE=1.5V
20
64
89
PP1V5_S3
18 19 24
60
22 24
89
6 69
=PP3V3_S5_XDP
=PP3V3_S5_MEMRESET
=PP3V3_S5_LPCPLUS
52 53
49 70
89
MXM_GOOD
MAKE_BASE=TRUE
VOLTAGE=3.3V
70
"S3" RAILS
PP3V3_S5_REG
=PP3V3_S5_PCH
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP3V3_S5_PWRCTL
=PP3V3_S5_S3FET
=PP3V3_S5_S0FET
=PP3V3_S5_P1V05S5_VREG
=PP3V3_S5_SM_FET
=PP3V3_S5_CPURESET
22 24
ON IN RUN AND SLEEP
MAKE_BASE=TRUE
VOLTAGE=0V
LED605
69 6
13 16 63
72
PP3V3_S5
ITS_ALIVE
A DEVELOPMENT
=PP1V8_S0_CPU_PLL
71
18 22 24
18 19 22 24
89
89 49
PP1V05_S5_REG
=PP1V05_S5_SM_FET
MAKE_BASE=TRUE
VOLTAGE=1.05V
THIS NET IS NOT CONNECTED TO ANY VOLTAGE RAIL. INSTEAD ON PAGE 24 IT IS CONNECTED TO GND THROUGH A RESISTOR
89 63 6
PP1V5_S0_FET
=PP1V5_S0_AUD_DIG
=PP1V5_FWRS0_FWXIO
=PP1V5_S0_CK505
PP1V05_S0_REG
=PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH
=PP1V05_S0_SM_FET
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_CK505
MAKE_BASE=TRUE
VOLTAGE=1.05V
22 24
C600
Q610
PPVTT_S0_DDR_FET
=PP0V75_S0_MEM_VTT_B
=PP0V75_S0_MEM_VTT_A
MAKE_BASE=TRUE
VOLTAGE=1.1V
PM_ACDC_PS_ON
3
"S5" RAILS
ONLY ON IN RUN
=SMB_ACDC_SDA
PP12V_S0
13
LCD_PWM
"S0" RAILS
76833-0100
PLACE AT J600.
051-8600
REVISION
A.0.0
R
49
89
70
24
67
PP1V05_SM
MAKE_BASE=TRUE
VOLTAGE=1.05V
PP1V05_SM_FET
=PP1V05_SM_ME
47
68
72
22 24
63

BRANCH
PAGE
6 OF 110
SHEET
6 OF 92
SIZE
CPU Heatsink
ZH0700
4P75R4
OMIT
ZH0701
DIMM CONNECTOR NUTS
4mm Plated Holes (998-0850)

OMIT
4P75R4
1
OMIT
ZH0702
4P75R4
1
Nuts (805-9582)
OMIT
ZH0703
CRITICAL
CRITICAL
NUT0750
4P75R4
NUT-4.25OD1.4H-1.40-3.25-TH
NUT0751
NUT-4.25OD1.4H-1.40-3.25-TH
CRITICAL
NUT0752
NUT-4.25OD1.4H-1.40-3.25-TH
CRITICAL
NUT0753
NUT-4.25OD1.4H-1.40-3.25-TH
PCH HEATSINK
EMC Springs (870-1125) Removed 2009-10-05
C
Rear Cover
Standoffs (860-1255)
CRITICAL
CRITICAL
CRITICAL
SDF0714
CRITICAL
CRITICAL
STDOFF-6.8OD15.0H-1.56-TH
SDF0715
1
SDF0713
1
SDF0718
CRITICAL
SDF0719
1
SDF0717
Backer Plate
Nuts (835-0269)
CRITICAL
NUT0700
NUT-6.5OD1.4H-1.56-3.8-TH
1
CRITICAL
NUT0701
NUT-6.5OD1.4H-1.56-3.8-TH
1
CRITICAL
CRITICAL
NUT0702
NUT0703
NUT-6.5OD1.4H-1.56-3.8-TH
NUT-6.5OD1.4H-1.56-3.8-TH
For EMC
EMC Spring (870-1577); Near DIMMs
EMC POGO Pins (870-1698); Near DIMMs
SC0705
CRITICAL
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SC0702
1 EMI-SPRING
SC0706
2.0DIA-TALL-EMI-MLB-M97-M98
SM
PAGE TITLE
CRITICAL
NOSTUFF
Holes
CLIP-SM-K2
DRAWING NUMBER
CRITICAL
NOSTUFF
Apple Inc.
051-8600
REVISION
A.0.0

BRANCH
PAGE
7 OF 110
SHEET
7 OF 92
SIZE
UNUSED CPU SIGNALS

TP_CPU_RSVD<41..29>
NC_CPU_RSVD<41..29>
10
TP_CPU_RSVD<26..1>
NC_CPU_RSVD<26..1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CPU_FC_AE38
NC_CPU_FC_AE38
13
TP_CPU_FC_AG40
NC_CPU_FC_AG40
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
TP_PCI_T28_D2R_N<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCI_T28_D2R_P<3..0>
NO_TEST=TRUE
TP_PCI_T28_R2D_C_N<3..0>
NC ON UNUSED PCI ALIASES

20
20
20
20
21
TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
TP_PCI_PAR
TP_PCI_RESET_L
TP_PCIE_CLK100M_XDPP
NC_PCI_AD<31..0>
MAKE_BASE=TRUE
TP_PCI_T28_R2D_C_P<3..0>
NO_TEST=TRUE
NC_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_RESET_L
MAKE_BASE=TRUE
NC_PCIE_CLK100M_XDPN
21
TP_DMI_CLK100M_LAP
NC_DMI_CLK100M_LAP
21
TP_DMI_CLK100M_LAN
NC_DMI_CLK100M_LAN
MAKE_BASE=TRUE
TP_LPC_DREQ1_L
NC_LPC_DREQ1_L
TP_LPC_DREQ0_L
NC_LPC_DREQ0_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
20
TP_NV_CE_L<3..0>
NC_NV_CE_L<3..0>
20
TP_NV_DQS<1..0>
NC_NV_DQS<1..0>
20
TP_NV_DQ<15..0>
NC_NV_DQ<15..0>
20
TP_NV_WR_RE_L<1..0>
TP_NV_WE_CK_L<1..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_NV_RB_L
MAKE_BASE=TRUE
18
NC_HDA_SDIN3
18
TP_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE5P
18
TP_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5N
NO_TEST=TRUE
NC_NV_RCOMP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_7N
TP_USB_7P
NC_USB_7P
NO_TEST=TRUE
20
TP_USB_6N
NC_USB_6N
NO_TEST=TRUE
20
TP_USB_6P
NC_USB_6P
20
TP_USB_1N
20
TP_USB_1P
20
NO_TEST=TRUE
NO_TEST=TRUE
20
TP_USB_3N
TP_USB_3P
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_SATA_D_R2D_CP
NC_SATA_D_R2D_CP
18
TP_SATA_E_D2RN
NC_SATA_E_D2RN
18
TP_SATA_E_D2RP
NC_SATA_E_D2RP
18
TP_SATA_E_R2D_CN
NC_SATA_E_R2D_CN
18
TP_SATA_E_R2D_CP
NC_SATA_E_R2D_CP
18
TP_SATA_F_D2RN
NC_SATA_F_D2RN
18
TP_SATA_F_D2RP
NC_SATA_F_D2RP
18
TP_SATA_F_R2D_CN
NC_SATA_F_R2D_CN
18
TP_SATA_F_R2D_CP
NC_SATA_F_R2D_CP
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_USB_1N
MAKE_BASE=TRUE
NC_USB_1P
MAKE_BASE=TRUE
19
TP_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_CLK
19
TP_CRT_IG_DDC_DATA
NC_CRT_IG_DDC_DATA
19
TP_CRT_IG_RED
NC_CRT_IG_RED
19
TP_CRT_IG_GREEN
NC_CRT_IG_GREEN
19
TP_CRT_IG_BLUE
NC_CRT_IG_BLUE
NO_TEST=TRUE
19
TP_CRT_IG_HSYNC
NC_CRT_IG_HSYNC
NO_TEST=TRUE
19
TP_CRT_IG_VSYNC
NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_USB_3N
MAKE_BASE=TRUE
NC_USB_3P
MAKE_BASE=TRUE
NC_USB_5N
20
TP_USB_5P
NC_USB_5P
20
TP_USB_9N
20
TP_USB_9P
MAKE_BASE=TRUE
NC_USB_9N
NC_USB_9P
MAKE_BASE=TRUE
TP_USB_10N
NC_USB_10P
TP_USB_11N
NC_USB_11N
TP_USB_11P
NC_USB_11P
NC_PCH_PWM0
20
21
TP_PCH_PWM1
NC_PCH_PWM1
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_SST
MAKE_BASE=TRUE
TP_MEM_A_CS_L<7..4>
NC_MEM_A_CS_L<7..4>
TP_MEM_A_DQ_CB<7..0>
NC_MEM_A_DQ_CB<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_DQS_N<8>
MAKE_BASE=TRUE
NC_MEM_A_DQS_P<8>
12
TP_MEM_B_CS_L<7..4>
NC_MEM_B_CS_L<7..4>
12
TP_MEM_B_DQ_CB<7..0>
NC_MEM_B_DQ_CB<7..0>
MAKE_BASE=TRUE
TP_MEM_B_DQS_N<8>
NC_MEM_B_DQS_N<8>
83 12
TP_MEM_B_DQS_P<8>
NC_MEM_B_DQS_P<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_DP_IG_B_MLN<3..0>
TP_DP_IG_B_MLP<3..0>
NC_DP_IG_B_MLP<3..0>
NO_TEST=TRUE
19
TP_DP_IG_B_AUX_N
NC_DP_IG_B_AUXN
19
TP_DP_IG_B_AUX_P
NC_DP_IG_B_AUXP
19
TP_DP_IG_B_HPD
NC_DP_IG_B_HPD
19
TP_DP_IG_B_DDC_CLK
NC_DP_IG_B_CTRL_CLK
19
TP_DP_IG_B_DDC_DATA
NC_DP_IG_B_CTRL_DATA
19
TP_DP_IG_C_MLN<3..0>
NC_DP_IG_C_MLN<3..0>
19
TP_DP_IG_C_MLP<3..0>
NC_DP_IG_C_MLP<3..0>
19
TP_DP_IG_C_AUX_N
NC_DP_IG_C_AUXN
19
TP_DP_IG_C_AUX_P
NC_DP_IG_C_AUXP
NO_TEST=TRUE
19
TP_DP_IG_C_HPD
NC_DP_IG_C_HPD
NO_TEST=TRUE
19
TP_DP_IG_C_CTRL_CLK
NC_DP_IG_C_CTRL_CLK
19
TP_DP_IG_C_CTRL_DATA
NC_DP_IG_C_CTRL_DATA
19
TP_DP_IG_D_MLN<3..0>
NC_DP_IG_D_MLN<3..0>
19
TP_DP_IG_D_MLP<3..0>
NC_DP_IG_D_MLP<3..0>
19
TP_DP_IG_D_AUXN
NC_DP_IG_D_AUXN
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_12N
MAKE_BASE=TRUE
NC_USB_12P
MAKE_BASE=TRUE
NC_USB_13N
MAKE_BASE=TRUE
NC_USB_13P
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
18
PCIE_EXCARD_D2R_N
NC_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
PCIE_EXCARD_R2D_C_N
NC_PCIE_EXCARD_R2D_C_N
19
TP_DP_IG_D_AUXP
NC_DP_IG_D_AUXP
19
TP_SDVO_TVCLKINN
NC_SDVO_TVCLKINN
19
TP_DP_IG_D_HPD
NC_DP_IG_D_HPD
19
TP_DP_IG_D_CTRL_CLK
NC_DP_IG_D_CTRL_CLK
19
TP_DP_IG_D_CTRL_DATA
NC_DP_IG_D_CTRL_DATA
TP_SDVO_TVCLKINP
TP_SDVO_STALLN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_TVCLKINP
MAKE_BASE=TRUE
NC_SDVO_STALLN
MAKE_BASE=TRUE
19
TP_SDVO_STALLP
NC_SDVO_STALLP
19
TP_SDVO_INTN
NC_SDVO_INTN
19
TP_SDVO_INTP
NC_SDVO_INTP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
18
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_DP_IG_B_MLN<3..0>
NC_PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_P
NO_TEST=TRUE
MAKE_BASE=TRUE
19
PCIE_EXCARD_D2R_P
19
NO_TEST=TRUE
83 12
TP_USB_13P
NO_TEST=TRUE
19
18
19
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_USB_13N
NO_TEST=TRUE
TP_MEM_A_DQS_P<8>
MAKE_BASE=TRUE
TP_USB_12P
18
NO_TEST=TRUE
MAKE_BASE=TRUE
20
20
NC ON UNUSED MEM ALIASES

12
TP_USB_12N
20
NO_TEST=TRUE
12
20
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_USB_10P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_10N
20
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC ON UNUSED DISPLAY ALIASES
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_USB_5N
TP_PCH_PWM0
NC_PCH_PWM3
18
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
20
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCH_PWM3
NC_SATA_D_R2D_CN
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
21
TP_SATA_D_R2D_CN
NO_TEST=TRUE
PCIE_CLK100M_EXCARD_N
21
MAKE_BASE=TRUE
18
NC_JTAG_XDP_TRST_L
83 12
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_EXCARD_P
TP_JTAG_XDP_TRST_L
83 12
MAKE_BASE=TRUE
NC_NV_WE_CK_L<1..0>
NC_PCH_PWM2
18
NO_TEST=TRUE
PCIE_CLK100M_EXCARD_P
25
TP_MEM_A_DQS_N<8>
MAKE_BASE=TRUE
TP_USB_7N
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCH_PWM2
NC_SATA_D_D2RP
NO_TEST=TRUE
18
20
MAKE_BASE=TRUE
20
NC_NV_WR_RE_L<1..0>
21
NC_SATA_D_D2RN
TP_SATA_D_D2RP
NO_TEST=TRUE
TP_HDA_SDIN3
TP_NV_RCOMP
TP_SATA_D_D2RN
18
NC_PCI_T28_R2D_C_P<3..0>
MAKE_BASE=TRUE
20
NC ON UNUSED MISC ALIASES
TP_PCH_SST
NO_TEST=TRUE
NC_HDA_SDIN2
20
21
MAKE_BASE=TRUE
NO_TEST=TRUE
NC ON UNUSED NAND ALIASES
20
NC_PCI_T28_R2D_C_N<3..0>
TP_HDA_SDIN2
20
NO_TEST=TRUE
MAKE_BASE=TRUE
18
TP_NV_RB_L
NO_TEST=TRUE
18
NO_TEST=TRUE
MAKE_BASE=TRUE
18
20
NC_PCI_T28_D2R_P<3..0>
MAKE_BASE=TRUE
18
NO_TEST=TRUE
TP_PCIE_CLK100M_XDPN
NO_TEST=TRUE
18
NO_TEST=TRUE
21
MAKE_BASE=TRUE
NC_HDA_SDIN1
NC_PCIE_CLK100M_XDPP
MAKE_BASE=TRUE
NC_PCI_T28_D2R_N<3..0>
TP_HDA_SDIN1
NO_TEST=TRUE
NC_PCI_PAR
NC ON UNUSED SATA ALIASES
10
13
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PAGE TITLE
NO_TEST=TRUE
UNUSED SIGNAL ALIAS

DRAWING NUMBER
NO_TEST=TRUE
Apple Inc.
NO_TEST=TRUE
051-8600
REVISION
A.0.0
13
TP_GFX_VID<0..6>
NC_GFX_VID<0..6>
NO_TEST=TRUE
13
TP_GFX_VSENSE_N
NC_GFX_VSENSE_N
NO_TEST=TRUE
13
TP_GFX_VSENSE_P
NC_GFX_VSENSE_P
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

BRANCH
PAGE
8 OF 110
SHEET
8 OF 92
SIZE
PEG Slot Support

THIS SIGNAL NAME IS CONNECTED TO MXM
18
IN
PEG_CLK100M_P
84
18
IN
PEG_CLK100M_N
84
10
IN
=PEG_R2D_C_P<0..15>
10
IN
=PEG_R2D_C_N<0..15>
10
OUT
=PEG_D2R_P<0..15>
10
OUT
=PEG_D2R_N<0..15>
18
IN
PEG_CLKREQ_L
73
MXM_RESET_L
GPU_CLK100M_PCIE_P
CLK_100M_MXM_P
OUT
73
GPU_CLK100M_PCIE_N
CLK_100M_MXM_N
OUT
73
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_P<0..15>
OUT
75 84
PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
OUT
75 84
PEG_D2R_P<0..15>
IN
75 84
PEG_D2R_N<0..15>
IN
75 84
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MXM_CLKREQ_L
OUT
MAKE_BASE=TRUE
PEG_RESET_L
73
27 91
MAKE_BASE=TRUE
R929
91 85 19
IN
PM_CLK32K_SUSCLK_R
1
PLACEMENT_NOTE=PLACE CLOSE TO U1800
22
PM_CLK32K_SUSCLK
OUT
45 85 91
5%
1/16W
MF-LF
402
PAGE TITLE
Signal Aliases
DRAWING NUMBER
Apple Inc.
051-8600
REVISION
A.0.0

BRANCH
PAGE
9 OF 110
SHEET
9 OF 92
SIZE
84 19 10
IN
84 19 10
IN
84 19 10
84 19 10
IN
IN
84 19 10
IN
84 19 10
IN
84 19 10
IN
84 19 10
84 19 10
IN
OUT
84 19 10
OUT
84 19 10
OUT
84 19 10
84 19 10
OUT
OUT
84 19 10
OUT
84 19 10
OUT
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
V1 DMI_RX_2*
W2 DMI_RX_3*
R1
U3
U1
W3
M1
N2
P1
R3
L1
N3
N1
R2
DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*
DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3
TP_CPU_FDI_TX_N<0>
TP_CPU_FDI_TX_N<1>
TP_CPU_FDI_TX_N<2>
TP_CPU_FDI_TX_N<3>
TP_CPU_FDI_TX_N<4>
TP_CPU_FDI_TX_N<5>
TP_CPU_FDI_TX_N<6>
TP_CPU_FDI_TX_N<7>
U5
V3
U7
W7
W4
R7
Y3
Y5
FDI_TX_0*
FDI_TX_1*
FDI_TX_2*
FDI_TX_3*
FDI_TX_4*
FDI_TX_5*
FDI_TX_6*
FDI_TX_7*
TP_CPU_FDI_TX_P<0>
TP_CPU_FDI_TX_P<1>
TP_CPU_FDI_TX_P<2>
TP_CPU_FDI_TX_P<3>
TP_CPU_FDI_TX_P<4>
TP_CPU_FDI_TX_P<5>
TP_CPU_FDI_TX_P<6>
TP_CPU_FDI_TX_P<7>
U6
V4
U8
W8
W5
R8
Y4
Y6
FDI_TX_0
FDI_TX_1
FDI_TX_2
FDI_TX_3
FDI_TX_4
FDI_TX_5
FDI_TX_6
FDI_TX_7
IN
IN
CPU_FDI_INT
AC2 FDI_INT
15
IN
15
IN
CPU_FDI_LSYNC<0>
CPU_FDI_LSYNC<1>
IN
15
(1 OF 10)
OMIT
AC4 FDI_FSYNC_0
AC3 FDI_FSYNC_1
15
LGA1156-SKT
DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3
CPU_FDI_FSYNC<0>
CPU_FDI_FSYNC<1>
15
U1000
LYNNFIELD
AD4 FDI_LSYNC_0
AD3 FDI_LSYNC_1
FLEXIBLE DISPLAY INTERFACE
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
T1 DMI_RX_0*
U2 DMI_RX_1*
DMI
OUT
84 19 10
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
D11
C10
B10
A11
84
CPU_PEG_COMP
84
CPU_PEG_RBIAS
8
8
PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*
D9
C8
A6
C6
B5
C4
D3
E2
F1
G2
H1
J2
K1
L3
P4
T4
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
C9
B8
A7
B6
A5
B4
C3
D2
E1
G3
G1
J3
J1
L2
P3
T3
=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*
D7
E6
F5
F4
G5
H3
G7
J5
K4
J8
L5
M3
L7
N5
N8
R6
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
C7
E7
E5
F3
G6
H4
F7
J6
K3
H8
L6
M4
K7
N6
M8
R5
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>
8
8
IN
IN
IN
IN
R1012
750
1%
1/16W
MF-LF
402
R1010
49.9
1%
1/16W
MF-LF
402
8
8
A12
AD2
AE2
AH40
AJ39
AK12
AK13
AK14
AK15
AK16
AK18
AK25
AK26
AK27
AK28
AK29
AL12
AL14
TP_CPU_RSVD<1>
TP_CPU_RSVD<2>
TP_CPU_RSVD<3>
TP_CPU_RSVD<4>
TP_CPU_RSVD<5>
TP_CPU_RSVD<6>
TP_CPU_RSVD<7>
TP_CPU_RSVD<8>
TP_CPU_RSVD<9>
TP_CPU_RSVD<10>
TP_CPU_RSVD<11>
TP_CPU_RSVD<12>
TP_CPU_RSVD<13>
TP_CPU_RSVD<14>
TP_CPU_RSVD<15>
TP_CPU_RSVD<16>
TP_CPU_RSVD<17>
TP_CPU_RSVD<18>
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
14
OUT
16
OUT
18
OUT
OUT
OUT
8
PLACE R1010 AND R1012 CLOSE TO CPU BALLS
8
8
8
8
8
8
8
8
8
84 25
IN
84 25
IN
84 25
IN
84 25 15
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
84 25
IN
E8
G8
E10
F10
H10
H9
E9
F9
G12
H12
K10
K8
J12
L8
K9
K12
H7
L11
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
U1000
RSVD_A12
RSVD_AL15
RSVD_AD2
RSVD_AL17
RSVD_AE2 LYNNFIELDRSVD_AL18
RSVD_AH40 LGA1156-SKTRSVD_AL26
RSVD_AJ39
RSVD_AL27
(5 OF 10)
RSVD_AK12
RSVD_AL29
OMIT
RSVD_AK13
RSVD_AM13
RSVD_AK14
RSVD_AM14
RSVD_AK15
RSVD_AM15
RSVD_AK16
RSVD_AM16
RSVD_AK18
RSVD_AM17
RSVD_AK25
RSVD_AM18
RSVD_AK26
RSVD_AM19
RSVD_AK27
RSVD_AM20
RSVD_AK28
RSVD_AM21
RSVD_AK29
RSVD_AM25
RSVD_AL12
RSVD_AM26
RSVD_AL14
RSVD_AM27
RSVD_AM28
CFG_0
RSVD_AM29
CFG_1
RSVD_AM30
CFG_2
RSVD_L12
CFG_3
RSVD_M12
CFG_4
CFG_5
RSVD_NCTF_A4
CFG_6
RSVD_NCTF_AU40
CFG_7
RSVD_NCTF_AV1
CFG_8
RSVD_NCTF_AV39
CFG_9
RSVD_NCTF_AW2
CFG_10
RSVD_NCTF_AW38
CFG_11
RSVD_NCTF_AY3
CFG_12
RSVD_NCTF_AY37
RSVD_NCTF_B3
CFG_13
CFG_14
RSVD_NCTF_C2
RSVD_NCTF_D1
CFG_15
CFG_16
RSVD_TP_AN11
CFG_17
RESERVED
PCI EXPRESS -- GRAPHICS
AL15
AL17
AL18
AL26
AL27
AL29
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM25
AM26
AM27
AM28
AM29
AM30
L12
M12
TP_CPU_RSVD<19>
TP_CPU_RSVD<20>
TP_CPU_RSVD<21>
TP_CPU_RSVD<22>
TP_CPU_RSVD<23>
TP_CPU_RSVD<24>
TP_CPU_RSVD<25>
TP_CPU_RSVD<26>
SNS_CPU_THERMD_P
SNS_CPU_THERMD_N
TP_CPU_RSVD<29>
TP_CPU_RSVD<30>
TP_CPU_RSVD<31>
TP_CPU_RSVD<32>
TP_CPU_RSVD<33>
TP_CPU_RSVD<34>
TP_CPU_RSVD<35>
TP_CPU_RSVD<36>
TP_CPU_RSVD<37>
TP_CPU_RSVD<38>
TP_CPU_RSVD<39>
TP_CPU_RSVD<40>
TP_CPU_RSVD<41>
A4
AU40
AV1
AV39
AW2
AW38
AY3
AY37
B3
C2
D1
TP_CPU_RSVD_NCTF<1>
TP_CPU_RSVD_NCTF<2>
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<4>
TP_CPU_RSVD_NCTF<5>
TP_CPU_RSVD_NCTF<6>
TP_CPU_RSVD_NCTF<7>
TP_CPU_RSVD_NCTF<8>
TP_CPU_RSVD_NCTF<9>
TP_CPU_RSVD_NCTF<10>
TP_CPU_RSVD_NCTF<11>
AN11
TP_CPU_RSVD_TP<1>
8
8
8
8
8
8
8
8
51 88
51 88
8
8
8
8
8
8
8
8
8
8
8
8
8
INTEL SUGGESTS TO KEEP THESE TPS
FOR LYNNFIELD PROCESSOR

CFG [1:0] :PCIE CONFIGURATION SELECT 11 = 1 X16 PCI EXPRESS
10 = 2 X8 PCI EXPRESS
FOR CLARKDALE PROCESSOR
CFG3 :PCIE LANE REVERSAL
1 = NORMAL OPERATION
0 = LANES REVERSED
CFG4 :NOT USED ON DESKTOP
NOSTUFF
J1050
LAI-TMS817
ST-SM
84 19 10
84 19 10
IN
IN
DMI_S2N_P<3..0>
26
DMI_S2N_N<3..0>
25
2
0
0
GND
CAP
CBP
CAN
CBN
GND
8
1
1
2
2
GND
CCP
12
CDP
CCN
11
CDN
GND
GND
CEP
15
CFP
CEN
17
CFN
GND
3
3
22
GND
CGP
21
24
CHP
CGN
23
CHN
GND
28
10 19 84
OUT
10 19 84
1
1
13
20
OUT
DMI_N2S_N<3..0>
0
10
DMI_N2S_P<3..0>
2
2
19
3
3
27
DMI MID-BUS PROBE

NOSTUFF
J1010
FTR-103-02-S-S
M-ST-SM
84 18
IN
DMI_MIDBUS_CLK100M_P
84 18
IN
DMI_MIDBUS_CLK100M_N
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
CLK
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
10 OF 110
SHEET
10 OF 92
=PPVTT_S0_CPU
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
84
84
84
84
R1112 1
20
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R1113
20
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
CLOSE
CLOSE
CLOSE
CLOSE
TO
TO
TO
TO
21
46
C11
B11
AF2
AF36
91 46 21
91 25
1K
5%
1/16W
MF-LF
402
C11
B11
AF2
AF36
CPU_COMP3
CPU_COMP2
CPU_COMP1
CPU_COMP0
BI
CPU_PROCHOT_L
AH34 PROCHOT*
OUT
PM_THRMTRIP_L
AF35 THERMTRIP*
91 19
91 25
GFX_CLK120M_DPLLSS_P
GFX_CLK120M_DPLLSS_N
IN
18 84
IN
18 84
AK39
OUT
25 84
AK40
FSB_CLK133M_ITP_P
FSB_CLK133M_ITP_N
PEG_CLK
PEG_CLK*
AA3
AA4
PCIE_CLK100M_CPU_P
PCIE_CLK100M_CPU_N
SM_DRAMRST*
AV8
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
AG1
AD1
AE1
PM_EXT_TS_0*
PM_EXT_TS_1*
AB5
AB4
BCLK_ITP
BCLK_ITP*
CPU_MEM_RESET_L
83
83
83
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
AJ38
AK37
IN
PM_SYNC
AH39 PM_SYNC
TCK
TMS
TRST*
AN37
AN40
AM39
XDP_TCK
XDP_TMS
XDP_TRST_L
TDI
TDO
AM37
AM38
XDP_TDI
XDP_TDO
TDI_M
TDO_M
AF37
AF38
CPU_TDO_M_TDI_M
DBR*
AL40
XDP_DBRESET_L
BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*
AL33
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
IN
CPU_PWRGD
AH35 VCCPWRGOOD_0
PM_MEM_PWRGD
AH37 SM_DRAMPWROK
CPUVTT_REG_PGOOD
AG37 VTTPWRGOOD
IN
COMES FROM VTT VR
AK34 TAPPWRGOOD
XDP_CPUPWRGD
OUT
AF34 RSTIN*
PLT_RESET_LS1V1_L
91 11
NOSTUFF
C1100
AL32
AK33
AK32
AM31
AL30
AK30
AK31
0.1UF
10%
16V
X7R-CERM
402
R1170
OUT
25 84
IN
18 84
IN
18 84
OUT
32 91
IN
46 91
IN
46 91
CPU_SM_RCOMP0
CPU_SM_RCOMP1
CPU_SM_RCOMP2
OUT
NOSTUFF1
91 67 63 62
AA8
Y8
XDP_PRDY_L
XDP_PREQ_L
IN
1%
1/16W
MF-LF
402
21 84
BCLK_1
BCLK_1*
PRDY*
PREQ*
3.01K
21 84
IN
AL39 RESET_OBS*
R1121
IN
FSB_CPURSTOUT_L
AH36 VCCPWRGOOD_1
91 25 21
FSB_CLK133M_CPU_P
FSB_CLK133M_CPU_N
(2 OF 10)
OMIT
AG35 PECI
1.1K
1%
1/16W
MF-LF
402
AA7
AA6
LGA1156-SKT
AG39 CATERR*
=PPVTT_S0_CPU
R1120
BCLK_0
BCLK_0*
LYNNFIELD
AK38 SKTOCC*
(GND)
CPU_PECI
BI
U1000
COMP3
COMP2
COMP1
COMP0
PWR MANAGEMENT
91 19
64 46 16 13 11 6
R1103
CPU_CATERR_L
R1110
R1111
R1112
R1113
5%
1/16W
MF-LF
402
CPU_SKTOCC_L
62
R1111
PLACE
PLACE
PLACE
PLACE
51
THERMAL
R1104
MISC
R1110 1
51
51
CLOCKS
R1101 1
R1100
DDR3
MISC
JTAG & MBP
64 46 16 13 11 6
OUT
25
IN
25
IN
25
IN
25
IN
25
IN
25
OUT
25
R1160 1
R1162 1
130
100
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R1161
24.9
1%
1/16W
MF-LF
402
PLACE R1160 CLOSE TO AE1

PLACE R1161 CLOSE TO AD1
PLACE R1162 CLOSE TO AG1
OUT
25 27 91
OUT
25 84
OUT
25 84
OUT
25 84
OUT
25 84
OUT
25 84
OUT
25 84
OUT
25 84
OUT
25 84
51
5%
1/16W
MF-LF
402
DIVIDER IS BASED ON 2009 WW04 MOW
=PP3V3_S5_CPURESET
=PPVTT_S0_CPU
6 11 13 16 46 64
R1127
150
1%
1/16W
MF-LF
402
R11261
10K
1%
1/16W
MF-LF
402
PLT_RESET_LS1V1_L
11 91
2
3
Q1177
PLT_RESET_LS3V3
MMDT3904-X-G
SOT-363-LF
R1125
91 27
IN
CPU_RESET_L
10K
CPU_RESET_L_R
Q1177
PAGE TITLE
MMDT3904-X-G
SOT-363-LF
1%
1/16W
MF-LF
402
CPU CLOCK/MISC/JTAG
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
11 OF 110
SHEET
11 OF 92
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
83 32
BI
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
83 32
BI
BI
83 30
OUT
83 30
OUT
83 30
OUT
83 30
OUT
83 30
OUT
83 30
83 28
OUT
OUT
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
6
AH1 SA_DQ_0
AJ4 SA_DQ_1
AL2 SA_DQ_2
AL1 SA_DQ_3
AG2 SA_DQ_4
AH2 SA_DQ_5
U1000
LYNNFIELD
LGA1156-SKT
(3 OF 10)
OMIT
AK1 SA_DQ_6
AK2 SA_DQ_7
AN3 SA_DQ_8
AN2 SA_DQ_9
AR3 SA_DQ_10
AR2 SA_DQ_11
AM3 SA_DQ_12
AM2 SA_DQ_13
AP1 SA_DQ_14
AR4 SA_DQ_15
AT4 SA_DQ_16
AU2 SA_DQ_17
AW3 SA_DQ_18
AW4 SA_DQ_19
AT3 SA_DQ_20
AT1 SA_DQ_21
AV2 SA_DQ_22
AV4 SA_DQ_23
AW5 SA_DQ_24
AY5 SA_DQ_25
AU8 SA_DQ_26
AY8 SA_DQ_27
AU5 SA_DQ_28
AV5 SA_DQ_29
AV7 SA_DQ_30
AW7 SA_DQ_31
AN27 SA_DQ_32
AT28 SA_DQ_33
AP28 SA_DQ_34
AP30 SA_DQ_35
AN26 SA_DQ_36
AR27 SA_DQ_37
AR29 SA_DQ_38
AN30 SA_DQ_39
AU30 SA_DQ_40
AU31 SA_DQ_41
AV33 SA_DQ_42
AU34 SA_DQ_43
AV30 SA_DQ_44
AW30 SA_DQ_45
AU33 SA_DQ_46
AW33 SA_DQ_47
AW35 SA_DQ_48
AY35 SA_DQ_49
AV37 SA_DQ_50
AU37 SA_DQ_51
AY34 SA_DQ_52
AW34 SA_DQ_53
AV36 SA_DQ_54
AW37 SA_DQ_55
AT39 SA_DQ_56
AT40 SA_DQ_57
AN38 SA_DQ_58
AN39 SA_DQ_59
AU38 SA_DQ_60
AU39 SA_DQ_61
AP39 SA_DQ_62
AP40 SA_DQ_63
AV20 SA_BS_0
AU19 SA_BS_1
AU12 SA_BS_2
AU22 SA_CAS*
AT20 SA_RAS*
AT22 SA_WE*
AF3 SA_DIMM_VREFDQ
CPU_DIMM_VREF_A
SA_CK_0
SA_CK_0*
SA_CKE_0
SA_CK_1
SA_CK_1*
AR22
5
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
AR21
AU10
MEM_A_CKE<0>
AP18
AN18
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
83 32
BI
83 32
BI
OUT
30 83
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
83 32
BI
SA_CKE_1
AW10
MEM_A_CKE<1>
OUT
30 83
83 32
AN21
BI
SA_CK_2
SA_CK_2*
MEM_A_CLK_P<2>
MEM_A_CLK_N<2>
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
SA_CKE_2
AV10
MEM_A_CKE<2>
83 32
BI
SA_CK_3
SA_CK_3*
AP19
AN19
MEM_A_CLK_P<3>
MEM_A_CLK_N<3>
SA_CKE_3
AY10
SA_CS_0*
SA_CS_1*
SA_CS_2*
SA_CS_3*
SA_CS_4*
SA_CS_5*
SA_CS_6*
SA_CS_7*
AV21
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*
SA_DQS_8*
AP21
MEM_A_CKE<3>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CS_L<2>
MEM_A_CS_L<3>
TP_MEM_A_CS_L<4>
TP_MEM_A_CS_L<5>
TP_MEM_A_CS_L<6>
TP_MEM_A_CS_L<7>
AW24
AU21
AU23
AK22
AM22
AL23
AK23
AV23
AV24
AY24
AJ2
AN1
AV6
AN29
AW31
AU35
AT38
AJ3
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
TP_MEM_A_DQS_N<8>
AP3
AU3
AW6
AT29
AW32
AV35
AR38
AM10
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS_8
AK3
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
AW18
SA_ECC_CB_0
SA_ECC_CB_1
SA_ECC_CB_2
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_5
SA_ECC_CB_6
SA_ECC_CB_7
AP10
AN10
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
TP_MEM_A_DQS_P<8>
AP2
AU4
AY6
AR28
AV32
AW36
AR39
AL10
AU15
AW14
AY13
AV14
AW13
AU14
AW12
AT19
AU13
AW11
AU24
AT11
AR10
TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<6>
TP_MEM_A_DQ_CB<7>
AR11
AP11
AK9
AL9
AK11
AM11
83 32
BI
OUT
32 83
83 32
BI
83 32
BI
83 32
BI
83 32
BI
OUT
30 83
83 32
BI
OUT
30 83
83 32
BI
OUT
30 83
83 32
BI
OUT
30 83
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
OUT
30 83
OUT
30 83
OUT
30 83
OUT
30 83
OUT
83 32
BI
32 83
83 32
BI
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
OUT
32 83
83 32
BI
83 32
BI
83 32
BI
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
8 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
BI
32 83
83 32
BI
8 83
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
AY15
AV15
OUT
32 83
30 83
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
AU1
30 83
OUT
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_ODT<2>
MEM_A_ODT<3>
AW23
OUT
OUT
30 83
OUT
30 83
OUT
30 83
OUT
30 83
OUT
30 83
OUT
30 83
OUT
30 83
OUT
30 83
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
83 32
BI
OUT
30 83
83 31
OUT
OUT
30 83
83 31
OUT
OUT
30 83
83 31
OUT
OUT
30 83
83 31
OUT
30 83
OUT
83 31
OUT
30 83
OUT
83 31
OUT
30 83
OUT
OUT
30 83
83 28
OUT
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
AD7
AD6
AH8
AJ8
AC7
AC6
AF5
AE6
AG5
AH7
AK6
AL4
AG6
AG4
AJ7
AK7
AL6
AN5
AP6
AR5
AL5
AM4
AN7
AP5
AT6
AR7
AR9
AM8
AN8
AR6
AL8
AT9
AN23
AP23
AR25
AR26
AT23
AP22
AP25
AT26
AT32
AP31
AR33
AM32
AT31
AR31
AR34
AT33
AR35
AT36
AN33
AP36
AP34
AT35
AN34
AP37
AL35
AM35
AJ36
AJ37
AN35
AM34
AJ35
AL36
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
AU25 SB_BS_0
AW25 SB_BS_1
AV12 SB_BS_2
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
AW27 SB_CAS*
AW26 SB_RAS*
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
U1000
SB_CK_0
AR17
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
32 83
AR16
OUT
32 83
AW8
MEM_B_CKE<0>
OUT
31 83
SB_CK_1
SB_CK_1*
AT15
OUT
32 83
AR15
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
32 83
SB_CKE_1
AY9
MEM_B_CKE<1>
OUT
31 83
SB_CK_2
SB_CK_2*
AN17
OUT
32 83
AN16
MEM_B_CLK_P<2>
MEM_B_CLK_N<2>
OUT
32 83
SB_CKE_2
AU9
MEM_B_CKE<2>
OUT
31 83
SB_CK_3
SB_CK_3*
AR19
OUT
32 83
AR18
MEM_B_CLK_P<3>
MEM_B_CLK_N<3>
OUT
32 83
SB_CKE_3
AV9
MEM_B_CKE<3>
OUT
31 83
SB_CS_0*
SB_CS_1*
SB_CS_2*
SB_CS_3*
SB_CS_4*
SB_CS_5*
SB_CS_6*
SB_CS_7*
AY27
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
AK24
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CS_L<2>
MEM_B_CS_L<3>
TP_MEM_B_CS_L<4>
TP_MEM_B_CS_L<5>
TP_MEM_B_CS_L<6>
TP_MEM_B_CS_L<7>
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
AU27
AU29
AV27
AU28
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_ODT<2>
MEM_B_ODT<3>
OUT
31 83
OUT
31 83
OUT
31 83
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AE4
AH4
AM7
AT7
AN24
AN32
AM33
AK35
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
AE5
AR13
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
TP_MEM_B_DQS_N<8>
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS_8
AF4
AH6
AN6
AR8
AT25
AP32
AR36
AL37
AR14
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
TP_MEM_B_DQS_P<8>
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
AU20
AU18
AV18
AU17
AY18
AV17
AW17
AU16
AT17
AY16
AY25
AW16
AW15
AW28
AY12
AV11
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_4
SB_ECC_CB_5
SB_ECC_CB_6
SB_ECC_CB_7
AR12
AT13
AN15
AP14
AM12
AN12
AN14
AP13
TP_MEM_B_DQ_CB<0>
TP_MEM_B_DQ_CB<1>
TP_MEM_B_DQ_CB<2>
TP_MEM_B_DQ_CB<3>
TP_MEM_B_DQ_CB<4>
TP_MEM_B_DQ_CB<5>
TP_MEM_B_DQ_CB<6>
TP_MEM_B_DQ_CB<7>
LGA1156-SKT SB_CKE_0
(4 OF 10)
OMIT
AU26 SB_WE*
AG3
CPU_DIMM_VREF_B
8
8
8
8
8
8
8
8
LYNNFIELD SB_CK_0*
SB_DIMM_VREFDQ
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY A
SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
SB_DQS_8*
AW29
AV26
AV29
AM23
AM24
AL24
AJ5
AM6
AP8
AR24
AR32
AR37
AM36
8
8
8
8
OUT
31 83
OUT
32 83
OUT
32 83
OUT
32 83
OUT
32 83
OUT
32 83
OUT
32 83
OUT
32 83
OUT
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
8 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
BI
32 83
8 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
OUT
31 83
8
8
8
8
8
8
8
8
PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
12 OF 110
SHEET
12 OF 92
CGC_TP_NCTF
B39
TP_CPU_CGC_NCTF
VCC_NCTF_0
VCC_NCTF_1
A38
C40
=PPVCORE_S0_CPU
6 13 16
FC_AE38
AE38
TP_CPU_FC_AE38
FC_AG40
AG40
TP_CPU_FC_AG40
PSI*
AG38
CPU_PSI_L
U40
U39
U38
U37
U36
U35
U34
U33
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
CPU_VID<7>
AF39
TP_CPU_VTTSELECT
VID_0/MSID_0
VID_1/MSID_1
VID_2/MSID_2
VID_3/CSC_0
VID_4/CSC_1
VID_5/CSC_2
VID_6
VID_7
VTT_SELECT
(Controlled by VTT_SELECT pin)
D
=PPVAXG_S0_CPU
17 6
THIS SUPPLY IS NEEDED ONLY FOR SYSTEM WITH DALE IG
16 64 89
OUT
16 64 89
OUT
16 64 89
OUT
16 64 89
OUT
16 64 89
OUT
16 64 89
OUT
16 64 89
OUT
16 64 89
OUT
16 64 89
VAXG_0
VAXG_1
VAXG_2
VAXG_3
VAXG_4
VAXG_5
VAXG_6
VAXG_7
VAXG_8
VAXG_9
VAXG_10
VAXG_11
VAXG_12
VAXG_13
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_18
VAXG_19
VAXG_20
VAXG_21
VAXG_22
VAXG_23
VAXG_24
VAXG_25
VAXG_26
VAXG_27
VAXG_28
VAXG_29
VAXG_30
VAXG_31
VAXG_32
VAXG_33
VAXG_34
VAXG_35
VAXG_36
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
U1000
LYNNFIELD
LGA1156-SKT
( 7 OF 10 )
OMIT
VSSAXG_SENSE
VAXG_SENSE
B13
A13
TP_GFX_VSENSE_N
TP_GFX_VSENSE_P
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VID_5
GFX_VID_6
G10
B12
E12
E11
C12
G11
J11
TP_GFX_VID<0>
TP_GFX_VID<1>
TP_GFX_VID<2>
TP_GFX_VID<3>
TP_GFX_VID<4>
TP_GFX_VID<5>
TP_GFX_VID<6>
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
F12
J10
F6
TP_GFX_VR_EN
TP_GFX_DPRSLPVR
8
8
8
8
8
8
6 16 29
AJ11
AJ13
AJ15
AT10
AT18
AT21
AU11
AV13
AV16
AV19
AV22
AV25
AV28
AW9
AY11
AY14
AY17
AY23
AY26
=PP1V8_S0_CPU_PLL
VCCPLL_0
VCCPLL_1
VCCPLL_2
=PP1V5_CPU_MEM
VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
6 16 63
AF7
AF8
AG8
PAGE TITLE
T40
VR_CPU_IOUT
T35
T34
CPU_VCC_PKG_SENSE_P
CPU_VCC_PKG_SENSE_N
AE35
AE36
CPU_VTTSENSE_P
CPU_VTTSENSE_N
OUT
49 64 89
OUT
64 89
CPU POWER
DRAWING NUMBER
CONNECTED TO THE IMON OUT FROM CPU REG

IN 64 88
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
OUT
A14
A15
A17
A18
B14
B15
B17
B18
C14
C15
C17
C18
C20
C21
D14
D15
D17
D18
D20
D21
E14
E15
E17
E18
E20
F14
F15
F17
F18
F19
G14
G15
G17
G18
H14
H15
H17
J14
J15
J16
K14
K15
K16
L14
L15
L16
M14
M15
M16
SENSE
LINES
OMIT
AA33
AA34
AA35
AA36
AA37
AA38
AB7
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
AC5
AC8
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AE33
AE34
AE39
AE40
AE8
AF33
AG33
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ32
AK19
AK20
AK21
AL20
AL21
L10
M10
M11
M9
N7
P6
P7
P8
T2
T6
T7
T8
V2
V33
V34
V35
V36
V37
V38
V39
V40
V6
V7
V8
W1
W6
Y33
Y34
Y35
Y36
Y37
Y38
GRAPHICS VIDS
(6 OF 10)
6 11 16 46 64
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
VTT_77
DDR3-1.5V RAILS
LGA1156-SKT
1.8V
(10 OF 10)
OMIT
LYNNFIELD
POWER
LGA1156-SKT
U1000
CPU CORE SUPPLY
U1000
LYNNFIELD
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
1.1V RAIL POWER
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC
J21
J22
J24
J25
J27
J28
J30
J31
J33
J34
J36
J37
J39
J40
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
K36
K38
K39
L17
L19
L20
L22
L23
L25
L26
L28
L29
L31
L32
L34
L35
L37
L38
L40
M17
M19
M21
M22
M24
M25
M27
M28
M30
M33
M34
M36
M37
M39
M40
N33
N35
N36
N38
N39
P33
P34
P35
P36
P37
P38
P39
P40
R33
R34
R35
R36
R37
R38
R39
R40
=PPVTT_S0_CPU
A23
A24
A26
A27
A33
A35
A36
B23
B25
B26
B28
B29
B31
B32
B34
B35
B37
B38
C23
C24
C25
C27
C28
C30
C31
C33
C34
C36
C37
C39
D23
D24
D26
D27
D29
D30
D32
D33
D35
D36
D38
D39
E22
E23
E25
E26
E28
E29
E31
E32
E34
E35
E37
E38
E40
F21
F22
F24
F25
F27
F28
F30
F31
F33
F34
F36
F37
F39
F40
G20
G21
G23
G24
G26
G27
G29
G30
G32
G33
G35
G36
G38
G39
H19
H20
H22
H23
H25
H26
H28
H29
H31
H32
H34
H35
H37
H38
H40
J18
J19
6 13 16
NCTF
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU
POWER
16 13 6
GRAPHICS
CPU VIDS
SENSE LINES
Apple Inc.
051-8600
49 67 89
OUT
67 89

A.0.0
OUT
SIZE
REVISION
BRANCH
PAGE
13 OF 110
SHEET
13 OF 92
A16
A25
A28
A34
A37
AA5
AB3
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AB6
AB8
AC1
AD5
AD8
AE3
AE37
AE7
AF1
AF40
AG34
AG36
AG7
AH3
AH33
AH38
AH5
AJ1
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28
AJ30
AJ33
AJ34
AJ40
AJ6
AJ9
AK10
AK17
AK36
AK4
AK5
AK8
AL11
AL13
AL16
AL19
AL22
AL25
AL28
AL3
AL31
AL34
AL38
AL7
AM1
AM40
AM5
AM9
AN13
AN20
AN22
AN25
AN28
AN31
AN36
AN4
AN9
AP12
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
U1000
LYNNFIELD
LGA1156-SKT
( 8 OF 10 )
OMIT
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
AP15
AP16
AP17
AP20
AP24
AP26
AP27
AP29
AP33
AP35
AP38
AP4
AP7
AP9
AR1
AR20
AR23
AR30
AR40
AT12
AT14
AT16
AT2
AT24
AT27
AT30
AT34
AT37
AT5
AT8
AU32
AU36
AU6
AU7
AV3
AV31
AV34
AV38
AY33
AY36
AY4
AY7
B16
B24
B27
B30
B33
B36
B7
B9
C13
C16
C19
C22
C26
C29
C32
C35
C38
C5
D10
D12
D13
D16
D19
D22
D25
D28
D31
D34
D37
D4
D40
D5
D6
D8
E13
E16
E19
E21
D
E24
E27
E3
E30
E33
E36
E39
E4
F11
F13
F16
F2
F20
F23
F26
F29
F32
F35
F38
F8
G13
G16
G19
G22
G25
G28
G31
G34
G37
G4
G40
G9
H11
H13
H16
H18
H2
H21
H24
H27
H30
H33
H36
H39
H5
H6
J13
J17
J20
J23
J26
J29
J32
J35
J38
J4
J7
J9
K11
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
U1000
LYNNFIELD
LGA1156-SKT
(9 OF 10)
OMIT
VSS
VSS
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
K13
K19
K2
K22
K25
K28
K31
K34
K37
K40
K5
K6
L13
L18
L21
L24
L27
L30
L33
L36
L39
L4
L9
M13
M18
M2
M20
M23
M26
M29
M32
M35
M38
M5
M6
M7
N34
N37
N4
N40
P2
P5
R4
T33
T36
T37
T38
T39
T5
U4
V5
W33
W34
W35
W36
W37
W38
Y7
AF6
1157
SKT MNT HOLE
1158
1159
PAGE TITLE
CPU GROUNDS
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
14 OF 110
SHEET
14 OF 92
84 25 10
CPU_CFG<3>
15 6
15 6
1.5K
R1500 1
5%
1/16W
MF-LF
402
R1508
R1507
R1503
R1504
R1506
R1509
10K
10K
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R15381
R1591
R15351
R15341
R15391
BUF_CLK
R15151
R15171
10K
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PCH_GPIO8_FCIM_EN_L
PCH_GPIO0_BMBUSY_L
PCH_GPIO19_SATA1GP
PCH_GPIO37_SATA3GP
PCH_GPIO21_SATA0GP
FW_PME_L
PCH_GPIO6_TACH2
36 18
36 21
91 19
ENET_ENERGY_DET
ENET_LOW_PWR
PM_LAN_PWRGD
21 25
21 25
18 25
21 40
R1511
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
18 44
21
21
R15991
1K
5%
1/16W
MF-LF
402
R15221
R15231
R15241
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
AP_PWR_EN
21 33
18 25 33
PCH_GPIO38_SLOAD
PCH_GPIO39_SDATAOUT0
FW_CLKREQ_L
15 6
R15291
R15251
MINI_CLKREQ_L
R15751
20 25
FCIM
2
15 6
15 6
18 36
R1510
10K
19 45 91
21
FW_PWR_EN
R1501
PM_BATLOW_L
ENET_CLKREQ_L
PCH_GPIO14_OC7_L
BRCRYPT_PWR_EN
PCH_GPIO15
18 25
21
21
21
18 25 40
R15741 R15731
R15711 R15701
NOSTUFF
10K
10K
10K
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R15361
NOSTUFF
R15431 R15421 R15411
R15321
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
15 6
R15331
10K
2
15 6
EXCARD_CLKREQ_L
PCH_NV_CLE
20
PCH_NV_ALE
PCH_SPKR
PM_CLKRUN_L
SPI_DESCRIPTOR_OVERRIDE_L
BRCRYPT_RESET
PCH_CLKOUTFLEX1
PCH_CLKOUTFLEX2
PCH_CLKOUTFLEX3
18
T28_CLKREQ_L
PEB_CLKREQ_L
20
18
R15261
18
18
19 45 47 91
18 45
R15271
PCH_VRM
R15281
R15301
R15901
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NOSTUFF
18 44
R15371
18
10K
5%
1/16W
MF-LF
402
18
18
PCH_GPIO24
PCH_GPIO27_VRMEN
IF LIKE TO HAVE THE PEB CLOCKS ENABLED. STUFF R1535 AND UNSTUFF R1534
R15721
10K
5%
1/16W
MF-LF
402
42 21
37 21
20
20
20
20
21
PCH_GPIO34_STP_PCI_L
SMC_RUNTIME_SCI_L
PCH_GPIO49_SATA5GP
21
21
21
21 45
21 25
MLB_VR
R15981
ODD_PWR_EN_L
WOL_EN
PCH_PCI_GNT3_L
PCH_PCI_GNT2_L
PCH_PCI_GNT1_L
PCH_PCI_GNT0_L
PCH_INIT3V3_L
1K
10
10
10
10
10
NOSTUFF
R1550 1
B
2
NOSTUFF
R1551 1
NOSTUFF
R15521
1K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NOSTUFF
R15531
NOSTUFF
R15541
R15551 R15121
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPU_FDI_FSYNC<0>
CPU_FDI_FSYNC<1>
CPU_FDI_INT
CPU_FDI_LSYNC<1>
CPU_FDI_LSYNC<0>
19
19
19
19
19
R1560 1
R1561 1
R15621
1K
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R15631
R15641
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PCH_FDI_FSYNC<0>
PCH_FDI_FSYNC<1>
PCH_FDI_INT
PCH_FDI_LSYNC<1>
PCH_FDI_LSYNC<0>
R1565 1
R1566 1
R15671
1K
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R15681
R15691
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PAGE TITLE
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
15 OF 110
SHEET
15 OF 92
CPU Power On Configuration (POC) Straps

Intel recommends all option straps should be provided in layout
64 46 16 13 11 6
=PPVTT_S0_CPU
NO STUFF
CPUPOC4U
R1600 1
R1602 1
NO STUFF
R1604 1
1K
1K
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPUPOC3U
CPU VCORE DECOUPLING

INTEL RECOMMENDATION 17X 22UF 0805
=PPVCORE_S0_CPU
C1600
22UF
2
C1601
22UF
20%
6.3V
CERM-X5R
805-3
C1602
22UF
20%
6.3V
CERM-X5R
805-3
C1603
22UF
20%
6.3V
CERM-X5R
805-3
20%
6.3V
CERM-X5R
805-3
C1604
22UF
2
20%
6.3V
CERM-X5R
805-3
C1605
22UF
2
20%
6.3V
CERM-X5R
805-3
C1606
22UF
2
20%
6.3V
CERM-X5R
805-3
C1607
22UF
22UF
20%
6.3V
CERM-X5R
805-3
C1608
20%
6.3V
CERM-X5R
805-3
C1609
22UF
20%
6.3V
CERM-X5R
805-3
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
89 64 13
OUT
R1601
R1603
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NOSTUFF
1
20%
6.3V
CERM-X5R
805-3
22UF
C1611
20%
6.3V
CERM-X5R
805-3
22UF
C1612
20%
6.3V
CERM-X5R
805-3
22UF
C1613
20%
6.3V
CERM-X5R
805-3
22UF
C1614
20%
6.3V
CERM-X5R
805-3
22UF
C1615
20%
6.3V
CERM-X5R
805-3
22UF
C1616
20%
6.3V
CERM-X5R
805-3
22UF
NOSTUFF
C1617
20%
6.3V
CERM-X5R
805-3
22UF
NOSTUFF
C1618
20%
6.3V
CERM-X5R
805-3
22UF
C1619
=PPVTT_S0_CPU
NO STUFF1
R1616 1
R1618
1K
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPUPOC3D
1
R1611
R1613
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
VID[2:0]
VID[5:3]
VID[6]
VID[7]
PSI#
=
=
=
=
=
R1615
1K
CPUPOC5D
R1617
1K
5%
1/16W
MF-LF
2 402
FUNCTION MSI[2:0] DEFAULT (110)

IMON CONFIG DEFAULT (101)
Reserved (0)
VRD SELECT (0)
Reserved (0)
TABLE_BOMGROUP_HEAD
BOM GROUP
PLACEMENT_NOTE (C1650-C1657):
64 46 16 13 11 6
R1614 1
5%
1/16W
MF-LF
402
MSI - MARKET SEGMENT IDENTIFICATION

PREVENTS THE PLATFORM BOOTING USING A HIGHER POWERED CPU
INTEL RECOMMENDATION 9X22UF 0805
5%
1/16W
MF-LF
2 402
1K
20%
6.3V
CERM-X5R
805-3
BULK CAPS ON CPU VREG PAGE 74
8X 22UF 0805, 7X 10UF 0805
1K
CPUPOC4D
R1612 1
NO STUFF
22UF
VTT (CPU Uncore) DECOUPLING
R1607
1K
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
CPU_VID<7>
CPU_PSI_L
NO STUFF
C1610
NO STUFF
R1605
5%
1/16W
MF-LF
402
CPUPOC5U
1
1K
R1610 1
R1608 1
1K
13 6
NO STUFF
R1606 1
IMAX @ 900mV
CPU Gain Setting
BOM OPTIONS
Equivalent Gain
TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_DIS
Place under socket cavity on secondary side.
000
CPUPOC3D,CPUPOC4D,CPUPOC5D
TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_0_40
40A
001
CPUPOC3D,CPUPOC4D,CPUPOC5U
45
C1657
CPUPOC_IMAX_40_60
60A
010
CPUPOC3D,CPUPOC4U,CPUPOC5D
30
22UF
CPUPOC_IMAX_60_80
80A
011
CPUPOC3D,CPUPOC4U,CPUPOC5U
22.5
CPUPOC_IMAX_80_100
100A
100
CPUPOC3U,CPUPOC4D,CPUPOC5D
18
CPUPOC_IMAX_100_120
120A
101
CPUPOC3U,CPUPOC4D,CPUPOC5U
15
CPUPOC_IMAX_120_140
140A
110
CPUPOC3U,CPUPOC4U,CPUPOC5D
12.857
CPUPOC_IMAX_140_180
180A
111
CPUPOC3U,CPUPOC4U,CPUPOC5U
10
TABLE_BOMGROUP_ITEM
C1650
22UF
2
20%
6.3V
CERM-X5R
805
C1651
22UF
2
20%
6.3V
CERM-X5R
805
C1652
22UF
2
20%
6.3V
CERM-X5R
805
C1653
22UF
2
20%
6.3V
CERM-X5R
805
C1654
22UF
2
20%
6.3V
CERM-X5R
805
C1655
22UF
2
20%
6.3V
CERM-X5R
805
C1656
22UF
2
20%
6.3V
CERM-X5R
805
20%
6.3V
CERM-X5R
805
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
PLACEMENT_NOTE (C1660-C1666):
TABLE_BOMGROUP_ITEM
Place at edge of socket.

1
C1660
10uF
20%
6.3V
X5R
603
C1661
TABLE_BOMGROUP_ITEM
10uF
20%
6.3V
X5R
603
C1662
10uF
20%
6.3V
X5R
603
C1663
10uF
20%
6.3V
X5R
603
C1664
10uF
20%
6.3V
X5R
603
C1665
10uF
20%
6.3V
X5R
603
C1666
10uF
NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
Instead call out appropriate BOM GROUP defined in tables above.
20%
6.3V
X5R
603
BULK CAPS ON CPU VREG PAGE 72
Memory (CPU VCCDDR) DECOUPLING

2x 22uF 0805, 5x 1uF 0402
29 13 6
=PP1V5_CPU_MEM
C1680
22uF
20%
6.3V
CERM-X5R
805
C1681
22uF
20%
6.3V
CERM-X5R
805
C1682
1UF
10%
10V
X5R
402
C1683
1UF
10%
10V
X5R
402
C1684
1UF
10%
10V
X5R
402
C1685
1UF
10%
10V
X5R
402
C1686
1UF
10%
10V
X5R
402
PLL (CPU VCCSFR) DECOUPLING
63 13 6
PAGE TITLE
CPU NON-GFX DECOUPLING
1x 22uF 0805, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402

=PP1V8_S0_CPU_PLL
DRAWING NUMBER
Apple Inc.
1
C1690
20%
6.3V
CERM-X5R
805
22uF
C1691
10%
6.3V
X5R-CERM
603
4.7UF
C1692
10%
6.3V
X5R
402
2.2UF
C1693
10%
10V
X5R
402
1UF
051-8600
1UF
10%
10V
X5R
402

A.0.0
C1694
SIZE
REVISION
BRANCH
PAGE
16 OF 110
SHEET
16 OF 92
13 6
=PPVAXG_S0_CPU
Grounding the Rail because Integrated Graphics wont be used
R1700
0
5%
1/16W
MF-LF
402
R1750
6
=PP3V3_S0_PCH_VCCADAC
69 mA
PP3V3_S0_PCH_VCCA_DAC
5%
1/16W
MF-LF
402
VOLTAGE=3.3V
69 mA
22 89
R1760
6
=PP1V05_S0_PCH_VCCADPLL
150 MA
PP1V05_S0_PCH_VCCADPLLA
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
22 89
75 MA
R1765
1
PP1V05_S0_PCH_VCCADPLLB
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
75 MA
22 89
PAGE TITLE
CPU/PCH GFX DECOUPLING

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
17 OF 110
SHEET
17 OF 92
1
24 22 19 6
24 22 6
PLACE THIS RESISTOR NEAR THE PCH PIN
=PP3V3_S0_PCH
RTCX1
RTCX2
OMIT
U1800
FCBGA
18
85 18
85 18
15
85 18
85 55
IN
8
8
8
85 18
45 15
IN
36 15
AP28
SRTCRST*
PCH_INTRUDER_L
AN24
PCH_INTVRMEN_L
AW31
INTVRMEN
HDA_BIT_CLK_R
AW14
HDA_BCLK
HDA_SYNC_R
AU15
PCH_SPKR
AJ38
HDA_RST_R_L
AV14
HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
AV13
AP18
AU13
AN16
HDA_SDOUT_R
AP16
SPI_DESCRIPTOR_OVERRIDE_L
ENET_ENERGY_DET
AT16
AR16
(IPD)
HDA_RST*
(IPD)
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
GPIO33 (IPU)
GPIO13
JTAG_PCH_TMS
AL34
JTAG_TMS
(IPU)
25 18
IN
JTAG_PCH_TDI
AL36
JTAG_TDI
(IPU)
OUT
JTAG_PCH_TDO
AN34
JTAG_TDO
R1822 1
5%
OUT
22
1/16W
SPI_CLK_1_R V31
5%
IN
TRST*
(IPU)
(IPU)
SPI_CLK
V32
T32
22 SPI_MOSI_1_R T34
1/16W
SPI_CS0*
SPI_CS1*
SPI_MOSI
(IPD)
SPI_MISO
(IPU)
MF-LF 402
SPI_MISO
V30
1
R1861
5% 1/16W
2 33 LPC_AD<1>
MF-LF 402
BI
45 47 85
LPC_R_AD<2>
1
R1862
5% 1/16W
2 33 LPC_AD<2>
MF-LF 402
BI
45 47 85
AM16
LPC_R_AD<3>
R1863
2 33 LPC_AD<3>
MF-LF 402
LPC_FRAME_R_L
1
R1864
5% 1/16W
2 33 LPC_FRAME_L
MF-LF 402
1
5% 1/16W
TP_LPC_DREQ0_L
TP_LPC_DREQ1_L
AL12
AP14
LPC_SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
W41
V40
U38
V38
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
Y38
Y37
AB36
AB35
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD36
AD35
AB31
AB32
SATA_SSD_D2R_N
SATA_SSD_D2R_P
SATA_SSD_R2D_C_N
SATA_SSD_R2D_C_P
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AC41
AC39
AB37
AB38
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AF41
AE40
AD38
AE38
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AF35
AF34
AD33
AD32
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
SATAICOMPO
SATAICOMPI
MF-LF 402
SPI_CS0_R_L
SPI_MOSI_R R1823
85 54 47
JTAG_TCK
SPI
SPI_CLK_R
AL35
TP_SPI_CS1_L
OUT
SPKR
IN
85 47
85 54 47
(IPD)
25 18
AK33
TP_JTAG_PCH_TRST_L
OUT
HDA_SYNC
LPC_R_AD<1>
AL40
SERIRQ
(IPD)
JTAG_PCH_TCK
25
85 54 47
INTRUDER*
LDRQ0*
LDRQ1*/GPIO23
(IPU)
T41
T39
85
BI
45 47 85
OUT
45 47 85
37.4
1%
1/16W
MF-LF
402
1
86 36
86 36
IN
86 36
OUT
10K
86 36
OUT
84 33
IN
84 33
IN
5%
1/16W
MF-LF
402
8
84 33
OUT
84 33
OUT
45 47
84 39
IN
42 84
84 39
OUT
IN
42 84
84 39
OUT
OUT
42 84
8
42 84
8
IN
IN
42 84
OUT
OUT
IN
42 84
OUT
42 84
OUT
42 84
IN
42 84
IN
42 84
OUT
42 84
OUT
42 84
8
8
8
8
8
8
8
8
8
8
SATA0GP/GPIO21
SATA1GP/GPIO19
AJ37
AH38
PCH_GPIO21_SATA0GP
PCH_GPIO19_SATA1GP
20K
5%
1/16W
MF-LF
402
R1800
330K
5%
1/16W
MF-LF
402
10%
10V
X5R
402
PERN4
PERP4
PETN4
PETP4
TP_PCIE_T28_D2R_N<0>
TP_PCIE_T28_D2R_P<0>
TP_PCIE_T28_R2D_C_N<0>
TP_PCIE_T28_R2D_C_P<0>
C12
B13
H12
G12
PERN5
PERP5
PETN5
PETP5
D8
C9
G11
H11
A12
B11
D11
D10
PERN7
PERP7
PETN7
PETP7
C7
B8
K12
J12
PERN8
PERP8
PETN8
PETP8
18 42
84 33
OUT
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
15 25
33 25 15
IN
MINI_CLKREQ_L
84 39
OUT
84 39
OUT
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
IN
FW_CLKREQ_L
OUT
OUT
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
IN
EXCARD_CLKREQ_L
AN35
T10
T9
AM39
M6
M7
AP38
M9
M10
AP33
5%
1/16W
MF-LF
402
8
8
44 15
84 10
18 91
P7
P6
T28_CLKREQ_L
IN
OUT
OUT
15
AW37
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
Y8
Y9
BRCRYPT_PWR_EN
AW38
V7
V8
PEB_CLKREQ_L
SMBALERT*/GPIO11
AL31
SMC_WAKE_SCI_L
SMBCLK
SMBDATA
AV32
AM31
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML0ALERT*/GPIO60
BA33
SML_PCH_0_ALERT_L
SML0CLK
SML0DATA
AW33
AT34
SML_PCH_0_CLK
SML_PCH_0_DATA
SML1ALERT*/GPIO74
AY32
SML_PCH_1_ALERT_L
SML1CLK/GPIO58
SML1DATA/GPIO75
AV31
AR31
SML_PCH_1_CLK
SML_PCH_1_DATA
PEG_A_CLKRQ*/GPIO47
AV39
PEG_CLKREQ_L
IN
Y6
Y7
PEG_CLK100M_N
PEG_CLK100M_P
OUT
OUT
CLKOUT_DMI_N
CLKOUT_DMI_P
H40
J41
PCIE_CLK100M_CPU_N
PCIE_CLK100M_CPU_P
OUT
11 84
OUT
11 84
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
H37
H38
OUT
11 84
OUT
11 84
CLKIN_DMI_N
CLKIN_DMI_P
H20
G20
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
IN
26 84
IN
26 84
CLKIN_BCLK_N
CLKIN_BCLK_P
Y32
Y31
FSB_CLK133M_PCH_N
FSB_CLK133M_PCH_P
IN
26 84
IN
26 84
AM22
AL22
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
IN
26 84
IN
26 84
CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P
Y34
Y35
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
IN
26 84
IN
26 84
REFCLK14IN
AF7
PCH_CLK14P3M_REFCLK
IN
26 85
PCH_CLK33M_PCIIN
IN
27 85
IN
27 85
OUT
27 85
OMIT
U1800
IBEX-PEAK-DESKTOP
FCBGA
(2 OF 10)
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PERN6
PERP6
PETN6
PETP6
AW35
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0*/GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1*/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2*/GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_PCILOOPBACK
OUT
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4*/GPIO26
XTAL25_IN
XTAL25_OUT
Y4
Y2
XCLK_RCOMP
AA3
48 88
18
OUT
48 88
48 88
BI
18
OUT
48 88
48 88
BI
PCH_CLK25M_XTALIN
PCH_CLK25M_XTALOUT
85
48 88
BI
DOES THIS NEED LENGTH MATCH???
PCIECLKRQ3*/GPIO25
CLKOUT_PCIE5N
CLKOUT_PCIE5P
AL11
18 45
PCH_XCLK_RCOMP
CLKOUTFLEX0/GPIO64
AD10
BRCRYPT_RESET
CLKOUTFLEX1/GPIO65
AK1
PCH_CLKOUTFLEX1
15
CLKOUTFLEX2/GPIO66
AB6
PCH_CLKOUTFLEX2
15
CLKOUTFLEX3/GPIO67
AL3
PCH_CLKOUTFLEX3
15
15 44
(IPD)
PCIECLKRQ5*/GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ*/GPIO56
(IPD)
(IPD)
(IPD)
18
18
18
18 42
C1803
1UF
V2
W1
TP_PCIE_CLK100M_T28_N
TP_PCIE_CLK100M_T28_P
24 19 18 6
10%
10V
X5R
402
R1853
XDP
25 18
5%
1/16W
MF-LF
2 402
R1810
85 18
HDA_BIT_CLK_R
JTAG_PCH_TMS
85 18
JTAG_PCH_TDI
33
HDA_BIT_CLK
45 18
R1812
51
XDP
R1882
85 18
HDA_RST_R_L
5%
1/16W
MF-LF
402
100
5%
1/16W
MF-LF
2 402
XDP
R1884
100
5%
1/16W
MF-LF
2 402
33
85 18
HDA_SDOUT_R
33
HDA_SYNC
OUT
5%
1/16W
MF-LF
402
R1855
10K
5%
1/16W
MF-LF
2 402
SMC_WAKE_SCI_L
18
SML_PCH_0_ALERT_L
18
SML_PCH_1_ALERT_L
HDA_RST_L
OUT
PCH SATA/PCIE/CLK/LPC/SPI
55 85
DRAWING NUMBER
Apple Inc.
R1813
33
PAGE TITLE
HDA_SDOUT
051-8600

A.0.0
55 85
SIZE
REVISION
OUT
5%
1/16W
MF-LF
402
55 85
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
10K
55 85
R1811
HDA_SYNC_R
R1856
OUT
R1854
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10K
PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)
200
5%
1/16W
MF-LF
2 402
25 18
XDP
R1883
200
JTAG_PCH_TCK
=PP3V3_S5_PCH
=PP3V3_S5_PCH
R1881
D14
D13
K14
L14
ENET_CLKREQ_L
10K
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
IN
R18501
24 19 18 6
25 18
PERN3
PERP3
PETN3
PETP3
OUT
15 25
PCH_SATALED_L
1
1UF
B15
C14
H14
G14
84 33
84 10
C1802
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
36 15
15
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
PERN2
PERP2
PETN2
PETP2
OUT
1M
5%
1/16W
MF-LF
402
B17
A16
H16
G16
84 36
R1803
R1801
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
20K
PERN1
PERP1
PETN1
PETP1
OUT
=PP3V3_S0_SATALED
5%
1/16W
MF-LF
402
D15
C16
D18
D17
84 36
15
R1802 1
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
PCH_SATALED_L
42 6
IN
OUT
PCH_SATAICOMP
AN39
PP3V3_G3_RTC
IN
84 39
IN
40 25 15
89 27 24 22
IN
R1820
BI
SATALED*
(IPU)
45 47 85
AT12
AK16
AL16
FWH4/LFRAME* AR14
RTC
LPC
PCH_SRTCRST_L
(1 OF 10)
IN
25 18
RTCRST*
IHDA
18
AK24
SATA
18
RTC_RESET_L
JTAG
91 18
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
BI
SMBUS
OUT
AW30
BA30
R1830 1
2 33
LPC_AD<0>
MF-LF 402
PEG
85 27
PCH_CLK32K_RTCX1
PCH_CLK32K_RTCX2
1
R1860
5% 1/16W
PCI-E*
IN
(IPU)
85 27
LPC_R_AD<0>
1%
1/16W
MF-LF
402
FROM CLK BUFFER
IBEX-PEAK-DESKTOP
R1890
90.9
CLOCK
FLEX
68 24 21 6
BRANCH
PAGE
18 OF 110
SHEET
18 OF 92
=PP3V3_S5_PCH
10K
1%
1/16W
MF-LF
402
=PP3V3_S5_PCH
R1900
OMIT
6 18 19 24
U1800
49.9
1%
1/16W
MF-LF
402 2
2
1%
1/16W
MF-LF
402
FCBGA
IBEX-PEAK-DESKTOP
84 10
IN
84 10
IN
84 10
IN
84 10
IN
84 10
IN
84 10
IN
84 10
IN
84 10
IN
84 10
OUT
84 10
OUT
84 10
OUT
84 10
OUT
84 10
OUT
84 10
OUT
84 10
OUT
84 10
OUT
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
A19
B20
E20
G18
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
B18
C19
D20
H18
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
J22
G22
H24
L24
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
H22
F22
G24
K24
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
OMIT
U1800
FCBGA
(3 OF 10)
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
K30
H30
D31
F31
K31
C30
A33
C33
TP_PCH_FDI_RX_N<0>
TP_PCH_FDI_RX_N<1>
TP_PCH_FDI_RX_N<2>
TP_PCH_FDI_RX_N<3>
TP_PCH_FDI_RX_N<4>
TP_PCH_FDI_RX_N<5>
TP_PCH_FDI_RX_N<6>
TP_PCH_FDI_RX_N<7>
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
J30
G30
D32
G31
J31
B31
B32
B34
TP_PCH_FDI_RX_P<0>
TP_PCH_FDI_RX_P<1>
TP_PCH_FDI_RX_P<2>
TP_PCH_FDI_RX_P<3>
TP_PCH_FDI_RX_P<4>
TP_PCH_FDI_RX_P<5>
TP_PCH_FDI_RX_P<6>
TP_PCH_FDI_RX_P<7>
FDI_INT
B36
PCH_FDI_INT
FDI_FSYNC0
FDI_FSYNC1
C21
D21
DMI_ZCOMP
DMI_IRCOMP
IN
PM_SYSRST_L
AL38
SYS_RESET*
91 63 32
IN
PM_SYS_PWRGD
AT38
SYS_PWROK
91 63
IN
PM_PCH_PWRGD
AM24
PWROK
91 63
IN
PM_ME_PWRGD
AL33
MEPWROK
91 15
IN
PM_LAN_PWRGD
AY31
LAN_RST*
91 11
OUT
PM_MEM_PWRGD
AW32
DRAMPWROK
IN
PM_RSMRST_PCH_L
AL24
PM_SUS_PWR_ACK
AT37
91 45 27
91 62
91
RSMRST*
FDI_LSYNC0
FDI_LSYNC1
SYSTEM POWER
MANAGEMENT
PCH_DMI_COMP
85
SHORT THESE TWO PINS VERY NEAR THE PINS
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT
E34
E36
C35
D35
PCH_FDI_FSYNC<0>
PCH_FDI_FSYNC<1>
PCH_FDI_LSYNC<0>
PCH_FDI_LSYNC<1>
1
R1925
(IPD)
(IPD)
PCIE_WAKE_L
OUT
15
OUT
15
OUT
15
OUT
15
OUT
15
WAKE*
AR33
PCIE_WAKE_L
AJ40
PM_CLKRUN_L
SUS_STAT*/GPIO61
AK31
LPC_PWRDWN_L
OUT
45 47
SUSCLK/GPIO62
AH31
PM_CLK32K_SUSCLK_R
OUT
9 85 91
SLP_S5*/GPIO63
AU36
PM_SLP_S5_L
OUT
45 91
OUT
19 32 91
SUS_PWR_DN_ACK/GPIO30
AP35
PM_SLP_S4_L
SLP_S3*
AV35
PM_SLP_S3_L
91 45 25
IN
PM_PWRBTN_L
AK36
PWRBTN*
19
IN
PCH_ACPRESENT_GPIO31
AP40
ACPRESENT/GPIO31
IN
PM_BATLOW_L
(IPU)
SLP_M*
AT36
PM_SLP_M_L
TP23
AH35
TP_PM_SLP_DSW_L
C37
PM_SYNC
IN
PCH_RI_L
R1909
GPIO72
AT33
RI*
PMSYNCH
SLP_LAN*/GPIO29
BA35
SDVO_STALLN
SDVO_STALLP
P3
N2
TP_SDVO_STALLN
TP_SDVO_STALLP
SDVO_INTN
SDVO_INTP
N4
M3
TP_SDVO_INTN
TP_SDVO_INTP
AB13
AB12
TP_DP_IG_B_DDC_CLK
TP_DP_IG_B_DDC_DATA
L2
M1
J1
TP_DP_IG_B_AUX_N
TP_DP_IG_B_AUX_P
TP_DP_IG_B_HPD
J8
K10
J11
K11
F6
H6
H4
G4
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
AB10
AB11
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
L10
L9
J3
TP_DP_IG_C_AUX_N
TP_DP_IG_C_AUX_P
TP_DP_IG_C_HPD
F4
E3
G3
F2
C4
B4
D2
D3
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>
BI
AB7
AB9
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
OUT
5 32 33 37 46 62 63 91
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
L4
K4
H2
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
OUT
5 62 91
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
B6
C5
D7
D6
G8
F8
G9
F9
TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>
OUT
11 91
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
AB2
AC3
AC1
CRT_BLUE
CRT_GREEN
CRT_RED
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
AG2
AG4
CRT_DDC_CLK
CRT_DDC_DATA
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
AD4
AD3
CRT_HSYNC
CRT_VSYNC
PCH_DAC_IREF
AE2
AB4
DAC_IREF
CRT_IRTN
TP_SLP_LAN_L
KEEPING TP, IF NEED TO USE IT LATER
8
8
SDVO_CTRLCLK
SDVO_CTRLDATA
19 33 37
15 45 47 91
10K
1%
1/16W
MF-LF
402
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
19 33 37
AY34
L7
L6
1K
GPIO32
SLP_S4*
(4 OF 10)
SDVO_TVCLKINN
SDVO_TVCLKINP
1%
1/16W
MF-LF
402 2
91 45 15
IBEX-PEAK-DESKTOP
6 18 22 24
R1915
100K
DIGITAL DISPLAY INTERFACE
6 18 19 24
DMI
FDI
R1905
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
(IPU)
DDPC_CTRLCLK
DDPC_CTRLDATA
8
8
8
8
8
8
8
8
8
8
8
EXTERNAL DP
8
8
8
8
8
8
8
8
8
(IPD)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
(IPU)
DDPD_CTRLCLK
DDPD_CTRLDATA
8
8
8
8
8
INTERNAL DP
8
8
8
8
8
8
8
8
(IPD)
CRT
8
8
8
8
8
8
8
8
8
8
8
R1951
1K
=PP3V3_S5_PCH
5%
1/16W
MF-LF
6 18 19 24
2 402
PLACE CLOSE TO U1800 PIN
1
R1961
10K
1%
1/16W
MF-LF
402
NOSTUFF
R1960
46 45
SMC_ADAPTER_EN
PCH_ACPRESENT_GPIO31
19
5%
1/16W
MF-LF
402
R1967
2
PM_SLP_S4_L
To U3300
33
5%
1/16W
MF-LF
402
91
62
PM_SLP_S4_2_L
5%
1/16W
MF-LF
402
R1966
91 32 19
33
PM_SLP_S4_1_L
To U6900
45 46
91
To R5089,R4953
R1968
2
33
PM_SLP_S4_3_L
5 91
To Q500
PAGE TITLE
PCH DMI/FDI/GRAPHICS
5%
1/16W
MF-LF
402
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
19 OF 110
SHEET
19 OF 92
IBEX-PEAK-DESKTOP
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
6
=PP3V3_S0_PCH_GPIO
R2010
R2011
R2012
R2013
10K
10K
10K
10K
R2015
R2016
R2017
R2018
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
85
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
85
15
15
15
15
R2030
10K
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
60
R2031
10K
2
61
R2020
R2021
10K
10K
R2022
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8
R2023
R2024
10K
10K
R2027
10K
R2025
R2026
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AV3
AY6
AP5
AW10
C/BE0*
C/BE1*
C/BE2*
C/BE3*
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
AT8
AR4
AT11
BA5
PIRQA*
PIRQB*
PIRQC*
PIRQD*
PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
91 27
OUT
85 27
OUT
85 27
OUT
85 27
OUT
REQ0*
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
PCI_INTE_L
AUD_IP_PERIPHERAL_DET
PCI_INTG_L
AUD_I2C_INT_L
AU8
AH7
AP12
AW4
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
TP_PCI_RESET_L
AH10
PCIRST*
PCI_SERR_L
PCI_PERR_L
AV6
AT4
SERR*
PERR*
PCI_IRDY_L
TP_PCI_PAR
PCI_DEVSEL_L
PCI_FRAME_L
AP7
AP6
AT6
AL7
IRDY*
PAR
DEVSEL*
FRAME*
AN8
AL6
T33
P35
T31
P33
M35
L33
M36
M34
M30
F36
H33
F37
E39
G33
D40
F33
TP_NV_DQ<0>
TP_NV_DQ<1>
TP_NV_DQ<2>
TP_NV_DQ<3>
TP_NV_DQ<4>
TP_NV_DQ<5>
TP_NV_DQ<6>
TP_NV_DQ<7>
TP_NV_DQ<8>
TP_NV_DQ<9>
TP_NV_DQ<10>
TP_NV_DQ<11>
TP_NV_DQ<12>
TP_NV_DQ<13>
TP_NV_DQ<14>
TP_NV_DQ<15>
NV_ALE
NV_CLE
J34
L35
PCH_NV_ALE
PCH_NV_CLE
NV_RCOMP
L36
TP_NV_RCOMP
NV_RB*
M32
TP_NV_RB_L
NV_WR0_RE*
NV_WR1_RE*
J36
J35
TP_NV_WR_RE_L<0>
TP_NV_WR_RE_L<1>
NV_WE_CK0*
NV_WE_CK1*
M31
F38
TP_NV_WE_CK_L<0>
TP_NV_WE_CK_L<1>
AW25
AY25
BA23
AY24
AW23
AY22
AR22
AP22
AV21
AV22
AY20
AW21
AK20
AL20
AV20
AW19
BA19
AY18
AM20
AN20
AV17
AV18
AR20
AT20
AK18
AL18
AY17
BA16
USB_HUB1_UP_N
USB_HUB1_UP_P
TP_USB_1N
TP_USB_1P
USB_BRCRYPT_N
USB_BRCRYPT_P
TP_USB_3N
TP_USB_3P
USB_WM_N
USB_WM_P
TP_USB_5N
TP_USB_5P
TP_USB_6N
TP_USB_6P
TP_USB_7N
TP_USB_7P
USB_HUB2_UP_N
USB_HUB2_UP_P
TP_USB_9N
TP_USB_9P
TP_USB_10N
TP_USB_10P
TP_USB_11N
TP_USB_11P
TP_USB_12N
TP_USB_12P
TP_USB_13N
TP_USB_13P
(IPU)
GNT0*
(IPU)
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
PCI_STOP_L
PCI_TRDY_L
NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
(IPD)
AK11
AK6
BA9
AM3
AK12
TP_NV_DQS<0>
TP_NV_DQS<1>
(IPD)
PCH_PCI_GNT0_L
PCH_PCI_GNT1_L
PCH_PCI_GNT2_L
PCH_PCI_GNT3_L
PCI_PLOCK_L
5%
AP4
AW5
AY4
AH8
P36
F40
(5 OF 10)
PLOCK*
STOP*
TRDY*
TP_PCI_PME_L
AH11
PME*
PLT_RESET_L
AV34
PLTRST*
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
AF6
AD7
AF9
AD9
AD12
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
(IPU)
(DPD)
NV_DQS0
NV_DQS1
FCBGA
EHCI1
TP_NV_CE_L<0>
TP_NV_CE_L<1>
TP_NV_CE_L<2>
TP_NV_CE_L<3>
(DPD)
H36
H35
P32
E41
EHCI2
NV_CE0*
NV_CE1*
NV_CE2*
NV_CE3*
OMIT
U1800
NVRAM
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
NOTE: Internal pull-downs on all USB pins
AT9
AP11
AU6
AY10
AP9
AV8
AR9
AV7
AW9
AR3
AW7
AR8
AU3
AP2
AU1
AN3
AM2
AM11
AM4
AY8
AL10
AT5
AL2
AT2
AL4
AV10
AL9
AN7
AK7
AN6
AH12
AN11
PCI
TP_PCI_AD<0>
TP_PCI_AD<1>
TP_PCI_AD<2>
TP_PCI_AD<3>
TP_PCI_AD<4>
TP_PCI_AD<5>
TP_PCI_AD<6>
TP_PCI_AD<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS*
USBRBIAS
AY15
AV15
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
AT31
AT30
AK28
AP30
AP31
AL28
AL30
AM30
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
15
15
8
8
8
8
BI
34 85
BI
34 85
BI
BI
BI
44 85
BI
44 85
BI
BI
BI
44 85
BI
44 85
BI
BI
BI
BI
BI
BI
BI
35 85
BI
35 85
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
USB HUB 1
Unused
Blu-ray transcript
Unused
WM
Unused
Unused
Unused
USB HUB 2
Unused
=PP3V3_S5_PCH_GPIO
Unused
NOSTUFF
1
Unused
R2061
Unused
10K
85
TIE TRACES TOGETHER CLOSE TO PINS
5%
1/16W
MF-LF
402
R2067
10K
10K
Unused
R2060 1
PCH_USB_RBIAS
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
R2064
10K
5%
1/16W
MF-LF
402
2
R2062 1
R2066
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2065 1
10K
5%
1/16W
MF-LF
402
PCH_GPIO59_OC0_L
25
USB_HUB_SOFT_RESET_L 25 34
PCH_GPIO41_OC2_L
25
PCH_GPIO42_OC3_L
25
PCH_GPIO43_OC4_L
25
PCH_GPIO9_OC5_L
25
PCH_GPIO10_OC6_L
25
PCH_GPIO14_OC7_L
15 25
R2070 1
22.6
1%
1/16W
MF-LF
402
PLACE THE RESISTOR CLOSE TO COMMON POINT
PAGE TITLE
PCH PCI/FLASHCACHE/USB
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
20 OF 110
SHEET
20 OF 92
=PP3V3_S0_PCH
IPU* = Only on TACH function.
47K
5%
1/16W
MF-LF
402
15
45 15
AK41
BMBUSY*/GPIO0
40 15
FW_PME_L
AL14
TACH1/GPIO1
TACH2/GPIO6
(IPU*)
IN
SMC_RUNTIME_SCI_L
AY11
TACH3/GPIO7
(IPU*)
PCH_GPIO8_FCIM_EN_L
AK30
GPIO8
ENET_LOW_PWR
AU34
LAN_PHY_PWR_CTRL/GPIO12
PCH_GPIO15
AY36
GPIO15
AUD_IPHS_SWITCH_EN
AH39
SATA4GP/GPIO16
61 25
LPCPLUS_GPIO
IN
42 15
15
IN
15
32 25
OUT
15
92 91 44 25
(IPD)
TACH0/GPIO17
(IPU*)
ODD_PWR_EN_L
AN41
SCLOCK/GPIO22
PCH_GPIO24
AR34
GPIO24
PCH_GPIO27_VRMEN
AP37
GPIO27
ISOLATE_CPU_MEM_L
AV40
GPIO28
PCH_GPIO34_STP_PCI_L
AT40
STP_PCI*/GPIO34
MXM_GOOD
AR41
GPIO35
SDCARD_RESET
AK39
SATA2GP/GPIO36
AR38
SATA3GP/GPIO37
PCH_GPIO38_SLOAD
AM38
SLOAD/GPIO38
15
PCH_GPIO39_SDATAOUT0
AL39
SDATAOUT0/GPIO39
37 15
WOL_EN
AV36
PCIECLKRQ6*/GPIO45
33 15
AP_PWR_EN
AP36
PCIECLKRQ7*/GPIO46
15
FW_PWR_EN
AG38
SDATAOUT1/GPIO48
25 15
PCH_GPIO49_SATA5GP
AG40
SATA5GP/GPIO49
85 47
SPIROM_USE_MLB
AL32
GPIO57
TP_PCH_PWM0
TP_PCH_PWM1
TP_PCH_PWM2
TP_PCH_PWM3
BA12
AR12
AW12
AY13
PWM0
PWM1
PWM2
PWM3
TP_PCH_SST
AN31
SST
8
8
A40
A5
AW41
AY2
AY41
B2
B40
B41
BA1
BA2
C1
C41
E1
TP_DMI_CLK100M_LAN
TP_DMI_CLK100M_LAP
AG37
PCH_A20GATE
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
L38
K38
FSB_CLK133M_CPU_N
FSB_CLK133M_CPU_P
PECI
D36
CPU_PECI
MISC
PCH_GPIO37_SATA3GP
CLKOUT_PCIE7N
CLKOUT_PCIE7P
T7
T6
FCBGA
(6 OF 10)
(IPU)
15
25 15
AW11
TP_PCIE_CLK100M_XDPN
TP_PCIE_CLK100M_XDPP
U1800
AV11
15
U4
V4
IBEX-PEAK-DESKTOP
OUT
36 15
47
(IPU*)
PCH_GPIO6_TACH2
15
CLKOUT_PCIE6N
CLKOUT_PCIE6P
OMIT
A20GATE
CPU
R21901
PCH_GPIO0_BMBUSY_L
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
AM40
PCH_RCIN_L
PROCPWRGD
B38
CPU_PWRGD
THRMTRIP*
C38
PM_THRMTRIP_L
TP1
L18
TP_PCH_TP1
TP2
K18
TP_PCH_TP2
TP3
J20
TP_PCH_TP3
TP4
P12
TP_PCH_TP4
TP5
P13
TP_PCH_TP5
TP6
T13
TP_PCH_TP6
TP7
T12
TP_PCH_TP7
TP8
V34
TP_PCH_TP8
TP9
AT24
TP_PCH_TP9
TP10
AR24
TP_PCH_TP10
TP11
V20
TP_PCH_TP11
TP12
P10
TP_PCH_TP12
TP13
P9
TP_PCH_TP13
TP20
AU39
TP_PCH_TP20
TP_PCH_TP21
RCIN*
GPIO
25 15
RSVD
=PP3V3_S0_PCH
NCTF
68 24 21 18 6
(IPD)
TP21
AH30
TP22_NCTF0
TP22_NCTF1
TP22_NCTF2
TP22_NCTF3
A3
A41
AY1
BA41
TP18
AK35
TP_PCH_TP18
TP19
AN36
TP_PCH_TP19
NC0
NC1
NC2
NC3
NC4
AF15
V10
V11
Y11
Y12
INIT3_3V*
6 18 21 24 68
8
8
R2150 1
10K
5%
1/16W
MF-LF
402
8
8
OUT
11 84
OUT
11 84
BI
R2155
10K
5%
1/16W
MF-LF
402
11
OUT
11 25 91
IN
11 46 91
PCH_INIT3V3_L
AR39
15
THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
PAGE TITLE
PCH MISC
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
21 OF 110
SHEET
21 OF 92
OMIT
C2200
0.1UF
20%
10V
CERM
402
PLACE C2260 ON THE BACK SIDE NEAR AF27
PCH output, for decoupling only

89 PPVOUT_G3_PCH_DCPRTC
C2210
L39
196 MA (VCCVRM[0-3] TOTAL)
0.1UF
2
AY38
VOLTAGE=3.3V
20%
10V
CERM
402
R2
75 MA
T1
M18
M20
M22
3.251 A
(VCCIO[1-56] total)
AA27
AH20
AH22
89 PPVOUT_S0_PCH_DCPSST
VOLTAGE=3.3V
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
B
24 6
89 27 24 18
AF30
DCPSUS
AH18
AJ14
AJ16
B39
A39
< 1 mA
24 6
V5REF_SUS
24 6
89 24
PP1V05_S0_PCH_VCCAPLL_EXP
24 19 18 6
40 mA (if GPIO27 is low)
VCCME16
VCCME17
VCCME18
VCCME19
VCCME20
VCCME21
VCCME22
VCCME23
VCCME24
VCCME25
VCCME26
PPVOUT_S0_PCH_VCCRTC_NCTF
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3_G3_RTC
2 mA S0-S5, ~6 uA G3
BA39
AY29
AN1
< 1 mA S0-S5
24 89
< 1 mA
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
AK14
AV2
AY3
U40
AW1
BA3
VCCSATAPLL
P41
B25
3.251 A
(VCCIO[1-56] total)
PP1V8R1V5_S0_PCH_VCCVRM
PP1V05_S0_PCH_VCCAPLL_SATA
VCC3_3_4
VCC3_3_5
VCC3_3_6
V_CPU_IO
V_CPU_IO_NCTF
VCCRTC_NCTF
VCCRTC
VCCVRM3
L40
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
C24
C25
D24
D25
F26
G26
H26
J26
K26
L26
M16
VCCME12
VCCME13
VCCME14
VCCME15
AF16
AF8
AG5
AH1
VCCSUSHDA
AJ18
6 22 24
357 mA
(VCC3_3[1-14] total)
VCC3_3_NCTF0
VCC3_3_NCTF1
VCCIO8
3.251 A
(VCCIO[1-56] total)
24 89
6 22 24
24 89
6 22 24
24 22 6
89 24 22
HDA_SYNC
VCCVRM
PLL POWERS
1 (IPU)
0 (IPD)
1.8V
Float
1 (IPU)
1.5V
Float
1.5V
1.05V
1.8V
1.05V
M39
M41
P30
VCCPNAND0
VCCPNAND1
VCCPNAND2
N38
N40
VCCME3_3_0
VCCME3_3_1
M24
VCCIO23
A21
VCCAPLLEXP
M26
N16
N18
N20
N22
N24
N26
P15
P16
P18
P19
P24
P38
P39
R37
R38
R40
T15
T19
T29
T30
T36
T37
U15
U19
V15
V29
V36
Y26
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VCCIO41
VCCIO42
VCCIO43
VCCIO44
VCCIO45
VCCIO46
VCCIO47
VCCIO48
VCCIO49
VCCIO50
VCCIO51
VCCIO52
Y29
Y36
VCCIO53
VCCIO54
A9
VCC3_3_0
C2
VCCVRM0
GPIO27
VCCDMI
357 mA (VCC3_3[1-14] total)
22 24 89
A23
85 mA S0, 22 mA M-on
PP5V_S0_PCH_V5REF
V5REF
VCCVRM1
AY40
BA40
AW16
C3
156 MA (1.8V)
24 22 18 6
357 mA
(VCC3_3 - 9 TOTAL PINS)
24 6
24 6
65 MA
PP5V_S5_PCH_V5REFSUS
VCCIO1
VCCIO2
VCCIO3
DCPSST
AH13
AH3
AH4
AH6
AJ2
AJ4
AJ5
Y15
Y16
Y18
Y19
C2230
VCCIO20
VCCIO21
VCCIO22
VCCADAC
196 MA ( TOTAL 4 PINS)
VCCADPLLB
AH33
VOLTAGE=3.3V

89 PPVOUT_S5_PCH_DCPSUS
0.1UF
89 24 22
6 24
163 mA S0, 65 mA S3-S5

(VCCSUS3_3 - 17 TOTAL)
24 22 6
AF1
6 22 24
VCCADPLLA
VCCSUS3_3_NCTF0
VCCSUS3_3_NCTF1
75 MA
C2220
3.251 A
(VCCIO[1-56] total)
89 17
VCCVRM2
(7 OF 10)
PP3V3_S0_PCH_VCCA_DAC
69 MA
89 17
DCPRTC
89 24 22
PCI/GPIO/LPC
SATA
PCI/GPIO/LPC
CPU
VCCME0
VCCME1
VCCME2
VCCME3
VCCME4
VCCME5
VCCME6
VCCME7
VCCME8
VCCME9
VCCME10
VCCME11
AK26
AL26
AM26
AN26
AP26
AR26
AT26
AU26
AU27
AV25
AV27
AV29
AW26
AW39
AW40
AY27
BA26
89 17
RTC
HDA
20%
10V
CERM
402
AA15
AA16
AA18
AB15
AB16
AD13
AD15
AD16
AE15
AE16
AF10
AF13
2.222A S0, 800 MA M-ON

(VCCME[1-16] total)
0.1UF
DCPSUSBYP
24 22 6
C2260
AF27
VOLTAGE=3.3V
VCCSUS3_3_0
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_9
VCCSUS3_3_10
VCCSUS3_3_11
VCCSUS3_3_12
VCCSUS3_3_13
VCCSUS3_3_14
VCCSUS3_3_15
VCCSUS3_3_16
FCBGA
NAND / SPI DMI CRT
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
AH23
AJ22
AT28
B24
U1800
6 24
VCC CORE

89 PPVOUT_S5_PCH_DCPSUSBYP
VCCLAN0
VCCLAN1
CLOCK AND MISCELLANEOUS
Y20
Y22
372 MA S0, 78 MA M-ON
VCCIO4
VCCIO5
VCCIO6
VCCIO7
3.251 A
(VCCIO[1-56] total)
VCCIO
D
NOSTUFF 1
VCCACLK
USB
AA1
24 6
OMIT
FCBGA
(10 OF 10)
PP1V05_S0_PCH_VCCA_CLK
89 24
IBEX-PEAK-DESKTOP
U1800
IBEX-PEAK-DESKTOP
89 24
PP1V05_S0_PCH_VCCAPLL_FDI
24 22 18 6
A37
AA26
3.251 A
(VCCIO[1-56] total)
VCCFDIPLL
VCCIO0
FDI
HVCMOS
VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCCCORE7
VCCCORE8
VCCCORE9
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE17
VCCCORE18
VCCCORE19
VCCCORE20
VCCCORE21
VCCCORE22
VCCCORE23
VCCCORE24
VCCCORE25
VCCCORE26
VCCCORE27
VCCCORE28
VCCCORE29
VCCCORE30
VCCCORE31
VCCCORE32
VCCCORE33
VCCCORE34
VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE39
VCCCORE40
VCCCORE41
VCCCORE42
VCCCORE43
VCCCORE44
VCCCORE45
VCCCORE46
VCCCORE47
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE51
VCCCORE52
VCCCORE53
VCCCORE54
VCCCORE55
VCCCORE56
VCCCORE57
A26
A28
AA23
AA24
AB24
AB26
AD18
AD20
AD23
AD26
AE18
AE19
AE20
AE22
AE23
AE24
AE26
AF19
AF20
AF22
AF23
AF24
B27
B29
C26
C28
D27
D28
D29
E26
E27
E29
F28
G28
H28
J28
K28
L28
M28
N28
P26
P27
P29
T20
T22
T23
T24
T26
T27
U20
U22
U23
U26
V23
V24
V26
Y23
Y24
VCC3_3_1
VCC3_3_2
VCC3_3_3
AD27
AE27
AH16
6 24
1.629 A
B
357 mA (VCC3_3[1-14] total)
6 22 24
Note: 1.5V option consumes more current than 1.8V

PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
6 22 24
2.222 A S0, 800 MA M-ON

(VCCME[1-16] total)
6 24
6 MA S0
C2250
0.1UF
20%
10V
2 CERM
402
PAGE TITLE
PCH POWER
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
22 OF 110
SHEET
22 OF 92
IBEX-PEAK-DESKTOP
A14
A30
A35
A7
AA19
AA20
AA22
AA38
AA39
AA4
AA41
AB18
AB19
AB20
AB22
AB23
AB27
AB29
AB30
AB33
AB34
AB40
AB5
AB8
AC37
AC5
AD11
AD19
AD2
AD22
AD24
AD29
AD30
AD31
AD34
AD39
AD40
AD6
AD8
AE3
AE39
AE4
AF11
AF12
AF18
AF26
AF29
AF3
AF31
AF32
AF33
AF36
AF37
AF39
AF5
AH15
AH19
AH24
AH26
AH27
AH29
AH32
AH34
AH36
AH41
AH9
AJ20
OMIT
U1800
FCBGA
(8 OF 10)
VSS
VSS
IBEX-PEAK-DESKTOP
AJ24
AJ26
AJ28
AK10
AK22
AK3
AK32
AK34
AK37
AK5
AK8
AK9
AL8
AM10
AM12
AM14
AM18
AM28
AM32
AN12
AN14
AN18
AN22
AN28
AN30
AN37
AN5
AP20
AP24
AR1
AR11
AR18
AR28
AR30
AT14
AT18
AT22
AU12
AU16
AU19
AU20
AU22
AU23
AU29
AU30
AU33
AU37
AU38
AU41
AU5
AU9
AV24
AV28
AV5
AW17
AW18
AW24
AW28
AW3
B10
B22
BA14
BA21
BA28
BA37
BA7
C10
C11
C17
C18
C23
C31
C32
C39
D22
D34
D37
D39
E12
E13
E15
E16
E19
E22
E23
E30
E33
E37
E4
E5
E6
E8
E9
F11
F12
F14
F16
F18
F20
F24
F30
F34
F5
G1
G34
G38
G39
G41
H31
H5
H7
H9
J14
J16
J18
J24
J37
J39
J5
J6
J7
K16
K2
K20
K22
K3
K32
K39
K40
L11
L12
L16
L20
OMIT
U1800
FCBGA
(9 OF 10)
VSS
VSS
L22
L3
L30
L31
L32
L34
L8
M11
M12
M14
M33
M37
M5
M8
N14
N37
N5
P1
P11
P20
P22
P23
P31
P34
P4
P8
R4
R5
T11
T16
T18
T3
T35
T5
T8
U16
U18
U2
U24
U27
U3
U39
V12
V13
V16
V18
V19
V22
V27
V3
V33
V35
V39
V6
V9
W3
W37
W39
W5
Y10
Y13
Y27
Y30
Y33
Y40
Y5
PAGE TITLE
PCH GROUNDS
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
23 OF 110
SHEET
23 OF 92
19 18 6
6
=PP3V3_S5_PCH
=PP5V_S5_PCH
PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)
1 mA S0-S5
R2400
NC
C2400
20%
10V
CERM
402
1UF
10%
6.3V
CERM
402
1
22 89
VOLTAGE=5V
<1 MA S0-S5
C2421
0.1UF
PLACEMENT_NOTE:
R2401
D2400
100
NC
BAT54DW-X-G
NC
5%
1/16W
MF-LF
402
SOT-363
357 MA S0 /
88 MA S3-S5
PP5V_S0_PCH_V5REF
C2401
22 89
VOLTAGE=5V
<1 MA
(VCCSUS3_3 Total)
1 mA
10%
10V
X5R
402
C2425
PLACEMENT_NOTE:
0.1UF
PLACE C2445 NEAR BALL AJ18
10%
16V
X5R
402
C2445
22 6
10%
6.3V
CERM
402
<1 MA
C2450
20%
6.3V
X5R
603
4.7UF
C2426
0.1UF
0.1UF
10%
16V
X5R
402
PLACEMENT_NOTEs:
C2427
C2476
1UF
2
C2451
C2452
0.1UF
10%
16V
X5R
402
0.1UF
10%
16V
X5R
402
3.251 A S0 /
369 MA IDLE
10%
6.3V
CERM
402
C2480
PCH VCCIO BYPASS

(PCH USB 1.05V PWR)
PLACEMENT_NOTEs (all 3):

PLACE C2450 NEAR BALL B39
C2488
4.7UF
PLACE C2426 NEAR BALL AW39

PCH VCCIO BYPASS

(PCH DMI 1.05V PWR)
PCH VCCME3_3 BYPASS

(PCH ME 3.3V PWR)
GPIO27: 1 = enabled, 0 = disabled

PCH_VRM
6
R2410
=PP1V8R1V5_S0_PCH_VCCVRM
196 MA
MLB_VR
6
5%
1/16W
MF-LF
402
R2411
=PP1V05_S0_PCH
VOLTAGE=1.5V
MAKE_BASE=TRUE
(OR
5%
1/16W
MF-LF
402
MLB_VR
196 MA
PLACEMENT_NOTE:
10UF
20%
6.3V
X5R
603
C2435
10%
16V
X5R
402
PLACEMENT_NOTE:
10%
16V
220-OHM-1.4A
C2437
10%
16V
X5R
402
0.1UF
10%
C2465
22UF
C2438
20%
6.3V
CERM
805
0.1UF
10%
2 16V
X5R
2 16V
X5R
402
402
C2466
20%
6.3V
CERM
805
10UF
20%
6.3V
X5R
603
C2415
PLACE
PLACE
PLACE
PLACE
PLACE
PCH VCC3_3 BYPASS

(PCH SATA 3.3V PWR)
1UF
10%
6.3V
CERM
402
PLACEMENT_NOTEs:
22 6
1
Place C2414 within 2.54mm of ball

PLACE C2415 AT BALL A37
L2416
220-OHM-1.4A
1
PP1V05_S0_PCH_VCCAPLL_SATA
MLB_VR
MLB_VR
C2416
5%
1/16W
MF-LF
402
89
10UF
20%
6.3V
X5R
603
10%
6.3V
CERM
402
C2468
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
PLACE
PLACE
PLACE
PLACE
PLACE
C2469
1UF
10%
6.3V
CERM
402
C2465
C2491
C2492
C2493
C2465
NEAR
NEAR
NEAR
NEAR
NEAR
BALL
BALL
BALL
BALL
BALL
P18
P18
P15
U15
P24
C2465
C2466
C2467
C2468
C2469
NEAR
NEAR
NEAR
NEAR
NEAR
BALL
BALL
BALL
BALL
BALL
AB15
AH4
AH1
AJ4
AF10
C2446
10%
16V
X5R
402
PLACEMENT_NOTEs:
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
22 6
PCH VCCACLK Filter

(PCH Misc PLL PWR)
L2418
220-OHM-1.4A
1.629 A
C2470
22 89
PLACEMENT_NOTEs:
MLB_VR
1
10UF
C2419
20%
6.3V
X5R
603
C2471
1UF
10%
6.3V
CERM
402
C2472
4.7UF
20%
6.3V
X5R
603
C2473
22UF
PAGE TITLE
PLACEMENT_NOTEs:
805
DRAWING NUMBER
Apple Inc.

Pre-Silicon Mobile Estimates.
051-8600
SIZE
REVISION
A.0.0
Place C2418 within 2.54mm of balls

PLACE C2419 AT BALL AA1
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3).
PCH DECOUPLING
20%
2 6.3V
CERM
PLACE C2470 NEAR BALL AE18

1UF
10%
6.3V
CERM
402
10UF
VOLTAGE=1.05V
2
0603
C2494
1UF
1UF
MLB_VR
20%
6.3V
X5R
603
C2493
C2417
PP1V05_S0_PCH_VCCA_CLK_F
C2418
10%
6.3V
CERM
402
PLACE C2446 NEAR BALL U40
Place C2416 within 2.54mm of balls

PLACE C2417 AT BALL P41
C2492
1UF
10%
6.3V
CERM
402

1
10UF
20%
6.3V
X5R
603
1UF
22 89
VOLTAGE=1.05V
C2491
VOLTAGE=1.05V
0603
R2418 1
10%
6.3V
CERM
402
1UF
0.1UF
PLACEMENT_NOTE:
PCH VCCSATAPLL Filter

(PCH SATA PLL PWR)
MLB_VR
PLACEMENT_NOTEs:
MLB_VR
C2414
C2467
22UF
PLACE C2436 NEAR BALL AV2

PLACE C2437 NEAR BALL AH16
VOLTAGE=1.05V
2
0603
0.1UF
22 89
2.22 A
22 6
PLACEMENT_NOTE:
PP1V05_S0_PCH_VCCAPLL_FDI
20%
6.3V
CERM
805
NOSTUFF
PCH VCCFDIPLL Filter

(PCH FDI PLL PWR)
MLB_VR
L2414
22UF
PCH VCCME BYPASS

(PCH 1.05V ME Core PWR)
C2436
C2485
22 19 18 6
C2490
402
PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)
22 6
PCH VCCIO BYPASS

(PCH PCIE 1.05V PWR)
5%
1/16W
MF-LF
2 402
0.1UF

PLACE C2439 NEAR BALL A9
PLACEMENT_NOTEs:
R2460
2 X5R
1UF
10%
6.3V
CERM
402
PLACE C2485 NEAR BALL Y26

PLACE C2465 NEAR BALL Y29
C2439
20%
6.3V
CERM
805
PLACEMENT_NOTE:
1K
0.1UF
C2413
C2486
372 MA
22 18 6
22UF
22 6
PLACE C2455 NEAR BALL A23
PLACEMENT_NOTE:
Place C2412 within 2.54mm of ball

PLACE C2413 AT BALL A21
10%
16V
X5R
402
PCH VCCLAN BYPASS

(PCH 1.05V LAN Core PWR)
22 89
MLB_VR
C2412
PCH CORE/VCC3_3 BYPASS

(PCH MISC 3.3V PWR)
22 6
PP1V05_S0_PCH_VCCAPLL_EXP
PLACEMENT_NOTE:
PLACE C2430 NEAR BALL N38
VOLTAGE=1.05V
2
0603
C2430
10%
6.3V
CERM
402
0.1UF
1.5V)
NOTE: VccVRM input also supports

1.5V, but draws more current.
HDA_SYNC: 0 = 1.8V, 1 = 1.5V
220-OHM-1.4A
L2412 - 155S0441
10%
6.3V
CERM
402
PCH VCCIO BYPASS

(PCH SATA 1.05V PWR)
C2455
22 89
PCH VCCAPLLEXP Filter

(PCH PCIe PLL PWR)
L2412
65 MA
1UF
1UF

22 6
20%
6.3V
X5R
603
PLACEMENT_NOTE:
22 6
C2477
1UF
10%
6.3V
CERM
402
PLACE C2475 NEAR BALL D25

PLACE C2476 NEAR BALL H26
22 6
10%
16V
X5R
402
10%
6.3V
CERM
402
PLACEMENT_NOTEs:
C2475
1UF
PCH V_CPU_IO BYPASS

(PCH 1.1V/1.05V CPU I/O PWR)
22 6
1UF
PCH USB/VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)
PLACE C2401 NEAR BALL AN1
402
PCH VCCIO BYPASS

(PCH CLK 1.05V PWR)
1
PLACE C2425 NEAR BALL AV25
PLACEMENT_NOTE:
10%
6 MA
1UF
0.1UF
2 16V
X5R
22 6
PLACEMENT_NOTE:
24 22 6
C2441
PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)
PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)
10%
16V
X5R
402
PLACE C2440 NEAR BALL P30

PLACE C2441 NEAR BALL P30
(PCH SUSPEND USB 3.3V PWR)

24 22 6
=PP3V3_S0_PCH
=PP5V_S0_PCH
PLACEMENT_NOTE:
10%
16V
X5R
402
PCH VCCSUS3_3 BYPASS
PLACE C2400 NEAR BALL AW16
C2422
0.1UF
10%
16V
X5R
402
0.1UF

PLACE C2421 NEAR BALL AY29
PLACE C2420 NEAR BALL AY29
0.1UF
NOSTUFF
C2440
C2420
BAT54DW-X-G
SOT-363
22 6
2 mA S0-S5 /
6 uA G3
D2400
2
NC
5%
1/16W
MF-LF
402
21 18 6
68
3
PCH VCCPNAND BYPASS
(PCH NAND 1.8V/3.3V PWR)
PP3V3_G3_RTC
89 27 22 18
10
PCH VCCRTC BYPASS

(PCH RTC 3.3V PWR)
(VCCIO TOTAL)
BRANCH
PAGE
24 OF 110
SHEET
24 OF 92
PROCESSOR XDP
6
=PPVTT_S0_XDP
XDP_CPU_BPM
CRITICAL
XDP_CONN
RP2500
84 11
IN
84 11
IN
84 11
IN
84 11
IN
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
1
2
0
5%
1/16W
SM-LF
3
4
BSH-030-01-L-D-A-TR
F-ST-SM
5
11
XDP_CPU_CFG
11
RP2501
84 10
IN
84 10
IN
84 10
84 10
IN
IN
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
1
2
0
5%
1/16W
SM-LF
3
4
XDP_PREQ_L
XDP_PRDY_L
BI
IN
84
84
OBSFN_A0
OBSFN_A1
XDP_OBSDATA_A<0>
XDP_OBSDATA_A<1>
OBSDATA_A0
OBSDATA_A1
6
5
84
84
XDP_OBSDATA_A<2>
XDP_OBSDATA_A<3>
OBSDATA_A2
OBSDATA_A3
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.

84 10
IN
84 10
IN
84 11
IN
84 11
XDP
R2510
91 21 11
IN
XDP
1
J2500
CPU_PWRGD
1K
CPU_CFG<17>
CPU_CFG<16>
XDP_BPM_L<4>
XDP_BPM_L<5>
IN
84 11
IN
84 11
IN
2
91 45 25 19
91 11
IN
IN
48 25
BI
48 25
BI
11
OBSDATA_B0
OBSDATA_B1
XDP_BPM_L<6>
XDP_BPM_L<7>
91
5%
1/16W
MF-LF
402
OBSFN_B0
OBSFN_B1
OUT
OBSDATA_B2
OBSDATA_B3
XDP_PWRGD
PM_PWRBTN_L
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
XDP_CPUPWRGD
TP_XDP_HOOK3
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
TCK1
TCK0
XDP_TCK
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
51
PLACE IT NEAR THE XDP
OBSFN_C0
OBSFN_C1
CPU_CFG<8>
CPU_CFG<9>
IN
10 84
IN
10 84
OBSDATA_C0
OBSDATA_C1
CPU_CFG<0>
CPU_CFG<1>
IN
10 84
OBSDATA_C2
OBSDATA_C3
IN
10 84
CPU_CFG<2>
CPU_CFG<3>
IN
10 84
IN
10 15 84
OBSFN_D0
OBSFN_D1
CPU_CFG<10>
CPU_CFG<11>
IN
10 84
IN
10 84
OBSDATA_D0
OBSDATA_D1
CPU_CFG<4>
CPU_CFG<5>
IN
10 84
IN
10 84
OBSDATA_D2
OBSDATA_D3
CPU_CFG<6>
CPU_CFG<7>
IN
10 84
IN
10 84
IN
11 84
IN
11 84
XDP
R2511
1K
OUT
IN
11
OUT
11
OUT
11
OUT
11
FSB_CPURSTOUT_L
5%
1/16W
MF-LF
402
11 25 27 91
IN
11 91
PLACEMENT_NOTE=Place close to CPU to minimize stub.
XDP
1
516S0450
0.1uF
10%
16V
X5R
402
5%
1/16W
MF-LF
402
FSB_CLK133M_ITP_P
ITPCLK/HOOK4
FSB_CLK133M_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP_PRESENT#
XDP
C2500
R2515
C2501
0.1uF
10%
16V
X5R
402
PCH XDP
6
=PP3V3_S0_XDP
6
=PP3V3_S5_XDP
CRITICAL
XDP_CONN
R2555
200
5%
1/16W
MF-LF
BSH-030-01-L-D-A-TR
F-ST-SM
TP_XDPPCH_OBSFN_A<0>
TP_XDPPCH_OBSFN_A<1>
OBSFN_A0
OBSFN_A1
XDP
R2580
34 20
20
IN
IN
USB_HUB_SOFT_RESET_L
1
5%
MF-LF
R2581
PCH_GPIO41_OC2_L
1
5%
MF-LF
XDP
20
IN
2
1/16W
402
2
1/16W
402
20
IN
20
IN
20
IN
PCH_GPIO43_OC4_L
PCH_GPIO9_OC5_L
1
5%
MF-LF
2
1/16W
402
PCH_GPIO43_OC4_L_R
PCH_GPIO9_OC5_L_R
R2583
1
5%
MF-LF
XDP
PCH_GPIO41_OC2_L_R
PCH_GPIO42_OC3_L
TP_XDPPCH_OBSFN_B<0>
TP_XDPPCH_OBSFN_B<1>
XDP
R2582
0
PCH_GPIO59_OC0_L
USB_HUB_SOFT_RESET_L_R
2
1/16W
402
20
IN
20 15
IN
91 63 32 6
IN
91 45 25 19
PCH_GPIO10_OC6_L
PCH_GPIO14_OC7_L
ALL_SYS_PWRGD_R
PM_PWRBTN_L
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
48 25
48 25
18
OUT
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
JTAG_PCH_TCK
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
XDP
J2550
XDP
2 402
R2575
0
OBSFN_C0
OBSFN_C1
ISOLATE_CPU_MEM_L_R
PCH_GPIO0_BMBUSY_L
OBSDATA_C0
OBSDATA_C1
FW_CLKREQ_L_R
MINI_CLKREQ_L_R
OBSDATA_C2
OBSDATA_C3
PCH_GPIO21_SATA0GP
PCH_GPIO19_SATA1GP
OBSFN_D0
OBSFN_D1
TP_XDPPCH_OBSFN_D<0>
TP_XDPPCH_OBSFN_D<1>
OBSDATA_D0
OBSDATA_D1
SDCARD_RESET_R
PCH_GPIO37_SATA3GP
IN
15 21
OBSDATA_D2
OBSDATA_D3
AUD_IPHS_SWITCH_EN_R
PCH_GPIO49_SATA5GP
IN
15 21
IN
27
1
5%
MF-LF
IN
2
1/16W
402
15 21
ISOLATE_CPU_MEM_L
1
5%
MF-LF
FW_CLKREQ_L
2
1/16W
402
R2577
IN
15 18
IN
15 18
IN
21 32
IN
15 18 40
IN
15 18 33
XDP
R2576
1
5%
MF-LF
XDP
2
1/16W
MINI_CLKREQ_L
402
XDP
R2578
1
5%
MF-LF
2
1/16W
402
SDCARD_RESET
IN
21 44 91 92
AUD_IPHS_SWITCH_EN
IN
21 61
R2579
1
5%
MF-LF
TP_XDPPCH_HOOK4
ITPCLK/HOOK4
TP_XDPPCH_HOOK5
ITPCLK#/HOOK5
VCC_OBS_CD
XDPPCH_PLTRST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
JTAG_PCH_TDO
TDO
TP_JTAG_XDP_TRST_L
TRSTn
JTAG_PCH_TDI
TDI
JTAG_PCH_TMS
TMS
XDP_PRESENT#
XDP
2
1/16W
402
1K series R on PCH Support Page
11 25 27 91
IN
18
OUT
18
OUT
18
PAGE TITLE
516S0450
1
EXTENDED DEBUG PORT(XDP)
XDP
R2556
100
DRAWING NUMBER
5%
1/16W
MF-LF
402
Apple Inc.
SIZE
A.0.0
051-8600
REVISION
BRANCH
PAGE
25 OF 110
SHEET
25 OF 92
D
BUF_CLK
BUF_CLK
L2600
=PP1V05_S0_CK505
89
R2650
FERR-120-OHM-1.5A
PP1V05_S0_CK505_F
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.05V
0402
BUF_CLK
L2650
FERR-120-OHM-1.5A
6
BUF_CLK
BUF_CLK
C2600
20%
6.3V
X5R
603
10UF
BUF_CLK
C2602
10%
16V
X5R
402
0.1UF
BUF_CLK
C2603
10%
16V
X5R
402
0.1UF
=PP1V5_S0_CK505
C2604
10%
16V
X5R
402
0.1UF
2
0402
BUF_CLK
C2605
89
PP1V5_S0_CK505_F
2.2
VOLTAGE=1.5V
5%
1/16W
MF-LF
402
0.1UF
10%
16V
X5R
402
89
BUF_CLK
C2650
PP1V5_S0_CK505_R
BUF_CLK
20%
6.3V
X5R
603
BUF_CLK
PLACE IT CLOSE TO POWER PINS
10UF
C2651
0.1UF
0.1UF
PLACE IT CLOSE TO L2650
10%
16V
X5R
402
C2652
10%
16V
X5R
402
BUF_CLK
L2610
FERR-120-OHM-1.5A
6
=PP3V3_S0_CK505
89
PP3V3_S0_CK505_F
VOLTAGE=3.3V
0402
BUF_CLK
C2610
BUF_CLK
1
10UF
20%
6.3V
X5R
603
BUF_CLK
C2615
0.1UF
2
C2616
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402

18pF
2
5%
50V
CERM
402
NO STUFF
1
R2616
10M
5%
1/16W
MF-LF
2 402
1
5%
25
31
16
4
22
PLACE R2699 NEAR PIN 26

BUF_CLK
CRITICAL
U2600
BUF_CLK
R2615
0
VDD_CORE
C2621
VDD_REF
BUF_CLK
1
VDD_96_IO
BUF_CLK
18pF
VDD_27
VDD_SATA_IO
5%
50V
CERM
402
5X3.2-SM
VDD_SRC_IO
14.31818
VDD_CPU_IO
C2620
17
Y2620
CK505_XTAL_OUT_R
BUF_CLK
CRITICAL
CK505_XTAL_IN
85 CK505_XTAL_OUT
85
2
1/16W
48
91 64 63 5
R2699
SLG2AP108
QFN
X1
X2
REF 26
OMIT
=SMBUS_CK505_SCL
SCL
CPU* 18
CPU 19
BI
=SMBUS_CK505_SDA
SDA
SRC_2* 11
IN
PM_PGOOD_PVCORE_CPU
CKPWRGD/PD*
MF-LF 402
48
24
23
IN
91
CK505_27MHZ_EN
32
SRC_2 10
SATA* 15
27MHZ_EN
SATA 14
27MHZ 29
BUF_CLK
27MHZ_SS 30
R2600
DOT_96* 7
DOT_96 6
5% 1
1/16W
33
FSB_CLK133M_PCH_N
FSB_CLK133M_PCH_P
OUT
18 84
OUT
18 84
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
OUT
18 84
OUT
18 84
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
OUT
18 84
OUT
18 84
OUT
18 84
OUT
18 84
2 402
MF-LF
PCH_CLK14P3M_REFCLK
OUT
18 85
PCH BCLK 133MHZ

PCH DMI/PCIe 100MHz
PCH SATA 100MHZ
CK505_CLK27M
TP_CK505_CLK27M_SS
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
THRM
PAD
33
VSS_CORE
21
VSS_REF
27
VSS_96
VSS_27
28
VSS_SATA
13
VSS_CPU
20
5%
1/16W
MF-LF
2 402
12
10K
VSS_SRC
PCH_CLK14P3M_REFCLK_R
PCH USB Clock 96MHz
BUF_CLK
R2690
10K
5%
1/16W
MF-LF
2 402
PAGE TITLE
CLOCK (CK505)
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
26 OF 110
SHEET
26 OF 92
Platform Reset Connections
RTC Power Sources
Unbuffered
D2800
BAT54DW-X-G
Coin-Cell Holder
89
PP3V3_G3_RTC
PPVBATT_G3_RTC
1K
5%
1/16W
MF-LF
402
18 22 24 89
R2881
VOLTAGE=3.3V
R2800
VOLTAGE=3.3V
SOT-363
=PP3V3_S5_RTC_D
91 20
89
PPVBATT_G3_RTC_R
VOLTAGE=3.3V
NC
NC 2
NC
IN
PLT_RESET_L
5%
1/16W
MF-LF
402
J2800
511-0054
33
33
NOTE: R2800 and D2800 form the doublefault protection for RTC battery.
OUT
47 91
SMC_LRESET_L
OUT
45 91
LAN_RESET_L
OUT
36 91
FW_RESET_L
OUT
39 91
MINI_RESET_L
OUT
33 91
OUT
25
5%
1/16W
MF-LF
402
R2882
SM
DEBUG_RESET_L
R2883
NC
BB10201-C1403-7H
33
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
R2892
33
PCH RTC Crystal

12pF
5%
1/16W
MF-LF
402
R2811
10M
CRITICAL
Y2810
5%
1/16W
MF-LF
402 2
85 18
SM-2
32.768K
NC
NC
R2895
1
27 6
=PP3V3_S0_RSTBUF
FCIM
PCH_CLK25M_XTALOUT_R
5%
1/16W
MF-LF
402
FCIM
R28161
10M
CRITICAL
FCIM
Y2815
5%
1/16W
MF-LF
402 2
85 18
25.0000M
SM-3.2X2.5MM
NC
NC
20%
10V
CERM
402
5%
1/16W
MF-LF
2 402
44 91
33
C
PEG_RESET_L
9 91
OUT
5%
1/16W
MF-LF
402
R2880
100K
0.1UF
OUT
R2890
SOT23-5-HF
4
PLT_RST_BUF1_L
C2880
SDCARD_PLT_RST_L
MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
OMIT
C2816
12pF
PCH_CLK25M_XTALIN
OUT
2
5%
50V
CERM
402
MC74VHC1G08
U2880
12pF
PCH_CLK25M_XTALOUT
IN
C2815
85 18
33
5%
1/16W
MF-LF
402
Buffered
PCH 25MHz Crystal

0
XDPPCH_PLTRST_L
5%
1/16W
MF-LF
402
12pF
FCIM
1K
C2811
1
R2815
R2888 not necessary with WLAN

RESET circuit (see R4785)
R2889
1
5%
50V
CERM
402
XDP
2
5%
50V
CERM
402
PCH_CLK32K_RTCX1
OUT
33
5%
1/16W
MF-LF
402
C2810
PCH_CLK32K_RTCX2_R
PCH_CLK32K_RTCX2
IN
R2888
1
R2810
85 18
5%
1/16W
MF-LF
402
2
5%
50V
CERM
402
27 6
=PP3V3_S0_RSTBUF
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
MC74VHC1G08
TABLE_5_ITEM
116S0004
RES,0,5%,0402
C2816
2
U2890
3
C2890
R2893
B
6
R2891
1
33
CPU_RESET_L
5%
1/16WVTT
MF-LF
402
OUT
11 91
voltage divider on CPU page
100K
0.1UF
20%
10V
CERM
402
SOT23-5-HF
4
PLT_RST_BUF2_L
5%
1/16W
MF-LF
2 402
Reset Button
=PP3V3_S0_PCH_PM
1
R2897
4.7K
5%
1/16W
MF-LF
402
R2825
85 20
IN
PLACEMENT_NOTE=Place close to U1800
LPC_CLK33M_SMC_R
R2896
IN
XDP_DBRESET_L
5%
1/16W
MF-LF
402
PM_SYSRST_L
DEVELOPMENT
85 20
OUT
19 45 91
IN
SW2800
SM
85 20
IN
PCH_CLK33M_PCIOUT
33
LPC_CLK33M_SMC
OUT
45 85
LPC_CLK33M_LPCPLUS
OUT
47 85
PCH_CLK33M_PCIIN
OUT
18 85
R2826
1
33
5%
1/16W
MF-LF
402
R2827
NTC020-CC1J-B260T
1
33
5%
1/16W
MF-LF
402
XDP
91 25 11
5%
1/16W
MF-LF
402
PAGE TITLE
SILK_PART=SYS RESET
CHIPSET SUPPORT
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
28 OF 110
SHEET
27 OF 92
6
30 29 28 6
28 6
=PP1V5_S3_MEM_A
=PP3V3_S3_VREFMRGN
VREFMRGN
R2909
28 6
5%
1/16W
MF-LF
402
VREFMRGN
R2901
48
=I2C_VREFMRGN_A_SDA
BI
C2900
12.1K2
1
ISL90728WIE627ZTK
SC-70
VREFMRGN
I2C_VREFMARGIN_DIMMA_SCL
3 SCL
RH 6
I2C_VREFMARGIN_DIMMA_SDA
4 SDA
RW 5
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
U2901
10%
16V
2 X5R
402
VREFMRGN
LM321
SOT23-5
R2904
1
353S1961
VREFMARGIN_DIMMA_DACOUT
VREFMRGN
R2905
VREFMRGN
2.2
12.1K
=PP1V5_S3_MEM_B
OUT
28 83
VREFMRGN
C2902
1UF
1%
1/16W
MF-LF
2 402
VREFMARGIN_DIMMA_OPFB
1%
1/16W
MF-LF
2 402
VREFMARGIN_DIMMA_DQ
5%
1/16W
MF-LF
402
100
R2903
I2C ADDR = 0X7C (WRITE)

I2C ADDR = 0X7D (READ)
31 29 28 6
C2901
GND
353S2370
VREFMRGN
0.1UF
VREFMRGN
R2902
VDD
U2900
VREFMRGN
=I2C_VREFMRGN_A_SCL
IN
VREFMARGIN_DIMMA_P5V
1%
1/16W
MF-LF
402
VREFMRGN
10%
16V
2 X5R
402
R2900
48
10
0.1UF
VREFMRGN
=PP5V_S3_VREFMRGN
10%
6.3V
2 CERM
402
VREFMRGN
R2919
28 6
28 6
=PP5V_S3_VREFMRGN
=PP3V3_S3_VREFMRGN
R2910
=I2C_VREFMRGN_B_SCL
IN
I2C_VREFMARGIN_DIMMB_SCL 3 SCL
R2911
48
BI
=I2C_VREFMRGN_B_SDA
12.1K2
1%
1/16W
MF-LF
402
I2C_VREFMARGIN_DIMMB_SDA 4
RH 6
RW 5
SDA
ISL90727WIE627ZTK
SC-70
VREFMRGN
VREFMRGN
R2912
1
VDD
U2910
5%
1/16W
MF-LF
402
10%
16V
2 X5R
402
VREFMRGN
U2911
VREFMRGN
LM321
SOT23-5
R2914
353S1961
VREFMRGN
VREFMARGIN_DIMMB_DACOUT
R2915
353S2369
R2913
I2C ADDR = 0X5C (WRITE)

I2C ADDR = 0X5D (READ)
5%
1/16W
MF-LF
402
12.1K
VREFMARGIN_DIMMB_OPFB
1%
1/16W
MF-LF
2 402
VREFMARGIN_DIMMB_DQ
OUT
28 83
VREFMRGN
1
C2912
1UF
10%
6.3V
2 CERM
402
1%
1/16W
MF-LF
2 402
VREFMRGN
5%
1/16W
MF-LF
402
2.2
100
GND
2
48
C2911
0.1UF
VREFMRGN
10%
16V
2 X5R
402
VREFMRGN
VREFMRGN
C2910
0.1UF
VREFMARGIN_DIMMB_P5V
1%
1/16W
MF-LF
402
VREFMRGN
1
10
=PP1V5_S3_MEM_A
30 29 28 6
30 29 28 6
R2970
=PP1V5_S3_MEM_A
1K
1%
1/16W
MF-LF
2 402
VREFMRGN
R2958
NOSTUFF
R2993
0
83 28
PP0V75_S3_MEM_VREFDQ_A
R2971
1K
INT_VREF
83
CPU_DIMM_VREF_A_SW
Q2993
SOT23-HF1
1%
1/16W
MF-LF
2 402
NOSTUFF
R2995
NOSTUFF
1
C2950
83 28
VREFMARGIN_DIMMA_DQ
PP0V75_S3_MEM_VREFCA_A
5%
1/16W
MF-LF
402
10%
2 16V
X5R
402
R2989
1K
1%
1/16W
MF-LF
2 402
PLACE IT CLOSE TO DIMM CONNECTOR PIN
5%
1/16W
MF-LF
402
2N7002
30 89
0.1UF
1%
1/16W
MF-LF
2 402
R2950
INT_VREF
2
CPU_DIMM_VREF_A
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
83 12
VREFMARGIN_DIMMA_DQ
R2988
30 89
NOSTUFF
1
C2921
0.1UF
10%
16V
2 X5R
402
ISOLATE_CPU_MEM_5V_L
28 32
=PP1V5_S3_MEM_B
31 29 28 6
R2975
30 29 28 6
=PP1V5_S3_MEM_A
1K
1%
1/16W
MF-LF
2 402
VREFMRGN
R2956
83 28
NOSTUFF
VREFMARGIN_DIMMB_DQ
R2991
1
CPU_DIMM_VREF_B
R2976
1K
INT_VREF
R2953
INT_VREF
2
3
S
G
83
CPU_DIMM_VREF_B_SW
Q2991
R2978
1K
PP0V75_S3_MEM_VREFDQ_B
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
83 12
1%
1/16W
MF-LF
2 402
R2996
NOSTUFF
1
1%
1/16W
MF-LF
2 402
NOSTUFF
31 89
C2951
83 28
VREFMARGIN_DIMMB_DQ
0.1UF
10%
2 16V
X5R
402
R2979
1K
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
2N7002
SOT23-HF1
PP0V75_S3_MEM_VREFCA_B
5%
1/16W
MF-LF
402
PAGE TITLE
NOSTUFF
1
DDR3 VREF MARGINING

DRAWING NUMBER
C2991
0.1UF
Apple Inc.
10%
2 16V
X5R
402

28 32
051-8600
SIZE
REVISION
A.0.0
31 89
BRANCH
PAGE
29 OF 110
SHEET
28 OF 92
DIMM A (FURTHER FROM CPU)

29 16 13 6
CAPS TO COUPLE CPU 1V5_MEM
DIMM B (CLOSER TO CPU)
=PP1V5_CPU_MEM
1
C3016
1UF
C3017
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C3018
1UF
C3019
1UF
10%
2 6.3V
CERM
402
C3010
1UF
10%
2 6.3V
CERM
402
C3025
1UF
10%
2 6.3V
CERM
402
C3026
1UF
10%
2 6.3V
CERM
402
C3027
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C3028
1UF
C3029
1UF
10%
2 6.3V
CERM
402
C3020
1UF
10%
2 6.3V
CERM
402
C3021
1UF
10%
2 6.3V
CERM
402
C3022
1UF
10%
2 6.3V
CERM
402
C3023
1UF
10%
2 6.3V
CERM
402
C3014
1UF
10%
2 6.3V
CERM
402
C3030
1UF
10%
2 6.3V
CERM
402
C3031
1UF
10%
2 6.3V
CERM
402
C3032
1UF
10%
2 6.3V
CERM
402
C3033
1UF
10%
2 6.3V
CERM
402
10%
6.3V
2 CERM
402
D
EXTRA DECOUPLING CAPS FOR CPU MEM RAIL
29 16 13 6
=PP1V5_CPU_MEM
C3041
1UF
1UF
10%
2 6.3V
CERM
402
29 16 13 6
C3042
10%
2 6.3V
CERM
402
C3044
1UF
C3046
10%
2 6.3V
CERM
402
C3040
1UF
1UF
10%
2 6.3V
CERM
402
C3043
1UF
10%
6.3V
2 CERM
402
C3045
1UF
10%
6.3V
2 CERM
402
C3047
1UF
10%
6.3V
2 CERM
402
C3048
1UF
10%
6.3V
2 CERM
402
C3049
1UF
10%
6.3V
2 CERM
402
C3090
1UF
10%
6.3V
2 CERM
402
C3091
1UF
10%
6.3V
2 CERM
402
C3092
1UF
10%
6.3V
2 CERM
402
C3093
1UF
10%
6.3V
2 CERM
402
C3094
1UF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
=PP1V5_CPU_MEM
1
C30A0
1UF
10%
6.3V
2 CERM
402
C30A1
1UF
10%
6.3V
2 CERM
402
C30A2
1UF
10%
6.3V
2 CERM
402
C30A3
1UF
C30A4
1UF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
C30A5
1UF
C30A6
1UF
10%
6.3V
2 CERM
402
C30A7
1UF
10%
6.3V
2 CERM
402
C30A8
1UF
10%
6.3V
2 CERM
402
C30A9
1UF
10%
6.3V
2 CERM
402
C30AA
1UF
10%
6.3V
2 CERM
402
C30AB
1UF
10%
6.3V
2 CERM
402
C30AC
1UF
10%
6.3V
2 CERM
402
C30AD
1UF
10%
6.3V
2 CERM
402
C30AE
1UF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR
30 28 6
=PP1V5_S3_MEM_A
B
1
C3050
10UF
2
20%
6.3V
X5R
603
C3051
10UF
20%
6.3V
X5R
603
C3052
1UF
10%
6.3V
2 CERM
402
C3053
1UF
10%
6.3V
2 CERM
402
C3054
1UF
10%
6.3V
2 CERM
402
C3055
1UF
10%
6.3V
2 CERM
402
C3056
1UF
10%
6.3V
2 CERM
402
C3057
1UF
10%
6.3V
2 CERM
402
C3058
1UF
10%
6.3V
2 CERM
402
C3059
1UF
10%
6.3V
2 CERM
402
C3060
1UF
10%
6.3V
2 CERM
402
C3061
1UF
10%
6.3V
2 CERM
402
C3062
1UF
10%
6.3V
2 CERM
402
C3063
1UF
10%
6.3V
2 CERM
402
C3064
1UF
10%
6.3V
2 CERM
402
C3065
1UF
C3066
1UF
10%
6.3V
2 CERM
402
C3067
1UF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
C3068
1UF
C3069
1UF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

31 28 6
=PP1V5_S3_MEM_B
C3070
10UF
2
20%
6.3V
X5R
603
C3071
10UF
20%
6.3V
X5R
603
C3072
1UF
10%
2 6.3V
CERM
402
C3073
1UF
10%
2 6.3V
CERM
402
C3074
1UF
10%
2 6.3V
CERM
402
C3075
1UF
10%
2 6.3V
CERM
402
C3076
1UF
10%
2 6.3V
CERM
402
C3077
1UF
10%
2 6.3V
CERM
402
C3078
1UF
10%
2 6.3V
CERM
402
C3079
1UF
10%
2 6.3V
CERM
402
C3080
1UF
10%
2 6.3V
CERM
402
C3081
1UF
10%
2 6.3V
CERM
402
C3082
1UF
10%
2 6.3V
CERM
402
C3083
1UF
10%
2 6.3V
CERM
402
C3084
1UF
10%
2 6.3V
CERM
402
C3085
1UF
10%
2 6.3V
CERM
402
C3086
1UF
10%
2 6.3V
CERM
402
C3087
1UF
10%
2 6.3V
CERM
402
C3088
1UF
10%
2 6.3V
CERM
402
C3089
1UF
10%
2 6.3V
CERM
402
PAGE TITLE
MEMORY CAPS
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
30 OF 110
SHEET
29 OF 92
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
83 12
30 29 28 6
83 30 12
83 30 12
83 30 12
83 30 12
83 30 12
83 30 12
83 30 12
32
32
83 30 12
83 30 12
83 30 12
83 30 12
83 30 12
83 12
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
30
46 30 6
30
30 6
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<27>
MEM_A_CKE<2>
=PP1V5_S3_MEM_A
MEM_A_BA<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
=MEM_A_CLK_P<2>
=MEM_A_CLK_N<2>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<3>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_DIMM2_SA<0>
=PPSPD_S0_MEM_A
MEM_DIMM2_SA<1>
73A
75A
77A
79A
81A
83A
85A
87A
89A
91A
93A
95A
97A
99A
101A
103A
105A
107A
109A
111A
113A
115A
117A
119A
121A
123A
125A
127A
129A
131A
133A
135A
137A
139A
141A
143A
145A
147A
149A
151A
153A
155A
157A
159A
161A
163A
165A
167A
169A
171A
173A
175A
177A
179A
181A
183A
185A
187A
189A
191A
193A
195A
197A
199A
201A
203A
409
VREFDQ
VSS_0
VSS_1CRITICAL DQ4
DQ0
DQ5
F-RT-TH
VSS_2
DQ1
(1 OF 2)
VSS_3
DQS0*
DM0
DQS0
VSS_5
VSS_4
DQ2
DQ6
DQ7
DQ3
VSS_6
VSS_7
DQ8
DQ12
DQ9
DQ13
VSS_8
VSS_9
DQS1*
DM1
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ11
DQ15
VSS_12
VSS_13
DQ16
DQ20
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
DQS2
VSS_16
VSS_17
DQ22
DQ18
DQ23
DQ19
VSS_18
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DM3
DQS3
VSS_22
VSS_23
DQ26
DQ30
DQ27
DQ31
VSS_24
VSS_25
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A9
A7
VDD_4
VDD_5
A8
A6
A5
A4
VDD_6
VDD_7
A3
A2
A1
A0
VDD_8
VDD_9
CK0
CK1
CK0*
CK1*
VDD_10
VDD_11
A10_AP
BA1
BA0
RAS*
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
A13
ODT1
S1*
NC_1
VDD_16
VDD_17
TEST
VREFCA
VSS_26
VSS_27
DQ32
DQ36
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
DQS4
VSS_30
VSS_31
DQ38
DQ34
DQ39
DQ35
VSS_32
VSS_33
DQ44
DQ40
DQ45
DQ41
VSS_34
VSS_35
DQS5*
DM5
DQS5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ48
DQ52
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
DQS6
VSS_42
VSS_43
DQ54
DQ50
DQ55
DQ51
VSS_44
VSS_45
DQ60
DQ56
DQ61
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ59
DQ63
VSS_51
VSS_50
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT_0
VTT_1
J3100
MTG PIN
MTG PIN
2A
4A
6A
8A
10A
12A
14A
16A
18A
20A
22A
24A
26A
28A
30A
32A
34A
36A
38A
40A
42A
44A
46A
48A
50A
52A
54A
56A
58A
60A
62A
64A
66A
68A
70A
72A
74A
76A
78A
80A
82A
84A
86A
88A
90A
92A
94A
96A
98A
100A
102A
104A
106A
108A
110A
112A
114A
116A
118A
120A
122A
124A
126A
128A
130A
132A
134A
136A
138A
140A
142A
144A
146A
148A
150A
152A
154A
156A
158A
160A
162A
164A
166A
168A
170A
172A
174A
176A
178A
180A
182A
184A
186A
188A
190A
192A
194A
196A
198A
200A
202A
204A
5
89 30 28
=MEM_A_DQ<4>
=MEM_A_DQ<5>
30 32
32 30
=MEM_A_DQ<0>
=MEM_A_DQ<1>
30 32
32 30
=MEM_A_DM<0>
30 32
32 30
30 32
32 30
30 32
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
32 30
30 32
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DM<1>
MEM_RESET_L
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQ<20>
=MEM_A_DQ<21>
=MEM_A_DM<2>
30 32
32 30
30 32
32 30
30 32
32 30
30 31 32 91
32 30
30 32
32 30
30 32
32 30
30 32
32 30
30 32
32 30
30 32
32 30
32 30
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
30 32
30 32
32 30
32 30
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
30 32
30 32
32 30
32 30
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
30 32
=MEM_A_DQ<30>
=MEM_A_DQ<31>
MEM_A_CKE<3>
=PP1V5_S3_MEM_A
MEM_A_A<15>
MEM_A_A<14>
30 32
32 30
30 32
32 30
30 32
32 30
12 83
83 12
6 28 29 30
30 29 28 6
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<27>
MEM_A_CKE<0>
=PP1V5_S3_MEM_A
12 30 83
12 30 83
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
=MEM_A_CLK_P<3>
=MEM_A_CLK_N<3>
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CS_L<2>
MEM_A_ODT<2>
MEM_A_ODT<3>
83 30 12
12 30 83
83 30 12
12 30 83
83 30 12
12 30 83
83 30 12
12 30 83
83 30 12
12 30 83
83 30 12
12 30 83
83 30 12
32
32
32
32
12 30 83
83 30 12
12 30 83
83 30 12
12 83
83 30 12
12 83
83 30 12
12 83
83 30 12
83 12
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DM<4>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
=MEM_A_CLK_P<0>
=MEM_A_CLK_N<0>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>
28 30 89
30 32
32 30
30 32
32 30
30 32
32 30
32 30
=MEM_A_DQ<38>
=MEM_A_DQ<39>
MEM_A_BA<2>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
30 32
30 32
32 30
32 30
=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
30 32
30 32
32 30
32 30
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
30 32
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<52>
=MEM_A_DQ<53>
=MEM_A_DM<6>
30 32
32 30
30 32
32 30
30 32
32 30
30 32
32 30
30 32
32 30
30 32
32 30
32 30
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
30 32
30 32
32 30
32 30
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
30 32
30 32
32 30
32 30
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
30 32
30 32
=MEM_A_DQ<62>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
32 30
30 32
32 30
30 32
32 30
30 31 46
30 48
30 48
6 30
30
46 30 6
30
30 6
=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_DIMM0_SA<0>
=PPSPD_S0_MEM_A
MEM_DIMM0_SA<1>
4
1B
3B
5B
7B
9B
11B
13B
15B
17B
19B
21B
23B
25B
27B
29B
31B
33B
35B
37B
39B
41B
43B
45B
47B
49B
51B
53B
55B
57B
59B
61B
63B
65B
67B
69B
71B
73B
75B
77B
79B
81B
83B
85B
87B
89B
91B
93B
95B
97B
99B
101B
103B
105B
107B
109B
111B
113B
115B
117B
119B
121B
123B
125B
127B
129B
131B
133B
135B
137B
139B
141B
143B
145B
147B
149B
151B
153B
155B
157B
159B
161B
163B
165B
167B
169B
171B
173B
175B
177B
179B
181B
183B
185B
187B
189B
191B
193B
195B
197B
199B
201B
203B
VREFDQ
VSS_0
VSS_1
DQ4
DQ0
DQ5
F-RT-TH
DQ1
VSS_2
(2 OF 2)
VSS_3
DQS0*
CRITICAL
DM0
DQS0
VSS_4
VSS_5
DQ2
DQ6
DQ3
DQ7
VSS_6
VSS_7
DQ8
DQ12
DQ9
DQ13
VSS_8
VSS_9
DQS1*
DM1
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ11
DQ15
VSS_12
VSS_13
DQ16
DQ20
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
DQS2
VSS_16
VSS_17
DQ22
DQ18
DQ23
DQ19
VSS_18
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DM3
DQS3
VSS_22
VSS_23
DQ26
DQ30
DQ27
DQ31
VSS_24
VSS_25
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A9
A7
VDD_4
VDD_5
A8
A6
A5
A4
VDD_6
VDD_7
A3
A2
A1
A0
VDD_8
VDD_9
CK0
CK1
CK0*
CK1*
VDD_10
VDD_11
A10_AP
BA1
BA0
RAS*
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
A13
ODT1
S1*
NC_1
VDD_16
VDD_17
TEST
VREFCA
VSS_26
VSS_27
DQ32
DQ36
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
DQS4
VSS_30
VSS_31
DQ38
DQ34
DQ39
DQ35
VSS_32
VSS_33
DQ44
DQ40
DQ45
DQ41
VSS_34
VSS_35
DQS5*
DM5
DQS5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ48
DQ52
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
DQS6
VSS_42
VSS_43
DQ54
DQ50
DQ55
DQ51
VSS_44
VSS_45
DQ60
DQ56
DQ61
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ59
DQ63
VSS_50
VSS_51
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT_0
VTT_1
J3100
DDR3-SODIMM-DUAL
=MEM_A_DM<0>
DDR3-SODIMM-DUAL
32 30
7
1A
3A
5A
7A
9A
11A
13A
15A
17A
19A
21A
23A
25A
27A
29A
31A
33A
35A
37A
39A
41A
43A
45A
47A
49A
51A
53A
55A
57A
59A
61A
63A
65A
67A
69A
71A
DIMM 2
32 30
=MEM_A_DQ<0>
=MEM_A_DQ<1>
32 30
DIMM 0
8
89 30 28
2B
4B
6B
8B
10B
12B
14B
16B
18B
20B
22B
24B
26B
28B
30B
32B
34B
36B
38B
40B
42B
44B
46B
48B
50B
52B
54B
56B
58B
60B
62B
64B
66B
68B
70B
72B
3
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
30 32
DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)
30
MEM_DIMM0_SA<1>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DM<1>
MEM_RESET_L
30
MEM_DIMM0_SA<0>
30 32
=PPSPD_S0_MEM_A
30 32
30 32
30 32
30 32
R3140
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
30
MEM_DIMM2_SA<0>
30
MEM_DIMM2_SA<1>
=MEM_A_DQ<20>
=MEM_A_DQ<21>
30 32
30 31 32 91
30 32
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
30 32
=PPSPD_S0_MEM_A
30 32
MEM_A_CKE<1>
=PP1V5_S3_MEM_A
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
=MEM_A_CLK_P<1>
=MEM_A_CLK_N<1>
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CS_L<0>
MEM_A_ODT<0>
C3140
2.2UF
30 32
20%
6.3V
CERM
402-LF
30 32
30 32
30 32
30 32
30 32
89 30 28
=MEM_A_DQ<30>
=MEM_A_DQ<31>
30 32
30 32
C3135
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DM<4>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<44>
=MEM_A_DQ<45>
C3136
2.2UF
12 83
6 28 29 30
0.1UF
20%
6.3V
CERM
402-LF
12 30 83
20%
10V
CERM
402
12 30 83
12 30 83
12 30 83
89 30 28
12 30 83
12 30 83
C3130
C3131
2.2UF
12 30 83
2
12 30 83
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
32
32
30 6
12 30 83
12 30 83
12 83
C3150
2.2UF
12 83
MEM_A_ODT<1>
5%
1/16W
MF-LF
402
30 32
=MEM_A_DQ<22>
=MEM_A_DQ<23>
R3143
10K
30 32
46 30 6
=MEM_A_DM<2>
5%
1/16W
MF-LF
402
30 32
=MEM_A_DQ<14>
=MEM_A_DQ<15>
R3142
10K
R3141
10K
74B
76B
78B
80B
82B
84B
86B
88B
90B
92B
94B
96B
98B
100B
102B
104B
106B
108B
110B
112B
114B
116B
118B
120B
122B
124B
126B
128B
130B
132B
134B
136B
138B
140B
142B
144B
146B
148B
150B
152B
154B
156B
158B
160B
162B
164B
166B
168B
170B
172B
174B
176B
178B
180B
182B
184B
186B
188B
190B
192B
194B
196B
198B
200B
202B
204B

46 30 6
=MEM_A_DQ<6>
=MEM_A_DQ<7>
30 32
12 83
C3151
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
28 30 89
30 32
30 32
30 32
30 32
30 32
Page Notes
30 32
Power aliases required by this page:
30 32
- =PP1V5_S0_MEM_A
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
30 32
- =PP1V5_S3_MEM_A
30 32
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
=MEM_A_DQ<46>
=MEM_A_DQ<47>
30 32
Signal aliases required by this page:

30 32
- =I2C_SODIMMA_SCL
=MEM_A_DQ<52>
=MEM_A_DQ<53>
- ALL DQ, DQS, DM SIGNALS;

TO FACILITATE BITSWAPS WITH ALIASES
- =I2C_SODIMMA_SDA
30 32
BOM options provided by this page:
30 32
(NONE)
=MEM_A_DM<6>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<62>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
30 32
30 32
30 32
30 32
30 32
SYNC_MASTER=MASTER
PAGE TITLE
30 32
30 32
SYNC_DATE=N/A
DDR3 SO-DIMMs 0 & 2

DRAWING NUMBER
Apple Inc.
30 32
30 32
051-8600
30 31 46

30 48
30 48
6 30
SIZE
REVISION
A.0.0
410
BRANCH
PAGE
31 OF 110
SHEET
30 OF 92
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
83 12
31 29 28 6
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
32
32
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 12
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
31
31 6
31
31 6
=MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<27>
MEM_B_CKE<2>
=PP1V5_S3_MEM_B
MEM_B_BA<2>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
=MEM_B_CLK_P<2>
=MEM_B_CLK_N<2>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<3>
=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DM<5>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DM<7>
=MEM_B_DQ<58>
=MEM_B_DQ<59>
MEM_DIMM3_SA<0>
=PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
73A
75A
77A
79A
81A
83A
85A
87A
89A
91A
93A
95A
97A
99A
101A
103A
105A
107A
109A
111A
113A
115A
117A
119A
121A
123A
125A
127A
129A
131A
133A
135A
137A
139A
141A
143A
145A
147A
149A
151A
153A
155A
157A
159A
161A
163A
165A
167A
169A
171A
173A
175A
177A
179A
181A
183A
185A
187A
189A
191A
193A
195A
197A
199A
201A
203A
409
VREFDQ
VSS_0
VSS_1CRITICAL DQ4
DQ0
DQ5
F-RT-TH
VSS_2
DQ1
(1 OF 2)
VSS_3
DQS0*
DM0
DQS0
VSS_5
VSS_4
DQ2
DQ6
DQ7
DQ3
VSS_6
VSS_7
DQ8
DQ12
DQ9
DQ13
VSS_8
VSS_9
DQS1*
DM1
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ11
DQ15
VSS_12
VSS_13
DQ16
DQ20
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
DQS2
VSS_16
VSS_17
DQ22
DQ18
DQ23
DQ19
VSS_18
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DM3
DQS3
VSS_22
VSS_23
DQ26
DQ30
DQ27
DQ31
VSS_24
VSS_25
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A9
A7
VDD_4
VDD_5
A8
A6
A5
A4
VDD_6
VDD_7
A3
A2
A1
A0
VDD_8
VDD_9
CK0
CK1
CK0*
CK1*
VDD_10
VDD_11
A10_AP
BA1
BA0
RAS*
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
A13
ODT1
S1*
NC_1
VDD_16
VDD_17
TEST
VREFCA
VSS_26
VSS_27
DQ32
DQ36
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
DQS4
VSS_30
VSS_31
DQ38
DQ34
DQ39
DQ35
VSS_32
VSS_33
DQ44
DQ40
DQ45
DQ41
VSS_34
VSS_35
DQS5*
DM5
DQS5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ48
DQ52
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
DQS6
VSS_42
VSS_43
DQ54
DQ50
DQ55
DQ51
VSS_44
VSS_45
DQ60
DQ56
DQ61
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ59
DQ63
VSS_51
VSS_50
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT_0
VTT_1
J3200
MTG PIN
MTG PIN
2A
4A
6A
8A
10A
12A
14A
16A
18A
20A
22A
24A
26A
28A
30A
32A
34A
36A
38A
40A
42A
44A
46A
48A
50A
52A
54A
56A
58A
60A
62A
64A
66A
68A
70A
72A
74A
76A
78A
80A
82A
84A
86A
88A
90A
92A
94A
96A
98A
100A
102A
104A
106A
108A
110A
112A
114A
116A
118A
120A
122A
124A
126A
128A
130A
132A
134A
136A
138A
140A
142A
144A
146A
148A
150A
152A
154A
156A
158A
160A
162A
164A
166A
168A
170A
172A
174A
176A
178A
180A
182A
184A
186A
188A
190A
192A
194A
196A
198A
200A
202A
204A
5
89 31 28
=MEM_B_DQ<4>
=MEM_B_DQ<5>
31 32
31 32
32 31
32 31
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DQ<0>
=MEM_B_DQ<1>
31 32
31 32
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DM<2>
32 31
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
30 31 32 91
32 31
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
32 31
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
31 32
31 32
32 31
32 31
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
31 32
31 32
32 31
32 31
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
31 32
=MEM_B_DQ<30>
=MEM_B_DQ<31>
MEM_B_CKE<3>
=PP1V5_S3_MEM_B
MEM_B_A<15>
MEM_B_A<14>
31 32
32 31
31 32
32 31
31 32
32 31
12 83
6 28 29 31
83 12
31 29 28 6
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<27>
MEM_B_CKE<0>
=PP1V5_S3_MEM_B
12 31 83
12 31 83
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
=MEM_B_CLK_P<3>
=MEM_B_CLK_N<3>
MEM_B_BA<1>
MEM_B_RAS_L
MEM_B_CS_L<2>
MEM_B_ODT<2>
MEM_B_ODT<3>
83 31 12
12 31 83
83 31 12
12 31 83
83 31 12
12 31 83
83 31 12
12 31 83
83 31 12
12 31 83
83 31 12
12 31 83
83 31 12
32
32
32
32
12 31 83
83 31 12
12 31 83
83 31 12
12 83
83 31 12
12 83
83 31 12
12 83
83 31 12
83 12
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DM<4>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
=MEM_B_CLK_P<0>
=MEM_B_CLK_N<0>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<1>
28 31 89
31 32
32 31
31 32
32 31
31 32
32 31
32 31
=MEM_B_DQ<38>
=MEM_B_DQ<39>
MEM_B_BA<2>
=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
31 32
31 32
32 31
32 31
=MEM_B_DQ<44>
=MEM_B_DQ<45>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
31 32
31 32
32 31
32 31
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
31 32
=MEM_B_DQ<46>
=MEM_B_DQ<47>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DM<6>
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
31 32
32 31
32 31
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DM<5>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
31 32
31 32
32 31
32 31
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
31 32
31 32
32 31
32 31
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
31 32
31 32
=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
32 31
31 32
32 31
31 32
32 31
30 31 46
31 48
31 48
6 31
31
31 6
31
31 6
=MEM_B_DM<7>
=MEM_B_DQ<58>
=MEM_B_DQ<59>
MEM_DIMM1_SA<0>
=PPSPD_S0_MEM_B
MEM_DIMM1_SA<1>
4
1B
3B
5B
7B
9B
11B
13B
15B
17B
19B
21B
23B
25B
27B
29B
31B
33B
35B
37B
39B
41B
43B
45B
47B
49B
51B
53B
55B
57B
59B
61B
63B
65B
67B
69B
71B
73B
75B
77B
79B
81B
83B
85B
87B
89B
91B
93B
95B
97B
99B
101B
103B
105B
107B
109B
111B
113B
115B
117B
119B
121B
123B
125B
127B
129B
131B
133B
135B
137B
139B
141B
143B
145B
147B
149B
151B
153B
155B
157B
159B
161B
163B
165B
167B
169B
171B
173B
175B
177B
179B
181B
183B
185B
187B
189B
191B
193B
195B
197B
199B
201B
203B
VREFDQ
VSS_0
VSS_1CRITICAL DQ4
DQ0
DQ5
F-RT-TH
DQ1
VSS_2
(2 OF 2)
VSS_3
DQS0*
DM0
DQS0
VSS_4
VSS_5
DQ2
DQ6
DQ3
DQ7
VSS_6
VSS_7
DQ8
DQ12
DQ9
DQ13
VSS_8
VSS_9
DQS1*
DM1
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ11
DQ15
VSS_12
VSS_13
DQ16
DQ20
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
DQS2
VSS_16
VSS_17
DQ22
DQ18
DQ23
DQ19
VSS_18
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DM3
DQS3
VSS_22
VSS_23
DQ26
DQ30
DQ27
DQ31
VSS_24
VSS_25
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A9
A7
VDD_4
VDD_5
A8
A6
A5
A4
VDD_6
VDD_7
A3
A2
A1
A0
VDD_8
VDD_9
CK0
CK1
CK0*
CK1*
VDD_10
VDD_11
A10_AP
BA1
BA0
RAS*
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
A13
ODT1
S1*
NC_1
VDD_16
VDD_17
TEST
VREFCA
VSS_26
VSS_27
DQ32
DQ36
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
DQS4
VSS_30
VSS_31
DQ38
DQ34
DQ39
DQ35
VSS_32
VSS_33
DQ44
DQ40
DQ45
DQ41
VSS_34
VSS_35
DQS5*
DM5
DQS5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ48
DQ52
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
DQS6
VSS_42
VSS_43
DQ54
DQ50
DQ55
DQ51
VSS_44
VSS_45
DQ60
DQ56
DQ61
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ59
DQ63
VSS_50
VSS_51
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT_0
VTT_1
J3200
DDR3-SODIMM-DUAL
32 31
DDR3-SODIMM-DUAL
32 31
=MEM_B_DQ<0>
=MEM_B_DQ<1>
7
1A
3A
5A
7A
9A
11A
13A
15A
17A
19A
21A
23A
25A
27A
29A
31A
33A
35A
37A
39A
41A
43A
45A
47A
49A
51A
53A
55A
57A
59A
61A
63A
65A
67A
69A
71A
DIMM 3
32 31
DIMM 1
8
89 31 28
2B
4B
6B
8B
10B
12B
14B
16B
18B
20B
22B
24B
26B
28B
30B
32B
34B
36B
38B
40B
42B
44B
46B
48B
50B
52B
54B
56B
58B
60B
62B
64B
66B
68B
70B
72B
74B
76B
78B
80B
82B
84B
86B
88B
90B
92B
94B
96B
98B
100B
102B
104B
106B
108B
110B
112B
114B
116B
118B
120B
122B
124B
126B
128B
130B
132B
134B
136B
138B
140B
142B
144B
146B
148B
150B
152B
154B
156B
158B
160B
162B
164B
166B
168B
170B
172B
174B
176B
178B
180B
182B
184B
186B
188B
190B
192B
194B
196B
198B
200B
202B
204B
3
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
31 32
31 32
31 32
31 6
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DM<1>
MEM_RESET_L
=PPSPD_S0_MEM_B
31 6
=PPSPD_S0_MEM_B
31 32
31 32
31 32
31 32
31
30 31 32 91
R3240
31 32
31
=MEM_B_DQ<14>
=MEM_B_DQ<15>
31 32
R3242
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MEM_DIMM1_SA<1>
MEM_DIMM1_SA<0>
31
MEM_DIMM3_SA<1>
31
MEM_DIMM3_SA<0>
R3243
10K
5%
1/16W
MF-LF
402
31 32
31 32
R3241
10K
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DM<2>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
31 32
31 32
5%
1/16W
MF-LF
402
31 32
31 32
31 6
=PPSPD_S0_MEM_B
31 32
31 32
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<30>
=MEM_B_DQ<31>
MEM_B_CKE<1>
=PP1V5_S3_MEM_B
MEM_B_A<15>
MEM_B_A<14>
31 32
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
=MEM_B_CLK_P<1>
=MEM_B_CLK_N<1>
MEM_B_BA<1>
MEM_B_RAS_L
MEM_B_CS_L<0>
MEM_B_ODT<0>
31 32
31 32
89 31 28
12 83
6 28 29 31
12 31 83
12 31 83
C3235
=MEM_B_DM<4>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<44>
=MEM_B_DQ<45>
20%
10V
CERM
402
12 31 83
12 31 83
12 31 83
89 31 28
12 31 83
32
32
C3230
C3231
2.2UF
2
12 31 83
0.1UF
20%
6.3V
CERM
402-LF
20%
10V
CERM
402
12 31 83
12 83
12 83
12 83
C3250
2.2UF
28 31 89
=MEM_B_DQ<36>
=MEM_B_DQ<37>
C3236
0.1UF
20%
6.3V
CERM
402-LF
12 31 83
2.2UF
12 31 83
31 6
MEM_B_ODT<1>
20%
6.3V
CERM
402-LF
31 32
MEM_B_A<11>
MEM_B_A<7>
C3240
2.2UF
31 32
31 32
C3251
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
31 32
31 32
31 32
31 32
Page Notes
31 32
31 32
- =PP1V5_S0_MEM_B
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
31 32
- =PP1V5_S3_MEM_B
31 32
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
=MEM_B_DQ<46>
=MEM_B_DQ<47>
31 32

31 32
- =I2C_SODIMMB_SCL
=MEM_B_DQ<52>
=MEM_B_DQ<53>
- ALL DQ, DQS, DM SIGNALS;

TO FACILITATE BITSWAPS WITH ALIASES
- =I2C_SODIMMB_SDA
31 32
31 32
(NONE)
=MEM_B_DM<6>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
31 32
31 32
31 32
31 32
31 32
SYNC_MASTER=MASTER
SYNC_DATE=N/A
PAGE TITLE
DDR3 SO-DIMM CONNECTOR B
31 32
31 32
DRAWING NUMBER
Apple Inc.
31 32
31 32
051-8600
30 31 46

31 48
31 48
6 31
SIZE
REVISION
A.0.0
410
BRANCH
PAGE
32 OF 110
SHEET
31 OF 92
CPU CHANNEL A DQS 0 -> DIMM A DQS 7

83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DM<0>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU CHANNEL B DQS 0 -> DIMM B DQS 7

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DM<7>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQ<62>
=MEM_A_DQ<63>
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12

83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DM<1>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DM<2>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DM<6>
=MEM_A_DQ<49>
=MEM_A_DQ<52>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<48>
=MEM_A_DQ<53>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DM<3>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DM<5>
=MEM_A_DQ<40>
=MEM_A_DQ<45>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<41>
=MEM_A_DQ<44>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DM<4>
=MEM_A_DQ<37>
=MEM_A_DQ<33>
=MEM_A_DQ<35>
=MEM_A_DQ<34>
=MEM_A_DQ<36>
=MEM_A_DQ<32>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
30
30
83 12
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DM<5>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DM<3>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQ<27>
=MEM_A_DQ<31>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<26>
=MEM_A_DQ<30>
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DM<6>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DM<7>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DM<2>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DM<3>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DM<4>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
32 6
=PP3V3_S3_MEMRESET
32 6
=PP5V_S3_MEMRESET
6
31
R3351
R3350
31
31
31
5%
1/16W
MF-LF
402
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DM<3>
=MEM_B_DQ<28>
=MEM_B_DQ<24>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQ<29>
=MEM_B_DQ<25>
=MEM_B_DQ<27>
=MEM_B_DQ<26>
20K
ISOLATE_CPU_MEM
31
31
5%
32 11
91
1/16W
MF-LF
402
CPU_MEM_RESET_L
31
32
ISOLATE_CPU_MEM_L_R1
Q3306
2N7002DW-X-G
R3353
2N7002DW-X-G
2N7002
20K
R
H
L
L
CLK
X
X
X
D
X
X
X
Q
H
L
H
QB
L
H
H
POSEDGE
POSEDGE
0.0022UF
5%
1/16W
MF-LF
402
10%
50V
2 CERM
402
MEM_RESET_L
30 31 91
31
C3353
SOT23-HF1
SOT-363
Q3304
Q3306
SOT-363
31
5%
1/16W
MF-LF
402
28
31
31
31
S5
CPU_RESET_L
0
ISOLATE_L
3.3V
S0
3.3V
S0
1.5V
3.3V
1.5V
S3
1.5V
S0
1.5V
3.3V
1.5V
S5
3.3V
MEM_RESET_L
0
31
31
31
31
31
R3385
=PP3V3_S5_MEMRESET
MEM_RESET_HW
C3300 1
0.1UF
31
31
31
91 63 19
31
32 6
31
PM_SLP_S4_L
PM_SYS_PWRGD
=PP3V3_S3_MEMRESET
PM_SLP_S4_D_L
=PP3V3_S3_MEMRESET
32 CPU_MEM_RESET3V3_L
19 5 PM_SLP_S3_L
32 6
31
DHVQFN
1Q 5
1Q* 6
3 1CP
1 1RD*
32
31
ISOLATE_CPU_MEM_L
10 2SD*
12 2D
2Q 9
2Q* 8
11 2CP
13 2RD*
5%
1/16W
MF-LF
402
32 6
PM_SLP_S4_D_L 32
NOSTUFF
TP_PM_SLP_S4_D
0 2
ISOLATE_CPU_MEMHW_L 1
MEM_RESET_HW
ISOLATE_CPU_MEM_L_R1
31
ALL_SYS_PWRGD_R 1
10K
31
32 6
R3387
DDRVTT_EN
31
5%
1/16W
37
MF-LF
19
40233
31
DDRSYS_EN
PM_SLP_S3_L
5
32
91 63 62 46
31
SOT23-HF1
SOT23-HF
C3390
31
NOSTUFF
MC74VHC1G08
U3390
SOT23-5-HF
4 SLP_S3_CTL_L
20%
10V
CERM
402
31
R3393
0
32
63 62
32 19 5
46 37 33
91
PM_SLP_S3_L
31
31
20K
5%
1/16W
MF-LF
2 402
PM_SLP_S3_5V
PM_SLP_S3_5V_L
R3394
R3384
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
0.1UF
31
NOSTUFF
31
31
20K
R3391
91 70 62
NOSTUFF
2N7002
=PP5V_S3_MEMRESET
31
31
Q3360
2N3904
5%
1/16W
MF-LF
402
=PP3V3_S5_MEMRESET
Q3350
MEM_RESET_HW
1
30
83 12
30
83 12
30
83 12
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DM<5>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DM<2>
=MEM_B_DQ<18>
=MEM_B_DQ<20>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DQ<19>
=MEM_B_DQ<21>
=MEM_B_DQ<17>
=MEM_B_DQ<16>
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DM<6>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DM<1>
=MEM_B_DQ<8>
=MEM_B_DQ<14>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<9>
=MEM_B_DQ<15>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
PM_SLP_S3_5V_R2 2
Q3370
2N7002DW-X-G
32
SOT-363
Q3370
2N7002DW-X-G
SOT-363
2
1
5%
1/16W
MF-LF
402
31
31
R3386
31
31
31
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
30
83 12
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DM<7>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FDMC8296
31
31
31
6
POWER33
PPVTT_S0_DDR_FET
31
R3388
31
10
31
31
31
MEMORY CLOCK ALIASING

83 12
31
83 12
31
83 12
31
83 12
31
83 12
31
R3340
100K
PM_SLP_S3_5V_L
5%
1/16W
MF-LF
32
2 402
83 12
83 12
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CLK_P<2>
MEM_A_CLK_N<2>
MEM_A_CLK_P<3>
MEM_A_CLK_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_CLK_P<0>
=MEM_A_CLK_N<0>
=MEM_A_CLK_P<1>
=MEM_A_CLK_N<1>
=MEM_A_CLK_P<2>
=MEM_A_CLK_N<2>
=MEM_A_CLK_P<3>
=MEM_A_CLK_N<3>
3
30
31
83 12
31
83 12
31
83 12
31
83 12
31
83 12
31
83 12
31
83 12
31
83 12
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CLK_P<2>
MEM_B_CLK_N<2>
MEM_B_CLK_P<3>
MEM_B_CLK_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Q3380
30
30
32
PM_SLP_S3_5V 1
2N7002
SOT23-HF1
30
30
30
30
30
PAGE TITLE
31
VTT_R
31
31
5%
1/16W
MF-LF
402
=PP0V75_S0_MEM_VTT_S0FET
83 12
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<1>
=MEM_B_DQ<3>
=MEM_B_DQ<7>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DQ<0>
Q3375
31
31
5%
1/16W
MF-LF
402
31
31
NOSTUFF
31

=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
=MEM_A_DM<0>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<3>
=MEM_A_DQ<2>
=MEM_A_DQ<1>
=MEM_A_DQ<0>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
MEM_RESET_HW
R3380
CPU_MEM_RESET_L
32
CPU_MEM_RESET3V3
MEM_RESET_HW
91 32 11
32 6
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R3382
10K
5%
1/16W
MF-LF
402
CPU_MEM_RESET_R_L
NOSTUFF
63 25 6
91
10K
TP_ISOLATE_CPU
R3390
31
R3381
5%
1/16W
MF-LF
402
31
31
MEM_RESET_HW
1
32
CPU_MEM_RESET3V3_L
31
31
=PP3V3_S5_MEMRESET
R3383
THRM
GND PAD
31
31
74LVC74ABQ
4 1SD*
2 1D
31
91 19
25 21
U3300
31
31
MEM_RESET_HW
VCC
20%
10V
CERM 2
402
31
91 63 62 46 37 33 32
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DM<4>
=MEM_B_DQ<32>
=MEM_B_DQ<39>
=MEM_B_DQ<37>
=MEM_B_DQ<38>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<36>
=MEM_B_DQ<33>
R3355
R3352
5%
1/16W
MF-LF
402
31
32 6
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DM<5>
=MEM_B_DQ<45>
=MEM_B_DQ<40>
=MEM_B_DQ<42>
=MEM_B_DQ<47>
=MEM_B_DQ<44>
=MEM_B_DQ<41>
=MEM_B_DQ<46>
=MEM_B_DQ<43>
NOSTUFF
20K
20K
31
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DM<6>
=MEM_B_DQ<51>
=MEM_B_DQ<54>
=MEM_B_DQ<53>
=MEM_B_DQ<52>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQ<50>
=MEM_B_DQ<55>
=PP1V5_S3_MEMRESET
S
L
H
L
31

=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DM<1>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DQ<10>
=MEM_A_DQ<15>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<11>
=MEM_A_DQ<14>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DM<1>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>

=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DM<2>
=MEM_A_DQ<17>
=MEM_A_DQ<16>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>

83 12
31

83 12
31

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DM<4>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LFD CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DM<7>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DQ<58>
=MEM_B_DQ<59>

83 12
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DM<0>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

83 12
4
DDR3 RESET Support
83 12
14
15
=MEM_B_CLK_P<0>
=MEM_B_CLK_N<0>
=MEM_B_CLK_P<1>
=MEM_B_CLK_N<1>
=MEM_B_CLK_P<2>
=MEM_B_CLK_N<2>
=MEM_B_CLK_P<3>
=MEM_B_CLK_N<3>
DDR3 SUPPORT AND BITSWAPS
31
DRAWING NUMBER
31
Apple Inc.
31
31
051-8600

31
31
A.0.0
R
31
31
SIZE
REVISION
BRANCH
PAGE
33 OF 110
SHEET
32 OF 92
L3400
PP3V3_MINI_FILT
CRITICAL
J3400
C3400 1
F-ST-SM
17
10uF
20%
10V
CERM 2
402
20%
6.3V 2
X5R
603
L3430
90-OHM-100MA
DLP11S
MINI_CLKREQ_L
PCIE_WAKE_L
MINI_RESET_L
SYM_VER-1
OUT
15 18 25
OUT
19 37
IN
27 91
0.1uF
20%
10V
CERM 2
402
C3401 1 C3402 1
0.1uF
33 89
2
0402
20247-916E-01F
PP3V3_MINI
FERR-120-OHM-1.5A
VOLTAGE=3.3V
PCIE_CLK100M_MINI_CON_N
PCIE_CLK100M_MINI_CON_P
8
9
PCIE_CLK100M_MINI_P
IN
18 84
PCIE_CLK100M_MINI_N
IN
18 84
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
10
11
12
PCIE_MINI_R2D_N
PCIE_MINI_R2D_P
13
14
15
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
16
PLACEMENT_NOTE=PLACE CLOSE TO U1400.

OUT
18 84
OUT
18 84
C3431
0.1uF
1
L3440
18
4
518S0731
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
PCIE_MINI_R2D_L_N
PCIE_MINI_R2D_L_P
PCIE_MINI_R2D_C_N
IN
18 84
10%
16V
X5R
402
PLACEMENT_NOTE=PLACE CLOSE TO U1400.
C3430
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
0.1uF
1
PCIE_MINI_R2D_C_P
IN
18 84
10%
16V
X5R
402
AP POWER ENABLE CIRCUIT

AP_PWR_ON = S0 || (S3 && AP_EN)
R3466
1
5%
1/8W
MF-LF
805
5%
1/16W
MF-LF
2 402
R3462
1
AP_PWR_EN_L
6
100K
5%
1/16W
MF-LF
402
NOSTUFF
Q3403
33 89
C3461
0.1UF
NOSTUFF
1 2
NOSTUFF
10K
VOLTAGE=3.3V
10%
2 16V
X5R
402
R3461
PP3V3_MINI
NOSTUFF
5 6
SOT-6
=PP3V3_S3_MINI
4
NOSTUFF
Q3401
FDC606P_G
NOSTUFF
C3462
0.1UF
AP_PWR_ENABLE
2
10%
X5R
16V
402
2N7002DW-X-G
21 15
AP_PWR_EN
SOT-363
3
1
A
91 63 62 46 37 32 19 5
PM_SLP_S3_L
NOSTUFF
D
1
Q3407
2N7002
SOT23-HF1
PAGE TITLE
PCI-E Wireless Connector
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
34 OF 110
SHEET
33 OF 92
USB HUB-1
L3558
FERR-120-OHM-1.5A
35 34 6
=PP3V3_S3_USB_HUB
C3536
0.01UF
10UF
100PF
10%
16V
2 CERM
402
C3518
C3537
C3538
10UF
5%
50V
2 CERM
402
R3541
20K
C3539
0.1UF
20%
6.3V
2 X5R
603
R3540
0402
1
=PP3V3_S3_USB_RESET
USB_HUB1_VDDPLL3V3
10%
16V
2 X7R-CERM
402
NOSTUFF
C3541
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
100PF
20%
2 6.3V
X5R
603
5%
50V
CERM 2
402
USB_HUB_RESET
L3559
Q3540
FERR-120-OHM-1.5A
1
=PP3V3_S3_USB_HUB
USB_HUB1_VDDA3V3
0402
1
C3542
0.01UF
C3543
100PF
10%
16V
2 CERM
402
C3544
10UF
5%
50V
2 CERM
402
C3545
0.1UF
20%
6.3V
2 X5R
603
10%
16V
2 X7R-CERM
402
C3546
0.1UF
10%
16V
2 X7R-CERM
402
2N7002DW-X-G
C3547
C3523
0.1UF
10%
16V
2 X7R-CERM
402
0.1UF
10%
16V
2 X7R-CERM
402
C3525 1 C3526
0.1UF
10%
16V
2 X7R-CERM
402
0.01UF
10%
16V
2 CERM
402
C3529
91 72
0.01UF
PGOOD_P3V3_S3 2
D
5
NOSTUFF
10%
16V
2 CERM
402
C3540
35 91
SOT-363
6 34 35
USB_HUB_RESET_L 34
Q3540
2N7002DW-X-G
SOT-363
0.47UF
10%
6.3V
2 CERM-X5R
402
C
NOSTUFF
10K
Y3500
5%
1/16W
MF-LF
402 2
5X3.2X1.4-SM
C3519
R3591
18PF
5%
50V
2 CERM
402
1M
R3597
CRITICAL
24.000M-60PPM-16PF
1
R3545
=PP3V3_S3_USB_HUB
NOSTUFF
5%
1/16W
MF-LF
402 2
18PF
91 35 34
USB_HUB_RESET_L
IN
85
85
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
3
4
USB_IR_N
USB_IR_P
6
7
USB_EXTA_N
USB_EXTA_P
24
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
R3504
8
9
USB_EXTC_N
USB_EXTC_P
25
HS_IND/CFG_SEL1
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
PRTPWR4/BC_EN4*
12
16
18
20
10K
OCS1*
OCS2*
OSC3*
OSC4*
13
17
19
21
5%
1/16W
MF-LF
2 402
1 A0
2 A1
3 A2
C3534
0.1UF
10%
16V
2 X5R
402
SOI
RBIAS
35
5%
1/16W
MF-LF
402 2
VBUS_DET
27
USBDM_UP
USBDP_UP
30
31
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
RESET*
33
32
XTALIN/CLKIN
XTALOUT
28
34 PLLFILT
10K
10K
5%
1/16W
MF-LF
402 2
U3514
AT24C02B
R3598
R3594
10K
8
VCC
26
14 CRFILT
1 NOSTUFF
R35921
NOSTUFF
TEST
22
USB_HUB1_CFG_SEL1
USB2514-AEZG
QFN USBDM_DN1/PRT_DIS_M1
11
SDA 5
SCL 6
R3501
10K
WP 7
GND
4
NOSTUFF
R3566
10K
5%
1/16W
MF-LF
2 402
WP_HUB1
R3565
10K
5%
1/16W
MF-LF
2 402
R3567
10K
5%
1/16W
MF-LF
2 402
44 85
44 85
44 85
44 85
43 85
43 85
43 85
43 85
TP_USB_HUB1_PRTPWR1
TP_USB_HUB1_PRTPWR2
TP_USB_HUB1_PRTPWR3
TP_USB_HUB1_PRTPWR4
TP_USB_HUB1_OCS1_L
TP_USB_HUB1_OCS2_L
=PP3V3_S3_USB_HUB
R3580
10K
R3581
R3550
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
6 34 35
5%
1/16W
MF-LF
2 402
USB_EXTA_OC_L
USB_EXTC_OC_L
USB_HUB1_RBIAS
43
43
85
USB_HUB1_VBUS_DET
USB_HUB1_UP_N
USB_HUB1_UP_P
IN
20 85
IN
20 85
THRM_PAD
37
35 34
OMIT
USB_CAMERA_N
USB_CAMERA_P
USB_HUB1_SMBDATA
USB_HUB1_SMBCLK
U3500
1
2
USB_HUB1_LOCAL_PWR
5%
1/16W
MF-LF
402
USB_HUB1_XTAL1
USB_HUB1_XTAL2
=PP3V3_S3_USB_HUB
6
VDD33
100K
5%
50V
2 CERM
402
5%
1/16W
MF-LF
402
USB_HUB_SOFT_RESET_L
R3599
C3520
25 20
5
10
15
23
29
36
35 34 6
USB_HUB1_TEST
R3500
1
12K
1%
1/16W
MF
402
SEL0
DESCRIPTION
DEFAULT K23F ==> 0
SEL1
Internal Default with Self powered Operation
SMBUS Slave Config
BOM TABLE
TABLE_5_HEAD
USB_HUB1_VDD1V8
Internal Default with Bus powered Operation
EEPROM Supported
PART#
C3524
0.1UF
0
0
DEFAULT K23F ==> 1
1
NON_REM0
0
1
0
1
DESCRIPTION
CRITICAL
U3500,U3600
CRITICAL
BOM OPTION
TABLE_5_ITEM
338S0721
SMSC USX2061-AEZG
USB_HUB1_VDD1V8PLL
A
NON_REM1
QTY
10%
16V
2 X7R-CERM
402
DESCRIPTION
C3527
1UF
10%
16V
2 X5R
402
C3528
0.1UF
10%
16V
2 X7R-CERM
402
C3530
1UF
10%
16V
2 X5R
402
PAGE TITLE
All ports are Non removable

Port1 is non removable
Port 1 and 2 are non removable
Port1,2 and 3 are non Removable
USB HUB 1
DRAWING NUMBER
Apple Inc.
SIZE
A.0.0
051-8600
REVISION
BRANCH
PAGE
35 OF 110
SHEET
34 OF 92
USB HUB-2
L3658
35 34 6
FERR-120-OHM-1.5A
=PP3V3_S3_USB_HUB
USB_HUB2_VDDPLL3V3
2
0402
C3636
0.01UF
100PF
10%
2 16V
CERM
402
1
C3637
C3638
10UF
5%
2 50V
CERM
402
C3639
0.1UF
20%
2 6.3V
X5R
603
10%
2 16V
X7R-CERM
402
C3618
10UF
20%
6.3V
2 X5R
603
L3629
FERR-120-OHM-1.5A
1
=PP3V3_S3_USB_HUB
USB_HUB2_VDDA3V3
0402
C3642
C3643
0.01UF
1
CRITICAL
18PF
5%
50V
2 CERM
402
10%
16V
2 X7R-CERM
402
10K
5X3.2X1.4-SM
5%
50V
2 CERM
402
IN
C3634
0.1UF
10%
16V
2 X5R
402
R3692
U3614
AT24C02B
WP_HUB2
0.01UF
3
4
USB_SDCARD_N
USB_SDCARD_P
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
6
7
USB_EXTB_N
USB_EXTB_P
8
9
USB_EXTD_N
USB_EXTD_P
HS_IND/CFG_SEL1
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
PRTPWR4/BC_EN4*
12
16
18
20
TP_USB_HUB2_PRTPWR1
TP_USB_HUB2_PRTPWR2
TP_USB_HUB2_PRTPWR3
TP_USB_HUB2_PRTPWR4
OCS1*
OCS2*
OSC3*
OSC4*
13
17
19
21
TP_USB_HUB2_OCS1
TP_USB_HUB2_OCS2
RBIAS
35
VBUS_DET
27
USB_HUB2_VBUS_DET
USBDM_UP
USBDP_UP
30
31
USB_HUB2_UP_N
USB_HUB2_UP_P
XTALIN/CLKIN
XTALOUT
USB_HUB2_LOCAL_PWR
28
USB_HUB2_SMBDATA
22
24
14 CRFILT
R3698
34 PLLFILT
10K
5%
1/16W
MF-LF
2 402
SDA 5
SCL 6
R3601
10K
NOSTUFF
R3665 1R3666 1R3667
5%
1/16W
MF-LF
2 402
C3629
10%
2 16V
CERM
402
33
32
5%
1/16W
MF-LF
2 402
10K
USB_BT_N
USB_BT_P
USB_HUB2_XTAL1
USB_HUB2_XTAL2
WP 7
GND
4
0.01UF
10%
2 16V
CERM
402
1
2
RESET*
10K
5%
1/16W
MF-LF
402 2
0.1UF
26
R3694
10K
NOSTUFF 8
VCC
C3625 1 C3626
10%
2 16V
X7R-CERM
402
USB2514-AEZG
QFN USBDM_DN1/PRT_DIS_M1
TEST
USB_HUB_RESET_L
NOSTUFF
OMIT
USB_HUB2_CFG_SEL1 25
SOI
0.1UF
10%
16V
2 X7R-CERM
402
U3600
USB_HUB2_TEST 11
91 34
C3623
10%
2 16V
X7R-CERM
402
0.1UF
18PF
5%
1/16W
MF-LF
402
1 A0
2 A1
3 A2
C3647
C3620
R3691
5%
1/16W
MF-LF
402 2
=PP3V3_S3_USB_HUB
5%
1/16W
MF-LF
402
10%
16V
2 X7R-CERM
402
VDD33
USB_HUB2_SMBCLK
10K
0.1UF
100K
5%
1/16W
MF-LF
402 2
85
R36041
C3646
NOSTUFF
NOSTUFF
85
35 34 6
=PP3V3_S3_USB_HUB
1M
0.1UF
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
10K
44 85
44 85
44 85
44 85
43 85
43 85
43 85
43 85
=PP3V3_S3_USB_HUB
1
R3680
10K
5%
1/16W
MF-LF
402 2
R3681
10K
5%
1/16W
MF-LF
402 2
6 34 35
R36821
10K
5%
1/16W
MF-LF
402 2
USB_EXTB_OC_L
USB_EXTD_OC_L
43
IN
20 85
IN
20 85
43
USB_HUB2_RBIAS
85
THRM_PAD
5%
1/16W
MF-LF
2 402
37
C3619
C3645
R36971 R36991
Y3600
20%
6.3V
2 X5R
603
24.000M-60PPM-16PF
1
C3644
10UF
5%
50V
2 CERM
402
35 34 6
100PF
10%
16V
2 CERM
402
5
10
15
23
29
36
6 34 35
R3600
1
12K
1%
1/16W
MF
402
USB_HUB2_VDD1V8
USB_HUB2_VDD1V8PLL
C3624
0.1UF
10%
16V
2 X7R-CERM
402
C3627
1UF
10%
16V
2 X5R
402
C3628
0.1UF
10%
16V
2 X7R-CERM
402
C3630
1UF
10%
16V
2 X5R
402
PAGE TITLE
USB HUB 2
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
36 OF 110
SHEET
35 OF 92
Page Notes
- PP3V3_ENET
(CAESAR II)
- =PP1V2_ENET
CRITICAL
=PP1V2_ENET
37 36
VOLTAGE=1.2V
PP1V2_LAN_PLL_VDDL
2
SM
C3746
10%
6.3V
X5R-CERM
603
4.7UF
CRITICAL
=PP1V2_ENET
1
C3747
C3726
10UF
0.1UF
10%
16V
X7R-CERM
402
=PP1V2_ENET
PP1V2_LAN_VDDL
2
SM
C3748
4.7UF
2
SM
C3750
4.7UF
10%
16V
X7R-CERM
402
10%
16V
X7R-CERM
402
CRITICAL
VOLTAGE=3.3V
PP3V3_LAN_AVDDH
0.1UF
10%
6.3V
X5R-CERM
603
10%
16V
X7R-CERM
402
OUT
C3717
2
10%
0.1uF
86 18
16V
X5R
AVDDL
402
2
10%
0.1uF
16V
X5R
402
PCIE_ENET_D2R_C_N
86 PCIE_ENET_D2R_C_P
86
25
26
PLACEMENT_NOTE=PLACE C3718,C3719 CLOSE TO SB
PCIE_ENET_R2D_C_P
IN
C3718
2
10%
0.1uF
86 18
PCIE_ENET_R2D_C_N
IN
C3719
16V
X5R
402
PCIE_ENET_R2D_P
86 PCIE_ENET_R2D_N
10%
16V
X5R
402
84 18
WAKE#
Must Isolate from PCIE WAKK# if
Phy is powered-down in S3/S5.
37
91 27
R3723
ENET_WAKE_L
1.24K2
IN
LAN_RESET_L
5%
1/16W
MF-LF
402
R3701
IN
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
IN
84 18
18 15
OUT
1%
1/16W
MF-LF
402
89 37 36
IN
IN
86
89 37 36
=PP3V3_S0_ENET
1K
12
WAKE*
ENET_CLKREQ_L
11
CLKREQ*
ENET_RDAC
37
RDAC
R3700
ENET_LOW_PWR
21 15
R3702
1K
UART_MODE
VMAIN_PRSNT
2
R3703
VAUX_PRSNT
5%
1/16W
MF-LF
402
86
ENET_CLK25M_XTALI
R3704
1
200
86
C3720
27PF
5%
50V
CERM
402
SM-3-LF
35
23
36
6
15
19
56
61
5
17
55
24
33
13
20
34
60
QFN
40
41
44
43
46
47
50
49
ENET_ENERGY_DET
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
ENET_LED_ACT_L
2
1 ENET_LED_LINK10_100_L
ENET_LED_LINK1000_L
67
ENET_LED_LINK_L
66
SCLK/EECLK
SI
SO/EEDATA
65
63
64
VMAIN_PRSNT
54
VAUX_PRSNT
CS*
62
16
SUPER_IDDQ
SMB_CLK
SMB_DATA
58
57
21
22
XTALI
XTALO
68
DC0
DC1
NC
THRM_PAD
OUT
4
7
8
REGCTL12
14
REGOUT12_IO
18
ENET_SCLK
ENET_MISO
ENET_MOSI
ENET_CS
C3727
10%
6.3V
X5R-CERM
603
38 86
BI
38 86
BI
38 86
BI
38 86
BI
38 86
BI
38 86
BI
38 86
BI
38 86
C3725
36 37
SM
0.1UF
10%
16V
X7R-CERM
402
36 37 89
37
37
37
36
R3765
10K
5%
1/16W
MF-LF
2 402
36
36
R3766
Flash Strapping Support

Atmel
SO, CS, SCLK logic high; SI logic low
ST Micro
CS logic high; SCLK, SI, SO logic low
10K
5%
1/16W
MF-LF
2 402
36
Note: CAESAR II has internal pullups on SPI pins

Pullup provisions will be removed in Proto 2
SI PIN OF CAESAR II SHOULD BE CONNECTED TO SO OF
AT45DB011D, AND VICE VERSA
ENET_SMB_CLK
ENET_SMB_DATA
NC
NC
NC
OUT
PP1V2_ENET_VDDCIO
OUT
VOLTAGE=1.2V
PP3V3_ENET
89 37 36
ENET_CTRL12
=PP1V2_ENET
15 18
BI
PP3V3_ENET
37
37
C3788
0.1UF
36
NOSTUFF
1
10%
16V
X7R-CERM
402
2
NOSTUFF
1
R3714
R3715
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NOSTUFF
OMIT
VCC
AT45DB011D
SOIC-8S1
36
ENET_SCLK
SCK
36
ENET_CS
CS*
WP*
R3718
4.7K
U3701
5%
1/16W
MF-LF
402
SI 1
ENET_MOSI
36
ENET_MISO
36
C3721
27PF
59
GPIO_0/SERIAL_DO
GPIO_1/SERIAL_DI
GPIO_2
L3710
FERR-600-OHM-0.5A
4.7UF
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
36 37 89
CRITICAL
SM
ENERGY_DET
LINKLED*
SPD100LED*
SPD1000LED*
TRAFFICLED*
LOW_PWR
ENET_CLK25M_XTAL
U3700
BCM5764M
UART_MODE
197S0167
CL = 20PF
86
OMIT
CRITICAL
PP3V3_ENET
CRITICAL
L3711
FERR-600-OHM-0.5A
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM 1
2
PP1V2_LAN_GPHY_PLLVDDL
VOLTAGE=1.2V
53
NC 38
NC 52
NC
CRITICAL
25.0000M
ENET_CLK25M_XTALO
5%
1/16W
MF-LF
402
Y3700
VDDIO
2
SM
10%
16V
X7R-CERM
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PP3V3_ENET
BCM5764M_WAKE_L
VDDC_IO
PCIE_REFCLK_P
PCIE_REFCLK_N
PERST*
29
28
10
NOSTUFF
PP3V3_ENET
PCIE_TXD_N
PCIE_TXD_P
31 PCIE_RXD_P
32 PCIE_RXD_N
86
0.1uF
10%
16V
X7R-CERM
402
69
86 18
VDDC
37 89
FERR-600-OHM-0.5A
C3724
GPHY_PLLVDDL
C3716
PCIE_ENET_D2R_P
AVDDH
XTALVDDH
PCIE_ENET_D2R_N
10%
16V
X7R-CERM
402
BIASVDDH
OUT
0.1UF
PCIE_VDDL
27
30
10%
16V
X7R-CERM
402
0.1UF
C3753
PCIE_PLLVDDL
39
45
51
C3752
42
48
PP3V3_ENET 36
CRITICAL
L3718
0.1UF
SM
86 18
36 37 89
C3715
PP3V3_LAN_BIASVDDH
VOLTAGE=3.3V
1
C3723
PP3V3_LAN_XTALVDDH
0.1UF
L3700
FERR-600-OHM-0.5A
C3714
4.7UF
C3751
0.1UF
10%
6.3V
X5R-CERM
603
PP3V3_ENET
C3713
PP3V3_ENET
VOLTAGE=1.2V
PP1V2_LAN_AVDDL
D
36
0.1UF
10%
16V
X7R-CERM
402
10%
16V
X7R-CERM
402
L3701
89 37 36
0.1UF
C3749
FERR-600-OHM-0.5A
=PP1V2_ENET
C3712
0.1UF
10%
6.3V
X5R-CERM
603
CRITICAL
37 36
10%
16V
X7R-CERM
402
PP1V2_ENET_VDDCIO
VOLTAGE=1.2V
36 37
C3762
0.1UF
10%
6.3V
X5R
805
L3702
FERR-600-OHM-0.5A
37 36
L3703
FERR-600-OHM-0.5A
5%
50V
CERM
402
NOSTUFF
R3719
4.7K
5%
1/16W
MF-LF
402
RESET*
GND
NOSTUFF
R3716
4.7K
SO 8
R3717
4.7K
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
PAGE TITLE
ETHERNET (CAESAR II)

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
37 OF 110
SHEET
36 OF 92
CAESAR II DECOUPLING
37 36
=PP1V2_ENET
C3800
89 37 36
20%
6.3V
CERM
603
C3801
0.1UF
4.7UF
2
C3802
0.1UF
10%
16V
X7R-CERM
402
10%
16V
X7R-CERM
402
C3803
0.1UF
10%
16V
X7R-CERM
402
C3804
0.1UF
10%
16V
X7R-CERM
402
C3805
0.1UF
10%
16V
X7R-CERM
402
C3806
C3807
0.1UF
0.1UF
10%
16V
X7R-CERM
402
C3810
C3808
20%
6.3V
CERM
603
10%
16V
X7R-CERM
402
C3811
0.1UF
4.7UF
0.1UF
10%
16V
X7R-CERM
402
PP3V3_ENET
C3812
0.1UF
10%
16V
X7R-CERM
402
C3813
0.1UF
10%
16V
X7R-CERM
402
10%
16V
X7R-CERM
402
ENET POWER ENABLE CIRCUIT
ENET_PWR_ON = "S0" || (S3 power && WOL_EN)
CAESAR II 1V2 RAIL SUPPLY
CRITICAL
Q3802
R3831
10K
WOL_EN
Q3803
PP3V3_ENET
89 37 36
100K
C3817
4.7UF
20%
6.3V
2 CERM
603
C3832
1.5
36 37 89
C3818
MAX CURRENT = 396MA
5%
1/4W
MF-LF
1206
10%
16V
2 X5R
402
CRITICAL
PBSS5540ZDG
SOT223
10%
CERM
16V
402
36
ENET_CTRL12
C3825
20%
6.3V
2 X5R
603-2
2N7002DW-X-G
=PP1V2_ENET
36 37
10UF
Q3803
Q3810
PM_SLP_S3_L
VOLTAGE=3.3V
1
SOT-363
PP_ENET_CTRL12
89
0.1UF
0.01UF
ENET_PWR_L
5%
1/16W
MF-LF
402
91 63 62 46 33 32 19 5
R3832
10%
2 16V
X5R
402
2N7002DW-X-G
21 15
C3831
0.1UF
WOL_EN_L
R3802
PP3V3_ENET
VOLTAGE=3.3V
5%
1/16W
MF-LF
2 402
=PP3V3_S3_ENET
NTR4101P
SOT-23-HF
C3826
0.1UF
PP1V2_S5_ENET
89
MAKE_BASE=TRUE
VOLTAGE=1.2V
10%
16V
2 X5R
402
SOT-363
S
1
CAESAR II LED SUPPORT

89 37 36
PP3V3_ENET
PP3V3_ENET
36 37 89
DEVELOPMENT
R3841
R3805
10K
Q3841
G 1
S
37 36
ENET_WAKE_L
R3807
330
DEVELOPMENT
R3808
330
5%
1/16W
MF-LF
2 402
330
DEVELOPMENT
1
5%
1/16W
MF-LF
2 402
36 37
SOD-VESM-HF
R3806
5%
1/16W
MF-LF
2 402
ENET_ACT
ENET_WAKE_L
DEVELOPMENT
1
5%
1/16W
MF-LF
2 402
D
3
PCIE_WAKE_L
330
5%
1/16W
MF-LF
2 402
SSM3K15FV
33 19
DEVELOPMENT
ENET_LINK10
DEVELOPMENT
ENET_LINK1000
DEVELOPMENT
LED3801
LED3802
LED3803
GREEN-3.6MCD
2.0X1.25MM-SM
GREEN-3.6MCD
2.0X1.25MM-SM
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:ACT
SILKSCREEN:10/100
SILKSCREEN:10/1000
ENET_LINK
DEVELOPMENT
LED3804
K
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:LINK
PAGE TITLE
36
36
36
36
CAESAR II SUPPORT
DRAWING NUMBER
ENET_LED_ACT_L
ENET_LED_LINK10_100_L
ENET_LED_LINK1000_L
ENET_LED_LINK_L
Apple Inc.
SIZE
A.0.0

051-8600
REVISION
BRANCH
PAGE
38 OF 110
SHEET
37 OF 92
T3900
LFE9287APF
SOI
1 TCT1
MCT1 24
ENET_MCT0
MX1+ 23
ENET_MDI_T_P<0>
38 86
ENET_MDI_T_N<0>
38 86
ENET_MDI_T_P<1>
38 86
86 36
ENET_MDI_P<0>
2 TD1+ 1CT:1CT
86 36
ENET_MDI_N<0>
3 TD1-
MX1- 22
4 TCT2
MCT2 21
86 36
ENET_MDI_P<1>
5 TD2+ 1CT:1CT
MX2+ 20
RJ45-10/100TX-K22
ENET_MCT1
F-ANG-TH
86 38
86 38
86 36
ENET_MDI_N<1>
6 TD2-
MX2- 19
7 TCT3
MCT3 18 ENET_MCT2
8 TD3+ 1CT:1CT
MX3+ 17
ENET_MDI_T_N<1>
38 86
86 38
86 38
86 36
ENET_MDI_P<2>
86 38
ENET_MDI_T_P<2>
86 38
38 86
86 38
86 36
ENET_MDI_N<2>
MX3- 16
9 TD3-
ENET_MDI_T_N<2>
10 TCT4
MCT4 15 ENET_MCT3
CRITICAL
J3900
86 38
ENET_MDI_T_P<0>
ENET_MDI_T_N<0>
ENET_MDI_T_P<1>
ENET_MDI_T_P<2>
ENET_MDI_T_N<2>
ENET_MDI_T_N<1>
ENET_MDI_T_P<3>
ENET_MDI_T_N<3>
ENET_MDI
TRAN_P0
TRAN_N0
TRAN_P1
TRAN_P2
TRAN_N2
TRAN_N1
TRAN_P3
TRAN_N3
2
3
4
5
6
7
8
38 86
9
10
86 36
ENET_MDI_P<3>
11 TD4+ 1CT:1CT
MX4+ 14
ENET_MDI_T_P<3>
38 86
86 36
ENET_MDI_N<3>
12 TD4-
MX4- 13
ENET_MDI_T_N<3>
38 86
SHIELD
PINS
514-0654
B
NOTE: DELTA RECOMMENDS CENTER-TAP BE FLOATING
R3900
ENET_TCT
75
C3901
0.1UF
20%
2 10V
CERM
402
C3902
0.1UF
20%
2 10V
CERM
402
C3903
0.1UF
20%
2 10V
CERM
402
C3904
0.1UF
20%
2 10V
CERM
402
5%
1/16W
MF-LF
2 402
R3901
75
5%
1/16W
MF-LF
2 402
R3902
75
5%
1/16W
MF-LF
2 402
R3903
75
5%
1/16W
MF-LF
2 402
ENET_MCT_BS
NOSTUFF
PLACE ONE CAP PER TCT PIN
C3900
1000PF
10%
2 2KV
CERM
1206
NOTE: BOB SMITH TERMINATION FOR EMC INVESTIGATION.
PAGE TITLE
ETHERNET CONNECTOR
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
39 OF 110
SHEET
38 OF 92
8
6
41 40 39 6
=PP3V3_FWRS0_FWXIO
=PP3V3_FW_FWPHY
C4100
C4101
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4102
C4103
1UF
2
10%
6.3V
CERM
402
C4104
1UF
10%
6.3V
CERM
402
1UF
10%
6.3V
CERM
402
C4105
C4124
1UF
2
10%
6.3V
CERM
402
C4123
C4122
C4121
C4120
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4106
R4110
10%
6.3V
CERM
402
5%
1/16W
MF-LF
402
1
5%
1/16W
MF-LF
402
VOLTAGE=3.3V
C4110
R4117
10%
6.3V
CERM
402
5%
1/16W
MF-LF
402
89
C4111
1UF
10%
6.3V
CERM
402
C4112
C4113
1UF
2
1UF
1UF
2
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4114
1UF
10%
6.3V
CERM
402
1UF
10%
6.3V
CERM
402
C4115
10%
6.3V
CERM
402
C4132
14.3K
1%
1/16W
MF-LF
402
84
402
84
84
402
402
=FW_CLKREQ_L
84 18
IN
84 18
IN
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
J12
A1
B1
REFCLK_SEL
FWXIO_SCL
FWXIO_SDA
J13
SCL
SDA
H12
NC
NC
NC
NC
NC
NC
NC
NC
5%
1/16W
MF-LF
2 402
=FW_PME_L
OUT
N2
P2
N3
N4
P5
P6
N6
N8
TP_FWXIO_GRST_L
R4153
P1
P8
FWXIO_CYCLEOUT
NO STUFF
C13
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
TP_FWXIO_JTAG_TMS
TP_FWXIO_JTAG_TDO
TP_FWXIO_JTAG_TDI
R4160
5%
1/16W
MF-LF
402
91
FWXIO_SNOOP_EN
(Snoop Enable, for FireBug)
R4180
1K
5%
1/16W
MF-LF
402
E12
F12
F13
G12
1K
R4182
NC
NC
NC
K12
NC
NC
NC
NC
NC
NC
NC
NC
NC
M11
L12
L13
M8
M12
M13
N10
N11
N12
N13
P10
P11
D12
D13
1K
5%
1/16W
MF-LF
402
FWPHY_BMODE
FWPHY_TESTM
FWPHY_TESTW
A5
B2
A6
P13
NO STUFF 1
P14
R4189
B11
C12
M9
F3
C9
B5
B7
B9
B10
P7
B8
M6
K10
H3
G3
M4
M10
K9
J9
F10
A10
E10
K3
C3
J3
C8
B12
M5
C11
C4138
1
5%
1/16W
MF-LF
402
10%
6.3V
CERM
402
D1
=FWPHY_DS0
=FWPHY_DS1
FWOHCI_LINKON_L
FWPHY_LKON_DS2
LCLK_L
LCLK_P
G2
FWOHCI_CLK98M_LCLK
PCLK_L
PCLK_P
G1
PINT_L
PINT_P
D2
LPS_L
LPS_P
C1
LREQ_L
LREQ_P
F2
CTL0
CTL1
H1
D0
D1
D2
D3
D4
D5
D6
D7
J2
R0
R1
N1
PD
B3
CYCLEOUT
GRST*
(IPU)
RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
(JTAG_TMS)
(JTAG_TDO)
(JTAG_TDI)
(JTAG_TCK)
(IPU)
PP1V96_FW_XTAL
TESTM
TESTW_VREG_PD
SE
SM
GND
H5
G9
G8
G7
G6
G5
F9
F8
F7
F6
E7
E6
N5
VSS
VSSA
SM
CLK98M_FW_XI_R
5%
1/16W
MF-LF
402
OUT
TRI-ST/NC
NC
GND
IN
40
IN
40
IN
40
R4170
1
1K
6 39 40 41
R4171
470
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
H2
FWPHY_CLK98M_PCLK
DS2 hard-strapped to 1,
page assumes no more than
2 FW800 connectors
Strap DSx high on unused ports.
F1
FWPHY_PINT
D3
FWOHCI_LPS
C2
FWOHCI_LREQ
J1
K2
K1
L1
L2
L3
M2
M3
R4175
10K
E2
NC
NC
5%
1/16W
MF-LF
402
NC
NC
NC
NC
NC
NC
NC
NC
R4185
6.34K
FWPHY_R0
FWPHY_R1
M1
1%
1/16W
MF-LF
402
91
K13
TPA0_P
TPA0_N
TPA1_P
TPA1_N
TPA2_P
TPA2_N
K14
TPB0_P
TPB0_N
TPB1_P
TPB1_N
TPB2_P
TPB2_N
M14
G13
E13
L14
F14
G14
B14
C14
N14
40
R4186
390K
TP_FWPHY_CNA
FWPHY_CPS
P12
TPBIAS0
TPBIAS1
TPBIAS2
=PPVP_FW_PHY_CPS
1
5%
1/16W
MF-LF
402
FWPHY_RESET_L
1
PLLGND
E1
B4
BMODE
10%
6.3V
CERM-X5R
402
Y4190
22
0.22UF
98P3040MHZ
R4191
=PP3V3_FW_FWPHY
P9
PHY_RESET*
(JTAG_TRST)
C4190
VCC
A11
A2
TP/NC TPBIASx
TP/NC TPAx_P/TPAx_N
Ground TPBx_P/TPBx_N
VOLTAGE=1.96V
E8
CNA
CPS
Unused Ports:
5%
1/16W
MF-LF
2 402
N9
R4190
4.7
1UF
10%
6.3V
CERM
402
DS0
DS1
LINKON_L
LKON_DS2_P
OHCI_PME*
PP1V96_FW_PLLVDD
C4139
1UF
=FWPHY_PC0
(IPU)
1K
10%
6.3V
CERM
402
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
FW_P0_TPA_P
FW_P0_TPA_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P2_TPA_P
FW_P2_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
H14
BI
40
BI
40
BI
40
BI
40
BI
40
BI
40 86
BI
40 86
BI
40 86
BI
40 86
BI
40
BI
C4189
0.22UF
10%
6.3V
CERM-X5R
402
PAGE TITLE
FireWire LLC/PHY (XIO2213B)

DRAWING NUMBER
J14
Apple Inc.
D14
E14
051-8600
VSSA_PCIE

SIZE
REVISION
A.0.0
C7
PC0
PC1
PC2
1394B OHCI & PHY
5%
1/16W
MF-LF
402
89
R4135 1
VOLTAGE=1.96V
47K
=PP3V3_FW_FWPHY
1UF
E9
C6
C4137
CLK98M_FW_XI
TP_FWOHCI_XO
REFCLK_P
REFCLK_M
H13
R4152
40
10%
6.3V
CERM
402
P3
CLKREQ*
FWXIO_REFCLK_SEL
220
5%
1/16W
MF-LF
402 2
A8
Alias =FWPHY_PC0
as appropriate
PCI EXPRESS
TXP
TXN
C5
220
1K
A3
C4
R4151 1
A9
OUT
40
R4150 1
10%
6.3V
CERM
402
1UF
P4
Multiple-ports:
PC[0:2] = 100
RXP
RXN
B6
X5R
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PERST*
C10
16V
X5R
A4
F5
16V
PCIE_FW_R2D_P
PCIE_FW_R2D_N
A7
10%
X5R
FW_RESET_L
A14
16V
PLACEMENT_NOTE=Place C4145 close to UA200

PLACEMENT_NOTE=Place C4146 next to C4145
5%
1/16W
MF-LF
402
1UF
10%
6.3V
CERM
402
C4135
XI
RSVD_19
Single-port:
PC[0:2] = 000
K8
5%
1/16W
MF-LF
402
IN
REF0_PCIE
REF1_PCIE
K7
2
10%
0.1uF
402
B13
A12
K6
0.1uF
X5R
84
10%
0.1uF
91 27
16V
A13
K5
FWXIO_REF0_PCIE
FWXIO_REF1_PCIE
J8
C4146
C4130
1UF
10%
6.3V
CERM
402
BGA
J7
PCIE_FW_D2R_N
0.1uF
DVDD_CORE
U4100
J6
OUT
2
10%
VDDA_15
XIO2213B
J5
84 18
VDD_15
OMIT
CRITICAL
H9
1%
1/16W
MF-LF
402
R4140 1
AVDD_3_3
H8
232
H7
R4141
DVDD_3_3 VDDA_33
H6
VDD_33
VDD_33_COM_IO
OUT
C4145
C4131
1UF
VDD_33_COMB
84 18
PCIE_FW_D2R_P
10%
6.3V
CERM
402
VDD_15_COMB
IN
C4141
1UF
2
J10
10%
6.3V
CERM
402
H10
1UF
2
(VDD_33_AUX)
C4140
PCIE_FW_R2D_C_N
FWXIO_VDD15COMB
FWXIO_VDD33COMB
FWXIO_VDD33COMIO
PLLVDD_CORE
PCIE_FW_R2D_C_P
C4119
PLLVDD_3_3
IN
10%
6.3V
CERM
402
G10
C4118
PLACEMENT_NOTE=Place C4140 close to U1400

PLACEMENT_NOTE=Place C4141 next to C4140
5%
1/16W
MF-LF
402
1UF
2
PP1V95_FW_FWPHY 40
FWXIO_REF_PCIE
10%
6.3V
CERM
402
E3
10%
6.3V
CERM
402
For single-port systems, all FW power should

be tied together and powered by S0 or by the
5K pull-down device detect circuit.
1K
1UF
10%
6.3V
CERM
402
VOLTAGE=1.5V
1UF
M7
C4117
FWRS0_FWXIO nets are OHCI/PCIe power, and

can be S0.
R4181
1UF
2
C4125
1UF
C4126
89
FW_FWPHY nets are PHY power, and for

multi-port systems must come from bus power.
PP3V3_FW_PLLVDD
Power Aliases:
41 40 39 6
C4127
PP3V3_FW_VDDA
VOLTAGE=3.3V
84 18
10%
6.3V
CERM
402
C4128
VOLTAGE=3.3V
89
1UF
2
C4108
N7
5%
1/16W
MF-LF
402
1UF
R4119 1
PP1V5_FW_VDDA
PP3V3_FW_AVDD
89
C4107
1UF
R4125 1
89
84 18
1
=PP1V5_FWRS0_FWXIO
BRANCH
PAGE
41 OF 110
SHEET
39 OF 92
Termination
Place close to FireWire PHY
39
FW_P0_TPBIAS
VOLTAGE=1.86V
1394 PHY 1.95V SUPPLY
C4250
10%
2 6.3V
CERM
402
CRITICAL
L4250
U4200
41 40 39 6
PP1V95_FW_FWPHY 39
6 IN
4 EN
SON
89
MAKE_BASE=TRUE
TPS799195
=PP3V3_FW_FWPHY
OUT 1
NR 2
VOLTAGE=1.96V
P1V95_FW_NR
5 NC
1UF
GND
10%
6.3V
CERM 2
402
C4201
THRML
PAD
0.01UF
C4202
18NH-250MA
0402
FW_P0_TPA_L_P
86
VOLTAGE=1.86V
NO_TEST=TRUE
R42501
20%
2 4V
X5R
402
56.2
1%
1/16W
MF-LF
402 2
39
39
39
39
0402
2.2UF
10%
16V
CERM 2
402
L4251
18NH-250MA
TI PHY "Peaking Inductors" To improve Data Eye.
86
C4200
1UF
TI PHY requires 1UF, not 0.33uF spec value.
FW_P0_TPA_L_N
VOLTAGE=1.86V
NO_TEST=TRUE
R4251
56.2
1%
1/16W
MF-LF
2 402
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R42521
56.2
FireWire Aliases For Connectivity

39
=FW_CLKREQ_L
FW_CLKREQ_L
1%
1/16W
MF-LF
402 2
15 18 25
FW_PORT0_TPA_P
FW_PORT0_TPA_N
FW_PORT0_TPB_P
FW_PORT0_TPB_N
41 86
41 86
41 86
41 86
R4253
56.2
1%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
86
39
=FW_PME_L
FW_PME_L
39
=PPVP_FW_PHY_CPS
PPVP_FW_PHY_CPS
FW_P0_TPB_L_N
86
VOLTAGE=0V
NO_TEST=TRUE
15 21
MAKE_BASE=TRUE
VOLTAGE=0V
NO_TEST=TRUE
L4252
41 89
MAKE_BASE=TRUE
FW_P0_TPB_L_P
L4253
18NH-250MA
18NH-250MA
2
0402
2
0402
FW_P0_TPA_C
R4254
C4254 1
220PF
5%
25V
CERM 2
402
1394 PHY STRAPPING OPTIONS
41 40 39 6
4.99K
1%
1/16W
MF-LF
2 402
=PP3V3_FW_FWPHY
NOSTUFF
2ND & 3RD TPA/TPB PAIR UNUSED
R4255 1R4256
10K
5%
1/16W
MF-LF
2 402
39
=FWPHY_DS0
FW_PHY_DS0
39
=FWPHY_DS1
FW_PHY_DS1
10K
5%
1/16W
MF-LF
2 402
39
FW_P1_TPBIAS
NC_FW_PORT1_TPBIAS
MAKE_BASE=TRUE
NO_TEST=TRUE
86 39
FW_P1_TPA_P
NC_FW_PORT1_TPA_P
86 39
FW_P1_TPA_N
NC_FW_PORT1_TPA_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.
MAKE_BASE=TRUE
NO_TEST=TRUE
R4258
10K
5%
1/16W
MF-LF
2 402
39
FW_P2_TPBIAS
NC_FW_PORT2_TPBIAS
MAKE_BASE=TRUE
NO_TEST=TRUE
86 39
FW_P2_TPA_P
NC_FW_PORT2_TPA_P
86 39
FW_P2_TPA_N
NC_FW_PORT2_TPA_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
39
=FWPHY_PC0
FW_PHY_PC0
MAKE_BASE=TRUE
PAGE TITLE
iMacs are now one port only and have Power Code "000"
FW: 1394B MISC
R4257
10K
DRAWING NUMBER
5%
1/16W
MF-LF
2 402
Apple Inc.
SIZE
A.0.0
051-8600
REVISION
BRANCH
PAGE
42 OF 110
SHEET
40 OF 92
CRITICAL
INRUSH RESETABLE PTC
F4301
0.3AMP-60V
1
2
PLACEMENT_NOTE=PLACE CLOSE TO F4300
XW4300
SMD030F-SM
CRITICAL
POUR COPPER TO SINK HEAT
R4300
1
0.33 2
P12V_S5_FW_CL
SSOT6
VOLTAGE=12V
5%
1W
MF
2512
12 VOLTS
7 WATTS MAX PER PORT
CRS08-1.5A-30V
40 89
D4300
SM
FDC610PZ
VOLTAGE=12V
PPVP_FW_PHY_CPS
VOLTAGE=12V
Q4300
P12V_S5_FW_R
SM
CRITICAL
FAST NON-RESETABLE FUSE

THIS FUSE WILL NOT BLOW
IT IS HERE FOR SAFETY ONLY
CRITICAL
CRITICAL
L4300
F4300
P12V_S5_FW_D
VOLTAGE=12V
89
FW_PORT0_VP_F
VOLTAGE=12V
603
1
3
MMBT2907AXG
D4301
60V-600MA
89
FW_PORT0_VP
VOLTAGE=12V
C4300
0.01UF
5.1V
2
SM
10%
50V
2 X7R
603-1
SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
MMBZ5231BXG
SOT23
Q4301
FERR-250-OHM
3AMP-32V
2 5
=PP12V_S5_FW
41 6
SOT23
R4352
51.1K2
FW_CURRENT_LIMIT
41
1%
1/16W
MF-LF
402
R4301
10K
FW_TURN_ON_V
5%
1/16W
MF-LF
2 402
Q4302
CRITICAL
DP4310
DP4310
5%
1/16W
MF-LF
2 402
C4310
BAV99DW-X-G
1
0.01UF
10%
50V
X7R 2
402
FW_FET_LINEAR_LIMIT_OUT 41
FW_FET_LINEAR_LIMIT_IN 41
SOT23
& "Late VG" Protection
CRITICAL
20K
5%
1/10W
MF-LF
2 603
PP3V3_FW_ESD "Snapback"
15K
FW_CURRENT_LIMIT_Q
MMBT2222A7F
89 41
R4302 R4303
SOT-363
2
BAV99DW-X-G
SOT-363
5
C4311 1
0.01UF
6
1
10%
50V
X7R 2
402
PORT 0
1394B
PLACE CLOSE TO COMPARITOR

1
1
C4302
0.01UF
R4307
20K
5%
1/16W
MF-LF
2 402
20%
16V
CERM
402
86 40
CRITICAL
FW_PORT0_TPB_N
J4300
1394B-K22
86 40
F-ANG-TH
FW_PORT0_TPB_P
TPB-
TPB(R)
9
2
86 40
100K 2
86 40
89 41
DP4311
C4312
R4305
41
FW_CURRENT_LIMIT
100K 2
FW_CURRENT_LIMIT_R
5%
1/16W
MF-LF
402
SOI-HF
1
41
FW_CURRENT_LIMIT_RD
FW_FET_LINEAR_LIMIT_IN
10%
50V
X7R 2
402
MMBZ5231BXG
0.01UF
NC
FW_FET_LINEAR_LIMIT_OUT
6
1
SOT-363
5
C4332
0.01UF
R43351
41
C4305 1
2.2UF
10%
16V
X5R 2
603
1M
514-0656
GND
C4335
0.1UF
1%
1/16W
MF-LF
402 2
PLACE CLOSE TO COMPARATOR
TPA(R)
10%
50V
CERM 2
402
10%
50V
X7R 2
402
0.001UF
3
C4313 1
VG
SHIELD
PINS
11
NOSTUFF
BAV99DW-X-G
SOT-363
2
TPA+
10
DP4311
BAV99DW-X-G
10%
16V
X7R-CERM
402
LM393
CRITICAL
TPA-
5
4
0.1UF
V+
D4303
SOT23
PP3V3_FW_ESD
CRITICAL
U4300
6
C4304
5.1V
FW_PORT0_TPA_P
FW_PORT0_TPA_R
SOT23
=PP12V_S5_FW
VP
SC/NC
BAS40XG
FW_FET_LINEAR_LIMIT_FB
5%
1/16W
MF-LF
402
41 6
D4302
R4304
TPB+
FW_PORT0_TPA_N
10%
50V
2 X7R
603-1
R4306
200K
5%
1/16W
MF-LF
2 402
ESD Rail
R4390
40 39 6
=PP3V3_FW_FWPHY
332
PP3V3_FW_ESD
41 89
VOLTAGE=3.3V
CRITICAL
D4390
SOT23
1
[ LATE VG NOTES ]
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP
1%
1/16W
MF-LF
402
MMBZ5227BLT1H
PAGE TITLE
FIREWIRE CONNECTOR
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
43 OF 110
SHEET
41 OF 92
SATA Activity LED
SATA PORT A0 FOR HDD
SILKSCREEN:HDD
CRITICAL
18 6
=PP3V3_S0_SATALED
J4510
EP00-081-91
DEVELOPMENT
C4510
M-ST-SM
1
92
84
92
84
2
3
C4511
SATA_HDD_R2D_P
SATA_HDD_R2D_N
2
10%
0.01UF
1
16V
CERM
402
16V
CERM
402
2
10%
0.01UF
SATA_HDD_R2D_C_P
IN
18 84
SATA_HDD_R2D_C_N
IN
18 84
R4599 1
330
5%
1/10W
MF-LF
603
4
5
92 84
92 84
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
C4515
C4516
10%
1
16V
CERM
10%
16V
SATA_HDD_D2R_N
OUT
18 84
SATA_HDD_D2R_P
OUT
18 84
SATALED_R_L
A
DEVELOPMENT
DS4599
402
0.01UF
518S0251
0.01UF
CERM
GREEN-3.6MCD
2.0X1.25MM-SM
402
18
PCH_SATALED_L
SILK_PART=SATA ACTIVE
SATALED_L
MAKE_BASE=TRUE
518-0361
SATA PORT A1 FOR SLIMLINE ODD
SILKSCREEN:ODD
SATA PORT A2 FOR SSD
J4520
1735574
CRITICAL
M-ST-TH
14
J4530
C4520
GND
A+
AGND
BB+
S2
92 84
10%
0.01UF
C4521
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_R2D_C_P
16V
CERM
10%
16V
CERM
S5
92 84
S6
92 84
IN
18 84
402
10%
0.01UF
C4523
S7
10%
0.01UF
P1
P2
89
16V
16V
CERM
SATA_ODD_D2R_N
OUT
18 84
SATA_ODD_D2R_P
OUT
18 84
402
CERM
P5
C4524
84
SATA_SSD_D2R_C_N
SATA_SSD_D2R_C_P
10%
1
C4532
C4533
=PP3V3_S0_ODD
C4525
16V
CERM
SATA_SSD_R2D_C_P
IN
18 84
SATA_SSD_R2D_C_N
IN
18 84
SATA_SSD_D2R_N
OUT
18 84
SATA_SSD_D2R_P
OUT
18 84
402
2
10%
16V
CERM
402
0.01UF
10%
16V
CERM
402
0.01UF
10%
16V
CERM
402
6 42
R45201
1UF
10%
6.3V
2 CERM
402
15
84
518S0251
1UF
P6
5
7
PP5V_S0_SATA_FET
P4
0.01UF
402
NET_PHYSICAL_TYPE=POWER
P3
C4531
SATA_SSD_R2D_P
84 SATA_SSD_R2D_N
84
0.01UF
C4522
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
C4530
M-ST-SM
18 84
SATA_ODD_R2D_C_N
0.01UF
IN
402
S4
KEY
MD
GND
GND
92 84
S3
GND
DP
+5V
+5V
S1
EP00-081-91
10%
6.3V
2 CERM
402
33K
5%
1/10W
MF-LF
603
SMC_ODD_DETECT
45 92
R4550
0
Q4500
5%
1/8W
MF-LF
805
42 6
NOSTUFF
R4500
ODD_PWR_LS5V_L
=PP3V3_S0_ODD
NOSTUFF
R45021
100K
5%
1/16W
MF-LF
402 2
6
D
100K 2
D
G
10%
10V
2 CERM
402
NOSTUFF
C4500
0.01UF
ODD_PWR_SS
5%
1/16W
MF-LF
402
10%
16V
CERM
402
Q4502
2N7002DW-X-G
ODD_PWR_EN
NOSTUFF
C4501
0.068UF
5%
1/16W
MF-LF
402 2
5 6
NOSTUFF
1
100K
NOSTUFF
R45011
2 3
=PP5V_S0_SATA
1
NOSTUFF
TPCP8102
23V1K-SM
3
D
SOT-363
S
1
Q4502
PAGE TITLE
2N7002DW-X-G
21 15
ODD_PWR_EN_L 5
ODD PWR CONTROL
SOT-363
SATA Connectors
DRAWING NUMBER
Apple Inc.
SIZE
A.0.0
051-8600
REVISION
BRANCH
PAGE
45 OF 110
SHEET
42 OF 92
CRITICAL
U4601
TPS2060
34
USB_EXTC_OC_L
35
USB_EXTD_OC_L
IN
USB/SMC DEBUG MUX
EN2*
GND TPAD
5%
1/16W
MF-LF
2 402
9
1
20%
10V
2 CERM
402
0.1UF
20%
2 10V
CERM
402
CRITICAL
1
C4631
20%
10V
2 CERM
402
89
SM
PP5V_USB2_PORT3_F
VOLTAGE=5V
C4630
0.01uF
(PUT CAP ON CONNECTOR SIDE)
=PP3V3_G3H_SMCUSBMUX
0.1UF
PP5V_USB2_PORT3
VOLTAGE=5V
20%
16V
CERM
402
C4650
0.1UF
20%
2 10V
CERM
402
C4606
CRITICAL
J4630
CRITICAL
330UF
20%
2 6.3V
POLY-TANT
CASE-D3L-SM
5 M+
4 M-
SMC_RX_L
SMC_TX_L
47 46 45
MOJOMUX
U4650
F-ANG-TH
5
L4631
120-OHM-90MA
VCC
47 46 45
USB-K22
CRITICAL
C4605
C4621
0.1UF
USB_PWR_ENA_L
89
OC2*
10K
L4630
FERR-250-OHM
OUT2 6
EN1*
5
4
R4600
CRITICAL
OC1*
OUT1
MSOP
DLP0NS
Y+ 1
Y- 2
VDD
DD+
GND
SYM_VER-1
85
USB_D_MUXED_N
85
USB_PORT3_N
PI3USB102ZLE
85 35
TQFN
85
SEL 10
8 OE*
2 5 3 4
6 VBUS
R4651
0
PRODUCTION
R4652
0
SLP1210N6
CRITICAL
CRITICAL
L4620
FERR-250-OHM
89
U4600
USB_EXTA_OC_L
8
3
35
TPS2060
OUT2 6
EN1*
89
5 OC2*
4
EN2*
USB_EXTB_OC_L
PP5V_USB2_PORT1
VOLTAGE=5V
0.1UF
C4601
0.1UF
20%
10V
2 CERM
402
20%
2 10V
CERM
402
CRITICAL
1
C4602
330UF
C4611
20%
2 10V
CERM
402
CRITICAL
20%
2 6.3V
POLY-TANT
CASE-D3L-SM
J4610
USB-K22
CRITICAL
F-ANG-TH1
5
L4611
120-OHM-90MA
DLP0NS
85 35
USB_EXTB_N
USB_EXTB_P
85
85
VDD
DD+
GND
SYM_VER-1
85 35
C4620
20%
16V
CERM
402
CRITICAL
CERM
402
0.1UF
PP5V_USB2_PORT2_F
VOLTAGE=5V
J4620
0.01uF
20% (PUT CAP ON CONNECTOR SIDE)
16V
C4603
C4610
GND TPAD
1
PP5V_USB2_PORT1_F
VOLTAGE=5V
SM
1
89
89
0.01uF
(PUT CAP ON CONNECTOR SIDE)
FERR-250-OHM
2
SM
L4610
MSOP
OC1*
PP5V_USB2_PORT2
VOLTAGE=5V
CRITICAL
OUT1 7
IN
USB_PORT1_N
USB_PORT1_P
3
4
F-ANG-TH
5
DLP0NS
VDD
DD+
GND
SYM_VER-1
85 34
85 34
USB_EXTC_N
USB_EXTC_P
85
85
USB_PORT2_N
USB_PORT2_P
6 VBUS
1
2
3
4
VBUS
DATADATA+
GND
514-0659
2 5 3 4
6 VBUS
1 GND
NC
IO
NC
IO
USB-K22
CRITICAL
L4621
120-OHM-90MA
VBUS
DATADATA+
GND
2 5 3 4
PORT 1
514-0659
RCLAMP0502N
CRITICAL
=PP5V_S3_USB
D4630
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1 GND
PRODUCTION
VBUS
DATADATA+
GND
45 46
2N7002
34
USB_PORT3_P
GND
Q4600
43 6
85
NC
IO
NC
IO
PM_EN_USB_PWR
USB_D_MUXED_P
SOT23-HF1
62
USB_DEBUGPRT_EN_L
SEL=0: CHOOSE SMC
SEL=1: CHOOSE USB
NC
IO
NC
IO
7 D+
6 D-
USB_EXTD_P
USB_EXTD_N
85 35
PORT 3
PORT 2
=PP5V_S3_USB
43 6
D4620
514-0672
1 GND
RCLAMP0502N
SLP1210N6
CRITICAL
D4610
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
L4600
FERR-250-OHM
1
PP5V_USB2_PORT0
VOLTAGE=5V
2
SM
89
PP5V_USB2_PORT0_F
VOLTAGE=5V
C4600
0.01uF
20% (PUT CAP ON CONNECTOR SIDE)
16V
CERM
402
CRITICAL
J4600
USB-K22
CRITICAL
F-ANG-TH1
5
L4601
120-OHM-90MA
DLP0NS
VDD
DD+
GND
SYM_VER-1
85 34
85 34
USB_EXTA_N
USB_EXTA_P
85
85
USB_PORT0_N
USB_PORT0_P
2
3
4
VBUS
DATADATA+
GND
PAGE TITLE
EXTERNAL USB CONNECTORS

DRAWING NUMBER
2 5 3 4
NC
IO
NC
IO
6 VBUS
PORT 0
89
Apple Inc.
051-8600
514-0672

D4600
RCLAMP0502N
SLP1210N6
CRITICAL
A.0.0
1 GND
SIZE
REVISION
BRANCH
PAGE
46 OF 110
SHEET
43 OF 92
CAMERA CONNECTOR & FILTER
BLURAY DECRYPTOR CONN & FLTR
CRITICAL
L4701
120-OHM-90MA
DLP0NS
SYM_VER-1
=PP3V3_S3_BRCRYPT
BRAY
85 34
J4760
AXK820225WG
BRAY
CRITICAL
L4760
120-OHM-90MA
DLP0NS
SYM_VER-1
85 20
85 20
USB_BRCRYPT_P
USB_BRCRYPT_N
NC
3
85
85 34
M-ST-SM
21
85
18 15
USB_BRCRYPT_L_P
USB_BRCRYPT_L_N
NC
BRCRYPT_RESET
1
3
5
7
9
11
13
15
17
19
USB_CAMERA_P
USB_CAMERA_N
92 85
BRCRYPT_PWR_EN
2
4
6
8
10
12
14
16
18
20
NC
=PP5V_S3_BRAY
NC
USB_IR_N
USB_IR_P
=PP5V_S3_IR
USB_IR_L_N
USB_IR_L_P
PP5V_S3_IR_FLT
VOLTAGE=5V
92 85
92 85
L4703
FERR-250-OHM
1
SM
PP5V_S3_CAMERA_FLT
C4701 1
0.1UF
4
5
VOLTAGE=5V
20%
10V
CERM 2
402
518S0668
LAYOUT NOTE:
PLACE C4700, C4701 & L4700
NEAR J4700 PINS 4 AND 5 IN THE
ORDER LISTED, AND NOT ON
BOTH SIDES OF THE PIN.
K37L (BLUETOOTH) CONNECTOR

CRITICAL
M-RT-SM
5
89
C4700
10UF
NC
NC
89
20%
6.3V
2 CERM
805-1
53261-8604
SYM_VER-1
85 34
1
2
FERR-250-OHM
2
SM
1UF
10%
402
53261-8605
M-RT-SM
SYM_VER-1
85 35
85 35
6
6
518S0667
6.3V
CERM
CRITICAL
J4720
L4720
120-OHM-90MA
DLP0NS
C4781
2
CRITICAL
USB_BT_N
USB_BT_P
92 85
92 85
USB_BT_L_N
USB_BT_L_P
1
2
3
4
5
L4721
=PP3V3_S3_BT
FERR-250-OHM
1
89
PP3V3_S3_BT_FLT
7
VOLTAGE=3.3V
SM
CRITICAL
C4720
10UF
C4721
0.1UF
20%
2 6.3V
CERM
805-1
NOSTUFF
518S0761
CRITICAL
53261-8606
7
85 35
92 85
92 85
USB_SDCARD_L_N
USB_SDCARD_L_P
PP3V3_S3_SDCARD_FLT
10K
3
4
518S0690
10%
6.3V
CERM
402
=PP3V3_S3_WM
FERR-250-OHM
NOSTUFF
FERR-250-OHM
89
PP12V_S3_WM_FLT
C4741
2
SM
Q4710
NOSTUFF
SOT-363
PP3V3_S3_WM_FLT
L4742
=PP12V_S3_WM
2N7002DW-X-G
89
VOLTAGE=3.3V
SM
6
D
GND
BRAID
L4741
89
1UF
1%
1/16W
MF-LF
402
SDCARD_RESET
USB_WM_L_N
85 USB_WM_L_P
85
NOSTUFF
C4750
R4750
1
VOLTAGE=3.3V
SM
85 20
USB_WM_N
USB_WM_P
SDCARD_RESET_L
92 91 25 21
85 20
FERR-250-OHM
SYM_VER-1
L4751
=PP3V3_S3_SDCARD
120-OHM-90MA
DLP0NS
CRITICAL
M-RT-SM
8
L4740
J4740
SM07B-SRKHFS-G
NOSTUFF
M-RT-SM
SYM_VER-1
USB_SDCARD_N
USB_SDCARD_P
WM CONNECTOR
CRITICAL
J4750
L4750
120-OHM-90MA
DLP0NS
85 35
518S0688
20%
2 10V
CERM
402
SD Card Reader Board Connector
J4780
L4702
120-OHM-90MA
DLP0NS
85 34
M-RT-SM
L4700
=PP5V_S3_CAMERA
CRITICAL
CRITICAL
J4700
53780-8605
CRITICAL
15 18
516S0823
IR RECEIVER CONNECTOR
92 85
CRITICAL
USB_CAMERA_L_P
USB_CAMERA_L_N
22
1UF
10%
16V
2 X5R
603
VOLTAGE=12V
1
NOSTUFF
C4740
1UF
10%
6.3V
2 CERM
402
R4751
10K
1%
1/16W
MF-LF
2 402
SDCARD_PLT_RST_R_L
Internal USB Connections
91 27
SDCARD_PLT_RST_L
DRAWING NUMBER
Q4710
Apple Inc.
2N7002DW-X-G
SOT-363
PAGE TITLE

SIZE
A.0.0
051-8600
REVISION
BRANCH
PAGE
47 OF 110
SHEET
44 OF 92
D
=PP3V3_G3H_SMC
46 45 6
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
91 63
IN
91 62
OUT
46
OUT
91 25 19
OUT
46
OUT
81
IN
81
IN
81
IN
81
IN
81
OUT
81 78
OUT
85 47 18
BI
85 47 18
BI
85 47 18
BI
85 47 18
BI
85 47 18
IN
91 27
IN
85 27
IN
47 18
BI
NC
PM_RSMRST_L
CPUIMVP_VR_ON
PM_PWRBTN_L
ESTARLDO_EN
SMC_VIDEO_ON
AUXCH_P_STATE
AUXCH_N_STATE
SMC_DP_HPD
BIDIVI_AUDIO_MUX_SEL
DPMUX_VIDEO_IN_SEL
NC
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
NC
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
46
48
BI
46
OUT
46
OUT
(OC)
SMC_GFX_THROTTLE_L
NC
NC
NC
47 46 45 43
OUT
47 46 45 43
IN
48
BI
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
103
102
101
100
99
98
97
96
121
122
123
124
125
126
127
128
SMC_PM_G2_R
P60
P61
P62
P63
P64
P65
P66
P67
78
79
80
81
82
83
84
85
P20
P21
P22
P23
P24
P25
P26
P27
P70
P71
P72
P73
P74
P75
P76
P77
68
69
70
71
72
73
74
75
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P30
P31
P32
P33
P34
P35
P36
P37
P80
P81
P82
P83
P84
P85
P86
129
130
131
132
133
134
135
SMC_WAKE_SCI_L
P90
P91
P92
P93
P94
P95
P96
P97
24
23
22
21
20
19
18
17
136
137
138
2
3
4
5
6
P40
P41
P42
P43
P44
P45
P46
P47
16
15
14
P50
P51
P52
(OC)
R4950
U4900
H8S2117
TQFP
(1 OF 3)
OMIT
NC
NC
NC
NC
NC
89 46
SMC_PM_G2_EN OUT
46 45 6
PP3V3_G3H_AVREF_SMC
=PP3V3_G3H_SMC
5%
1/16W
MF-LF
402
SMC_ADAPTER_EN
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLPS3_BUF2_L
SMC_P94
NOTE:
PM_SLP_S4_S5
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
C4902
22UF
OUT
46
IN
46
IN
49 88
IN
49 88
IN
50 88
IN
50 88
IN
46
IN
46
IN
46
IN
46
OUT
18
IN
R4999
1
4.7
C4904
0.1UF
20%
10V
CERM
402
2mA/1mA/5uA
20%
10V
CERM
402
C4905
20%
10V
CERM
402
0.1UF
C4906
0.1UF
20%
10V
CERM
402
SMC_VCL
Peak/Ave/Standby= 2mA/1mA/5uA
5%
1/16W
MF-LF
402
89
PP3V3_G3H_SMC_AVCC
VOLTAGE=3.4V
C4920
20%
10V
CERM
402
AVCC
VCC
VCL AVREF
43 45 46 47
IN
43 45 46 47
=PP3V3_G3H_SMC
88 46
6 45 46
88 46
48
BI
SMC_RESET_L
SMC_XTAL
SMC_EXTAL
143
144
RES*
XTAL
EXTAL
10K
R4901
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
SMC_KBC_MDE
MD1
MD2
9
25
NMI
11
SMC_NMI
ETRST*
27
SMC_TRST_L
AVSS
67
IN
47
47
1 NOSTUFF
R4952
IN
46
IN
46
IN
46
IN
6 46
10K
5%
1/16W
MF-LF
2 402
R4954
0
Rename to BaseArch
5%
1/16W
MF-LF
402
9 85 91
48
BI
R4909 1
TQFP
15 19 47 91
IN
H8S2117
(3 OF 3)
OMIT
91 47 46
10%
6.3V
CERM-X5R
402
U4900
PLACEMENT_NOTE=Place R4999 close to U4900 pin 76

PLACEMENT_NOTE=Place C4920 close to U4900 pin 76
19 47
C4907
0.47UF
0.1UF
OUT
IN
C4903
0.1UF
PLACEMENT_NOTE=Place C4907 close to U4900 pin 13
IN
OUT
20%
6.3V
CERM
805
19 46
Peak/Ave/Standby
Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA
13
IN
P10
P11
P12
P13
P14
P15
P16
P17
5%
1/16W
MF-LF
2 402
77
OUT
112
110
109
108
107
106
105
104
10K
1
36
86
46
91 63
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD_SMC
RSMRST_PWRGD
R4951
76
OUT
NOSTUFF
PM_SLP_S4_2_L
PM_SLP_S5_L
IN
IN
VSS
19 46 91
NOSTUFF
XW4900
SM
IN
47
NOSTUFF
R4902
10K
19 91
7
42
95
111
139
46
Remove R4950,R4951 after Proto-1

1
5%
1/16W
MF-LF
2 402
R4998
10K
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
R4953
NOTE: P94 and P95 are shorted, P95 could be spare.
5%
1/16W
MF-LF
402
GND_SMC_AVSS
46 49 50 88
R4955
1
(DEBUG_SW_1)
(DEBUG_SW_2)
OUT
91 27 19
OUT
46 43
OUT
46
IN
46
IN
46
91 19 15
SMC_PA0
SPI_DESCRIPTOR_OVERRIDE_L (OC)
PM_SYSRST_L
(OC)
USB_DEBUGPRT_EN_L
(OC)
MEM_EVENT_A_L
(OC)
MEM_EVENT_B_L
(OC)
SYS_ONEWIRE
(OC)
PM_BATLOW_L
(OC)
46
18 15
BI
OUT
NC
21 15
OUT
92 42
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_PB3
(See below)
SMC_EXCARD_CP
46
51
IN
46
IN
46
IN
52
OUT
52
OUT
53
OUT
46
OUT
52
IN
52
IN
53
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
NC
41
40
39
38
37
35
34
33
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
120
119
118
117
116
115
114
113
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
94
93
92
91
90
89
88
87
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
66
65
64
63
62
61
60
59
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
U4900
H8S2117
TQFP
(2 OF 3)
OMIT
PE0
PE1*
PE2*
PE3*
PE4*
PF0
32
31
30
29
28
50
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
G3_POWERON_L
PF1
PF2
PF3
PF4
PF5
PF6
PF7
49
48
47
46
45
44
43
SMC_SYS_LED
SMC_LID
BIDIVI_AUX_TERM_EN
BIDIVI_PNL_PWR_EN
SMC_PF5
BIDIVI_BKL_ON
BIDIVI_BKL_PWM
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
58
57
56
55
54
53
52
51
PH0
PH1
PH2
PH3
PH4
PH5
10
12
26
140
141
142
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN
46
IN
46 47
IN
46 47
OUT
5%
1/16W
MF-LF
402
REMOVE R4953/4/5 AFTER PROTO-1
46 47
IN
46 47
IN
46
OUT
46
OUT
46
OUT
81
OUT
81
OUT
81
46
OUT
SMC_PNL_BL_PWM
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
IN
IN
IN
81
46 81
46
BI
48
BI
48
BI
48
BI
48
BI
48
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
48
OUT
46
OUT
46
OUT
46
46
NC
NC
PAGE TITLE
SMC
DRAWING NUMBER
Apple Inc.
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)
SIZE
A.0.0
SMC_PB3:
051-8600
REVISION
BRANCH
PAGE
49 OF 110
SHEET
45 OF 92
=PP3V3_G3H_SMC
C5000
CRITICAL
0.1uF
20%
10V
CERM
402
DEVELOPMENT
S5000
NTC020-CC1J-B260T
1
SM
CD
NC
GND
45
SMC_PBUS_VSENSE
88
SMC_CPU_INPUT_VSENSE
MAKE_BASE=TRUE
45
SMC_BATT_ISENSE
45
SMC_NB_MISC_ISENSE
10K
81 45
GND_SMC_AVSS 45
45
46 49 50 88
47 45 43
5%
1/16W
MF-LF
402
SMC_CPU_VTT_ISENSE
SMC_RESET_L
OUT
45 47 91
47 45 43
45
49 88
45
SMC_CPU_VTT_VSENSE
47 45
49 88
MAKE_BASE=TRUE
47 45
47 45
47 45
1.3uA
PORT D ANALOG SENSORS (INTERNAL PULLUPS)
SILK_PART=SMC RESET
45
SMS_X_AXIS
45
SMS_Y_AXIS
SMC_CPU_1V5_VSENSE
45
49 88
45
MAKE_BASE=TRUE
45
SMC_DIMM_1V5_VSENSE
50 88
MAKE_BASE=TRUE
45
SMS_Z_AXIS
45
SMC_CPU_1V8_ISENSE
49 88
MAKE_BASE=TRUE
45
SMC_ANALOG_ID
SMC_CPU_1V8_VSENSE
49 88
MAKE_BASE=TRUE
45
SMC_XTAL
Y5020
20.000M
SM-4
ALS_LEFT
45
ALS_RIGHT
S5010
1
SM
1K
45
45
NC_ALS_RIGHT
10K
GND_SMC_AVSS 45
45
ALS_GAIN
45
SMC_EXCARD_PWR_EN
45
SMS_ONOFF_L
5%
1/16W
MF-LF
402
45
45
SMC_RSTGATE_L
46 45
NC_ALS_GAIN
45
NO_TEST=TRUE
TP_SMC_EXCARD_PWR_EN
91 63 62 37 33 32 19 5
80
TP_SMS_ONOFF_L
45 6
MAKE_BASE=TRUE
SMC_ONOFF_L
OUT
45 46
50 49 46 6
MAKE_BASE=TRUE
46 49 50 88
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
91 45 19
R5093
R5099
MEM_EVENT_B_L
SMC_GFX_OVERTEMP_L
SMC_CASE_OPEN
PM_SLP_S3_L
MAKE_BASE=TRUE
PM_SLPS3_BUF1_L
PM_SLPS3_BUF2_L
PM_SLP_S4_2_L MAKE_BASE=TRUE
10K
10K
R5046
R5094
10K
100K
R5089
100K
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMC_P41
=PP3V3_S0_SMC
5%
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
45
5%
1/16W
MF-LF
402
45
UNUSED TP/NC ALIASES
R5010
45 43
10K
100K
10K
10K
100K
2.0K
100K
10K
10K
10K
10K
10K
10K
10K
100K
100K
10K
10K
10K
10K
10K
10K
R5004
MAKE_BASE=TRUE
CRITICAL
NTC020-CC1J-B260T
10K
45 19
5%
1/16W
MF-LF
402
50 88
NC_ALS_LEFT
DEVELOPMENT
SMC_DIMM_1V5_ISENSE
518S0665
2
5%
50V
CERM
402
49 88
MAKE_BASE=TRUE
22PF
SMC_EXTAL
SMC_NB_DDR_ISENSE
POWER_BUTTON_L
C5021
2
88 45
M-RT-SM
3
5%
50V
CERM
402
CRITICAL
45
J5010
SMC_CPU_1V5_ISENSE
MAKE_BASE=TRUE
53261-8602
22PF
88 45
45
SILK_PART=PWR BTN
C5020
MAKE_BASE=TRUE
POWER BUTTON
SMC Crystal Circuit
SMC_NB_CORE_ISENSE
45
R5003
R5032
R5033
R5034
R5035
R5036
R5037
R5038
R5039
R5040
R5041
R5042
R5043
R5096
R5092
R5095
R5097
R5047
R5049
R5098
R5091
R5087
R5086
SMC_ONOFF_L
SMC_PNL_BL_PWM
SMC_PH2
SMC_TX_L
SMC_RX_L
SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_EXCARD_OC_L
SMC_PA0
SMC_BIL_BUTTON_L
SMC_FAN_3_CTL
SMC_FAN_3_TACH
SMC_BC_ACOK
SMC_ADAPTER_EN
USB_DEBUGPRT_EN_L
=SMC_SMS_INT
SMC_SMS_INT
MAKE_BASE=TRUE
SMC_LID
G3_POWERON_L
46 45
R5002
SMC_CPU_INPUT_ISENSE
=PP3V3_G3H_SMC
46 45 6
MAKE_BASE=TRUE
0.01UF
OUT
IN
88
10K
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
SOT23-5-HF
10%
16V
CERM
402
R5000
SMC_DCIN_ISENSE
5%
1/16W
MF-LF
2 402
NCP303LSN
NC
C5001
45
1K
U5000
SMC_MANUAL_RST_L
PORT 7 ANALOG SENSORS

1
R5001
SMC Reset Button / Brownout Detect

46 45 6
TP_SMC_P41
MAKE_BASE=TRUE
C5010
45
ESTARLDO_EN
45
SMC_SYS_LED
45
SMC_PF5
TP_ESTARLDO_EN
MAKE_BASE=TRUE
0.1UF
20%
10V
CERM
402
TP_SMC_SYS_LED
SMC PROCHOT 3.3V LEVEL SHIFTING
MAKE_BASE=TRUE
TP_SMC_PF5
MAKE_BASE=TRUE
SILK_PART=SYS POWER
45
SMC_PB3
TP_SMC_PB3
64 46 16 13 11 6
CRITICAL
SOT23-3
IN
C5065
46 45
45 89
SMC_GFX_OVERTEMP_L
MXM_ALERT_L
45
SMC_GFX_THROTTLE_L
45
CPUIMVP_VR_ON
MXM_PWR_LEVEL
74
5uA
C5066
TO CPU
20%
6.3V
X5R
603
3.3K
11
BI
CPU_PROCHOT_L
TABLE_ALT_HEAD
C5067
PART NUMBER
ALTERNATE FOR
PART NUMBER
353S1381
353S1912
0.01UF
10%
16V
CERM
402
BOM OPTION
REF DES
COMMENTS:
ALL
Intersil ISL60002-33
45
IN
SMC_PROCHOT
D
G
Q5077
MMDT3904-X-G
SOT-363-LF
Q5077
MMDT3904-X-G
Q5095
SOT-363-LF
SOT-363
45
OUT
CPU_PROCHOT_L_R
2N7002DW-X-G
TO SMC
CPU_PROCHOT_BUF
5%
1/16W
MF-LF
402
FROM SMC
TABLE_ALT_ITEM
3.3K
SMC_PROCHOT_3_3_L
5%
1/16W
MF-LF
402 2
R5071
1
63 91
MAKE_BASE=TRUE
10uF
10%
6.3V
CERM-X5R
402
SMC_DELAYED_PWRGD
470
5%
1/16W
MF-LF
402 2
R5070 1
74
MAKE_BASE=TRUE
R5078 1
=PPVTT_S0_CPU
MAKE_BASE=TRUE
VOLTAGE=3.3V
OUT
0.47UF
PP3V3_G3H_AVREF_SMC
REF3333
GND
3
MISC. SIGNAL ALIASES
VR5065
=PP3V42_G3H_AVREF
=PP3V3_S0_SMC_LS
51 46 6
MAKE_BASE=TRUE
SMC AVREF Supply
GND_SMC_AVSS
45 46 49 50 88
VOLTAGE=0V
SMC & MXM THERMTRIP LEVEL SHIFTING

51 46 6
PM_EXTTS_L / MEM_EVENT LEVEL SHIFTING

64 46 16 13 11 6
10K
R5085
10K
5%
1/16W
MF-LF
2 402
NOSTUFF
R5082
10K
5%
1/16W
MF-LF
2 402
=PPSPD_S0_MEM_A
R50801
10K
A
31 30
FROM DIMMS
MEM_EVENT_L
IN
6 NOSTUFF
Q5080
5%
1/16W
MF-LF
402
PM_EXT_TS_L<1>
TO CPU
3 NOSTUFF
MXM
Q5096
MXM
11 21 91
Q5095
2N7002DW-X-G
SOT-363
OUT
PULL-UP ON PAGE 14
2N7002DW-X-G
SOT-363
S
1
2N7002DW-X-G
IN
MXM_OVERT_L
11 91
SOT-363
45
FROM MXM
IN
SMC_THRMTRIP
FROM SMC
SOT-363
S
1
SOT-363
PAGE TITLE
SMC Support
4
45
PM_THRMTRIP_L
Q5096
11 91
2N7002DW-X-G
5%
1/16W
MF-LF
402
Q5080
D
5
5%
1/16W
MF-LF
402
MXM_THRMTRIP
74
PM_EXT_TS_L<0>
R5069
2N7002DW-X-G
MEM_EVENT
5%
1/16W
MF-LF
402 2
R5079
1
30 6
NOSTUFF
5%
1/16W
MF-LF
2 402
MXM_THRMTRIP_L 1
3.3K
5%
1/16W
MF-LF
2 402
10K
=PP3V3_S0_SMC
R5068
R5083
R5018
MXM
MXM
=PPVTT_S0_CPU
1
50 49 46 6
MXM
=PP3V3_S0_SMC_LS
MEM_EVENT_A_L
DRAWING NUMBER
MAKE_BASE=TRUE
Apple Inc.
TO/FROM SMC
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
50 OF 110
SHEET
46 OF 92
LPC+SPI Connector
FRANK CONNECTOR
CRITICAL
LPCPLUS
J5100
55909-0374
6
6
85 45 18
BI
85 45 18
BI
85 47
IN
85 47
OUT
85 45 18
IN
91 45 19 15
OUT
46 45
OUT
91 27
IN
46 45
OUT
45
IN
45
OUT
46 45 43
IN
M-ST-SM
31
32
=PP3V3_G3H_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD<0>
LPC_AD<1>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
BI
BI
OUT
27 85
18 45 85
18 45 85
21 47 85
IN
47 85
IN
47 85
BI
18 45
IN
19 45
OUT
45 46
OUT
45 46
OUT
45 46 91
OUT
45
OUT
43 45 46
OUT
21
516S0573
Alternate SPI ROM Support

47 6
54 6
=PP3V3_S5_LPCPLUS
=PP3V3_S5_ROM
1
20K
5%
1/16W
MF-LF
402 2
85 54
OUT
SPI_MLB_CS_L
C5144
47 6
=PP3V3_S5_LPCPLUS
0.1UF
R51441
20%
2 10V
CERM
402
LPCPLUS
R5140 1
100K
5%
1/16W
MF-LF
402 2
U5100
NC7SB3157P6XG
PATH=I96
SC70
1 B1
SEL 6
SPIROM_USE_MLB
MAKE_BASE=TRUE
21 47 85
2 GND
VCC 5
LPCPLUS
R5145
0
85 47
OUT
SPI_ALT_CS_L
Pull-up on debug card
4
B0
VER 1
CRITICAL
85
SPI_CS0_L
2
SPI_CS0_R_L IN 18 85
5% PLACEMENT_NOTE=Place near U1400
1/16W
MF-LF
402
PRODUCTION
R5146
5%
1/16W
MF-LF
402
2
PLACEMENT_NOTE=PLACE NEXT TO U5100
SPI Bus Series Resistance Option

LPCPLUS
R5156
85 47
OUT
SPI_ALT_CLK
85 47
OUT
SPI_ALT_MOSI
LPCPLUS
R5158
85 47
IN
SPI_ALT_MISO
PLACEMENT_NOTE=Place next to R6105
SPI_CLK_R
IN
18 54 85
SPI_MOSI_R
IN
18 54 85
OUT
18 54 85
LPCPLUS
R5157
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SPI_MISO
5%
1/16W
MF-LF
402
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
51 OF 110
SHEET
47 OF 92
PCH "SMBUS" CONNECTIONS
PCH "SML 0" CONNECTIONS
SMC "A" SMBus Connections

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE
=PP3V3_S3_SMBUS
48 6
NOSTUFF
R5200
PCH
88 18
88 18
5%
1/16W
MF-LF
402
=PP3V3_S3_SMBUS_SMC_A_S3
NOSTUFF
1
6.8K
U1800
(MASTER)
=PP3V3_S0_SMBUS
R5201
6.8K
5%
1/16W
MF-LF
402
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
R5202
MEMORY A VREF
PCH
U2900
(WRITE: 0X7C READ: 0X7D)
U1800
(MASTER)
=I2C_VREFMRGN_A_SCL
28
88 18
=I2C_VREFMRGN_A_SDA
28
88 18
8.2K
5%
1/16W
MF-LF
402
R5203
R52701
SMC
8.2K
SML_PCH_0_CLK
MAKE_BASE=TRUE
SML_PCH_0_DATA
MAKE_BASE=TRUE
R5271
4.7K
5%
1/16W
MF-LF
402 2
45
SMB_A_S3_CLK
88
45
SMB_A_S3_DATA
88
ALS
4.7K
U4900
(MASTER)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
SMBUS_SMC_A_S3_SCL
(WRITE: 0X72 READ: 0X73)
TP_I2C_ALS_SCL
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
TP_I2C_ALS_SDA
MAKE_BASE=TRUE
MEMORY B VREF
U2910
=I2C_VREFMRGN_B_SCL
28
=I2C_VREFMRGN_B_SDA
28
POTENTIAL SMC SLAVE SMBUS CONNECTIONS

6
=PP3V3_S0_SMBUS_SMC_BSA
R5280 1
SMC
3
91 72 63
PGOOD_P3V3_S0
5%
1/16W
MF-LF
2 402
SI2302ADSE3
SOT23-3-HF
Q5201
SI2302ADSE3
45
SOT23-3-HF
88
R5260 1
2.2K
5%
1/16W
MF-LF
402
SMB_B_S0_CLK
88
R5261
2.2K
5%
1/16W
MF-LF
402
SMBUS_SMC_BSA_SCL
J3100-A/B
(Write: 0xA0 Read: 0xA1)
(WRITE: 0XA2 READ: 0XA5)
=I2C_SODIMMA_SCL
30
=I2C_SODIMMA_SDA
45
SMB_B_S0_DATA
SMBUS_SMC_BSA_SDA
SMBUS_SMC_B_S0_SCL
88
SMBUS_SMC_B_S0_SDA
EMC1047-2 HEX DIODE SENSOR

DIODE
FUNCTION
30
=I2C_SODIMMB_SDA
=SMB_REMOTE_TEMP_SCL
51
=SMB_REMOTE_TEMP_SDA
51
1
2
3
4
5
ODD TEMP
LCD TEMP
AMBIENT TEMP
CPU HEATSINK
MXM HEATSINK
AC/DC PS TEMPS
SMC
EMC1403-[1,2]: ACDC THRU J600
U4900
(MASTER)
(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)
R5290 1
4.7K
45
SMB_MGMT_CLK
88
45
SMB_MGMT_DATA
88
R5291
4.7K
5%
1/16W
MF-LF
402 2
3 SENSE POINTS - PRIMARY, SECONDARY, AMB
3.3K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
=SMB_ACDC_SDA
=I2C_AUDIO_SCL
61
=I2C_AUDIO_SDA
61
AC/DC PS POWER
CK505
U2600
(WRITE: 0XD2 READ: 0XD3)
=SMBUS_XDP_SCL
88
=SMBUS_XDP_SDA
88
SMBUS_PCH_S0_CLK
MAKE_BASE=TRUE
SMBUS_PCH_S0_DATA
MAKE_BASE=TRUE
=SMBUS_CK505_SCL
26
=SMBUS_CK505_SDA
26
79
=I2C_DP_EQLZ_SDA
79
U9100
=I2C_DP_DRV_SCL
78
=I2C_DP_DRV_SDA
78
XDP
25
=I2C_DP_EQLZ_SCL
DP TX EQLZ CONTROL
INA219: ACDC THRU J600
J2500/J2550
(MASTER)
25
U9200
OUTPUT VOLTAGE, CURRENT, POWER
5%
1/16W
MF-LF
2 402
DP RX EQLZ CONTROL
MAKE_BASE=TRUE
31
3.3K
MAKE_BASE=TRUE
=SMB_ACDC_SCL
MIKEY
R5209
77
=PP3V3_S0_SMBUS_SMC_MGMT
U6806
1
77
=SMB_DP_TCON_SDA
SMC "MANAGEMENT" SMBUS CONNECTIONS
(WRITE: 0X80, READ: 0X81))
R5208 1
=SMB_DP_TCON_SCL
REMOTE TEMPS
J3200-A/B
=I2C_SODIMMB_SCL
31
=PP3V3_S0_SMBUS
DP RX MASTER FOR MCCS

SMC SLAVE ADDRESS TBD
MAKE_BASE=TRUE
MEMORY B DIMMS
48 6
DISPLAY TCON
EMC1047-2, U5500, SEE TABLE

MAKE_BASE=TRUE
MEMORY A DIMMS
88
SMB_BSA_DATA
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
U4900
(MASTER)
NOSTUFF
5%
1/16W
MF-LF
402 2
SMB_BSA_CLK
45
=PP3V3_S0_SMBUS_SMC_B_S0
SMC
45
R5281
100K
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
R52101
100K
U4900
(MASTER)
SMC "B" SMBus Connections
R5211
NOSTUFF
Q5200
1
THIS CONNECTION IS BROKEN THROUGH

NOSTUFF RESISTORS ON PAGE 90
SMC "0" SMBus Connections

6
=PP3V3_S0_SMBUS_SMC_0_S0
R5250
SMC
PCH "SML 1" CONNECTIONS

48 6
=PP3V3_S0_SMBUS
PCH
U1800
(SLAVE)
88 18 SML_PCH_1_CLK
MAKE_BASE=TRUE
88 18 SML_PCH_1_DATA
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402 2
45
SMB_0_S0_CLK
88
45
SMB_0_S0_DATA
88
MXM TEMP
R5251
4.7K
5%
1/16W
MF-LF
2 402
GPU ON CARD - J8400

NV INSIDE (WRITE: 0X9E READ: 0X9F)
MXM CARD (WRITE: 0X98 READ: 0X99)
SMBUS_SMC_0_S0_SCL
74
=SMB_MXM_THRM_SDA
74
R5204
MAKE_BASE=TRUE
NOSTUFF
1
8.2K
5%
1/16W
MF-LF
402 2
SMBUS_SMC_0_S0_SDA
Also reserve 0x56 and 0x32 per spec
R5205
8.2K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
DIE TEMPS
R5206
PAGE TITLE
EMC1402-2: U5535
(WRITE: 0X9A READ: 0X9B)
51
=SMB_CPU_THRM_SDA
51
SMBus Connections
DRAWING NUMBER
R5207
=SMB_CPU_THRM_SCL
Apple Inc.
051-8600
SIZE
REVISION
A.0.0
DIODE1: CPU
5%
1/16W
MF-LF
402
=SMB_MXM_THRM_SCL
MAKE_BASE=TRUE
NOSTUFF
4.7K
U4900
(MASTER)
BRANCH
PAGE
52 OF 110
SHEET
48 OF 92
CPU 1.5V CURRENT SENSE
CPU 1.5V VOLTAGE SENSE
NOSTUFF
R5309
0.002
PP1V5_S3_REG
1
3
70 50 6
1%
1/4W
MF-LF
1206
CPU Voltage Sense / Filter

PP1V5_CPU_MEM
2
4
R5359
6 89
IMAX = 6A
R5300
89 64 13
0.002
PP1V5_S0_FET
1
3
72 6
SENSE_CPU_1V5_S3_P
88 SENSE_CPU_1V5_S3_N
NOSTUFF
R53081
0
5%
1/16W
MF-LF
402 2
88
NOSTUFF
R5307 R53061
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
88
SENSE_CPU_1V5_N
88
SENSE_CPU_1V5_P
4.53K2
2
4
SMC_CPU_1V5_VSENSE
=PP3V3_S0_SMC
SENSE_CPU_1V5_S0_P
88 SENSE_CPU_1V5_S0_N
R5305
1%
1/16W
MF-LF
402
6 46 49 50
5%
1/16W
MF-LF
2 402
GND_SMC_AVSS
SC70
OUT
4 IN+
88
GND_SMC_AVSS
45 46 49 50 88
CPU CURRENT SENSE AMP & FILTER

R5363
4.53K2
SMC_CPU_1V5_ISENSE
SMC_CPU_1V5_ISENSE_R 1
1%
1/16W
MF-LF
402
REF 1
GND
353S2073
GAIN = 200V/V
NOSTUFF
R53031
46 88
C5301
=PP5V_S0_ISENSE
21K
88
1%
1/16W
MF-LF
402
C5360
1
20%
6.3V
2 X5R
402
GND_SMC_AVSS
R5360
45 46 49 50 88
89 64
IN
VR_CPU_IMON
10K
88
1%
1/16W
MF-LF
402
VR_ISNS_CPU_P
VR_ISNS_CPU_N
3
2
PPVTT_S0_CPU_REG
67 6
R5319
0.0005
2
4
1%
1W
MF
0612
CPU VTT VOLTAGE SENSE

6 89
89 67 13
CPU_VTTSENSE_P
1
3
6 46 49 50
4.53K2
1%
1/16W
MF-LF
402
=PP3V3_S0_SMC
C5310
20%
2 6.3V
X5R
402
V+
88
SENSE_CPU_VTT_P 4 IN+
OUT 6
CRITICAL
88
SMC_CPU_VTT_ISENSE_R
1%
1/16W
MF-LF
402
REF 1
OUT
45 88
C5362
0.22UF
10%
2 6.3V
CERM-X5R
402
45 46 49 50 88
0.22UF
45 46 49 50 88
SMC_CPU_1V8_ISENSE
4.53K2
SMC_CPU_VTT_ISENSE
GND
353S2208
GAIN = 100V/V
46 88
R5311
INA214
IMAX = 2.79V
5%
1/16W
MF-LF
402
AMPLIFIED AND FILTERED ISNS TO SMC
5.1K 2 SMC_CPU_ISENSE
1
C5312
GND_SMC_AVSS
U5310
SC70
CRITICAL
R5364
GND_SMC_AVSS
1%
1/16W
MF-LF
2 402
SMC_CPU_VTT_VSENSE
OPA348
SC70-5
20%
2 6.3V
X5R
402
0.22UF
SENSE_CPU_VTT_N 5 IN-
10K
R5312
PPVTT_S0_CPU
88
R5361
PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)
U5360
4
88
IMAX = 35A
20%
16V
CERM
402
IMAX = 0.9V
CPU VTT CURRENT SENSE
SNS_PS_CPU_ISNS
0.01UF
0.22UF
10K
5%
1/16W
MF-LF
402 2
45 46 49 50 88
PLACE C CLOSE TO SMC
R5301
INA210
20%
6.3V
X5R
402
20%
6.3V
2 X5R
402
U5300
5 IN-
45 88
0.22UF
0.22UF
C5300
OUT
C5359
PLACE R CLOSE TO CPU
46 88
20%
6.3V
2 X5R
402
V+
SMC_CPU_VSENSE
C5302
0.22UF
4.53K
1%
1/16W
MF-LF
402
R5302
88
1%
1/4W
MF-LF
1206
CPU_VCC_PKG_SENSE_P
46 88
46 88
NOSTUFF
C5311
R5324
0.22UF
10K
20%
6.3V
2 X5R
402
5%
1/16W
MF-LF
402 2
GND_SMC_AVSS
C5321
0.22UF
20%
6.3V
2 X5R
402
45 46 49 50 88
GND_SMC_AVSS
45 46 49 50 88
WOULD PREFER A GAIN OF 150V/V
CPU 1.8V CURRENT SENSE
PP1V8_S0_REG
70 6
R5320
1
CPU 1.8V VOLTAGE SENSE

PP1V8_S0_CPU
6
89
IMAX = 1.35A
5%
1/8W
MF-LF
805
R5322
4.53K2
1%
1/16W
MF-LF
402
SMC_CPU_1V8_VSENSE
46 88
C5322
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
45 46 49 50 88
PAGE TITLE
CPU POWER SENSE

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
53 OF 110
SHEET
49 OF 92
1.5V S3 VOLTAGE SENSE
R5402
70 49 6
4.53K2
PP1V5_S3_REG
IMAX = 11.3A
SMC_DIMM_1V5_VSENSE
1%
1/16W
MF-LF
402
46 88
C5402
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
SMC_DIMM_1V5_ISENSE
45 46 49 50 88
46 88
R5403
10K
5%
1/16W
MF-LF
402 2
GND_SMC_AVSS
45 46 49 50 88
C
MXM PWRSRC CURRENT SENSE
MXM
CRITICAL
R5430
MXM PWRSRC VOLTAGE SENSE
PPV_S0_MXM_PWRSRC
MAKE_BASE=TRUE
89
0.002
=PPV_S0_MXM_PWR
1
3
1%
1/4W
MF
1206
MXM
=PPV_S0_MXM_PWRSRC
2
4
R5433
73
18.2K2
IMAX = 6A
=PP3V3_S0_SMC
1%
1/16W
MF-LF
402
6 46 49
C5430
0.22UF
88
MXM_ISENSE_P
5 IN-
INA210
SC70
4 IN+
C5432
0.22UF
20%
6.3V
2 X5R
402
MXM
45 46 49 50 88
PLACE RC CLOSE TO SMC
R5431
OUT
6 88 SMC_MXM_ISENSE_R
4.53K2
SMC_GPU_ISENSE
1%
1/16W
MF-LF
402
REF 1
NOSTUFF
R5432
10K
5%
1/16W
MF-LF
402 2
GND
2
6.04K
GND_SMC_AVSS
V+
U5430
MXM_ISENSE_N
R5434
20%
2 6.3V
X5R
402
MXM
45 88
MXM
1
1%
1/16W
MF-LF
402 2
MXM
88
SMC_GPU_VSENSE
353S2073
GAIN = 200V/V
45 88
MXM
1
C5431
0.22UF
20%
6.3V
2 X5R
402
B
GND_SMC_AVSS
45 46 49 50 88
PAGE TITLE
GRAPHICS / DIMM POWER SENSE

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
54 OF 110
SHEET
50 OF 92
REMOTE THERMAL SENSORS

HEATSINKS, AMBIENT, PANEL AND ODD
R5535
=PP3V3_S0_TSENS
22
L5553
FERR-220-OHM
88 51
SNS_T_DP1_DN6
M-RT-SM
3
2
92 88
L5554
92 88
FERR-220-OHM
88 51
SNS_T_DN1_DP6
SNS_ODD_P
SNS_ODD_N
SNS_T_DN1_DP6
2
92 88
L5564
FERR-220-OHM
88 51
SNS_T_DP1_DN6
92 88
SNS_SKIN_P
SNS_SKIN_N
0402
92 88
L5521
92 88
FERR-220-OHM
88 51
SNS_T_DN2_DP3
L5522
88 51
SNS_T_DN2_DP3
1
0402
92 88
L5523
92 88
FERR-220-OHM
88 51
SNS_T_DP2_DN3
OUT
TSSOP
CPU_TDIODE
R55361
100K
1UF
EMC1403-2-AIZL
CPU_TDIODE
C5535
10%
10V
X5R
402-1
R5537
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
DP1
THERM* 7
EMC1403_PD2 3
DN1
ALERT* 8
CPU_THMSNS_ALERT_L
DP2/DN3
SMDATA 9
=SMB_CPU_THRM_SDA
BI
48
DN2/DP3
SMCLK
=SMB_CPU_THRM_SCL
BI
48
1CPU_TDIODE
R5539
10
CPU_THMSNS_THERM_L
GND
10K
5%
1/16W
MF-LF
2 402
I2C Address is 9A/9B
SNS_CPU_THERMD_P
SIGNAL_MODEL=EMPTY
CPU_TDIODE
53780-8603
C5537
M-RT-SM
4
SNS_LCD_P
SNS_LCD_N
88 10
J5521
FERR-220-OHM
M-RT-SM
3
0402
SENSOR CH3
53780-8602
5%
1/16W
MF-LF
2 402
SILK_PART=AMBIENT TEMP
J5520
SNS_T_DP2_DN3
R5538
10K
SENSOR CH2
88 51
CRITICAL
518S0665
SILK_PART=LCD TEMP
L5520
2
4
518S0698
FERR-220-OHM
10%
50V
CERM
402
0402
CRITICAL
C5536
0.0022UF
CPU_TDIODE
CPU_TDIODE
CPU_TDIODE
U5535
NOSTUFF
Chan-1 is not used
CRITICAL
VDD
SIGNAL_MODEL=EMPTY
M-RT-SM
3
0402
353S2224
EMC1403_PD1
53261-8602
FERR-220-OHM
88 51
0402
VOLTAGE=3.3V
J5560
L5563
53780-8602
PP3V3_S0_CPU_THMSNS
5%
1/16W
MF-LF
402
SILK_PART=SKIN TEMP
J5551
CPU_TDIODE
51 6
SENSOR CH6
SILK_PART=ODD TEMP
CPU T-DIODE THERMAL SENSOR

1
SENSOR CH1
SNS_AMB_P
SNS_AMB_N
0.0022UF
10%
50V
CERM
402
1
88 10
OUT
SNS_CPU_THERMD_N
0402
0402
CRITICAL
518S0698
CRITICAL
518S0677
PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU
SENSOR CH5
SENSOR CH4
SILK_PART=CPU HSK
J5510
L5510
SNS_T_DP4_DN5
88 51
0402
88
L5511
88
FERR-220-OHM
88 51
SNS_T_DN4_DP5
SNS_T_DN4_DP5
MXM
88
L5513
88
FERR-220-OHM
0402
88 51
SNS_T_DP4_DN5
M-ST-SM
3
2
0402
SNS_CPU_H_P
SNS_CPU_H_N
53398-8602
FERR-220-OHM
M-ST-SM
3
J5511
MXM
L5512
53398-8602
FERR-220-OHM
88 51
SILK_PART=MXM HSK
SNS_MXM_P
SNS_MXM_N
2
4
0402
CRITICAL
518S0678
CRITICAL
MXM
518S0678
REMOTE THERMAL SENSORS (HEATSINKS AND ODD)
HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING

=PP3V3_S0_SMC_LS
46 6
51 6
=PP3V3_S0_TSENS
R5500
1
22
2 89
C5501
1UF
10%
10V
X5R
402-1
SNS_T_DN1_DP6
J5550
10%
50V
CERM
402
SNS_T_DP1_DN6
SNS_T_DP2_DN3
1
3 DN1/DP6
2 DP1/DN6
4 DP2/DN3
5 DN2/DP3
0.0022UF
10%
50V
CERM
402
88 51
88 51
SNS_T_DN2_DP3
SNS_T_DP4_DN5
8 DP4/DN5
7 DN4/DP5
DIFFERENTIAL_PAIR=SNS_T2
C5504
92 88
HDD_OOB_TEMP_FILT
U5500
TSSOP
C5503
CRITICAL
SMDATA 9
SMCLK 10
HDD_OOB_TEMP
1
1
200K
3.3K
88 51
U7030
R5551
1K
5%
1/16W
MF-LF
2 402
LM393
SOI-HF
1
88
SMC_HDD_OOB_TEMP
TO SMC
SMC_EXCARD_CP 45
MAKE_BASE=TRUE
GND
4
5%
1/16W
MF-LF
402 2
Drive active = valid signal protocol

Drive asleep = HDD drives HDD_OOB_TEMP low
Drive disconnected = pulled high
GND
Cannot pull low because some drives use this bit to

determine 1.5 Gbps vs. 3.0 Gbps SATA
Must pull high to 2.5V for compatibility with all drives
PAGE TITLE
Thermal Sensors
DRAWING NUMBER
Apple Inc.
051-8600

SIZE
REVISION
A.0.0
SNS_T_DN4_DP5
2 88 HDD_OOB_TEMP_R
5%
1/16W
MF-LF
402
0.0022UF
10%
50V
CERM
402
R5550
R5553
CRITICAL
518S0698
48
48
88
1V60_COMP_REF
V+
0402
=SMB_REMOTE_TEMP_SDA
=SMB_REMOTE_TEMP_SCL
8
63
L5552
VDD
5%
1/16W
MF-LF
2 402
FERR-220-OHM
0.0022UF
88 51
M-RT-SM
3
EMC10472AIZL
C5502
88 51
53780-8602
power/gnd and ref for this dual part

is on csa 70 with power sequencing
CRITICAL
R5554
62K
FROM DRIVE:
LOW: -0.3V TO 0.5V
HIGH: 2.0V TO 3.6V
SILK_PART=LCD TEMP
88 51
PP3V3_S0_TSENS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
BRANCH
PAGE
55 OF 110
SHEET
51 OF 92
FAN 0
53 52 6
2
CRITICAL
L5610
=PP12V_S0_FAN
220-OHM-1.4A
1
R5602
R5606
5%
1/4W
MF-LF
2 1206
10K
5%
1/16W
MF-LF
2 402
1.5K
5%
1/8W
MF-LF
805 2
3.9K2
F0_GATESLOWDN
C5607
0.01UF
NTHS5443T1H
ODD FAN
1
2
3
C5601
CRITICAL
0.47UF
SMC_FAN_0_CTL
Q5602
=PP3V3_S0_FAN
1
R5600
10K
SMC_FAN_0_TACH
47K
FAN_TACH0
2
0603
R5699
FAN_0_PWR
SOT23-HF1
L5620
220-OHM-1.4A
2N7002
D5600
NOTE:
92
92
FAN_0_PWR_L
FAN_TACH0_L
2
3
C5602
100UF
MMBD914XG
20%
2 16V
ELEC
6.3X5.5-SM1-HF
SOT23
CRITICAL
5%
1/16W
MF-LF
2 402
518S0730
FAN_0_GND
1
R5620
0
L5600
FERR-220-OHM
5%
1/10W
MF-LF
2 603
2
0402
PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3
ADDED TO PROTECT SMC
53 52 6
53 52 6
CRITICAL
L5630
=PP12V_S0_FAN
220-OHM-1.4A
1
=PP3V3_S0_FAN
92
89
R5611
R5610
10K
5%
PP12V_S0_FAN1_L
VOLTAGE=12V
0603
R56071
1.5K
5%
1/4W
MF-LF
2 1206
R5609
3.9K
1
C5609
0.01UF
HD FAN
1206A-03-HF
CRITICAL
L5640
220-OHM-1.4A
FAN_1_PWR
SOT23-HF1
2
0603
M-RT-SM
5
92
92
FAN_1_PWR_L
FAN_TACH1_L
2
3
53 52 6
=PP3V3_S0_FAN
D5601
CRITICAL
MMBD914XG
R5601
10K
C5605
100UF
1 SOT23
92
45
SMC_FAN_1_TACH
47K
R5630
0
FERR-220-OHM
1
FAN_TACH1
5%
1/10W
MF-LF
2 603
2
0402
5%
1/16W
MF-LF
402
518S0730
FAN_1_GND
1
CRITICAL
L5601
R5698
MOTOR CONTROL
TACH
GND
12V DC
20%
2 16V
ELEC
6.3X5.5-SM1-HF
5%
1/16W
MF-LF
2 402
J5601
53780-8604
CRITICAL
2 16V
X7R
805
Q5605
20%
2 16V
CERM
402
2 16V
X5R
603
C5603
2N7002
2.2UF
10%
Q5603
0.47UF
10%
C5628
NTHS5443T1H
1
2 16V
X5R
603
CRITICAL
5
F1_GATESLOWDN
5%
1/8W
MF-LF
805
SMC_FAN_1_CTL
C5608
2.2UF
10%
5%
1/8W
MF-LF
805 2
6
7
8
F1_VOLTAGE8R5
1.5K
1
2
3
1/16W
MF-LF
2 402
MOTOR CONTROL
TACH
GND
12V DC
6
92
FAN 1
45
M-RT-SM
5
CRITICAL
5%
1/16W
MF-LF
402
J5600
53780-8604
CRITICAL
10%
2 16V
X7R
805
3
D
20%
16V
2 CERM
402
1206A-03-HF
45
2 16V
CERM
1206-1
Q5600
5%
1/8W
MF-LF
805
C5606
4.7UF
20%
CRITICAL
5
R5605
F0_VOLTAGE8R5
53 52 6
VOLTAGE=12V
1.5K
PP12V_S0_FAN0_L
R5603
45
92
89
2
0603
=PP3V3_S0_FAN
6
7
8
53 52 6
PAGE TITLE
HD AND OD FAN
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
56 OF 110
SHEET
52 OF 92
FAN 2
52 6
CRITICAL
=PP12V_S0_FAN
L5710
220-OHM-1.4A
1
2
0603
53 52 6
=PP3V3_S0_FAN
R5704
R57011
1.5K
R5705
10K
5%
1/16W
MF-LF
2 402
C
45
1.5K
5%
1/4W
MF-LF
2 1206
5%
1/8W
MF-LF
805 2
F2_VOLTAGE8R5
C5709
0.01UF
20%
16V
2 CERM
402
16V
2 CERM
1206-1
3.9K 2
F2_GATESLOWDN
NTHS5443T1H
Q5700
CRITICAL
10%
2 16V
X7R
805
Q5702
2N7002
1
2
3
0.47UF
J5700
C5701
D5700
MMBD914XG
=PP3V3_S0_FAN
1
SOT23
R5700
M-RT-SM
5
FAN_2_PWR_L
92
0603 92 FAN_TACH2_L
CRITICAL
L5720
220-OHM-1.4A
FAN_2_PWR
SOT23-HF1
53780-8604
CRITICAL
6
7
8
2
3
C5702
92 89 PP12V_S0_FAN2_L
100UF
20%
2 16V
ELEC
6.3X5.5-SM1-HF
VOLTAGE=12V
CRITICAL
5%
1/16W
MF-LF
R5720
0
L5701
5%
1/10W
MF-LF
2 603
2
0402
R5797
SMC_FAN_2_TACH
47K
FAN_2_GND
518S0730
FERR-220-OHM
2 402
MOTOR CONTROL
TACH
GND
12V DC
6
92
10K
45
CPU FAN
1206A-03-HF
5%
1/8W
MF-LF
805
FAN_TACH2
R5703
SMC_FAN_2_CTL
53 52 6
C5708
4.7UF
20%
CRITICAL
5%
1/16W
MF-LF
402
PAGE TITLE
CPU FAN
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
57 OF 110
SHEET
53 OF 92
C
=PP3V3_S5_ROM
R6100 1
R6101
3.3K
R6150
85 47 18
IN
SPI_CLK_R

85 47
IN
SPI_MLB_CS_L
5%
1/16W
MF-LF
402 2
3.3K
5%
1/16W
MF-LF
2 402
85
SPI_CLK
C6100
47 6
20%
10V
CERM
402
CRITICAL
VDD
0.1UF
2
U6100
R6152
32MBIT
SCK
SOIC
SI
85
SPI_MOSI
SST25VF032B
5%
1/16W
MF-LF
402
SPI_WP_L
SPI_HOLD_L
3
7
CE*
WP*
HOLD*
OMIT
R6105
SO
85
SPI_MISO_R
5%
1/16W
MF-LF
402
SPI_MOSI_R
IN
18 47 85
SPI_MISO
OUT
18 47 85
5%
1/16W
MF-LF
402
VSS
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
61 OF 110
SHEET
54 OF 92
AUDIO CODEC
APPLE P/N 353S2592

=PP5V_S0_AUDIO
6
=PP1V5_S0_AUD_DIG
C6203
4.7UF
=PP3V3_S0_AUDIO IN
C6258
0.47UF
20%
4V
X5R
402
PP4V5_AUDIO_ANALOG
10%
10V
2 X5R
402
C6259
C6261 1
10UF
1%
1/16W
MF-LF
2 402
OUT
OUT
IN
AUD_SENSE_A
60
IN
10UF
VBIAS_DAC
20%
2 6.3V
X5R
603
C6206
20%
6.3V
CERM
402-LF
C6208
2.2UF
20%
6.3V
CERM
402-LF
CS4206_FLYN
85 18
IN
85 18
IN
HDA_SYNC
85 18
OUT
HDA_SDIN0
IN
81
IN
HDA_SDOUT
HDA_RST_L
AUD_SPDIF_IN_CODEC
22
OUT
AUD_SDI_R
VL_HD
VL_IF
8
5
5%
1/16W
MF-LF
402
11
AUD_SPDIF_OUT
22
85
47
48
AUD_SPDIF_CHIP
0.47UF
10%
C6262 10V
X5R
402-1
C6264
10UF
10%
10V
X5R 2
402
20%
2 16V
POLY-TANT
CASE-B2-SM
0.47UF
39
AUD_HP_PORT_REF
16
VCOM
28
LINEIN_L+
LINEIN_CLINEIN_R+
21
22
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
27
AUD_CODEC_MICBIAS
SPDIF_IN
SPDIF_OUT
60
IN
56
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
CS4206_VREF_ADC
56
IN
61
IN
61
IN
60
IN
60
TP_AUD_DMIC_CLK
NC
CRITICAL
CRITICAL
C6211 1
10%
20V 2
TANT
CASE-P3-HF
20%
2 16V
POLY-TANT
CASE-B2-SM
1UF
C6263
NOSTUFF
10UF
R6267
100K
5%
1/16W
MF-LF
2 402
HP OUT ZOBEL NETWORK
GND_AUDIO_HP_AMP_L
VOLTAGE=0V
55 56 59
56 55
IN
AUD_HP_PORT_L
56 55
IN
AUD_HP_PORT_R
C6298 1
C6297
0.1UF
OUT
DIFF FSINPUT= 2.45VRMS

SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
55
VOLTAGE=4.5V
L6201
=PP5V_S0_AUDIO
R6201
2.21K2
=PP3V3_S0_AUDIO 1
6 IN
91
SON
OUT
10%
16V
X7R-CERM 2
402
R62961
R62971
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
39
AUD_Z_R
AUD_Z_L
NC
NC
GND_AUDIO_HP_AMP_L
PP4V5_AUDIO_ANALOG
OUT
55 89
CRITICAL
4V5_REG_EN
4 EN
1%
1/16W
MF-LF
402
NR/FB 3
C6201
1UF
10%
2 10V
X5R
402-1
C6202
4V5_NR
C6266
0.1UF
1UF
10%
16V
X7R-CERM 2
402
10%
2 10V
X5R
402-1
PAGE TITLE
NC 5
GND
1
AUDIO: CODEC/REGULATOR
C6207
DRAWING NUMBER
1UF
10%
10V
2 X5R
402-1
Apple Inc.
GND_AUDIO_CODEC
051-8600
55 56 57 58 60 61
SIZE
REVISION
A.0.0

55 56 59
VOLTAGE=4.5V
VR6201
TPS71745
0402
0.1UF
10%
16V
X7R-CERM 2
402
39
APPLE P/N 353S2456

4.5V POWER SUPPLY FOR CODEC
FERR-220-OHM
1
2 4V5_REG_IN
89
56
IN
NC
AUD_GPIO_1
56
IN
DGND THRM_PAD AGND
5%
1/16W
MF-LF
2 402
IN
OUT
AUD_LI_COM
AUD_LI_P_R IN
MAKE_BASE=TRUE
VOLTAGE=0V
R6298
61 60 59 58 57 55 6
58
AUD_LI_P_L
23
DMIC_SCL
1%
1/16W
MF-LF
402 2
10K
58
100K
IN
57
CS4206_VCOM
R6299
61 55 6
57
AUD_LI_N_R
RESET*
55 56
59
SYNC
SDI
SDO
55 56
OUT
NC
100K
EDUCATION
IN
OUT
NC
5%
1/16W
MF-LF
2 402
58 60 61
AUD_HP_PORT_L
AUD_HP_PORT_R
MICBIAS
BITCLK
XW6201
SM
BETTER
20%
2 6.3V
X5R
603
AUD_LI_N_L
GND_AUDIO_CODEC
6 55 57 58 59 60 61
55 89
GND_AUDIO_HP_AMP_L 55 56 59
GND_AUDIO_CODEC 55 56 57
38
40
6 55 61
10UF
10%
10V 2
X5R
402
5%
1/16W
MF-LF
2 402
=PP3V3_S0_AUDIO
IN
AUD_LO2_P_L OUT
TP_AUD_LO2_N_L
AUD_LO2_P_R NC
OUT
TP_AUD_LO2_N_R
IN
VOLTAGE=4.5V
31
30
32
33
R6263
61 60 59 58 57 55 6
C6213
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
NOSTUFF
AUD_LO1_P_L OUT
TP_AUD_LO1_N_L NC
AUD_LO1_P_R OUT
TP_AUD_LO1_N_R
61 60 58 57 56 55
CRITICAL
C6265 1
35
34
36
37
R62951
5%
1/16W
MF-LF
402
25
FLYP
FLYC
FLYN
10
85
R6257
85 59
45
43
42
U6201
IN
85 18
SENSE_A
R6254
85 18
13
2
12
2.2UF
HDA_BIT_CLK
14
15
44
41
CS4206_FLYP
CS4206_FLYC
10%
10V 2
X5R
402
VD VA_REF VA_HP VA
VBIAS_DAC
CRITICAL HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206ACNZC HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-
29
CS4206_FP
CS4206_FN
46
C6205
26
61 57
61 58 57
AUD_MUX_CNTRL
AUD_GPIO_1
AUD_GPIO_2
AUD_GPIO_3
81
55
20%
6.3V 2
X5R
603
2.67K
K22 = NC
K23 LOW = S/PDIF IN, HIGH = DP SPDIF
10UF
24
C6204
R6255
49
IN
0.47UF
89 55
20%
16V 2
POLY-TANT
CASE-B2-SM
GND_AUDIO_HP_AMP_L
PP4V5_AUDIO_ANALOG
1UF
C6260 1
D
59 56 55
IN
BRANCH
PAGE
62 OF 110
SHEET
55 OF 92
1ST ORDER DAC FILTER PLACEHOLDER

R6324
55
IN
AUD_HP_PORT_L
AUD_HP_L
5%
1/10W
MF-LF
603
OUT
59
NOSTUFF
CRITICAL
C6320
5%
50V
C0G-CERM
603
2200PF
59 55
IN
GND_AUDIO_HP_AMP_L
NOSTUFF
CRITICAL
C6321
2200PF
5%
50V
C0G-CERM
603
R6325
55
IN
AUD_HP_PORT_R
AUD_HP_R
OUT
59
5%
1/10W
MF-LF
603
CODEC Nom SE RIN = 20K OHMS

FC = 5 HZ Max
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
NET RIN = 18K OHMS
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
59
7.87K2
AUD_LI_L
IN
CRITICAL
3.3UF
AUD_LI_LF
1%
1/16W
MF-LF
402
21.5K
1%
1/16W
MF-LF
402 2
OUT
55
NOSTUFF
C6301
820PF
10%
50V
2 CERM
402
CRITICAL
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
C6302
3.3UF
AUD_LI_GND
IN
AUD_LI_P_L
10%
10V
CERM-X5R
805-1
R63011
59 56
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
C6300
R6300
AUD_LI_N_L
OUT
55
10%
10V
CERM-X5R
805-1
R6303
10
1%
1/16W
MF-LF
2 402
B
61 60 58 57 55
IN
GND_AUDIO_CODEC
59
IN
AUD_LI_R
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
C6303
R6306
7.87K2
3.3UF
AUD_LI_RF
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
CRITICAL
1%
1/16W
MF-LF
402
AUD_LI_P_R
R63051
21.5K
1%
1/16W
MF-LF
402 2
OUT
55
C6304
820PF
10%
2 50V
CERM
402
CRITICAL
IN
55
NOSTUFF
1
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
C6305
59 56
OUT
10%
10V
CERM-X5R
805-1
3.3UF
AUD_LI_GND
AUD_LI_N_R
10%
10V
CERM-X5R
805-1
PAGE TITLE
AUDIO: FILTER/BUFFER
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
63 OF 110
SHEET
56 OF 92
TWEETER SPEAKER AMPLIFIER

MAX9736B APN:353S2042
GAIN = -4.8(20K/17.4K)
CODEC OUT = 1.335VRMS
AMP VOUT = 7.355VRMS
TURN ON TIME: 110MS

TURN ON DELAY: 150MS
RIN = 17.4 OHMS
FC = 19.5 HZ
POUT = 6.76 W INTO 8 OHMS @ 1% THD+N
VOLTAGE=12V
89 60 58
IN
PP12V_AUD_SPKRAMP_PLANE
C6499 1
C6401
220UF
60 58 57
IN
0.1UF
20%
16V 2
ELEC
SM-CASE-C1-HF
20%
16V
CERM 2
603
GND_AUDIO_SPKRAMP_PLANE
MAX9736_INT_1REG
C6402 1
1UF
NOSTUFF
C6403
C6412
C6496
55
IN
AUD_LO1_P_L
0.47UF
1
L01_P_L
AUD_LO1_P_R
17.4K2
AUD_MAX9736_1VREG 15
1%
1/16W
MF-LF
402
L01_P_R
R6403
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
17.4K2
1
IN
=PP3V3_S0_AUDIO
IN
=PP3V3_S0_AUDIO
61 55
60 58 57
IN
AUD_GPIO_3
IN
AUD_GPIO_2
IN
61 60 58 56 55
BOOT
MOD
MONO
SHDN*
MUTE*
REGEN
10%
10V
2 X5R
402-1
AUDSAMPCPN1
AUD_BOOT1
31
1
OUTL2+
OUTL2-
32
2
OUTR1+
OUTR1-
25
23
OUTR2+
OUTR2-
26
24
NC1
NC2
NC3
7
8
17
C6405
C6411
0.1UF
22
21
OUTL1+
OUTL1-
1UF
AUD_SPKRAMP_1SHDN_L
10%
2 50V
X7R
603-1
AUD_L_P1
CRITICAL
L6400
180-OHM-1.5A
1
CRITICAL
L6401
AUD_L_N1
0.5MM
0.2MM
L6402
0603-LF
180-OHM-1.5A
0.5MM
0.2MM CRITICAL 1
2
AUD_R_P1
NOSTUFF
R6406
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
100K
OUT
59 85 92
AUD_SPKR_OUTLO1L_NOUT
OUT
59 85 92
AUD_SPKR_OUTLO1R_POUT
OUT
59 85 92
AUD_SPKR_OUTLO1R_NOUT
OUT
59 85 92
0603-LF
CRITICAL
L6403
180-OHM-1.5A
AUD_R_N1
1
THM
AGND PGND PAD
C6410
2
0603-LF
C6406
C6408
0.1UF
10%
50V
2 X7R-CERM
805
1000PF
5%
25V
NP0-C0G 2
402
1000PF
5%
25V
NP0-C0G 2
402
C6409
1000PF
C6407
1000PF
R6407
AUD_SPKR_OUTLO1L_POUT
0603-LF
180-OHM-1.5A
5%
25V
2 NP0-C0G
402
5%
25V
2 NP0-C0G
402
AUD_SPKRAMP_1MUTE_L
5%
1/16W
MF-LF
402
CRITICAL
NOSTUFF
C1P
C1N
18 INR
19 FBR
20
4
10
9
11
5%
1/16W
MF-LF
402
R6405
61 58 55
AUDSAMPCPP1
TQFN
13
14
61 60 59 58 57 55 6
12 COM
C6413
R6404
0
AUD_MAX9736_1COM
0.001UF
1
REG
5 FBL
6 INL
20.0K2
1
10%
50V
X7R
402
PVDD
MAX9736BETJ+
AUD_MAX9736_1FBL
AUD_MAX9736_1INL
AUD_MAX9736_1INR
AUD_MAX9736_1FBR
R6402
VS
U6400
20.0K2
1%
1/16W
MF-LF
402
10%
10V
X5R
402
61 60 59 58 57 55 6
10%
50V
X7R
402
R6400
0.47UF
IN
C6495
55
R6401
10%
10V
X5R
402
1UF
10%
10V 2
X5R
402-1
0.001UF
33
27
30
IN
16
60 58 57
28
29
10%
10V
X5R 2
402-1
C6404
100PF
5%
50V
2 CERM
402
VOLTAGE=0V
GND_AUDIO_CODEC
PAGE TITLE
AUDIO: Tweeter Amp 1

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
64 OF 110
SHEET
57 OF 92
WOOFER SPEAKER AMPLIFIER

MAX9736B APN:353S2042
TURN ON TIME: 110MS
GAIN = -4.8(20K/17.4K)
TURN ON DELAY: 150MS
CODEC OUT = 1.335VRMS
RIN = 17.4 OHMS
AMP VOUT = 7.355VRMS
FC = 19.5 HZ
POUT = 6.76 W INTO 8 OHMS @ 1% THD+N
VOLTAGE=12V
89 60 57
IN
C6599 1
220UF
C6501
60 58 57
IN
0.1UF
20%
16V
CERM 2
603
20%
16V 2
ELEC
SM-CASE-C1-HF
MAX9736_INT_REG
C6502 1
1UF
NO STUFF
IN
AUD_LO2_P_L
L02_P_L
17.4K2
55
IN
AUD_LO2_P_R
IN
AUD_MAX9736_FBL
AUD_MAX9736_INL
R6503
17.4K2
L02_P_R
1%
1/16W
MF-LF
402
=PP3V3_S0_AUDIO
20
4
10
9
11
IN
=PP3V3_S0_AUDIO
IN
AUD_GPIO_3
R6506
100K
5%
1/16W
MF-LF
2 402
IN
61 60 57 56 55
5%
1/16W
MF-LF
402
22
21
3
31
1
OUTL2+
OUTL2-
32
2
OUTR1+
OUTR1-
25
23
OUTR2+
OUTR2-
26
24
NC1
NC2
NC3
7
8
17
THM
AGND PGND PAD
AUDSAMPCPN
10%
50V
2 X7R
603-1
AUD_BOOT
OUTL1+
OUTL1-
C6505
R6505
1
60 58 57
MOD
MONO
SHDN*
MUTE*
REGEN
10%
2 10V
X5R
402-1
AUD_SPKRAMP_SHDN_L
5%
1/16W
MF-LF
402
61 57 55
BOOT
13
14
61 60 59 58 57 55 6
CRITICAL
C6511
0.1UF
C1P
C1N
1UF
R6504
2
TQFN
NO STUFF
12 COM
18 INR
19 FBR
0.001UF
10%
50V
X7R
402
AUDSAMPCPP
MAX9736BETJ+
5 FBL
6 INL
AUD_MAX9736_INR
AUD_MAX9736_FBR
C6513
1
15 REG
AUD_MAX9736_COM
20.0K2
1%
1/16W
MF-LF
402
10%
10V
X5R
402
61 60 59 58 57 55 6
AUD_MAX9736_VREG
1%
1/16W
MF-LF
402
R6502
PVDD
U6500
20.0K2
1%
1/16W
MF-LF
402
0.47UF
VS
R6500
C6595
2
10%
50V
X7R
402
R6501
10%
10V
X5R
402
10%
10V
X5R 2
402-1
33
55
0.47UF
1UF
0.001UF
1
C6596
C6503
C6512
27
30
16
IN
28
29
60 58 57
10%
10V
X5R 2
402-1
AUD_L_POUT
CRITICAL
0.5MM
0.2MM
L6501
L6502
0603-LF
OUT
59 85 92
OUT
59 85 92
OUT
59 85 92
OUT
59 85 92
180-OHM-1.5A
0.5MM
0.2MM CRITICAL 1
0603-LF
CRITICAL
L6503
180-OHM-1.5A
2
AUD_R_NOUT 1
1
C6510
0603-LF
C6506
C6508
0.1UF
10%
2 50V
X7R-CERM
805
1000PF
1000PF
5%
25V
NP0-C0G 2
402
5%
25V
NP0-C0G 2
402
1
C6507
1000PF
5%
25V
2 NP0-C0G
402
AUD_SPKRAMP_MUTE_L
1
0603-LF
180-OHM-1.5A
2
AUD_L_NOUT 1
AUD_R_POUT
CRITICAL
L6500
180-OHM-1.5A
C6509
1000PF
5%
2 25V
NP0-C0G
402
C6504
100PF
5%
2 50V
CERM
402
VOLTAGE=0V
GND_AUDIO_CODEC
PAGE TITLE
AUDIO: Woofer Amp

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
65 OF 110
SHEET
58 OF 92
INTERNAL MIC CON

L6600
L6601
FERR-1000-OHM
86 60
OUT
AUD_MIC1_IN_N
AUD_MIC_IN1_N_EMI
2
0402
L6602
OUT
AUD_MIC1_IN_P
PROPERTIES FOR ALL SPKR NETS
53780-8603
92 AUD_MIC_IN1_N_CONN
VOLTAGE=0V
WOOFER (PRIMARY)
AUD_MIC_IN1_P_EMI
IN
92 85 58
IN
TWEETER (SECONDARY)
FERR-1000-OHM
0402
92 85 58
85 57
92
92 85 57
92
AUD_MIC_IN1_P_CONN
IN
IN
J6603
J6602
78048-0573
M-RT-SM
78048-0473
M-RT-SM
L6603
CRITICAL
CRITICAL
M-RT-SM
4
GND_AUDIO_MIC1_CONN
FERR-1000-OHM
86 60
J6601
FERR-1000-OHM
0402
PROPERTIES FOR ALL SPKR NETS
CRITICAL
APPLE P/N 518S0748

APPLE P/N 518S0656
APPLE P/N 518S0677
SPEAKER CABLE CONNECTORS
WOOFER (PRIMARY)
1
2
92 85 58
IN
92 85 58
IN
NO_TEST
TWEETER (SECONDARY)
92 85 57
92 85 57
NC
IN
IN
NC_J6702_3
1
2
3
4
5
0402
CRITICAL
DZ6600
CRITICAL
6.8V-100PF
DZ6601
402
5%
1/16W
MF-LF
2 402
R6600
6.8V-100PF
402
R6601
85 81
OUT
AUD_SPDIF_IN
L6604
61 60 58 57 55 6
IN
=PP3V3_S0_AUDIO
22
5%
1/16W
MF-LF
402
FERR-1000-OHM
2
0402
REMOTE I/O CONNECTOR
L6605
FERR-1000-OHM
60
OUT
AUD_LI_TIP_DET
R6610
56
OUT
AUD_LI_GND
56
OUT
AUD_LI_R
OUT
OUT
55
OUT
OUT
OUT
L6609
FERR-1000-OHM
0402
2
0402
XW6617
2
SM
R6617
GND_AUDIO_HP_AMP_L
L6616
220-OHM-0.7A-0.28-OHM
IN
AUD_HP_L
IN
OUT
60
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0402
23
24
L6615
FERR-1000-OHM
AUD_IP_PERPH_DET
AUD_HP_TIP_DET
L6614
AUD_HP_TYPE
VOLTAGE=3.3V
FERR-1000-OHM
0402
OUT
L6618
60
220-OHM-0.7A-0.28-OHM
AUD_HP_R
60
5%
1/10W
MF-LF
603
2
0402
VOLTAGE=0V
56
56
L6606
FERR-1000-OHM
AUD_SPDIFIN_JACK
89 PP3V3_AUDIO_SPDIF_JACK
AUD_LI_DET_JACK
AUD_LI_GND_JACK
AUD_LI_R_JACK
AUD_LI_GND_JACK
AUD_LI_L_JACK
HS_MIC_LO_JACK
HS_MIC_HI_JACK
AUD_HP_GND_JACK
AUD_HP_L_JACK
AUD_HP_GND_JACK
AUD_HP_R_JACK
AUD_HP_TYPEDET_JACK
AUD_IP_PERPH_JACK
AUD_HP_TIPDET_JACK
PP3V3_AUDIO_SPDIF_JACK
AUD_SPDIF_OUT_JACK
2
0402
HS_MIC_HI
AUD_HP_PORT_REF
F-RT-SM
21
20143-020E-20F
0402
HS_MIC_LO
56 55
61
L6607
FERR-1000-OHM
FERR-1000-OHM
AUD_LI_L
VOLTAGE=0V
61
J6600
L6608
56
CRITICAL
5%
1/10W
MF-LF
603
APPLE P/N 518S0723
2
0402
L6612
22
2
0402
FERR-1000-OHM
1
L6613
0402
FERR-1000-OHM
85 55
IN
AUD_SPDIF_OUT
2
2
0402
CRITICAL
DZ6603
6.8V-100PF
DZ6604
6.8V-100PF
1UF
10%
10V 2
X5R
402-1
CRITICAL
DZ6608
CRITICAL
DZ6610
CRITICAL
DZ6612
CRITICAL
DZ6614
CRITICAL
DZ6615
6.8V-100PF
402
2 1
6.8V-100PF
402
402
2 1
6.8V-100PF
402
CRITICAL
DZ6613
6.8V-100PF
402
2 1
6.8V-100PF
1
CRITICAL
DZ6611
6.8V-100PF
402
2
402
CRITICAL
DZ6609
6.8V-100PF
6.8V-100PF
402
C6601
DZ6606
6.8V-100PF
402
C6600
CRITICAL
402
402
2
CRITICAL
DZ6607
6.8V-100PF
6.8V-100PF
402
CRITICAL
CRITICAL
DZ6605
402
0.47UF
10%
2 10V
X5R
402
PAGE TITLE
Audio: MLB to I/O Conn.

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
66 OF 110
SHEET
59 OF 92
Internal Microphone Impedance Matching

5%
1/16W
MF-LF
402
CRITICAL
R6793 C6751
D
86 59
IN
0.1UF
1
C6750
86 59
IN
C6795
AUD_MIC1_IN_N
10%
25V
X7R 2
402
R6791
5%
1/16W
MF-LF
2 402
IN
55
IN
L6739
=PP12V_S0_AUDIO_SPKRAMP
FERR-250-OHM
1
R6792
3.40K
OUT
GND_AUDIO_CODEC
AUD_MIC_INP_R
OUT
NOSTUFF
OUT
R6748
57 58
5%
1/16W
MF-LF
402
AUD_MIC_INN_R
OUT
NOSTUFF
55
R6749
10%
16V
X5R
402
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
XW6702
SM
AUD_MIC1_IN_G
GND_AUDIO_CODEC
55 56 57 58 60 61
IPHS HS Detect Debounce CKT

61 60 59 58 57 55 6
=PP3V3_S0_AUDIO
R6797
100K
10K
100K
5%
1/16W
MF-LF
2 402
R67681
R67981
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
R6799
AUD_IP_PERPH_DET_DB
AUD_IP_PERPH_DET_INV
IN
17.4K2
1
1%
1/16W
MF-LF
402
AUD_IP_PER_DEB
61 60 59 58 57 55 6
IN
IN
60 55
=PP3V3_S0_AUDIO
CRITICAL
R6794
5%
1/16W
MF-LF
2 402
IN
AUD_HP_TYPE
IN
=PP3V3_S0_AUDIO
NC
IN
AUD_SENSE_A
61 60 59 58 57 55 6
IN
=PP3V3_S0_AUDIO
R6744
39.2K
1%
1/16W
MF-LF
2 402
100K
AUD_Q6702_D3
60 55
R67951
0.1%
1/16W
MF
2 402
100K
59
60 59 58 57 55 6
61
20K
R6790
0.1UF
5%
1/16W
MF-LF
402 2
R6701
100K
AUD_Q6701_D6
10K
5%
1/16W
MF-LF
402 2
NC
1%
1/16W
MF-LF
2 402
NOSTUFF
R6732
Q6700
NTZD3154NT1H AUD_HP_TYPE_INV
Q6702
59
NTZD3154NT1H
SOT-563-HF
IN
AUD_LI_TIP_DET
AUD_LI_TIP_D
5%
1/16W
MF-LF
402
SOT-563-HF
R67301
NOSTUFF
C6797
LI Insert Detect
AUD_SENSE_A
IN
NTZD3154NT1H
Headphone Out
AUD_SENSE_A
Q6701
GND_AUDIO_CODEC
Digital Out
60 55
20
10%
2 16V
X5R
402
0.1UF
OUT
1
1
NTZD3154NT1H
C6740
AUD_IP_PERIPHERAL_DET
SOT-563-HF
SOT-563-HF
1
Q6701
10%
2 16V
X5R
402
61 60 58 57 56 55
R6700
AUD_IP_PERPH_DET
AUD_IP_PERPH_DET_R
5%
1/16W
MF-LF
402
59
R6796
0
5%
1/16W
MF-LF
402
55 56 57 58 60 61
5%
1/16W
MF-LF
402
XW6704
SM
55
OMIT
OUT
R6747
XW6703
SM
55 56 57 58 60 61
GND_AUDIO_CODEC
NOSTUFF
57 58 89
OMIT
0.1UF
OMIT
SM-1
C6796
XW6705
SM
VOLTAGE=12V
2
SM-1
10%
16V
X5R
402
100K
Audio Ground Returns
FERR-250-OHM
AUD_CODEC_MICBIAS
20%
6.3V 2
TANT
603-HF
AUD_MIC1_IN_P
0.0082UF
L6738
4.7UF
3.40K
1%
1/16W
MF-LF
2 402
2.2K 2
Place Across Ground Split
R6743
AUD_INTMICBIAS
R6731
5%
1/16W
MF-LF
2 402
AUD_LI_TIP_DET_INV
61 60 59 58 57 55 6
IN
=PP3V3_S0_AUDIO
AUD_HP_TIP_DET_INV
R6762
Q6703
100K
5%
1/16W
MF-LF
2 402
59
IN
61 60 58 57 56 55
AUD_HP_TIP_DET
NTZD3154NT1H
SOT-563-HF
Q6700
NTZD3154NT1H
DP Audio Enable
Q6702
NTZD3154NT1H
SOT-563-HF
SOT-563-HF
81
IN
MUX_CNTRL
AUDIO: Detects/Grounding
DRAWING NUMBER
NTZD3154NT1H
Apple Inc.
SOT-563-HF
GND_AUDIO_CODEC
PAGE TITLE
Q6703
4
61 60 58 57 56 55
051-8600

SIZE
REVISION
A.0.0
GND_AUDIO_CODEC
BRANCH
PAGE
67 OF 110
SHEET
60 OF 92
FUNCTION
ENABLE/
CONVERTER VOLUME CNTRL TYPE
PIN
0X04
0X03
0X02
0X05
0X06
0X06
0X08
0X07
N/A
0X0B
0X0A
0X09
0X0C
0X0D(13,B,RIGHT)
0X0D (13,V22,B,LEFT)
0X10
0X0F
N/A
PRIMARY
SECONDARY
HEADPHONES
LINE INPUT
BUILT-IN MICROPHONE
HEADSET MICROPHONE
SPDIF OUT
SPDIF IN
MIKEY
0X04
0X03
0X02
0X05
0X06
0X06
N/A
N/A
N/A
DETECT/INTERRUPT
GPIO 3
GPIO 3
N/A
N/A
MICBIAS 80%
MIKEY
N/A
N/A
MCP GPIO_38
N/A
N/A
0X09 (A)
LINE IN
N/A
MIKEY
0X0C (B)
N/A
MCP GPIO_5
=PP5V_S0_AUDIO
IN
6 55
C6857
1UF
10%
10V
2 X5R
402-1
MIKEY RECEIVER CKT

WRITE: 0X72
READ: 0X73
IN
=PP3V3_S0_AUDIO
89
R6806
10K
5%
1/16W
MF-LF
402
R6803
48
BI
=I2C_AUDIO_SDA
20
OUT
IN
AUD_IPHS_SWITCH_EN1
HS_SCL
SCL
MICBIAS
HS_SDA
SDA
DETECT
INT*
BYPASS
10
R68071
CRITICAL
100K
C6852
5%
1/16W
MF-LF
402 2
10UF
C6850 1
ENABLE
GND
HS_MIC_BIAS
HS_SW_DET
CRITICAL
HS_RX_BP
C6854
4.7UF
THM
20%
2 6.3V
TANT
603-HF
C6899
0.01UF
10%
2 25V
X7R
402
0.001UF
20%
6.3V
X5R 2
603
5%
1/16W
MF-LF
402
61 60 58 57 56 55
U6806
CD3275
HS_RST
R6805
25 21
OUT
CRITICAL
AVDD
HS_INT_L
5%
1/16W
MF-LF
402
0.1UF
10%
2 16V
X5R
402
DRC
R6804
1
IN
SOD-323-HF
AUD_GPIO_3
C6851
5%
1/16W
MF-LF
402
AUD_I2C_INT_L
5%
1/16W
MF-LF
2 402
D6800
11
=I2C_AUDIO_SCL
NOSTUFF
1N4148WS-X-G
2
58 57 55
IN
OUT
PP3V3_S0_HS_F
48
AUD_GPIO_2
1
0402
R6802
IN
VOLTAGE=3.3V
L6840
FERR-1000-OHM
60 59 58 57 55 6
57 55
APN 353S2256
20%
50V
CERM 2
402
R6852
1K
5%
1/16W
MF-LF
2 402
B
GND_AUDIO_CODEC
R6809
55 56 57 58 60 61
2.2K
5%
1/16W
MF-LF
2 402
GND_AUDIO_CODEC
59
IN
HS_MIC_HI
R6808
100K
AUD_MIC_INF
1
C6801
0.1UF
1
C6853
10%
25V
2 X7R
402
HS_MIC_LO
AUD_MIC_INP_L
OUT
55
10%
16V
X5R
402
0.0082UF
5%
1/16W
MF-LF
2 402
IN
2.2K 2
5%
1/16W
MF-LF
402
59
R6810
C6802
0.1UF
1
AUD_MIC_INN_L
OUT
55
10%
16V
X5R
402
FLP = 8.82 KHZ

FHP = 80 HZ
PAGE TITLE
AUDIO: Mikey
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
68 OF 110
SHEET
61 OF 92
3
State
R6901
91 45
PM_RSMRST_L
IN
PM_RSMRST_PCH_L
OUT
5%
1/16W
MF-LF
402
63 62 6 5
PM_S4_STATE_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_M_L
N/A
Sleep (S3/M1)
On
Soft-Off (S5/M1)
On
Sleep (S3/M-Off)
Off
Soft-Off (S5/M-Off)
Off
Battery Off (G3Hot)
N/A
=PP3V3_S5_PWRCTL
C6910
0.1UF
SMC_PM_G2_ENABLE
Run (S0/M0)
SLP_S4 ENABLES
19 91
Manageability
20%
10V
CERM
402
D
MEMVTT_EN SEQUENCE
72 63 62 6 5
=PP3V3_S0_PWRCTL
91 19
D
14
PM_SLP_S4_1_L
74LVC08
R6911
TSSOP-HF
U6900
S4_ENABLES
10K
5%
1/16W
MF-LF
2 402
NOSTUFF
C6951
100PF
5%
50V
2 CERM
402
DDRVTT_EN
5%
1/16W
MF-LF
402
=PP3V3_S5_PWRCTL
Q6911
C6953
R6915
10%
16V
2 X5R
402
MMDT3904-X-G
SOT-363-LF
R6916
5%
1/16W
MF-LF
2 402
67 63 62 11
91
CPUVTT_REG_PGOOD
P12V_S3_EN
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
100K
33
10K
R6950
NOSTUFF
1
CPU_SKTOCC
100K 2
CPUVTT_RP_R
MMDT3904-X-G
NOSTUFF
C6921
0.47UF
10%
6.3V
10%
6.3V
CERM-X5R
C6923
0.47UF
CERM-X5R
402
10%
6.3V
CERM-X5R
402
2N7002DW-X-G
11
0.47UF
CPU_SKTOCC_L
10%
6.3V
2 CERM-X5R
402
0.47UF
72 91
Enable FET
NOSTUFF
Q6910
C6952
NOSTUFF
SOT-363-LF
5%
1/16W
MF-LF
402
C6920
402
Q6911
69 91
ENABLE REGULATOR
R6914
NOSTUFF
0.1UF
VTT_REG_PGOOD_R15
63 62 6 5
32 62 70 91
P5VS3_EN
5%
1/16W
MF-LF
402
R6953
VTT_REG_PGOOD_R2
1
33
5%
1/16W
MF-LF
2 402
72 91
Enable FET
R6912
R6952
10K
P3V3S3_EN
5%
1/16W
MF-LF
402
R6951
33
08
SOT-363
S
4
NOSTUFF
R6917
PLACE TOP SIDE

REWORK TO POWER UP WITH NO CPU
5%
1/16W
MF-LF
2 402
=PP5V_S3_PWRCTL
R6910
100K
5%
1/16W
MF-LF
2 402
69
P5VS3_REG_PGOOD
MAKE_BASE=TRUE
PM_EN_USB_PWR
43
NOSTUFF
1
C6924
0.47UF
=DDRREG_EN
10%
6.3V
70
CERM-X5R
402
SLP_M ENABLES
63 62 6 5
SLP_S3 ENABLES
=PP3V3_S5_PWRCTL
OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:
R6946
THIS SLP_M CIRCUIT IS A BACKUP IN CASE

VCC_ME IS REQUIRED IN ANY STATE
OTHER THAN S0. DELETE AFTER PROTO1
NOSTUFF
33
Enable FET
P3V3ME_EN 72
91 63 46 37 33 32 19 5
14
10
PM_SLP_S3_L
91
74LVC08
8
(PM_SLP_S3_L_BUF)
R6944
PLACE SERIES RS NEAR SOURCE
1%
1/16W
MF-LF
402
10K
63
PGOOD_P12V_S0
33
1
MAKE_BASE=TRUE
08
5%
1/16W
MF-LF
402
P3V3S0_EN
NOSTUFF
R6941
P5VS0_EN
5%
1/16W
MF-LF
402
PM_PGOOD_DDRREG_S3 1
PM_SLP_M_L
1K
P1V05_ME_SM_EN
5%
1/16W
MF-LF
402
=PP3V3_S0_PWRCTL
C6925
10%
6.3V
PM_SLP_S3_BUF_L
5%
1/16W
MF-LF
402
PM_SLP_S3_B_R
PCHCORE_PGOOD_R
10K
5%
1/16W
MF-LF
402
CERM-X5R
10%
6.3V
C6941
NOSTUFF
1
0.47UF
0.47UF
10%
6.3V
402
CERM-X5R
10%
6.3V
CERM-X5R
402
C6945
NOSTUFF
1
0.47UF
2
10%
6.3V
CERM-X5R
C6946
0.47UF
402
10%
6.3V
CERM-X5R
402
402
4
5
14
74LVC08
Q6910
TSSOP-HF
U6900
P1V05_ME_SM_DIS
72 63 62 6 5
2N7002DW-X-G
=PP3V3_S0_PWRCTL
SOT-363
R6942
08
R6926
PCHCORE_REG_PGOOD
68 63 62 5
91
C6944
CERM
402
62
NOSTUFF
1
P1V05_SM_DIS_L
R6925
10K
NOSTUFF
C6947
0.47UF
5%
1/16W
MF-LF
2 402
1UF
2
NOSTUFF
1
=PP3V3_S5_PWRCTL
2
91 72
5%
1/16W
MF-LF
402
Enable regulator
PCHCORE VREG
PCHCORE_REG_EN
68 91
91 68 63 62 5
MAKE_BASE=TRUE
P1V05_ME_S0_EN
POWER SEQUENCING ENABLES
72
DRAWING NUMBER
PGOOD_P5V_S0
Apple Inc.
1
C6926
C6942
CERM
R6949
10%
6.3V
CERM
402
402
5%
1/16W
MF-LF
402
Enable regulator
CPUVTT_REG_EN
CPUVTT VREG
67 91
91 67 63 62 11
Enable regulator
CPUVTT_REG_PGOOD
MAKE_BASE=TRUE
PM_EN_PVCORE_CPU
64
TO ENABLE OF CPU VREG
switch to alias after proto1
051-8600

SIZE
REVISION
A.0.0
1UF
1UF
10%
6.3V
PAGE TITLE
ENABLE FET
PCHCORE_REG_PGOOD
MAKE_BASE=TRUE
32 62 70 91
Enable regulator
R6927
5
6
62
63
72 91
DDRVTT_EN
switch to alias after proto1
Enable FET
Enable FET
P1V5_S0_EN
10K
72 63 62 6 5
72 91
72 91
62
5%
1/16W
MF-LF
402
R6922
91 19 5
OUT
5%
1/16W
MF-LF
402
PM_SLP_S3_BUF_L
91 70 5
72 91
Enable FET
R6948
0
OUT
Enable FET
R6947
TSSOP-HF
U6900
PP1V8_S0 VREG (CPU PLL)
5%
1/16W
MF-LF
402
10K
R6920
33
BRANCH
PAGE
69 OF 110
SHEET
62 OF 92
PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0

63 6
=PP3V3_S0_PWRCTL
72 63 62 6 5
=PP12V_S0_PWRCTL
ME PGOOD SEQUENCE
R7020
R7017
1%
1/16W
MF-LF
402
63 6
10K
1%
1/16W
MF-LF
402
CRITICAL
8
51
1V60_COMP_REF
=PP1V8_S0_CPU_PLL
1%
1/16W
MF-LF
402
U7030
5%
1/16W
MF-LF
2 402
PGOOD_1V8_S0_G2
NOSTUFF
PGOOD_P1V8_S0
MMDT3904-X-G
LM393
PGOOD_1V8_S0_G1
Q7011
5.6K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
=PP1V05_SM_ME
1
5%
50V
2 CERM
402
1%
1/16W
MF-LF
2 402
(1.67V/1.22V; 132mV Hysteresis)
C7041
100PF
30.1K
PM_ME_PWRGD
5%
NOSTUFF
R7041
SOT-363-LF
63 62 6 5
NOSTUFF
NOSTUFF
19 63 91
D
R7061
10K
NOSTUFF
MF-LF
402
5%
1/16W
MF-LF
2 402
C7042
0.1UF
Q7040
PGOOD_1V05ME_G25
=PP3V3_S5_PWRCTL
R7070
PM_ME_PWRGD_R 1/16W
NOSTUFF
MMDT3904-X-G
R7043
33K
COMPONENT VALUES FROM CRB

NEED TO VERIFY TIMINGS
Q7011
NOSTUFF
R7040
DELAY REQUIREMENTS
8.3 MS ON RISE/ 2.8MS ON FALL
63 91
SOT-363-LF
GND
1V80_COMP_REF
1%
1/16W
MF-LF
402
SOI-HF
V+
2.0K 2
10K
49.9K
20%
16V
CERM
603
R7002
16 13 6
R7007
C7010
5%
1/16W
MF-LF
2 402
R7018
0.1UF
R7021
=PP3V3_SM_PWRCTL
10K
=PP12V_S0_PWRCTL
72 6
64.9K
10%
2 16V
X5R
402
MMDT3904-X-G
SOT-363-LF
CPUVTT_REG_PGOOD
VTTS3PG_2
Q7060
MMDT3904-X-G
SOT-363-LF
PGOOD_1V05ME_G1
72 63 6
72 6
=PP12V_S5_PWRCTL
1
R7080
72 63 6
100K
1%
1/16W
MF-LF
402
CRITICAL
8
2
V+
R7082
89 6
PP12V_S0
49.9K
20%
16V
CERM
603
9V_91_COMP_REF
2.0K 2
1%
1/16W
MF-LF
402
12V_COMP_REF
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R70831
C7080
1%
1/16W
MF-LF
402
U7080
PGOOD_12V_S0_G2
D
G
Q7080
2N7002DW-X-G
PGOOD_12V_S0_G1
=PP3V3_S0_PWRCTL
SOT-363
Q7060
MMDT3904-X-G
SOT-363-LF
1
5 6 62 63 72
=PP3V3_S5_PWRCTL
5 6 62 63
CRITICAL
U7080
GND
2 VTTS3PG_1
DISABLE CPUVTT_REG_PGOOD WHEN SLP_S3_L = 0 (PER PIKETON PDG)
SOT-363
10K
5%
1/16W
MF-LF
402
62
2N7002DW-X-G
SOI-HF
PGOOD_P12V_S0
Q7080
LM393
2
D
PM_SLP_S3_L
10K
10K
0.1UF
R7081
91 62 46 37 33 32 19 5
10%
6.3V
2 CERM-X5R
402
R7086
R7084
=PP12V_S5_PWRCTL
C7040
0.47UF
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
33.2K
R7060
SOT-363-LF
NOSTUFF
301K
=PP3V3_S3_PWRCTL
MMDT3904-X-G
NOSTUFF
R7042
Q7040
11 62 67 91
LM393
1K
5%
1/16W
MF-LF
402
GND
(9.91V/9.58V; 330mV Hysteresis)
R7050
SOI-HF
V+
RSMRST_PWRGD
OUT
45 91
To SMC (2)
1
SPARE
C7050
0.1UF
10%
16V
2 X5R
402
FROM THIS SMC GENERATES PM_RSMRST_L

WHICH GOES INTO RSMRST_L OF PCH
DELAY IS ABOUT 200MS
S0 RAILS PGOOD
72 63 62 6 5
=PP3V3_S0_PWRCTL
=PP3V3_S0_PWRCTL
=PP3V3_S0_PWRCTL
72 63 62 6 5
5 6 62 63 72
R7025
10K
5%
1/16W
MF-LF
2 402
0.1UF
91 64 26 5
R7032
C7022
14
PM_PGOOD_PVCORE_CPU
74LVC08
TSSOP-HF
U7000
5
PM_SPARE_PGOOD
33
91
91
14
PGOOD_CPU_GFX_DDR 1
PGOOD_PCH_AND_P1V8 2
74LVC08
3 91 PGOOD_SYSPWROK
=PP3V3_S0_PWRCTL
91 63
10
PGOOD_P1V8_S0
91 72 48
91 68 62 5
PGOOD_P3V3_S0
13
PCHCORE_REG_PGOOD
12
14
R7071
1
63 62 6 5
74 73 6
=PP3V3_S0_MXM
=PM_MXM_PGOOD_PULLUP
74
12
PULL-UP ON MXM PAGE
14
NOSTUFF
R7024
1
NOSTUFF
R7031
100K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
APPROXIMATE DELAY OF 10-15MS

IBEX PEAK EDS
91 74
U6900
11
ALL_SYS_PWRGD
19 63 91
33
ALL_SYS_PWRGD_R
OUT
33
PM_SYS_PWRGD
19 32 91
5%
1/16W
MF-LF
402
PM_MXM_PGOOD
NOSTUFF
5%
1/16W
MF-LF
402
OPTION FOR PCH PWROK AND SYSPWROK

TO BE DRIVEN BY SAME SIGNAL
C7023
0.47UF
33
PAGE TITLE
R7027
6 25 32 91
R7028
08
10%
6.3V
2 CERM-X5R
402
PM_ME_PWRGD
5%
1/16W
MF-LF
402
TSSOP-HF
PM_PCH_PWRGD
POWER SEQUENCING PGOOD
19
91
DRAWING NUMBER
Apple Inc.
051-8600

SIZE
REVISION
A.0.0
ASK INTEL: NEED 100K PULL-DOWN?
R7023
74LVC08
33
5%
1/16W
MF-LF
402
=PP3V3_S5_PWRCTL
PGOOD_SYSPWROK_R 13
91
PGOOD_PCH_S0
08
ALL_SYS_PWRGD CIRCUIT
46 91
08
7
91
SMC_DELAYED_PWRGD
TSSOP-HF
TSSOP-HF
11
5%
1/16W
MF-LF
402
74LVC08
U7000
74LVC08
U7000
5%
1/16W
MF-LF
402
R7029
1
45 91
DELAYED PWRGD (BY 99MS)
R7030
NOSTUFF
72 63 62 6 5
OUT
OPTION FOR SMC TO OUPUT
08
=PP3V3_S0_PWRCTL
SMC
ALL_SYS_PWRGD_SMC
5%
1/16W
MF-LF
402
TSSOP-HF
U7000
33
14
74
R7022
08
7
72 63 62 6 5
PM_MXM_EN
5%
1/16W
MF-LF
402
20%
10V
CERM
402
BRANCH
PAGE
70 OF 110
SHEET
63 OF 92
CPU CORE REG 1.1V/110A

6
R7118
2
C7104
PPVCORE_S0_CPU_REG
1
89
2 VR_CPU_VSNS_XW_P
R7128
0
1
IN
89 13
IN
R7139
5%
1/16W
MF-LF
402
NET_PHYSICAL_TYPE=SNS_DIFF
XW7120
89 49 13
1K
VOLTAGE=1.1V
OMIT
89
R7127
SM
XW7130
SM
R7137
2 VR_CPU_VSNS_R_N
5%
1/16W
MF-LF
402
289 VR_CPU_VSNS_XW_N
VOLTAGE=0V
NET_PHYSICAL_TYPE=SNS_DIFF
OMIT
89 64
1%
1/16W
MF-LF
402
C7102
1K
0.0022UF
10%
2 50V
CERM
402
R71001
1.02K
1%
1/16W
MF-LF
402 2
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
20.0K
20.0K
R71051
R71551
1%
1/16W
MF-LF
402 2
R71781
1%
1/16W
MF-LF
402 2
10%
50V
CERM
402
R71771
5%
1/16W
MF-LF
402 2
89 64
MAX_NECK_LENGTH=3MM
VOLTAGE=5V
VR_CPU_PWM1
R7131
LOCAL 5V
R7146 1R7104
1M
806
NOSTUFF
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R7149
89
VR_VDF_R2 1 47.5 2
1%
1/16W
MF-LF
402
C7107
1UF
AGND_CPU 64
VR_CPU_FB
5%
1/16W
MF-LF
402 2
14 FB
U7100ISEN1+
NOSTUFF
C7130 1
15PF
1%
50V
C0G 2
402
C7180
0.1UF
20%
2 10V
CERM
402
6.8K
0603
1 R7106
1 R7107
21K
5%
1/16W
MF-LF
2 402
R7108
75K
1%
1/16W
MF-LF
2 402
28
ISEN1- 27
89
89
R7109
89
1%
1/16W
MF-LF
2 402
64
IN
89 64
64 6
=PP3V3_S0_VRD
R7111 1
PM_EN_PVCORE_CPU
PP5V_S0_CPU_VCORE_VCC
=PP3V3_S0_VRD
=PPVTT_S0_CPU
AGND_CPU
1K
200K
91 63 26 5
OUT
PM_PGOOD_PVCORE_CPU
89
VR_CPU_SS
VR_CPU_DAC
11 DAC
1%
1/16W
MF-LF
402
89
VR_CPU_REF
12 REF
89
PWM2 20
89
89
89
PWM3 31
2.0K
5%
1/16W
MF-LF
402 2
ISEN3+ 29
ISEN3- 30
PWM4 25
33 EN_VTT
VR_CPU_EN_VTT
C7109
0.01UF
10%
2 16V
CERM
402
R7114
R7115
1%
1/16W
MF-LF
402 2
49.9K
1%
1/16W
MF-LF
402 2
49.9K
1%
1/16W
MF-LF
2 402
89
5%
25V
2 CERM
402
OUT
R7145
1
NOSTUFF
IN
CPU_PSI_L
R7117
NSR0140P2T5G
2
SOD-923-HF
NOSTUFF
C7171
R7171
10%
50V
2 CERM
402
0.020UF
5%
1/16W
MF-LF
402
89
VR_CPU_IOUT_PD
89 16 13
89
IN
IN
65 89
1%
1/16W
MF-LF
402
VR_CPU_PWM2
5%
1/16W
MF-LF
402
VR_CPU_ISNS2_R_P
VR_CPU_ISNS2_R_N
R7141
165
1%
1/16W
MF-LF
402
VR_CPU_PWM3_R
NOSTUFF
C7140
15PF
5%
1/16W
MF-LF
402
1
C7141
C7142
VR_CPU_ISNS2_P
VR_CPU_ISNS2_N
220PF
5%
25V
2 CERM
402
10%
16V
2 X5R
402
5%
2 50V
CERM
402
C7143
0.1UF
150PF
1%
50V 2
C0G
402
65 89
OUT
R7142
VR_CPU_ISNS2_RR_2
65 89
IN
65 89
IN
R7143
1.02K2
VR_CPU_PWM4_R
89
89
89
VR_CPU_ISNS4_R_P
VR_CPU_ISNS4_R_N
1%
1/16W
MF-LF
402
R7150
2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
R7151
OUT
65 89
165
VR_CPU_ISNS3_P
IN
65 89
R7152
VR_CPU_ISNS3_RR_2
1%
1/16W
MF-LF
402
1
15PF
1%
50V
C0G 2
402
5%
1/16W
MF-LF
402
NOSTUFF
C7150
8 PSI*
VR_CPU_PWM3
5%
1/16W
MF-LF
402
C7151
150PF
5%
25V
2 CERM
402
0.1UF
5%
50V
2 CERM
402
C7153
220PF
C7152
10%
16V
2 X5R
402
VR_CPU_ISNS3_N
IN
65 89
R7153
1.02K2
5%
1/16W
MF-LF
402
2
89
VR_CPU_VRDHOT
10K
1%
1/16W
MF-LF
2 402
R7116
37 VR_FAN
VR_CPU_FAN
38 VR_HOT
C7112
0.0033UF
10%
50V
2 CERM
402
1%
1/16W
MF-LF
402
R7160
10 IMON
VR_CPU_IMON
EN_PWR 32
R7161
1
THRM_PAD
89 49
OMIT
OUT
XW7101
64
20
1%
1/16W
MF-LF
2 402
15PF
165
1%
50V 2
C0G
402
OUT
66 89
IN
66 89
IN
66 89
R7162
VR_CPU_ISNS4_RR_2
1%
1/16W
MF-LF
402
NOSTUFF
C7160
SM
1
2
MAX_NECK_LENGTH=3MM
VOLTAGE=0V
AGND_CPU
VR_CPU_PWM4
5%
1/16W
MF-LF
402
64
89 16 13
65 89
VR_CPU_IOUT
D7171
IN
1.02K2
VR_CPU_PWM2_R
41
88 13
VR_CPU_ISNS1_N
VR_CPU_PSI_L
VR_CPU_ISNS1_P
220PF
R7133
VR_CPU_ISNS3_R_P
VR_CPU_ISNS3_R_N
89
ISEN4+ 23
ISEN4- 24
36 VR_RDY
7
6
5
4
3
2
1
40
C7133
0.1UF
VR_CPU_ISNS1_R_P
VR_CPU_ISNS1_R_N
39 TM
VR_CPU_TM
NOSTUFF
1.02K
R71881
R7112 1
R71721
NOSTUFF
35 SS
5%
1/16W
MF-LF
402
NOSTUFF
5%
1/16W
MF-LF
402 2
64 6
46 16 13 11 6
34 FS
89
R7110
C7110
1500PF
10%
25V
X7R
402
62
VR_CPU_FS
C7132
10%
16V
2 X5R
402
5%
2 50V
CERM
402
R7140
ISEN2+ 22
ISEN2- 21
100K
1%
1/16W
MF-LF
2 402
C7131
1
1
5%
1/16W
MF-LF
402
150PF
9 OFS
VR_CPU_OFS
26
SYM_VER_2 PWM1
18 TCOMP
VR_CPU_TCOMP
5%
1/16W
MF-LF
402 2
VCC
CRITICAL
15 VDIFF
17 VSEN
16 RGND
5%
1/16W
MF-LF
402 2
89
RT7101
D
65 89
OUT
R7132
VR_CPU_ISNS1_RR_2
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
13 COMP
QFN
VR_CPU_VDIFF
10%
10V
2 X5R
402
VR_CPU_COMP
R7148 R7144
165
NOSTUFF NOSTUFF
R7147
LAYOUT: PLACE RT7101 NEAR HOT SPOT.
CPU VCORE
VOUT = VCORE
PEAK = 110A
AVG
= 90A
560PF
89
C7106
5%
1/8W
MF-LF
805
NOSTUFF
1%
1/16W
MF-LF
402
470PF
2.2
10%
50V
CERM
402
R7103
VR_VDF_R1 1
C7105
1%
1/16W
MF-LF
402
VR_HOT goes HIGH when VTM/VCC < 28%
and LOW when VTM/VCC > 33%.
R7102
C7103
VR_CPU_COMP_R
VR_CPU_COMP_RC
5%
1/16W
MF-LF
402
AGND_CPU
64
89
R7179
10%
50V
2 CERM
402
10%
2 50V
CERM
402
C7101
0.0022UF
0.0022UF
5%
1/16W
MF-LF
402
89
VR_CPU_RGND
89
5%
1/16W
MF-LF
402
R7138
1K
10
16.5K2
NOSTUFF
5%
50V
CERM
402
SIGNAL_MODEL=EMPTY
1
R7101
VR_CPU_VSEN
1.25 mOhm loadline
R7129
1
89
5%
1/16W
MF-LF
402
VR_CPU_VSNS_R_P
5%
1/16W
MF-LF
402
CPU_VCC_PKG_SENSE_P
CPU_VCC_PKG_SENSE_N
10
22PF
VR_CPU_FB_R
O/P= PPVCORE_S0_CPU_REG
=PP5V_S0_VRD
66 65 6
19
ISL6334
5%
1/16W
MF-LF
402
C7161
150PF
C7162
0.1UF
5%
2 50V
CERM
402
10%
2 16V
X5R
402
C7163
220PF
5%
2 25V
CERM
402
AGND_CPU
VR_CPU_ISNS4_P
VR_CPU_ISNS4_N
R7163
1.02K2
CPU_VID<7..0>
7
6
R7136
10K
5%
1/16W
MF-LF
402
4
3
2
R71351
1K
5%
1/16W
MF-LF
402 2
1
0
1%
1/16W
MF-LF
402
VR_CPU_EN_PWR
1
0.001UF
10%
2 50V
CERM
402
C7135
CRITICAL
A
6
L7100
0.36UH-45A-0.76MOHM
=PP12V_S0_VRD
MSQ1211R36LF-TH
IMAX = 10.5A
PP12V_S0_CPU_FLTRD
PAGE TITLE
VREG: PPVCORE_S0_CPU
65 66 89
VOLTAGE=12V
DRAWING NUMBER
152-0104
Apple Inc.
CPU CORE INPUT Filtering

SIZE
A.0.0
051-8600
REVISION
BRANCH
PAGE
71 OF 110
SHEET
64 OF 92
89 66 64
CRITICAL
C7270
270UF
CRITICAL
CRITICAL
C7271
20%
2 16V
ELEC
8X9-TH1
R7205
R7202
10
VR_CPU_DRV1_VCC
R7201
1
1
5%
1/10W
MF-LF
603 2
5%
1/10W
MF-LF
2 603
5%
1/10W
MF-LF
603 2
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV1_UVCC
1UF
10%
2 16V
X5R
603
ISL6622
DFN
VR_CPU_DRV1_GDSEL 3 GDSEL
BOOT
NOSTUFF
1 C7200 1
UGATE
CRITICAL
1UF
0
10%
5%
PHASE
2 16V
1/10W
X5R
MF-LF
603
4 PWM
603
LGATE
89
R7207
1UF
10%
16V 2
X5R
603
VR_CPU_DRV1_BOOT
89
VR_CPU_DRV1_UGATE
10
89
VR_CPU_PHASE1
89
VR_CPU_DRV1_LGATE
R72061
DIDT=TRUE
DIDT=TRUE
89
PPVCORE_S0_CPU_REG1
1 2
89
Q7202
376S0771
R7221
R72251
10
5%
1/10W
MF-LF
2 603
5%
1/10W
MF-LF
603 2
5%
1/10W
MF-LF
603 2
VR_CPU_DRV2_VCC
89
C7220
10%
VCC
PVCC
2 16V
X5R
C7221
1UF R72241
10%
16V
2 X5R
603
U7221
603
ISL6612
VR_CPU_PWM2
89
VR_CPU_DRV2_GDSEL
3 NC
8 NC
NOSTUFF
R7227
VR_CPU_DRV2_BOOT
UGATE 1
89
VR_CPU_DRV2_UGATE
NOSTUFF
R72421
LGATE 6
89
VR_CPU_DRV2_LGATE
DIDT=TRUE
DIDT=TRUE
NOSTUFF
R72261
5%
1/10W
MF-LF
2 6
D
5
89
IRF6795
89
1UF
10%
16V
603
C7240
NOSTUFF
VCC
PVCC
C7241
1UF R72441
10%
16V
2 X5R
603
U7241
2 X5R
ISL6612
DIRECTFET-MX
376S0771
4
89
89
CRITICAL
VR_CPU_PWM3
UGATE 1
VR_CPU_DRV3_GDSEL
NOSTUFF
R7247
PHASE 10
3 NC
8 NC
LGATE 6
IRF6710
S1
376S0772
1
3
1%
1W
MF
0612
VR_CPU_ISNS2_XW_N
1UF
C7230
0.001UF
10%
2 50V
X7R
402
C7231
0.001UF
10%
2 50V
X7R
402
C
PPVCORE_S0_CPU_REG
CRITICAL
270UF
20%
2 16V
ELEC
8X9-TH1
1
2
VR_CPU_ISNS2_XW_P
89
OMIT
XW7222
SM
SIGNAL_MODEL=EMPTY
1
VR_CPU_ISNS2_P
C7260
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
VR_CPU_DRV3_UGATE
VR_CPU_PHASE3
89 VR_CPU_DRV3_LGATE
89
C7261
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
10UF
C7247
1UF
C7250
0.001UF
10%
10%
16V
2 16V
X5R-CERM2 X5R
0805
603
64 89
OUT
64 89
10%
50V
2 X7R
402
C7251
0.001UF
10%
50V
402
2 X7R
C7243
C7262
R72461
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
2 6
89
XW7241
10%
2 50V
CERM
402
NOSTUFF
376S0771
4
CRITICAL
CRITICAL
C7264
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
6 64 65 66
VR_CPU_ISNS3_XW_P
2
OMIT
XW7242
SM
SIGNAL_MODEL=EMPTY
VR_CPU_ISNS3_P
VR_CPU_ISNS3_N
OUT
64 89
OUT
64 89
PPVCORE_S0_CPU_REG
1
89
PPVCORE_S0_CPU_REG
2
4
SM
128S0209
CRITICAL
330UF-0.006OHM
OMIT
0.001UF
DIRECTFET-MX
VR_CPU_ISNS3_XW_N
DIDT=TRUE
1 C7248
SIGNAL_MODEL=EMPTY 1
IRF6795
1%
1W
MF
0612
89
VR_CPU_PH3_SNUB
7CRITICAL
Q7242
DIDT=TRUE
20%
2 2V
POLY
CASE-D2-SM
PPVCORE_S0_CPU_REG3 1
5%
1/8W
MF-LF
805 2
C7263
89
2.2
DIDT=TRUE
DIDT=TRUE
152-0114
NOSTUFF
0.22UF
10%
2 16V
X7R
603
CRITICAL
R7248
0.0005
MSQ1208-TH
VR_CPU_DRV3_BOOT
CRITICAL
1
10%
16V
2 X5R-CERM
0805
L7241
DIDT=TRUE
OUTPUT BULK DECOUPLING:

CRITICAL
10UF
C7249
OUT
THESE TWO CAPS ARE FOR EMC
CRITICAL
1
C7246
0.36UH-35A
11
CRITICAL
1
CRITICAL
CRITICAL
5%
1/10W
MF-LF
603 2
89
PAD
6 64 65 66
2
4
89
C7245
VR_CPU_BOOT3_RC
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE
THRML
GND
5%
1/10W
MF-LF
2 603
64 89
R7228
2
OMIT
DIDT=TRUE
XW7221
1 C7228
SM
0.001UF
SIGNAL_MODEL=EMPTY
10%
1
2 50V
CERM
402
NOSTUFF
QFN1
BOOT 2
OUT
VR_CPU_DRV3_PVCC
4 PWM
C7227
10%
10%
16V
2 16V
X5R-CERM 2 X5R
0805
603
152-0114
Q7241
89
10UF
PPVCORE_S0_CPU_REG2
VR_CPU_PH2_SNUB
7CRITICAL
Q7222
2 603
VR_CPU_DRV3_UVCC
64 89

1
C7229
OUT
2.2
PHASE 3
10
IN
0.0005
5%
1/8W
MF-LF
805 2
R7241
5%
1/10W
MF-LF
603 2
VR_CPU_DRV3_VCC
10%
16V 2
X5R
603
10%
2 16V
X5R-CERM
0805
MSQ1208-TH
C7223
10%
2 16V
X7R
603
1
1
5%
1/10W
MF-LF
603 2
1UF
XW7202
SM
SIGNAL_MODEL=EMPTY
0.36UH-35A
0.22UF
DIDT=TRUE
VR_CPU_PHASE2
10UF
L7221
5%
1/10W
MF-LF
603 2
6 64 65 66
OMIT
CRITICAL
1
C7226
CRITICAL
DIDT=TRUE
DIDT=TRUE
CRITICAL
1
CRITICAL
89
R7245
10
402
CRITICAL
10%
VR_CPU_ISNS2_N
C7242
OMIT
XW7201
PAD
20%
2 16V
ELEC
8X9-TH1
VR_CPU_BOOT2_RC
PHASE 10
THRML
GND
5%
1/10W
MF-LF
2 603
89
CRITICAL
11
IN
BOOT 2
C7225
270UF
QFN1
4 PWM
CRITICAL
1UF
10%
16V 2
X5R
603
402
VR_CPU_ISNS1_P
IRF6710
S1
NOSTUFF
7
1UF
0.001UF
VR_CPU_ISNS1_XW_P
89
NOSTUFF
VR_CPU_DRV2_PVCC
VR_CPU_DRV2_UVCC
1
C7211
2 50V
X7R
PPVCORE_S0_CPU_REG
Q7221
376S0772
PHASE 2
NOSTUFF
10
10%
VR_CPU_ISNS1_N
R72221
C7222
0.001UF
2
4
SM
SIGNAL_MODEL=EMPTY
10%
2 50V
CERM
402
DIRECTFET-MX
C7208
0.001UF
IRF6795
89
DIDT=TRUE
CRITICAL
CRITICAL
1%
1W
MF
0612
1
3
VR_CPU_ISNS1_XW_N
VR_CPU_PH1_SNUB
6 7
D
5
C7210
2 50V
X7R
152-0114
2.2
5%
1/8W
MF-LF
805 2
DIDT=TRUE
1UF
10%
2 16V
X5R
603
0.0005
MSQ1208-TH
NOSTUFF
DIDT=TRUE
C7207
R7208
CRITICAL
CRITICAL
11
VR_CPU_PWM1
IN
89
10UF
L7201
PAD
5
89 64
THRML
GND
R72041
10%
16V
2 X5R-CERM
0805
10%
2 16V
X5R-CERM
0805
0.36UH-35A
1 C7203
DIDT=TRUE
0.22UF
10%
2 16V
X7R
603
5%
1/10W
MF-LF
603 2
U7201
VR_CPU_BOOT1_RC
VCC UVCC LVCC
C7202
89
C7215
C7201
C7206
10UF
20%
2 16V
ELEC
8X9-TH1
2
5
CRITICAL
CRITICAL
C7205
270UF
VR_CPU_DRV1_PVCC
S1
PHASE 1
10
CRITICAL
Q7201
IRF6710
376S0772
NOSTUFF
270UF
20%
2 16V
ELEC
8X9-TH1
89 64
PP12V_S0_CPU_FLTRD
1
89 64
PAGE TITLE
VREG: CPU CORE - PHASES 1-3
6 64 65 66
DRAWING NUMBER
110A MAX
Apple Inc.
C7265
051-8600
330UF-0.006OHM

A.0.0
20%
2 2V
POLY
CASE-D2-SM
SIZE
REVISION
BRANCH
PAGE
72 OF 110
SHEET
65 OF 92
7
89 65 64
PP12V_S0_CPU_FLTRD
CRITICAL
NOSTUFF
R7311
R7312
10
R7313
5%
1/10W
MF-LF
603 2
VR_CPU_DRV4_VCC
5%
1/10W
MF-LF
2 603
C7311
NOSTUFF
C7310
1UF
10%
16V 2
X5R
603
VCC
10%
16V
603
R7303
10%
16V 2
X5R
603
PVCC
U7301
2 X5R
4 PWM
89
VR_CPU_DRV4_GDSEL
BOOT 2
3 NC
8 NC
NOSTUFF
R7310
VR_CPU_DRV4_BOOT
C7306 C7307
1
10UF
10%
2 16V
X5R-CERM
0805
1UF
10%
2 16V
X5R
603
C7308
0.001UF
10%
50V
2 X7R
402
C7309
0.001UF
10%
50V
402
2 X7R
0.36UH-35A
1
C7303
89
VR_CPU_PHASE4
R73021
10%
2 16V
X7R
603
2.2
LGATE 6
89
VR_CPU_DRV4_LGATE
6 7
DIDT=TRUE
DIDT=TRUE
C7302
DIRECTFET-MX
89
VR_CPU_ISNS4_XW_N
0.001UF
376S0771
10%
2 50V
CERM
402
NOSTUFF
PPVCORE_S0_CPU_REG
6 64 65 66
2
4
89
VR_CPU_ISNS4_XW_P
89
DIDT=TRUE
1
IRF6795
1
3
1%
1W
MF
0612
152-0114
VR_CPU_PH4_SNUB
Q7302
DIDT=TRUE
PPVCORE_S0_CPU_REG4
5%
1/8W
MF-LF
805 2
CRITICAL
89
NOSTUFF
1 2
VR_CPU_DRV4_UGATE
89
PHASE 10
2
MSQ1208-TH
DIDT=TRUE
UGATE 1
R7301
0.0005
L7301
PAD
10UF
CRITICAL
CRITICAL
THRML
GND
5%
1/10W
MF-LF
2 603
89
CRITICAL
C7305
10%
2 16V
X5R-CERM
0805
0.22UF
5%
1/10W
MF-LF
603 2
ISL6612
VR_CPU_PWM4
OMIT
XW7301
SM
SIGNAL_MODEL=EMPTY
11
IN
QFN1
89 64
20%
2 16V
ELEC
8X9-TH1
DIDT=TRUE
1UF
1UF
VR_CPU_BOOT4_RC
270UF
CRITICAL
C7304
CRITICAL
VR_CPU_DRV4_PVCC
VR_CPU_DRV4_UVCC
C7312 1
S1
Q7301
IRF6710
PHASE 4
10
5%
1/10W
MF-LF
603 2
CRITICAL
376S0772
OMIT
XW7302
SM
SIGNAL_MODEL=EMPTY
VR_CPU_ISNS4_P
VR_CPU_ISNS4_N
OUT
64 89
OUT
64 89
66 65 64 6
PPVCORE_S0_CPU_REG
1
C7330
0.1UF
20%
10V
2 CERM
402
C7340
1UF
10%
16V
2 X5R
603
C7331
0.1UF
20%
10V
2 CERM
402
C7341
1UF
10%
16V
2 X5R
603
C7332
0.1UF
20%
10V
2 CERM
402
C7342
1UF
10%
16V
2 X5R
603
C7333
0.1UF
20%
10V
2 CERM
402
C7343
1UF
10%
16V
2 X5R
603
C7334
0.1UF
20%
10V
2 CERM
402
C7344
1UF
10%
16V
2 X5R
603
C7335
0.1UF
20%
10V
2 CERM
402
C7345
1UF
10%
16V
2 X5R
603
C7336
0.1UF
20%
10V
2 CERM
402
C7346
1UF
10%
16V
2 X5R
603
C7337
0.1UF
20%
10V
2 CERM
402
C7347
1UF
10%
16V
2 X5R
603
C7338
0.1UF
20%
10V
2 CERM
402
C7348
1UF
10%
16V
2 X5R
603
C7339
0.1UF
20%
10V
2 CERM
402
C7349
1UF
10%
16V
2 X5R
603
PAGE TITLE
VREG: CPU CORE - PHASE 4

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
73 OF 110
SHEET
66 OF 92
CPU VTT REG 1.1V/30A
CPU VTT
VOUT = 1.1V OR 1.05V
PEAK = 35A
AVG
= 30A
O/P= PPVTT_S0_CPU_REG
D
DIDT=TRUE
R7462
C7405
1000PF
10.5K2
42.2K2
89
10%
25V
X7R
402
89
89
NP0-C0G
5%
402
25V
10
20%
2 16V
ELEC
8X9-TH1
R7409
1K
1K
NOSTUFF
5%
1/16W
MF-LF
402
R7411
2
NOSTUFF
5%
1/16W
MF-LF
402
R7412
R7413
5%
1/16W
MF-LF
402
CRITICAL
Q7441
1C7402
89
FS
24 VTT_REG_BOOT1
25
23
27
29
18
BOOT2
UGATE2 17
PHASE2 19
LGATE2 14
(SELECT MODE= VRM10)
C7492
PPVTT_S0_CPU_REG
67 6
CRITICAL
1
RJK0365DPA
MLP5X6-LFPAK-WPAK 5
CRITICAL
1
10%
16V
2 X5R-CERM
1206
Q7450
C7450
10UF
C7451
10%
16V
402
10%
16V
2 X5R-CERM
1206
1UF
2 X5R
CRITICAL
1
C7452
10UF
270UF
20%
2 16V
ELEC
8X9-TH1
R7431
0
89
VTT_REG_UGATE2
DIDT=TRUE
C7460
88.7K2
1
L7454
DIDT=TRUE
Q7451
CRITICAL
RJK0348DPA 5
WPAK
D7450
89
VTT_REG_PH2_SNUB
DIDT=TRUE
0.022UF
VTT_REG_COMP1
1%
1/16W
MF-LF
402
C7418
4700PF
10%
25V
X7R
0402
VTT_REG_VIDFF2
R7418
R7419
100
89 67
PP5V_CPUVTT_VR
75K
89
1%
1/16W
MF-LF
402
CPU_VTTSENSE_R_P
R7425
VTT_REG_VSEN
100PF
10
R7461
1%
1/16W
MF-LF
402
100
CPU_VTTSENSE_N
13 89
PLACEMENT_NOTE=PLACE R7422 WITHIN 25.4MM OF CPU, NO STUBS.

PLACEMENT_NOTE=PLACE R7423 WITHIN 25.4MM OF CPU, NO STUBS.
CPU_VTTSENSE_P
13 49 89
VTT_REG_VSEN_1
1%
1/16W
MF-LF
402
28K
SM
PPVTT_S0_CPU_REG
PAGE TITLE
6 49 67
CPU VTT REGULATOR

DRAWING NUMBER
XW7422
Apple Inc.
OMIT
051-8600
TABLE_5_HEAD
QTY
DESCRIPTION
BOM OPTION

TABLE_5_ITEM
113S0127
RES,68k,0603,5%
TH7401
SIZE
REVISION
A.0.0
PART#
R7420
1%
1/10W
MF-LF
2 603
5%
25V
2 NP0-C0G
402
5%
1/16W
MF-LF
402
5%
50V
CERM 2
402
R7423
5%
25V
NP0-C0G 2
402
C7426
VTT_OFST
NOSTUFF
89
CPU_VTTSENSE_R_N
5%
1/16W
MF-LF
402
NOSTUFF
1 2 3
C7455
1000PF
R7422
89
1000PF
5%
1/16W
MF-LF
402
XW7421
89
NOSTUFF
1%
1/16W
MF-LF
402
C7423
R7460
10
VTT_REG_RGND_1
NOSTUFF
89
VTT_REG_VIDFF
1%
1/16W
MF-LF
402
50V
10%
CERM
603
VTT_REG_RGND
C7416
89
VTT_REG_VIDFF1
100
3.01K2
10%
50V
CERM
402
1.0K 2
1%
1/10W
MF-LF
603
R7416
NOSTUFF
1%
1/10W
MF-LF
2 603
VTT_REG_LGATE2 4
1%
1/16W
MF-LF
402
R7424
R7417
390PF
1.1
OMIT
SM
C7417
R7421
100PF
R7455
CTLSH3-30M833
TLM833
MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
5%
50V
2 CERM
402
C7462
MSQ1211R36LF-TH
VTT_REG_FB
CRITICAL
C7463
CRITICAL
1%
1/16W
MF-LF
402
C7422
0.36UH-45A-0.76MOHM
SWITCHNODE
VTT_REG_PHASE2
1%
1/16W
MF-LF
402
R7434
C7425
89 67
R7433
1K
CRITICAL
1 2 3
X7R-CERM
16V
0.1UF
10%
402
CRITICAL
C7461
330UF-0.0045OHM
330UF-0.0045OHM
20%
20%
2 2V
CRITICAL 2 2V
CRITICAL
POLY
POLY
1
1
CASE-D2-SM
CASE-D2-SM
330UF-0.0045OHM
330UF-0.0045OHM
20%
20%
2V
2
2 2V
POLY
POLY
CASE-D2-SM
CASE-D2-SM
C7431
2 VTT_REG_BOOT2_R
VTT_REG_ISEN2
VTT_REG_REF
VTT_REG_COMP
OUTPUT BULK DECOUPLING
D
5%
DIDT=TRUE 1/10W
MF-LF
603
89
C7453
89
89
6 49 67
NOSTUFF
89
C7440
1000PF
5%
25V
2 NP0-C0G
402
1 2 3
0.0022UF
5%
50V
CERM 2
402
NOSTUFF
DIDT=TRUE
10%
50V
2 CERM
402
100PF
X7R-CERM
16V
THRM_PAD
1.1
NOSTUFF
R7440
1%
1/10W
MF-LF
2 603
CRITICAL
89
DIDT=TRUE
1%
1/16W
MF-LF
402
VTT_REG_BOOT2
ISEN1 26
ISEN2 16
1K
89
VTT_REG_FS
5 COMP
5%
1/16W
MF-LF
402
89
DIDT=TRUE
R7432
VTT_REG_ISEN1
R7414
1K
10%
DIDT=TRUE
ENLL 20
BOOT1
UGATE1
PHASE1
LGATE1
D7440
CTLSH3-30M833
PGOOD 28
2 REF
6 FB
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm 402
VTT_REG_PH1_SNUB
0.1UF
2 VTT_REG_BOOT1_R
5%
1/10W
MF-LF
603
OCSET 10
VID4
VID3
VID2
VID1
VID0
VID12.5
VTT_REG_LGATE1
C7430
R7430
MSQ1211R36LF-TH
TLM833
WPAK
10%
2 16V
X7R
805
QFN
RJK0348DPA
1.0UF
7 VDIFF
SWITCHNODE
CRITICAL
CRITICAL
8 RGND
9 VSEN
22
21
30
31
32
1
VTT_REG_PHASE1
DIDT=TRUE
12 ISUM
13 IREF
VTT_VID4
VTT_VID3
VTT_VID2
VTT_VID1
VTT_VID0
VTT_VID12P5
0.36UH-45A-0.76MOHM
89 67
ISL6568
11 ICOMP
L7441
1 2 3
3 OFS
5%
1/16W
MF-LF
402
1K
1K
U7400
VTT_REG_IREF
NOSTUFF
R7410
VTT_REG_OCSET
89
VCC
PVCC
CRITICAL
1%
1/16W
MF-LF
402
NOSTUFF
VID0=0, VID[4-1]=1, VTT VR o/p= 1.10V

Internal Pu on VID lines
VTT_REG_ISUM
1%
1/16W
MF-LF
402
R7407
5%
1/16W
MF-LF
402
10%
16V
X7R 2
805
VTT_REG_ICOMP
4.99 2
NOSTUFF
1K
1.0UF
R7408
1
PPVTT_S0_CPU_REG
C74011
1%
1/16W
MF-LF
402
0.012UF
2
1%
1/16W
MF-LF
402
C7403
5%
25V
2 NP0-C0G
402
1%
1/16W
MF-LF
402
487
R7403
VTT_ICOMP1
1%
1/16W
MF-LF
402
270UF
10KOHM
C7404
1000PF
67 49 6
402
CRITICAL
C7445
5%
25V
NP0-C0G 2
402
2 16V
X5R
C7406 1
1000PF
NOSTUFF
10%
2 16V
X5R-CERM
1206
10UF
1%
1/16W
MF-LF
402
NOSTUFF
35.7K2
VTT_REG_PHASE2
20.0K2
89 67
R7401
VTT_ICOMP2
R7404
10%
C7444
1%
1/16W
MF-LF
402
R7402
2
VTT_REG_UGATE1
0603-LF
R7406
1UF
DIDT=TRUE
TH7401
35.7K2
VTT_REG_PHASE1
CRITICAL
C7443
D
89
OMIT
R7405
89 67
MLP5X6-LFPAK-WPAK 5
"PULL-UP" TO VTT RAIL ON CPU PAGE
CPUVTT_REG_EN
IN
10%
2 16V
X5R-CERM
1206
RJK0365DPA
67 89
33
91 62
CRITICAL
PP5V_CPUVTT_VR
C7442
10UF
Q7440
5%
1/10W
MF-LF
603
CRITICAL
CPUVTT_REG_PGOOD
OUT
4.7
15
91 63 62 11
67 6
BRANCH
PAGE
74 OF 110
SHEET
67 OF 92
IBEX PEAK CORE REG 1.05V
OUTPUT = PP1V05_S0_REG
PP1V05_S0_REG
VOUT = 1.05V
PEAK = 7.5A
AVG
= 3A
C
OP_1V05_S0_FB
89
91 62
IN
20%
6.3V
X5R
603
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
4
V5FILT
V5DRV
CRITICAL
6 PGOOD
(PP1V05_S0_FB)
3 VOUT
89
PCHCORE_REG_VFB
89
PCHCORE_REG_TRIP
10%
16V
2 X5R-CERM
0805
10%
25V
X5R
402
VBST 14
DRVH 13
89
PCHCORE_REG_UGATE
LL 12
89
PCHCORE_REG_PHASE
89
PCHCORE_REG_LGATE
DIDT=TRUE
PGND
0.1UF
DIDT=TRUE
C7613
10UF
10%
16V
2 X5R-CERM
0805
RJK0384DPA
10%
16V
2 X5R-CERM
0805
C7620
0.001UF
C7621
0.001UF
10%
50V
2 X7R
402
10%
50V
2 X7R
402
CRITICAL
L7614
WPAK
376S0801
S1/D2
G2
OMIT
XW7614
SM
1
R7615
0.499
1%
1/10W
MF
2 603
OMIT
CRITICAL
1
MF-LF
20%
2 6.3V
POLY-TANT
CASE-D3L-SM
2 402
NOSTUFF
CRITICAL
CRITICAL
C7607
8.45K
1%
1/16W
OUTPUT BULK DECOUPLING
NOSTUFF
R7614
OMIT
PCHCORE_REG_PHASE_C
XW7601
SM
5%
25V
2 CERM
603
NOSTUFF
C7614
1000PF
PCHCORE_PGND_XW
XW7600
SM
2
SM-IHLP-1
PP1V05_S0_REG
1.0UH-13A-5.6M-OHM
SWITCHNODE
1%
1/16W
MF-LF
2 402
330UF
C7608
10UF
10%
16V
2 X5R-CERM
0805
C7609
10UF
10%
16V
2 X5R-CERM
0805
R7616
(PPCHCORE_REG_FB)
1
C7612
10UF
10%
2 16V
X5R
402
Q7601
G1
S2
6.98K
CRITICAL
CRITICAL
C7611
CRITICAL
D1
DIDT=TRUE
15
R7660
C7610
10UF
0.1UF
DRVL 9
THRM_PAD
PCHCORE_REG_BOOT_R
C7650
DIDT=TRUE
11 TRIP
CRITICAL
89
TON 2
5 VFB
GND
DIDT=TRUE
DIDT=TRUE
QFN
SYM 2
1 EN_PSV
5%
1/10W
MF-LF
603
TPS51117RGY_QFN14
PCHCORE_REG_EN
PCHCORE_REG_BOOT 2
U7600
PCHCORE_REG_PGOOD
R7650
PCHCORE_REG_5V_FLT
89
200K 2
10UF
300
1%
1/16W
MF-LF
402 2
OUT
C7601
10K
R7670
PCHCORE_REG_TON
=PP3V3_S0_PCH
R76801
91 63 62 5
R7651
24 21 18 6
10
21K
1%
1/16W
MF-LF
2 402
C7670
1UF
10%
16V
2 X5R
402
AGND_PCHCORE_REG
Vout= 0.75*( 1+R7615/R7616)

Vout= 0.75*( 1 + 8.45/21) = 1.05
PAGE TITLE
IBEX PEAK CORE

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
76 OF 110
SHEET
68 OF 92
3V3 S5 REGULATOR
6
5V S3 REGULATOR
=PP12V_S5_P5VS3_VREG
=PP12V_S5_P3V3S5_VREG
EMC CAPS
PLACE CLOSE TO FET
Power Rating ?
CRITICAL
C7713 1
C7712
C7710
20%
16V 2
POLY
6.3X9-TH
10%
16V
X5R-CERM
0805
10%
16V
X5R-CERM
0805
2 16V
X5R
10UF
100UF
C7711
10UF
0.1UF
DIDT=TRUE
C7722
0.1UF
10%
C7750 C7751
10UF
270UF
10%
2 16V
X5R
402
CRITICAL
10%
16V
X5R-CERM
0805
20%
2 16V
ELEC
8X9-TH1
402
C7752
10%
16V
X5R-CERM
0805
C7753
10%
16V
X5R-CERM
0805
10UF
10UF
2
PP5V_S5_LDO
376S0801
2.2UH-14A
50V
10%
R7790
2 CERM 1
603
R7791
16.5K
G2
TLM833
R7740
10%
50V
89
P3V3S5_REG_BOOT_R
603-1
18
DIDT=TRUE
(P3V3S5_PHASE)
LDO5
PGOOD2 1
CRITICAL
P3V3S5_REG_UGATE 14 UGATE1
UGATE2 22
P3V3S5_REG_BOOT
DIDT=TRUE
89
15 BOOT1
89
89
P3V3S5_REG_ISEN 10
C7721
10%
16V
X5R-CERM
0805
XW7716
OMIT
330UF
20%
6.3V 2
POLY-TANT
CASE-D3L-SM
R77201
45.3K
1%
<Ra> 1/16W
MF-LF
402 2
C7723
0.1UF
2
20%
16V
CERM
603
C7716
R7721 1
<Rb> 10.0K
0.5%
1/16W
MF
402
0.1UF
2
20%
16V
CERM
603
R7724
976
1%
1/16W
MF-LF
402 2
C7720
89
P3V3S5_REG_FB
68K
91 62
23
89
P5VS3_REG_PHASE
LGATE2
20
89
P5VS3_REG_LGATE
ISEN2 26
89
P5VS3_REG_ISEN
OCSET2
25
89
VOUT2
27
DIDT=TRUE
NOSTUFF
C7757 1
0.001UF
FSET2 2
EN2
CRITICAL
D7750
CTLSH3-30M833
5V_SNUBBER
0.01UF
1/16W
MF-LF
10%
16V
402
CERM
CRITICAL
1
R7752
0.499
1% 1/10W
MF 603
2 NOSTUFF
P5VS3_REG_VOUT2
C7760
10UF
6.3V
2 20%
CERM 805-1
R7771
CRITICAL
C7761 1
330UF
C7762
330UF
20%
6.3V 2
POLY-TANT
CASE-D3L-SM
20%
2 6.3V
POLY-TANT
CASE-D3L-SM
14.3K
1%
1/16W
MF-LF
402 2
CRITICAL
Q7751
C7770
TLM833
DIDT=TRUE
14.3K
1%
402
6 92
R7770
10%
50V
CERM 2
402
P5VS3_REG_FB
PP5V_S3_REG
PAB0705AR-SM
SWITCHNODE
P5VS3_REG_OCSET
89
CRITICAL
1
10%
25V
X5R
402
FB2 28
CSD58851Q5A
P5VS3_REG_FSET2
MLP5X6-LFPAK-Q5A 1 2 3
24
376S0631
SM
THRM
PAD
P3V3S5_12VE_EN1
XW7751
OMIT
PGND
R7723
1
2
33K
5%
1/16W
MF-LF
2 402
P3V3S5_REG_FSET1
1
C7701
0.01UF
Vout = 0.6V * (1 + Ra / Rb)
EMC CAPS
PLACE CLOSE
TO L
PHASE2
12 EN1
5%
1/16W
MF-LF
2 402
1000PF
5%
25V
NP0-C0G
402
P5VS3_REG_BOOT
2.2UH-10A-12.5MOHM
DIDT=TRUE
89
10%
50V 2
X7R
402
L7750
0.1UF
P5VS3_REG_UGATE
BOOT2 21
8 FB1
6 FSET1
R7722
1 2 3
C7756
0.001UF
376S0631
19
10UF
10UF
10%
16V
X5R-CERM
0805
C7717
P3V3S5_REG_OCSET 11 OCSET1
P3V3S5_REG_VOUT1 9 VOUT1
P3V3S5_REG_FB_R
89
SM
CRITICAL
89
10%
50V
X7R
402
MLP5X6-LFPAK-Q5A
DIDT=TRUE
ISEN1
29
C7715
128S0237
DIDT=TRUE
C7764
0.001UF
CSD58851Q5A
DIDT=TRUE
P3V3S5_REG_LGATE 16 LGATE1
DIDT=TRUE
PLACEMENT_NOTE=PLACE NEXT TO C7716
DIDT=TRUE
P3V3S5_REG_PHASE 13 PHASE1
DIDT=TRUE
5%
1/10W
MF-LF
603
TP_P5VS3_REG_FCCM
QFN
DIDT=TRUE
89
FCCM 3
ISL62383
89
C7763
CRITICAL
Q7750
VIN 17
EMC: C7763,C7764
PLACE AT L7750.2
62
R7750
U7700
TP_P3V3S5_REG_PGOOD 7 PGOOD1
OUT
C7741
10%
16V
2 X5R
603
5%
1/10W
MF-LF
603
0.1UF
P5VS3_REG_PGOOD
1UF
10%
16V
X5R 2
603
R7710
X7R
D
1
1UF
C7714
10%
25V
X5R
402
DIDT=TRUE
P5V_S5_LDO_R
5V OUTPUT
0.1UF
2.2
P5V_S5_VCC1
1%
1/10W
MF
2 603
C7755
5%
1/8W
MF-LF
2 805
C7740
R7730
0.499
DIDT=TRUE
6 (P3V3S5_LGATE)
NOSTUFF
P3V3S5_REG_SNUB
20%
6.3V
2 CERM
603
GATE_NODE=TRUE
S2
1%
1/16W
MF-LF
2 402
NOSTUFF
1%
1/16W
MF-LF
402
C7742
4.7UF
CRITICAL
CTLSH3-30M833
5%
2 25V
NP0-C0G
402
16.5K
89
C7730
1000PF
GATE_NODE=TRUE
10%
25V
X5R
402
8200PF
D7700
S1/D2
VCC2
C7790
VCC1 5
MMD06CZ-SM
DIDT=TRUE
0.1UF
1 (P3V3S5_UGATE)
SWITCHNODE NET_PHYSICAL_TYPE=POWER
C7754
G1
P5VS3_REG_BOOT_R
WPAK
D1
RJK0384DPA
L7710
Q7710
CRITICAL
PP3V3_S5_REG
EMC: C7754,C7755
PLACE AT Q7330
3V3 OUTPUT
10%
16V
2 CERM
402
R7701
16.5K
1%
1/16W
MF-LF
2 402
R77591
976
1%
1/16W
MF-LF
402 2
P5VS3_EN
1
C7747
0.01UF
10%
2 16V
CERM
402
R7747
16.5K
1%
1/16W
MF-LF
2 402
C7759
NOSTUFF
1
1000PF
C7777
5%
25V
NP0-C0G 2
402
0.001UF
10%
50V
2 CERM
402
P5VS5_REG_FB_R
R77551
RA
75K
1%
1/16W
MF-LF
402 2
RB
1
R7756
10K
1%
1/16W
MF-LF
2 402
PAGE TITLE
5V_S3 / 3V3_S5 VREGS

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
77 OF 110
SHEET
69 OF 92
1.5 V DDR SUPPLY
PPDDR_S3_REG
VOUT = 1.5V
PEAK = 11A
AVG
= 6.7A
=PP12V_S5_DDR_VREG
R7801
2
89
PP5V_S3_DDR_REG_V5FILT
5%
1/16W
MF-LF
402
20%
6.3V
CERM
603
1UF
10%
10V
X5R
402
V5IN
V5FILT
C
IN
62
IN
DDRVTT_EN
=DDRREG_EN
OUT
PM_PGOOD_DDRREG_S3
91 62 5
10 S3
11 S5
13 PGOOD
MODE 4
VTT Enable
VDDQ/VTTREF Enable
VDDQ PGOOD
10mA max load
OMIT
805-3
XW7800
0.033UF
10%
16V
X5R
402
S5 VDDQ VTTREF
HI
ON
ON
HI
ON
ON
LO
OFF
OFF
S3
HI
LO
LO
S0
S3
S5
OMIT
SM
VTT
ON
OFF
OFF
D7831
5%
25V
NP0-C0G 2
402
CTLSH3-30M833
TLM833
NOSTUFF
CRITICAL
1
1V5_SNUBBER
C7835
330UF-0.009OHM
330UF-0.009OHM
20%
2 2V
20%
2V
POLY
CASE-D2-HF
POLY
CASE-D2-HF
DIDT=TRUE
CRITICAL
C7836 1
2
C7837
10UF
20%
6.3V
2 X5R
603
R7831
0.499
SM
(DDRREG_CSGND)
1NOSTUFF
1 2 3
XW7831
1%
1/10W
MF
2 603
OMIT
SM
XW7830
PLACEMENT_NOTE=PLACE NEXT TO L7830
(DDRREG_VDDQSNS)
NO STUFF
C7820
1
1
5%
50V
CERM
402
OMIT
(DDRREG_FB)
Vout = 0.75V * (1 + Ra / Rb)
R7832
15.0K
100PF
AGND_DDR_REG
<Ra>
1%
1/16W
MF-LF
2 402
R7833
<Rb>
15.0K
1%
1/16W
MF-LF
2 402
VOLTAGE=0V
R7852
C7855
1
1
10%
6.3V
2 X5R
805
CRITICAL
10UF
10%
6.3V
2 X5R
805
100K
5%
1/16W
MF-LF
2 402
R7853
100K
5%
1/16W
MF-LF
2 402
C7851
1UF
89
L7850
ISL8009B
DFN
CRITICAL
PP1V8_S0_REG
2.2UH-3.25A-68M-OHM
U7850
89
P1V8_REG_PHASE
LX 8
P1V8_REG_POR
3 POR
VFB 6
P1V8_REG_SKIP
4 SKIP
RSI 5
GND
7
CRITICAL
1
VIN
10%
16V
402
2 X5R
2 EN
MMD04BZ-SM
DIDT=TRUE
SWITCHNODE
P1V8_REG_VFB
6 49
<Ra>
120PF
C7850 5%
50V
59.0K
1/16W 1%
MF-LF 402
402 CERM
THRM_PAD
9
R7850
C7852
R7851
1/16W 1%
MF-LF 402
20%
6.3V
2 CERM
805
<Rb>
47.0K
22UF
C7853
22UF
20%
6.3V
2 CERM
805
PAGE TITLE
1.5V / 1.8V VREGS

DRAWING NUMBER
Apple Inc.
051-8600
Vo=0.8*(1+ Ra/Rb)
Vo=0.8*(1+ 59/47)=1.804V

SIZE
REVISION
A.0.0
6 49 50
MSQ12111R5LF-TH
C7841
1000PF
Q7831
PP1V5_S3_REG
1.8 V SUPPLY
C7854
10UF
NOSTUFF 1
XW7801
=PP5V_S0_P1V8_VREG
DIDT=TRUE
MLP5X6-LFPAK-Q5A
CRITICAL
2MIN_NECK_WIDTH=0.2 mm
SM
402
L7830
DIDT=TRUE
CSD58850Q5A
10%
50V
2 X7R
1.5UH-22A-4MOHM
CRITICAL
DDR_REG_PGND
C7839
0.001UF
10%
50V
X7R
402
CSD58851Q5A
SWITCHNODE
(DDRREG_DRVL)
DDR_REG_CSGND
C7838
Q7830
C7805
STATE
1 2 3
PLACEMENT_NOTE=PLACE NEXT TO Q7831

89
603
MLP5X6-LFPAK-Q5A
DDR_REG_FB
20%
16V
OMIT
20%
6.3V
CERM-X5R
805-3
89
DDR_REG_LGATE
17
22UF
PGND CS_GND
18
C7803
THRM_PAD GND
3
89
EMC CAPS
PLACE CLOSE TO L7830
0.1UF
CRITICAL
2
20%
25V
CERM
603
(DDRREG_LL)
VDDQSET 9
VTTGND
CRITICAL
22UF
20%
6.3V
CERM-X5R
7 NC0
12 NC1
25
C7804
NC
NC
C7834
DIDT=TRUE
DDR_REG_PHASE
DDR_REG_CS
R7840
89
89
2 CERM
0.001UF
C7840
DDR_REG_BOOT_R
LL 20
CS 16
0.1UF
5%
1/10W
MF-LF
603
2 VTTSNS
CRITICAL
2 89 DDR_REG_VTTSNS
NO_TEST=TRUE
FEEDBACK THROUGH SHORT
SHOULD NOT NEED TP
20%
16V
CERM
603
(DDRREG_DRVH)
DIDT=TRUE
DDR_REG_BOOT
89
10%
16V
X5R-CERM
0805
DDR_REG_UGATE
DRVL 19
SM
PPVTT_S0_DDR_LDO
1%
1/16W
MF-LF
402 2
89
24 VTT
C7833
0.1UF
10UF
6.04K
20%
6.3V
X5R
603
DDR_REG_VDDQSNS
89
C7832
XW7803
6
20%
16V 2
ELEC
8X9-TH1
DRVH 21
SYM (2 OF 2)
Vout = VDDQSNS/2
Vout = VTTREF
20%
16V 2
ELEC
8X9-TH1
270UF
89
DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
QFN
5 VTTREF
89
R7810
89
VBST 22
U7800
TPS51116
PPVTT_S3_DDR_BUF
(NOT USED)
CRITICAL
C7831 1
270UF
VDDQSNS 8
CRITICAL
91 62 32
VLDOIN
6 COMP
C7815
10UF
23
4.7UF
14
C7801
15
C7800
CRITICAL
C7830 1
VOLTAGE=5V
4.7
=PP5V_S3_DDR_VREG
6
EMC CAPS
PLACE CLOSE TO FET
DIDT=TRUE
BRANCH
PAGE
78 OF 110
SHEET
70 OF 92
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
R7910
0
5%
1/16W
MF-LF
402
89
PP12V_G3H_R
VOLTAGE=12V
89
C7910 1
10UF
VIN
10%
25V 2
X5R
805
P3V42G3H_BOOST
0.22UF
BOOST
20%
6.3V 2
X5R
402
U7900
LT3470A
8 SHDN*
NC
7 NC
DFN
R7911 allow G3H current measuremnet

Remove R7911 after Proto-1
C7900 1
VOLTAGE=12V
SW 4
BIAS 2
CRITICAL
GND
FB 1
THRM
PAD
9
PP12V_G3H
89 6
89
P3V42G3H_SW
CRITICAL
L7900
33UH
1
2
CDPH4D19FHF-SM
89
PP3V42_G3H_R
C7901 1
<Ra> R79001
5%
50V
CERM 2
402
1%
1/16W
MF-LF
402 2
22pF
Vout = 3.425
250mA max output
(Switcher limit)
5%
1/16W
MF-LF
402
353S2171
SWITCH_NODE=TRUE DIDT=TRUE
89
PP3V42_G3H_REG
R7911
348K
P3V42G3H_FB
C7902
22UF
20%
2 6.3V
X5R-CERM
603
<Rb> R79011
200K
1%
1/16W
MF-LF
402 2
Vout = 1.25V * (1 + Ra / Rb)
1.05V S5 SUPPLY
B
6
REMOVE for K60/K61
=PP3V3_S5_P1V05S5_VREG
NOSTUFF
NOSTUFF
1
C7960
10UF
10%
6.3V
2 X5R
805
NOSTUFF
C7961
10UF
10%
6.3V
2 X5R
805
NOSTUFF
R7980
100K
NOSTUFF
R7985
100K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R7986
100K
5%
1/16W
MF-LF
2 402
NOSTUFF
1
C7962
1 NOSTUFF
VIN
1UF
10%
16V
402
ISL8009B
DFN
2 EN
P1V05S5_REG_POR
P1V05S5_REG_SKIP
NOSTUFF
PP1V05_S5_REG
2.2UH-3.25A-68M-OHM
LX 8
3 POR
VFB 6
4 SKIP
RSI 5
GND
7
P1V05S5_REG_EN_R
NOSTUFF
L7950
U7950
2 X5R
THRM_PAD
9
P1V05_S5_REG_PHASE
1
2
MMD04BZ-SM
DIDT=TRUE
SWITCHNODE
1
NOSTUFF
89
C7981 120PF
5%
50V
CERM 2
402
89
P1V05S5_REG_VFB
NOSTUFF
R7981
31.6K
1%
1/16W
MF-LF
2 402
NOSTUFF
20%
6.3V
2 X5R
603
R7982
1K
100K
5%
1/16W
MF-LF
2 402
C7950
10UF
NOSTUFF
R7987
NOSTUFF
C7940
10UF
20%
6.3V
2 X5R
603
1%
1/16W
MF-LF
2 402
PAGE TITLE
1.05 S5 SUPPLY
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
79 OF 110
SHEET
71 OF 92
5V S0 FET (7A PK/2.7A AVG)
3.3V S0 FET (3.4APK / 1.9A AVG)
C8000
Q8053
PP5V_S0_FET
POWER33
=PP3V3_S5_S0FET
=PP3V3_S0_PWRCTL
72 63 62 6 5
NOSTUFF
Q8050
POWER33
S6
NC 3
GND
91 63 48
THRM
PAD
R8051
10K
5%
1/16W
MF-LF
2 402
SLG5AP001
TDFN
5D
7G
ON 2
CRITICAL
S6
8 PG
PGOOD_P3V3_S0
VCC
U8053
NC 3
91 34
THRM
PAD
GND
4
CRITICAL
7G
5%
1/16W
MF-LF
2 402
ON 2
8 PG
IN
R8084
CRITICAL
Q8025
NOSTUFF
PP1V5_S0_FET
R8020
10K
5%
1/16W
MF-LF
2 402
Q8080
POWER33
2
5
PP1V05_SM_SOURCE
S
1
PP1V05_SM_FET
C8080
0.47UF
10%
2 16V
X7R
805
TDFN
72 63 6
5D
CRITICAL
7G
THRM
PAD
GND
4
=PP3V3_S5_SM_FET
POWER33
C8082
10UF
20%
6.3V
2 X5R
603
20%
6.3V
2 X5R
603
63 6
72
10K
5%
1/16W
MF-LF
2 402
R8080
10K
10K
NOSTUFF
2
63 6
PM_ME_S0_EN_G1
NOSTUFF
R8070
5%
1/16W
MF-LF
2 402
P1V5_S0_EN
NOSTUFF
NOSTUFF
100K
SOT-363
10%
2 16V
X5R
402
=PP3V3_SM_PWRCTL
R8089
2N7002DW-X-G
91
10K
5%
1/16W
MF-LF
2 402
4
6
Q8082
62
P1V05_ME_S0_EN
NOSTUFF
POWER33
S0T23-3
MAKE_BASE=TRUE
VOLTAGE=12V
10K
5%
1/16W
MF-LF
2 402
NOSTUFF
P12V_S3_EN_G
=PP12V_S5_PWRCTL
NOSTUFF
NOSTUFF
R8060
C8030
R8061
10K
0.47UF
10%
10K
5%
1/16W
MF-LF
2 402
2 16V
X7R
805
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
NOSTUFF
R8062
P1V05_ME_SM_EN_D 1
3
Q8063
10K
5%
1/16W
MF-LF
402
2N7002DW-X-G
NOSTUFF
Q8031
91 62
IN
P12V_S3_EN
P1V05_ME_SM_EN
P3V3ME_EN
NOSTUFF
R8075
100K
C8060
5%
1/16W
MF-LF
2 402
0.47UF
10%
2 16V
X7R
805
NOSTUFF
R8063
10K
PAGE TITLE
DRAWING NUMBER
Apple Inc.
Q8063
051-8600

SIZE
REVISION
A.0.0
SOT-363
S3+S0 FETS
R8063 ADD FOR PROTO1 TO KEEP Q8060 OFF

REMOVE ALL OF THIS FOR PROTO2
GND
2N7002DW-X-G
91 62
THRM
PAD
NOSTUFF
SOT23-HF1
IN
S6
NC 3
2N7002
ON 2
NOSTUFF
5%
1/16W
MF-LF
2 402
SOT-363
3
D
91 62
TDFN
CRITICAL
1 NOSTUFF
R8031
10K
S
G
72 63 6
P1V05_ME_SM_EN_G
R8030
P1V05_ME_SM_EN_G2
NOSTUFF
P12V_S3_EN_D
PP12V_S3_FET
=PP1V05_S5_SM_FET
NOTE:
ALIAS =PP3V3_ME_PWRCTL TO
PP3V3_ME_FET
ON PAGE 6
3
2
TP0610
=PP12V_S5_S3_FET
7G
Q8060
FDMC8296
Q8030
SLG5AP001
5D
NOSTUFF
SOT-363
VCC
U8070
8 PG
PGOOD_P3V3_ME
2N7002DW-X-G
( < 200MA )
C8070
0.1UF
5%
1/16W
MF-LF
402
Q8082
NOSTUFF
R8082
=PP12V_S5_PWRCTL
NOSTUFF
PM_ME_S0_EN_R
91
5%
1/16W
MF-LF
2 402
12V S3 FET
R8081
NOSTUFF
C8083
S6
MAKE_BASE=TRUE
VOLTAGE=3.3V
FDMC8296
NOSTUFF
10UF
NOSTUFF
ON 2
PP3V3_SM_FET
NOSTUFF
Q8070
2
1
=PP12V_S5_PWRCTL
NC 3
8 PG
PGOOD_P1V5_S0
NOSTUFF
U8025
SLG5AP001
5%
1/10W
MF-LF
603
PM_ME_S0_EN_G
91
MAKE_BASE=TRUE
VOLTAGE=1.05V
NOSTUFF
VCC
=PP3V3_S0_ME
POWER33
BYPASS FET CIRCUIT FOR PROTO 1

KEEP PADS IN CASE VCC_3V3 ME IS REQUIRED
IN STATES OTHER THAN S0. DELETE AFTER PROTO1
R8071
Q8081
FDMC8296
3
3.3VME FET (86MA MAX)
NOSTUFF
FDMC8296
10%
16V
2 X5R
402
=PP12V_S5_PWRCTL
P1V5_S0_EN_G
NOSTUFF
=PP1V05_S0_SM_FET
6 49
MAKE_BASE=TRUE
VOLTAGE=1.5V
0.1UF
72
6
63
=PP3V3_S0_PWRCTL
C8025
SM: 387MA)
S
G
GND
THRM
PAD
P3V3S3_EN
IN
BYPASS FET CIRCUIT FOR PROTO 1

KEEP PADS IN CASE VCC ME IS REQUIRED
IN STATES OTHER THAN S0. DELETE AFTER PROTO1
5%
1/4W
MF-LF
1206
3
2
IN
S6
NC 3
POWER33
FDMC8296
91 62
CRITICAL
ON 2
P3V3S0_EN
1V05 ME FETS (S0: 2.2A MAX
1.5V S0 FET (6.2A PK / 3A AVG)
72 63 62 6 5
TDFN
7G
8 PG
PGOOD_P3V3_S3
91 62
=PPDDR_S3_S0FET
SLG5AP001
5D
P5VS0_EN
IN
91 62
VCC
U8050
P3V3_ME_EN_G
91 62
10K
TDFN
5D
P3V3_S3_EN_G
U8000
SLG5AP001
PGOOD_P5V_S0
S
G
P3V3_S0_EN_G
5%
1/16W
MF-LF
2 402
R8050
D
=PP3V3_S3_PWRCTL
VCC
P5V_S0_EN_G
10K
PP3V3_S3_FET
2
5
63 6
=PP3V3_S5_S3FET
=PP3V3_S0_PWRCTL
FDMC8296
R8000
PP3V3_S0_FET
10%
16V
2 X5R
402
CRITICAL
C8050
0.1UF
FDMC8296
POWER33
10%
2 16V
X5R
402
CRITICAL
FDMC8296
5
=PP12V_S5_PWRCTL
72 63 6
0.1UF
Q8000
=PP5V_S3_S0FET
C8053
10%
16V
2 X5R
402
CRITICAL
91 62
3.3V S3 FET (2.9A PK / 1.2A AVG)
=PP12V_S5_PWRCTL
72 63 6
0.1UF
72 63 62 6 5
=PP12V_S5_PWRCTL
72 63 6
BRANCH
PAGE
80 OF 110
SHEET
72 OF 92
Page Notes
- =PP3V3_S0_MXM
- =PP5V_S0_MXM
- =PPV_S0_MXM_PWRSRC
(NONE)

- MXM
=PP3V3_S0_MXM
MXM
CRITICAL
MXM
100K
19
155
153
MXM_RESET_L
156
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
MXM_PCIE_STD_SWING_L
CLK_100M_MXM_P
CLK_100M_MXM_N
84 75
154
MXM_CLKREQ_L
84 75
84 75
84 75
84 75
84 75
84 75
MXM_PCIE_D2R_N<0>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_N<2>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<5>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_P<6>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_N<11>
MXM_PCIE_D2R_P<11>
MXM_PCIE_D2R_N<12>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_D2R_N<15>
MXM_PCIE_D2R_P<15>
147
149
141
143
135
137
121
123
115
117
109
111
103
105
97
99
91
93
85
87
79
81
73
75
67
69
61
63
55
57
49
51
MXM_PCIE_R2D_N<0>
MXM_PCIE_R2D_P<0>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<5>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<8>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_N<10>
MXM_PCIE_R2D_P<10>
MXM_PCIE_R2D_N<11>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<12>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_N<13>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_N<14>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_N<15>
MXM_PCIE_R2D_P<15>
148
150
142
144
136
138
120
122
114
116
108
110
102
104
96
98
90
92
84
86
78
80
72
74
66
68
60
62
54
56
48
50
F-RT-SM
(2 OF 4)
APPLE P/N: 516S0699
CLK_REQ*
DP_A_AUX*
DP_A_AUX
PEX_STD_SW*
DP_A_HPD
PEX_REFCLK
PEX_REFCLK*
DP_A_L0*
DP_A_L0
PEX_RST*
DP_A_L1*
PEX_RX0*
DP_A_L1
PEX_RX0
DP_A_L2*
PEX_RX1*
DP_A_L2
PEX_RX1
DP_A_L3*
PEX_RX2*
DP_A_L3
PEX_RX2
DP_B_AUX*
PEX_RX3*
DP_B_AUX
PEX_RX3
PEX_RX4*
DP_B_HPD
PEX_RX4
DP_B_L0*
PEX_RX5*
DP_B_L0
PEX_RX5
DP_B_L1*
PEX_RX6*
DP_B_L1
PEX_RX6
DP_B_L2*
PEX_RX7*
DP_B_L2
PEX_RX7
DP_B_L3*
PEX_RX8*
DP_B_L3
PEX_RX8
PEX_RX9*
DP_C_AUX*
PEX_RX9
DP_C_AUX
PEX_RX10*
DP_C_HPD
PEX_RX10
PEX_RX11*
DP_C_L0*
PEX_RX11
DP_C_L0
PEX_RX12*
DP_C_L1*
PEX_RX12
DP_C_L1
PEX_RX13*
DP_C_L2*
PEX_RX13
DP_C_L2
PEX_RX14*
DP_C_L3*
PEX_RX14
DP_C_L3
PEX_RX15*
DP_D_AUX*
PEX_RX15
DP_D_AUX
PEX_TX0*
DP_D_HPD
PEX_TX0
PEX_TX1*
DP_D_L0*
PEX_TX1
DP_D_L0
PEX_TX2*
DP_D_L1*
PEX_TX2
DP_D_L1
PEX_TX3*
DP_D_L2*
PEX_TX3
DP_D_L2
PEX_TX4*
DP_D_L3*
PEX_TX4
DP_D_L3
PEX_TX5*
PEX_TX5
PEX_TX6*
PEX_TX6
PEX_TX7*
PEX_TX7
PEX_TX8*
PEX_TX8
PEX_TX9*
PEX_TX9
PEX_TX10*
PEX_TX10
PEX_TX11*
PEX_TX11
PEX_TX12*
PEX_TX12
PEX_TX13*
PEX_TX13
PEX_TX14*
PEX_TX14
PEX_TX15*
PEX_TX15
6 63 73 74
MXM
B35P101-0121
5%
1/16W
MF-LF
402 2
74
=PP3V3_S0_MXM
J8400
R84001
DP
74 73 63 6
PCI-E
277
279
MXM_DP_A_AUX_N
MXM_DP_A_AUX_P
276
MXM_DP_A_HPD
253
255
259
261
265
267
271
273
MXM_DP_A_ML_N<0>
MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<2>
MXM_DP_A_ML_N<3>
MXM_DP_A_ML_P<3>
270
272
MXM_DP_B_AUX_N
MXM_DP_B_AUX_P
274
MXM_DP_B_HPD
246
248
252
254
258
260
264
266
MXM_DP_B_ML_N<0>
MXM_DP_B_ML_P<0>
MXM_DP_B_ML_N<1>
MXM_DP_B_ML_P<1>
MXM_DP_B_ML_N<2>
MXM_DP_B_ML_P<2>
MXM_DP_B_ML_N<3>
MXM_DP_B_ML_P<3>
223
225
MXM_DP_C_AUX_N
MXM_DP_C_AUX_P
234
MXM_DP_C_HPD
199
201
205
207
211
213
217
219
MXM_DP_C_ML_N<0>
MXM_DP_C_ML_P<0>
MXM_DP_C_ML_N<1>
MXM_DP_C_ML_P<1>
MXM_DP_C_ML_N<2>
MXM_DP_C_ML_P<2>
MXM_DP_C_ML_N<3>
MXM_DP_C_ML_P<3>
230
232
MXM_DP_D_AUX_N
MXM_DP_D_AUX_P
236
MXM_DP_D_HPD
206
208
212
214
218
220
224
226
MXM_DP_D_ML_N<0>
MXM_DP_D_ML_P<0>
MXM_DP_D_ML_N<1>
MXM_DP_D_ML_P<1>
MXM_DP_D_ML_N<2>
MXM_DP_D_ML_P<2>
MXM_DP_D_ML_N<3>
MXM_DP_D_ML_P<3>
J8400
=PP5V_S0_MXM
MXM
B35P101-0121
F-RT-SM
(4 OF 4)
78 87
78 87
MXM
78
C8410
0.001UF
78 87
10%
2 50V
X7R
402
78 87
78 87
MXM
1
C8401
22UF
20%
2 6.3V
CERM-X5R
805-3
1
3
5
7
9
C8415
0.001UF
3V3
278
280
10%
2 50V
X7R
402
MXM
C8416
22UF
20%
2 6.3V
CERM-X5R
805-3
5V
=PPV_S0_MXM_PWRSRC
PWR_SRC
50
E2
E1
78 87
78 87
MXM
78 87
C8400
22UF
78 87
78 87
MXM SPEC POWER REQUIREMENTS
76 87
(NOT NECESSARILY THE SAME FOR EVERY MODULE)

VOLTAGE
CURRENT
POWER
76 87
76
3V3
5V
PWR (7-20V)
76 87
76 87
1.0 A
2.5 A
UP TO 10 A
20%
2 35V
ELEC
6.3X5.5-SM1
MXM
1
MXM
C8412
0.001UF
10%
50V
2 X7R
402
C8413
0.001UF
10%
50V
2 X7R
402
MXM
1
C8414
0.001UF
10%
50V
2 X7R
402
3.3 W
12.5 W
PLATFORM DEPENDENT
76 87
76 87
76 87
76 87
76 87
76 87
79 87
79 87
79
79 87
79 87
79 87
79 87
79 87
79 87
79 87
79 87
76 87
76 87
76
76 87
76 87
76 87
76 87
76 87
76 87
76 87
76 87
PAGE TITLE
MXM PCIe, DP & Power

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
84 OF 110
SHEET
73 OF 92
Page Notes
- =PP3V3_S0_MXM

- =SMB_MXM_THRM_DATA
- =PM_MXM_PGOOD_PULLUP
- =SMB_MXM_THRM_CLK
PULLUPS & PULLDOWNS AT MXM CONNECTOR
MXM
MXM
J8400
J8400
B35P101-0121
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
63
91 74 63
46
48
48
46
46
31
MXM_LVDS_A_CLK_N
MXM_LVDS_A_CLK_P
176
178
LVDS_LTX0*
LVDS_LTX0
MXM_LVDS_A_DATA_N<1>
MXM_LVDS_A_DATA_P<1>
194
196
LVDS_LTX1*
LVDS_LTX1
188
190
LVDS_LTX2*
LVDS_LTX2
182
184
LVDS_LTX3*
LVDS_LTX3
MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P
169
171
LVDS_UCLK*
LVDS_UCLK
MXM_LVDS_B_DATA_N<0>
MXM_LVDS_B_DATA_P<0>
193
195
LVDS_UTX0*
LVDS_UTX0
187
189
LVDS_UTX1*
LVDS_UTX1
181
183
LVDS_UTX2*
LVDS_UTX2
175
177
LVDS_UTX3*
LVDS_UTX3
PWR_EN
PWRGOOD
PWR_LEVEL
=SMB_MXM_THRM_SCL
=SMB_MXM_THRM_SDA
34
32
SMB_CLK
SMB_DAT
MXM_ALERT_L
MXM_OVERT_L
TP_MXM_TH_PWM
22
20
24
TH_ALERT*
TH_OVERT*
TH_PWM
TP_MXM_VGA_DDC_CLK
TP_MXM_VGA_DDC_DAT
160
158
VGA_DDC_CLK
VGA_DDC_DAT
TP_MXM_VGA_BLUE
TP_MXM_VGA_GREEN
TP_MXM_VGA_HSYNC
TP_MXM_VGA_RED
TP_MXM_VGA_VSYNC
172
170
164
168
162
VGA_BLUE
VGA_GREEN
VGA_HSYNC
VGA_RED
VGA_VSYNC
MXM_VGA_DISABLE_L
21
74
GPIO0
GPIO1
GPIO2
26
28
30
TP_MXM_GPIO0
TP_MXM_GPIO1
TP_MXM_GPIO2
HDMI_CEC
29
TP_MXM_HDMI_CEC
OEM0
OEM1
OEM2
OEM3
OEM4
OEM5
OEM6
OEM7
38
39
40
41
42
43
44
45
PNL_BL_EN
25
MXM_PNL_BL_EN
81
PNL_BL_PWM
27
MXM_PNL_BL_PWM
81
LVDS_LCLK*
LVDS_LCLK
200
202
8
6
18
VGA_DISABLE*
DVI_HPD
PM_MXM_EN
PM_MXM_PGOOD
MXM_PWR_LEVEL
F-RT-SM
(3 OF 4)
LVDS
87 76
TP_MXM_DVI_HPD
LVDS_DDC_CLK
LVDS_DDC_DAT
PNL_PWR_EN
SYSTEM MANAGEMENT
87 76
35
33
MANAGEMENT
POWER/THERMAL
74
MXM_LVDS_DDC_CLK
MXM_LVDS_DDC_DAT
ANALOG DISPLAY
74
B35P101-0121
F-RT-SM
(1 OF 4)
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
PRSNT_L*
PRSNT_R*
WAKE*
23
10
159
12
161
163
165
167
227
229
231
233
235
237
238
239
240
241
242
243
245
247
249
14
16
281
2
MXM_PNL_PWR_EN
81
11
13
15
17
36
37
46
47
52
53
58
59
64
65
70
71
76
77
82
83
88
89
94
95
100
101
106
107
112
113
118
119
124
125
133
134
139
140
GND
FLOAT = NORMAL VGA MODE

GND = SECONDARY DISPLAY CARD
GND
145
146
151
152
157
166
173
174
179
180
185
186
191
192
197
198
203
204
209
210
215
216
221
222
228
244
E3
250
251
256
257
262
263
268
269
275
282
283
E4
74
NOSTUFF
R8510
MXM_VGA_DISABLE_L
MF-LF 5%
1
1/16W
402
MXM
R8504
FLOAT = LOW SWING

GND = HIGH SWING
73
MXM_PCIE_STD_SWING_L
MF-LF 5%
1
1/16W
402
=PP3V3_S0_MXM
R8500
74
MXM_DETECT_L
100K 2
MF-LF
PULLED TO GROUND ON MXM

WE DONT USE CARD DETECT
5% 1/16W
402
R8501
74
MXM_DETECT_R
100K 2
MF-LF
5% 1/16W
402
=PM_MXM_PGOOD_PULLUP
MXM_DETECT_L
MXM_DETECT_R
6 63 73 74
63
SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
74
74
TP_MXM_WAKE_L
R8503
91 74 63
PM_MXM_PGOOD
10K
MF-LF 5%
1
1/16W
402
MXM SYSTEM INFORMATION ROM

PLACE CLOSE TO J7800
=PP3V3_S0_MXM
6 63 73 74
MXM
C8570
0.1UF
STUFF FOR WRITE PROTECT

NOSTUFF
R8570
5%
1/16W
MF-LF
402 2
I2C ADDRESS: AC 8
VCC
3 E2/NC2 MXM
5
2 E1/NC1 CRITICALSDA
1 E0/NC0
SCL 6
MXM_ROM_WP
20%
10V
2 CERM
402
MXM_LVDS_DDC_DAT
74
MXM_LVDS_DDC_CLK
74
PAGE TITLE
7 WC* U8570
M24C02-WMN6TPHF
SO8
VSS
4
MXM I/O
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
85 OF 110
SHEET
74 OF 92
MXM TX CAPS
84 9
84 9
PEG_R2D_C_P<0>
MXM
IN
MXM
IN
PEG_R2D_C_N<0>
84 9
IN
84 9
IN
84 9
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
C8602 0.1UF 1
MXM C8603 0.1UF 1
MXM
PEG_R2D_C_N<2>
MXM
IN
IN
PEG_R2D_C_P<2>
MXM
84 9
84 9
PEG_R2D_C_P<3>
MXM
IN
IN
PEG_R2D_C_N<3>
MXM
84 9
IN
PEG_R2D_C_N<4>
MXM
84 9
IN
PEG_R2D_C_P<4>
MXM
84 9
84 9
IN
PEG_R2D_C_N<5>
84 9
IN
PEG_R2D_C_P<5>
84 9
IN
PEG_R2D_C_P<6>
84 9
IN
PEG_R2D_C_N<6>
C8612 0.1UF 1
MXM C8613 0.1UF 1
PEG_R2D_C_N<7>
MXM
PEG_R2D_C_P<7>
MXM
IN
IN
IN
PEG_R2D_C_N<8>
84 9
IN
PEG_R2D_C_P<9>
84 9
IN
PEG_R2D_C_N<9>
84 9
IN
PEG_R2D_C_N<10>
84 9
IN
PEG_R2D_C_P<10>
84 9
IN
PEG_R2D_C_N<11>
84 9
IN
PEG_R2D_C_P<11>
C8608 0.1UF 1
C8609 0.1UF 1
MXM
IN
84 9
C8606 0.1UF 1
C8607 0.1UF 1
C8610 0.1UF 1
MXM C8611 0.1UF 1
84 9
PEG_R2D_C_P<8>
C8604 0.1UF 1
C8605 0.1UF 1
MXM
84 9
84 9
C8600 0.1UF 1
C8601 0.1UF 1
C8614 0.1UF 1
C8615 0.1UF 1
C8616 0.1UF 1
MXM C8617 0.1UF 1
MXM
C8618 0.1UF 1
MXM C8619 0.1UF 1
MXM
C8620 0.1UF 1
MXM C8621 0.1UF 1
MXM
C8622 0.1UF 1
MXM C8623 0.1UF 1
MXM
84 9
84 9
IN
PEG_R2D_C_P<12>
IN
PEG_R2D_C_N<12>
C8624 0.1UF 1
MXM C8625 0.1UF 1
MXM
IN
PEG_R2D_C_N<13>
MXM
84 9
IN
PEG_R2D_C_P<13>
MXM
84 9
PEG_R2D_C_P<14>
MXM
IN
MXM
IN
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
MXM
IN
PEG_R2D_C_P<15>
MXM
84 9
84 9
84 9
84 9
IN
C8626 0.1UF 1
C8627 0.1UF 1
C8628 0.1UF 1
C8629 0.1UF 1
C8630 0.1UF 1
C8631 0.1UF 1
MXM RX CAPS
2 10% 16V X5R 402
MXM_PCIE_R2D_P<15>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<15>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<14>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<14>
IN
MXM_PCIE_D2R_P<15>
MXM
84 73
IN
MXM_PCIE_D2R_N<15>
MXM
84 73
MXM_PCIE_D2R_P<14>
MXM
OUT
73 84
84 73
IN
OUT
73 84
84 73
IN
MXM_PCIE_D2R_N<14>
MXM_PCIE_R2D_P<13>
73 84
84 73
IN
MXM_PCIE_D2R_P<13>
MXM
OUT
2 10% 16V X5R 402
MXM_PCIE_R2D_N<13>
OUT
84 73
IN
MXM_PCIE_D2R_N<13>
MXM
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<12>
73 84
84 73
IN
MXM_PCIE_D2R_P<12>
MXM
OUT
2 10% 16V X5R 402
MXM_PCIE_R2D_N<12>
OUT
84 73
IN
MXM_PCIE_D2R_N<12>
MXM
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<11>
OUT
73 84
MXM_PCIE_R2D_N<11>
IN
MXM_PCIE_D2R_P<11>
MXM
84 73
2 10% 16V X5R 402
OUT
73 84
MXM
84 73
IN
MXM_PCIE_D2R_N<11>
IN
MXM_PCIE_D2R_P<10>
MXM
84 73
MXM
IN
MXM_PCIE_D2R_N<10>
IN
MXM_PCIE_D2R_P<9>
MXM
84 73
IN
MXM_PCIE_D2R_N<9>
MXM
84 73
IN
MXM_PCIE_D2R_P<8>
MXM
84 73
2 10% 16V X5R 402
MXM_PCIE_R2D_P<10>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<10>
OUT
73 84
84 73
2 10% 16V X5R 402
MXM_PCIE_R2D_P<9>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<9>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<8>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<8>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<7>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<7>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<6>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<6>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<5>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<5>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<4>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<4>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_P<3>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<3>
2 10% 16V X5R 402
MXM_PCIE_R2D_P<2>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<2>
OUT
OUT
84 73
IN
MXM_PCIE_D2R_N<8>
MXM
84 73
MXM_PCIE_D2R_P<7>
MXM
IN
IN
MXM_PCIE_D2R_N<7>
MXM
84 73
IN
MXM_PCIE_D2R_P<6>
MXM
84 73
IN
MXM_PCIE_D2R_N<6>
MXM
84 73
IN
MXM_PCIE_D2R_P<5>
MXM
84 73
MXM
84 73
IN
MXM_PCIE_D2R_N<5>
IN
MXM_PCIE_D2R_P<4>
MXM
84 73
MXM
IN
MXM_PCIE_D2R_N<4>
MXM
84 73
IN
MXM_PCIE_D2R_P<3>
84 73
IN
MXM_PCIE_D2R_N<3>
IN
MXM_PCIE_D2R_P<2>
MXM
84 73
73 84
OUT
73 84
OUT
73 84
MXM_PCIE_R2D_P<1>
OUT
73 84
2 10% 16V X5R 402
MXM_PCIE_R2D_N<1>
OUT
73 84
OUT
73 84
OUT
73 84
MXM_PCIE_R2D_P<0>
2 10% 16V X5R 402
MXM_PCIE_R2D_N<0>
C8636 0.1UF 1
C8637 0.1UF 1
C8638 0.1UF 1
C8639 0.1UF 1
C8640 0.1UF 1
C8641 0.1UF 1
C8642 0.1UF 1
C8643 0.1UF 1
C8644 0.1UF 1
C8645 0.1UF 1
C8646 0.1UF 1
C8647 0.1UF 1
C8648 0.1UF 1
C8649 0.1UF 1
C8650 0.1UF 1
C8651 0.1UF 1
C8652 0.1UF 1
C8653 0.1UF 1
C8654 0.1UF 1
C8655 0.1UF 1
2 10% 16V X5R 402
PEG_D2R_N<0>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<0>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<1>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<1>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<2>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<2>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<3>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<3>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<4>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<4>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<5>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<5>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<6>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<6>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<7>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<7>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<8>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<8>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<9>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<9>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<10>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<10>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<11>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<11>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<12>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<12>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<13>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<13>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<14>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<14>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_N<15>
OUT
9 84
2 10% 16V X5R 402
PEG_D2R_P<15>
OUT
9 84
73 84
2 10% 16V X5R 402
2 10% 16V X5R 402
C8632 0.1UF 1
C8633 0.1UF 1
C8634 0.1UF 1
MXM C8635 0.1UF 1
2 10% 16V X5R 402
84 73
C8656 0.1UF 1
MXM C8657 0.1UF 1
84 73
IN
MXM_PCIE_D2R_N<2>
MXM
84 73
MXM_PCIE_D2R_P<1>
MXM
IN
IN
MXM_PCIE_D2R_N<1>
MXM
84 73
IN
MXM_PCIE_D2R_P<0>
MXM
84 73
IN
MXM_PCIE_D2R_N<0>
MXM
84 73
C8658 0.1UF 1
C8659 0.1UF 1
C8662 0.1UF 1
C8663 0.1UF 1
C8660 0.1UF 1
C8661 0.1UF 1
PAGE TITLE
MXM PCIE CAPS

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
86 OF 110
SHEET
75 OF 92
Page Notes
- =PP3V3_S0_DP

(NONE)

(NONE)
Unused MXM Interfaces

87 74
MXM_LVDS_A_CLK_N
87 74
MXM_LVDS_A_CLK_P
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
MXM_LVDS_B_CLK_N
87 74
MXM_LVDS_B_CLK_P
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
NC_MXM_LVDS_A_CLK_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_CLK_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_CLK_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_CLK_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_N<0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
Unused MXM DP Interfaces

87 73
MXM_DP_B_ML_P<0..3>
87 73
MXM_DP_B_ML_N<0..3>
87 73
MXM_DP_B_AUX_P
87 73
MXM_DP_B_AUX_N
73
MXM_DP_B_HPD
87 73
MXM_DP_D_ML_P<0..3>
87 73
MXM_DP_D_ML_N<0..3>
87 73
MXM_DP_D_AUX_P
87 73
MXM_DP_D_AUX_N
73
MXM_DP_D_HPD
NC_MXM_DP_B_ML_P<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_ML_N<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_AUX_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_AUX_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_HPD
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_ML_P<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_ML_N<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_AUX_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_AUX_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_HPD
MAKE_BASE=TRUE
NO_TEST=TRUE
Display: Aliases
NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8600
3.0.0
OF
76
92
Page Notes
- =PP12V_S0_LCD
- =PP3V3_S0_VIDEO
INTERNAL DP INTERFACE

(NONE)
CRITICAL

IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR
J9002
NOSTUFF
=SMB_DP_TCON_SCL
48
NOSTUFF
R9051
0
=SMB_DP_TCON_SDA
48
F-RT-SM
33
518S0685
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
IN
DP_INT_LINK_P<0>
87 79
IN
DP_INT_LINK_N<0>
10%
87 79
IN
DP_INT_LINK_P<1>
87 79
IN
DP_INT_LINK_N<1>
87 79
IN
87 79
IN
87 79
IN
87 79
IN
C9040
10% 16V
C9041
C9044
10% 16V
C9045
10% 16V
DP_INT_LINK_P<2>
DP_INT_LINK_N<2>
C9046
10% 16V
C9047
10% 16V
DP_INT_LINK_P<3>
DP_INT_LINK_N<3>
DP_INT_AUXCH_N
DP_INT_AUXCH_P
5
6
7
0.1uF
X5R
1
87
402
87
0.1uF
16V
C9042
10% 16V
C9043
10% 16V
GND
2
4
87 79
87 79
87 79
I2C MASTER ON TCON

I2C_TCON_SCL
I2C_TCON_SDA
20389-Y30E-01
R9050
0
X5R
2
87
402
402
87
87
NO_TEST
NO_TEST
DP_INT_LINK_CONN_P<2>
DP_INT_LINK_CONN_N<2>
NO_TEST
NO_TEST
NO_TEST
NO_TEST
11
12
14
15
0.1uF
X5R
1
13
0.1uF
X5R
402
0.1uF
X5R
NO_TEST
NO_TEST
10
87
16
402
87
0.1uF
X5R
402
87
17
18
19
0.1uF
X5R
1
81
402
81 77
0.1uF
X5R
402
79
SPDIF_DP_AUDIO_OUT
VIDEO_ON
DP_HPD_INT
20
21
22
23
C
6
24
PANEL POWER CONTROL

=PP12V_S0_LCD
89
25
PP12V_LCD_CONN
26
VOLTAGE=12V
27
28
R9000 1
100K
FDC638P_G
R9001
100K
5%
1/16W
MF-LF
402 2
29.4K
0.1UF
=PP3V3_S0_VIDEO
89
PP12V_LCD
VOLTAGE=12V
C9010
C9020
C9001
10UF
10%
16V
X5R-CERM
0805
20%
50V
CERM
402
GND
34
0.001uF
SM
10%
50V
X7R
603-1
31
32
FERR-250-OHM
C9000
1%
1/16W
MF-LF
402
L9000
SM
R9002
30
Q9000
5%
1/16W
MF-LF
402 2
LCD_PANEL_PWR_L_DIV
29
CRITICAL
0.001uF
20%
50V
CERM
402
LCD_PANEL_PWR_L_RC
PLACE NEAR J9002

NOSTUFF
R9071
81
LCD_PANEL_PWR
LCD_PANEL_PWR_L
3
LCD_PANEL_PWR_G
5%
1/10W
MF-LF
603
R9072
81 77
VIDEO_ON
5%
1/10W
MF-LF
603
Q9001
2N7002
SOT23-HF1
S
2
=PP3V3_S0_DP
81 79 78 77 6
R90701
NOSTUFF
1
100K
5%
1/16W
MF-LF
402
C9011
0.1UF
20%
10V
2 CERM
402
CRITICAL
NOSTUFF
81 77
81
VIDEO_ON
LCD_BKL_ON_MUX
BACKLIGHT CONTROL SUPPORT
NOSTUFF
5 TC7SZ08AFEAPE
R9012
SOT665
U9050Y
LCD_BKL_MLB_EN
1K
81
L9050
FERR-250-OHM
LCD_PWM_FILT
LCD_PWM
SM
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
BACKLIGHT_PWM
R9081
47
guarantee backlight is
only on when Panel has valid video
Options for GPU or MLB HW controlled backlight enable are included
81 79 78 77 6
=PP3V3_S0_DP
VIDEO_ON_L
OUT
81 79 78 77 6
=PP3V3_S0_DP
14
81 77
VIDEO_ON
14
7
U9500
C9005
22UF
used by diag LED
20%
6.3V
CERM
805
D9000
SOT23
74LVC14
4
TSSOP-HF
U9520
SOT886
VIDEO_ON_L_DLY
LCD_BKL_ON_DLY
LCD_BKL_ON OUT
Display: Int DP Connector
DRAWING NUMBER
5%
1/16W
MF-LF
402
BAT54XG
2
R9009
1K
Apple Inc.
19.1K2
1%
1/16W
MF-LF
402

buffers are multiple parts, other parts are on csa 95
051-8600
SIZE
REVISION
A.0.0
PAGE TITLE
R9011
74AUP2G14GM
BRANCH
PAGE
90 OF 110
SHEET
77 OF 92
EQ & Re-Driver for DP source
87 73
IN
87 73
IN
87 73
IN
87 73
IN
87 73
IN
87 73
IN
81 79 78 77 6
C9123
10% 16V
C9124
10% 16V
C9125
10% 16V
C9126
10% 16V
C9127
10%
X5R
X5R
1/16W
73
OUT
87
87
0.1uF
87
402
402
0.1uF
499
87
87
87
MXM_DP_A_ML_C_P<0>
MXM_DP_A_ML_C_N<0>
MXM_DP_A_ML_C_P<1>
MXM_DP_A_ML_C_N<1>
MXM_DP_A_ML_C_P<2>
MXM_DP_A_ML_C_N<2>
MXM_DP_A_ML_C_P<3>
MXM_DP_A_ML_C_N<3>
402
402
1
MF-LF
87
0.1uF
X5R
1%
20%
10V
CERM
402
1/16W
NOSTUFF
R91022
402
1
C9103
0.1UF
C9104
0.1UF
20%
10V
CERM
402
C9105
Common mode bias for Tx EQ AUX interception
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
81 79 78 77 6
=PP3V3_S0_DP
PS8121ED
87
R91002
5%
0.1UF
U9100
402
X5R
1/16W
0.1uF
X5R
R91032
IN
402
X5R
10K
C9102
VCC
NOSTUFF
R91012
20%
10V
CERM
402
402
X5R
0.1UF
0.1uF
=PP3V3_S0_DP
NOSTUFF
80 78
402
C9101
0.1uF
16V
1/16W
10K
5%
10K
5%
38
39
41
42
44
45
47
48
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
PS8121_PC0
3
PS8121_PC1
4
PS8121_I2C_EN_L26
402
1
MF-LF
PS8121_REXT
OE*
MF-LF
87
87
87
87
87
87
87
MXM_DP_A_ML_EQ_P<0>
MXM_DP_A_ML_EQ_N<0>
MXM_DP_A_ML_EQ_P<1>
MXM_DP_A_ML_EQ_N<1>
MXM_DP_A_ML_EQ_P<2>
MXM_DP_A_ML_EQ_N<2>
MXM_DP_A_ML_EQ_P<3>
MXM_DP_A_ML_EQ_N<3>
DP_TX_EQ_AUXCH_P
DP_TX_EQ_AUXCH_N
8
9
AUX+
AUX-
=PP3V3_S0_DP
NC
HPD
36
2
32
BI
IN
MODE
CFGX
CFGY
DP_TX_EQ_AUXCH_P
NO_TEST
78 87
0.1uF
DP_TX_EQ_AUXCH_N
NO_TEST
78 87
X5R
402
402
20%
=PP3V3_S0_DP
1
NC
28
NC
29
NC
NC
THRM_PAD
49
5
12
18
24
31
37
43
A4
A8
A9
MXM_DP_A_AUX_P
NO_TEST
MXM_DP_A_AUX_N
NO_TEST
C9138
10% 16V
C9139
10%
16V
0.1uF
87
78
MXM_DP_A_AUX_C_P
NO_TEST
0.1uF
87
78
MXM_DP_A_AUX_C_N
NO_TEST
X5R
X5R
402
H9
J9
402
H8
J8
81 79 78 77 6
=PP3V3_S0_DP
From external source

to internal display via EQ
J2
87 79
OUT
87 79
OUT
87 79
OUT
87 79
OUT
87 79
OUT
87 79
OUT
87 79
OUT
87 79
OUT
87 79
BI
87 79
BI
DP_MUX_N<3>
DP_MUX_P<3>
NO_TEST
NO_TEST
B8
DP_MUX_N<2>
DP_MUX_P<2>
NO_TEST
NO_TEST
D8
DP_MUX_N<1>
DP_MUX_P<1>
NO_TEST
NO_TEST
E8
DP_MUX_N<0>
DP_MUX_P<0>
NO_TEST
NO_TEST
F8
DP_MUX_AUXCH_P
DP_MUX_AUXCH_N
10K
5%
1/16W
MF-LF
402 2
B9
D9
E9
F9
H6
NO_TEST
NO_TEST
J6
NC
NC
NOSTUFF
R91301
C
6 77 78 79 81
MXM_DP_A_HPD_EQ
A6
H5
J5
VDD
C9323
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
U9120
DIN1_1+
DIN1_1-
CBTL06141EE
BGA
DIN1_2+
DIN1_2-
CRITICAL
DIN1_3+
DIN1_3-
DOUT_0+
DOUT_0-
DAUX1+
DAUX1-
DOUT_1+
DOUT_1-
DDC_CLK1
DDC_DAT1
HPD_1
DOUT_2+
DOUT_2-
B2 87
B1 87
D2 87
D1 87
E2 87
E1 87
DIN2_0+
DIN2_0DOUT_3+
DOUT_3-
DIN2_1+
DIN2_1DIN2_2+
DIN2_2DIN2_3+
DIN2_3-
F2 87
F1 87
AUX+
AUX-
H2
HPDIN
J1
H1
NO_TEST
DP_EXT_LINK_C_P<0>
DP_EXT_LINK_C_N<0>
NO_TEST
NO_TEST
DP_EXT_LINK_C_P<1>
DP_EXT_LINK_C_N<1>
NO_TEST
C9131
10% 16V
C9132
10% 16V
C9133
C9134
10% 16V
C9135
10% 16V
NO_TEST
DP_EXT_LINK_C_P<3>
DP_EXT_LINK_C_N<3>
NO_TEST
C9136
10% 16V
C9137
10%
2
2
402
0.1uF
X5R
402
0.1uF
X5R
16V
16V
0.1uF
X5R
402
0.1uF
X5R
402
0.1uF
X5R
402
0.1uF
X5R
402
0.1uF
X5R
402
0.1uF
X5R
402
NO_TEST
NO_TEST
NO_TEST
DP_EXT_LINK_P<0>
DP_EXT_LINK_N<0>
NO_TEST
BI
80 87
BI
80 87
BI
80 87
BI
80 87
BI
80 87
BI
80 87
BI
80 87
BI
80 87
DP_EXT_AUXCH_P
DP_EXT_AUXCH_N
BI
80 81 87
BI
80 81 87
DP_HPD_EXT
BI
80 81
DP_CA_DET
IN
NO_TEST
DP_EXT_LINK_P<1>
DP_EXT_LINK_N<1>
NO_TEST
NO_TEST
DP_EXT_LINK_P<2>
DP_EXT_LINK_N<2>
NO_TEST
NO_TEST
DP_EXT_LINK_P<3>
DP_EXT_LINK_N<3>
NO_TEST
R9309
DDC_CLK2
DDC_DAT2
IN
DP_MUX_HPD
H3
HPD_2
81 45
IN
DPMUX_VIDEO_IN_SEL
A1
GPU_SEL
B7
XSD*
DP_HPD_EXT_R
1K
1%
1/16W
MF-LF
402
LO=PORT1
HI=PORT2
LO=AUX_CH
HI=DDC
DDC_AUX_SEL
C2
TST0
G2
GND
DisplayPort Mux 1
Analog mux at External Connector
C9130
10% 16V
10%
NO_TEST
DP_EXT_LINK_C_P<2>
DP_EXT_LINK_C_N<2>
NO_TEST
DAUX2+
DAUX2-
79
DPMUX1_ENABLE
C9322
0.1UF
DIN1_0+
DIN1_0-
B3
IN
0.1uF
X5R
X5R-CERM
B6
81
C9151
10% 16V
16V
48
A5
BI
MXM_DP_A_AUX_C_N
NO_TEST
10%
5%
1/16W
MF-LF
2 402
48
B5
87 73
87 78
C9150
100K
78 87
B4
BI
MXM_DP_A_AUX_C_P
NO_TEST
30
HPD_SINK
GND
87 73
87 78
R9151
4.7UF
10 PS8121_CEXT 6.3V
1
CEXT
402
81 79 78 77 6
5%
1/16W
MF-LF
402 2
C9106
CA_DET
100K
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
78 87
=I2C_DP_DRV_SDA
=I2C_DP_DRV_SCL
34
35
SDA_CTL
SCL_CTL
INT_PD
87
REXT
27
DP_CA_DET
MXM_DP_A_HPD
23
22
20
19
17
16
14
13
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
PC0/I2C_ADDR0 INT_PD
PC1/I2C_ADDR1 INT_PD
I2C_CTL_EN* INT_PD
25
402
1
MF-LF
R91501
QFN
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
To External connector
IN
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
C9122
10% 16V
0.1uF
20%
10V
CERM
402
J4
87 73
MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<0>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<2>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<3>
MXM_DP_A_ML_N<3>
C9100
0.1UF
402
78 80
H7
IN
X5R
C9121
10% 16V
0.1uF
A2
87 73
16V
H4
From iMac GPU
10%
G8
C9120
C8
=PP3V3_S0_DP
11
15
21
33
40
46
81 79 78 77 6
PAGE TITLE
Display: BiDiVi Mux1

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
91 OF 110
SHEET
78 OF 92
D
81 79 78 77 6
=PP3V3_S0_DP
C9200
IN
MXM_DP_C_ML_P<0>
NO_TEST
C9240
10% 16V
87 73
IN
MXM_DP_C_ML_N<0>
NO_TEST
C9241
10% 16V
87 73
IN
MXM_DP_C_ML_P<1>
NO_TEST
C9242
10% 16V
87 73
IN
MXM_DP_C_ML_N<1>
NO_TEST
C9243
87 73
IN
MXM_DP_C_ML_P<2>
NO_TEST
C9244
10% 16V
87 73
IN
MXM_DP_C_ML_N<2>
NO_TEST
C9245
10% 16V
IN
MXM_DP_C_ML_P<3>
NO_TEST
C9246
10% 16V
87 73
87 73
IN
MXM_DP_C_ML_N<3>
NO_TEST
10%
0.1uF
87
MXM_DP_C_ML_C_P<0>
NO_TEST
0.1uF
87
MXM_DP_C_ML_C_N<0>
NO_TEST
0.1uF
87
MXM_DP_C_ML_C_P<1>
NO_TEST
0.1uF
87
MXM_DP_C_ML_C_N<1>
NO_TEST
0.1uF
87
MXM_DP_C_ML_C_P<2>
NO_TEST
0.1uF
87
MXM_DP_C_ML_C_N<2>
NO_TEST
0.1uF
87
MXM_DP_C_ML_C_P<3>
X5R
2
402
X5R
402
X5R
16V
C9247
10%
402
X5R
402
X5R
2
402
X5R
2
402
X5R
1
16V
402
0.1uF
X5R
87
MXM_DP_C_ML_C_N<3>
402
C
81 79 78 77 6
=PP3V3_S0_DP
R92211 R92151 R92201

1K
1K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
1K
5%
1/16W
MF-LF
402 2
87 78
IN
87 78
IN
87 78
IN
87 78
IN
87 78
IN
87 78
IN
87 78
IN
87 78
IN
C9202
0.1UF
=I2C_DP_EQLZ_SDA
QFN
IN1_D0P
IN1_D0N
IN1_D1P
IN1_D1N
CRITICAL
IN1_D2P
IN1_D2N
IN1_D3P
IN1_D3N
IN1_PEQ/SDA_CTL
IN
=I2C_DP_EQLZ_SCL
14
15
17
18
20
21
23
24
67
IN2_D0P
IN2_D0N
IN2_D1P
IN2_D1N
IN2_D2P
IN2_D2N
IN2_D3P
IN2_D3N
IN2_PEQ/SCL_CTL
DP_MUX_P<0>
DP_MUX_N<0>
DP_MUX_P<1>
DP_MUX_N<1>
DP_MUX_P<2>
DP_MUX_N<2>
DP_MUX_P<3>
DP_MUX_N<3>
IN
DP_D0P
DP_D0N
DP_D1P
DP_D1N
DP_D2P
DP_D2N
DP_D3P
DP_D3N
61
60
58
57
55
54
52
51
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
TMDS_CH0P
TMDS_CH0N
TMDS_CH1P
TMDS_CH1N
TMDS_CH2P
TMDS_CH2N
43
42
46
45
49
48
NC
NC
NC
NC
NC
NC
TMDS_CLKN 39
TMDS_CLKP 40
NC
NC
DP_INT_LINK_P<0>
DP_INT_LINK_N<0>
DP_INT_LINK_P<1>
DP_INT_LINK_N<1>
DP_INT_LINK_P<2>
DP_INT_LINK_N<2>
DP_INT_LINK_P<3>
DP_INT_LINK_N<3>
OUT
77 87
OUT
77 87
OUT
77 87
OUT
77 87
OUT
77 87
OUT
77 87
OUT
77 87
OUT
77 87
64 MODE0
65 MODE1
69 MODE2
R9222 14.99K2
81 79 78 77 6
1/16W
=PP3V3_S0_DP
5%
87 73
BI
MXM_DP_C_AUX_P
NO_TEST
87 73
BI
MXM_DP_C_AUX_N
NO_TEST
87 78
BI
87 78
BI
DP_MUX_AUXCH_P
DP_MUX_AUXCH_N
NO_TEST
NO_TEST
C9248
10% 16V
C9249
10% 16V
1/16W
0.1uF
87 79
0.1uF
87 79
X5R
X5R
402
402
2 DP_EQLZ_ADDR
MF-LF 402
see below
NO_TEST DP_EQLZ_AUXCH_P
NO_TEST DP_EQLZ_AUXCH_N
DP_AC_AUXP 30
DP_AC_AUXN 31
NC 34 TMDS_SCL
NC 35 TMDS_SDA
DP_EQLZ_EXTC
INT_PD
66 SW/I2C_ADDR
BI
79
87
BI
79 87
20%
6.3V
X5R-CERM
402
To Internal display
DP_AUXP_SCL 32
DP_AUXN_SDA 33
28 IN1_AUXP_SCL
29 IN1_AUXN_SDA
DP_INT_AUXCH_P
DP_INT_AUXCH_N
NO_TEST
NO_TEST
BI
77 79 87
BI
77 79 87
25 IN2_AUXP_SCL
26 IN2_AUXN_SDA
5%
IN
4.7UF
MF-LF 402
MXM_DP_C_AUX_C_P
NO_TEST
MXM_DP_C_AUX_C_N
NO_TEST
R9281 1
77
C9212
CEXT 1
70 REXT
DP_EQLZ_EXTR
NOSTUFF
R9280 1
From Internal display
Note: INT_PD = Internal Pulldown

on this pin of >=100 kOhms
PS8325
2
3
5
6
8
9
11
12
68
1%
From external input

via MUX 1
20%
10V
CERM
402
VDD
DP_EQLZ_MODE0
DP_EQLZ_MODE1
DP_EQLZ_MODE2
From iMac GPU
DisplayPort
Equalizer & MUX 2
C9204
0.1UF
20%
10V
CERM
402
NO_TEST
48
C9203
0.1UF
20%
10V
CERM
402
U9200
MODE[2..0] = 111 SELECTS I2C CONTROL MODE
NO_TEST
48
From external input

via MUX 1
20%
10V
CERM
402
To Internal display
87 73
C9201
0.1UF
20%
10V
CERM
402
4
22
38
47
62
From iMac GPU
0.1UF
1/16W
1M
DP_EQLZ_CADET
MF-LF 402
DP_HPD_INT
NC
INT_PDIN1_CADET 7
INT_PDIN2_CADET 16
56 DP_CADET
NC
NC
53 DP_HPD INT_PD
IN1_HPDX 10
MXM_DP_C_HPD
OUT
73
TO IMAC GPU
41 TMDS_HPD INT_PD
IN2_HPDX 19
DP_MUX_HPD
OUT
78
TO EXTERNAL SOURCE VIA MUX1
NC 37 TMDS_PC0
NC 44 TMDS_PC1
=PP3V3_S0_DP
13
27
36
50
63
72
Pulls for AUX_CH

from DisplayPort Mux #2
THRM_PAD
73
NC 71 PIO INT_PD
NC 59 PDINT_PD GND
6 77 78 79 81
R92121
100K
1%
1/16W
MF-LF
402 2
AC caps for EQ AUX interception
MXM_DP_C_AUX_C_N
79 87
MXM_DP_C_AUX_C_P
79 87
87 79
BI
DP_EQLZ_AUXCH_P
NO_TEST
87 79 77
BI
DP_INT_AUXCH_P
NO_TEST
87 79
BI
DP_EQLZ_AUXCH_N
NO_TEST
87 79 77
BI
DP_INT_AUXCH_N
NO_TEST
C9290
10% 16V
C9291
10% 16V
0.1uF
X5R
402
R9213
100K
1%
1/16W
MF-LF
402 2
2
PAGE TITLE
0.1uF
X5R
BIDIVI DP MUX2
402
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
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PAGE
92 OF 110
SHEET
79 OF 92
80 6
C9480
10UF
20%
2 6.3V
X5R
603
D
IN
L9400
U9400
C9481
89
20%
2 10V
CERM
402
4 EN
OC* 3
PP3V3_S0_DPFUSE
VOLTAGE=3.3V
TPS2051B
SOT23
5 IN
OUT 1
0.1UF
89
PP3V3_S0_DPPWR
VOLTAGE=3.3V
0603
80 6
TP_DP_OC
=PP3V3_S0_DPCONN
CRITICAL
1
C9485
10UF
20%
6.3V
2 X5R
603
PM_SLPS3_BUF1_L
8
CRITICAL
VCC
20%
10V
2 CERM
402
0.01UF
20%
50V
CERM
603
C9450
0.1UF
C9400
U9450
D9410
RCLAMP0524P
81
SLP2510P8
IN
1
7
DP_SRC_AUX_TERM_EN
5
3
GND
6 NC
R9400
1
2
NOSTUFF
FL9400
4
87 78
IN
87 78
IN
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
89
NOSTUFF
CRITICAL
1%
1/16W
MF-LF
402
GND
87 78
IN
R9406
1
2
1%
1/16W
MF-LF
402
FL9403
12-OHM-100MA
TCM1210-4SM
NO_TEST
NO_TEST
87
87
DP_ML_CONN_P<0>
DP_ML_CONN_N<0>
5
7
SYM_VER-2
TCM1210-4SM
SYM_VER-2
CRITICAL
NOSTUFF
DP_EXT_LINK_P<1>
DP_EXT_LINK_N<1>
NOSTUFF
F-ANG-TH1
R9402
1
2
FL9401
12-OHM-100MA
IN
R9421
100K
MDP-K22
87 78
J9400
IO 1
NC 10
9 NC
2Z
VOLTAGE=0V
100K
APPLE PART NO 514-0686

2 IO
R9420 1
SLP2510P8
2Y
2E
1Z
RCLAMP0524P
SOT996-2
R9401
1
2
D9410
NX3L2G66GD
GND
VOLTAGE=3.3V
DP_EXT_LINK_P<0>
DP_EXT_LINK_N<0>
1Y
1E
GND_DPAUX
IO 4
NC 7
PP3V3_S0_DPAUX
5 IO
220-OHM-1.4A
GND
2
46
=PP3V3_S0_DPCONN
CRITICAL
NOSTUFF
CRITICAL
NO_TEST87 DP_ML_CONN_P<1>
NO_TEST 87 DP_ML_CONN_N<1>
11
13
R9403
1
2
NO_TEST
NO_TEST
87
87
15
DP_ML_CONN_P<2>
DP_ML_CONN_N<2>
17
19
HPD
CONFIG1
CONFIG2
GND
ML_LANE3P
GND
ML_LANE0P
ML_LANE0N
GND
ML_LANE1P
ML_LANE1N
GND
ML_LANE2P
ML_LANE2N
RETURN
ML_LANE3N
GND
AUX_CHP
AUX_CHN
DP_PWR
HDMI_CEC
R9407
1
2
4
8
10
87
12
87
DP_ML_CONN_P<3>
DP_ML_CONN_N<3>
DP_EXT_LINK_P<3> IN
DP_EXT_LINK_N<3> IN
NO_TEST
NO_TEST
16
DP_EXT_AUXCH_P
DP_EXT_AUXCH_N
18
78 81 87
20
NOSTUFF
CRITICAL
22
21
NOSTUFF
IN
87 78
IN
DP_EXT_LINK_P<2>
DP_EXT_LINK_N<2>
SYM_VER-2
RCLAMP0524P
SLP2510P8
5%
1/16W
MF-LF
402
5 IO
IO 4
NC 7
6 NC
GND
87 78
TCM1210-4SM
D9411
R9425
1M
20
FL9402
12-OHM-100MA
4
78 87
78 81 87
SHIELD PINS
R9404
78 87
14
D9400
R9405
1
2
RCLAMP0504F
D9411
SC70-6-1
RCLAMP0524P
SLP2510P8
2 IO
IO
NC
78
OUT
DP_CA_DET
DP_HPD_EXT
IN
78 81
R94221
10
1M
GND
9 NC
CRITICAL
NOSTUFF
CRITICAL
5%
1/16W
MF-LF
402
PAGE TITLE
Display: Ext DP Connector

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
94 OF 110
SHEET
80 OF 92
4
3
2
External AUX Channel and HPD Buffers & filters
PANEL/BACKLIGHT CONTROL MUX

81 79 78 77 6
81 79 78 77 6
=PP3V3_S0_DP
=PP3V3_S0_DP
C9550
CRITICAL
6
1
VCC
0.1UF
14
81 45
BIDIVI_AUX_TERM_EN
IN
81 78 45
74LVC14
2
14
U9540
20%
10V
CERM 2
402
U9500
NX3L1G66
SOT886
BIDIVI_AUX_TERM_EN_L
TSSOP-HF
81
5 TC7SZ08AFEAPE
DP_SINK_AUX_TERM_EN
SOT665
U9550Y
DPMUX_VIDEO_IN_SEL
IN
BIDIVI_BKL_MUX_SEL 81
C9500
0.1UF
81 79 78 77 6
20%
10V
2 CERM
402
NC
GND
3
U9510
16
VOLTAGE=3.3V
VCC
U9522
NOSTUFF
R9523
0
81
IN
81 74
IN
81 45
IN
74
IN
81 45
IN
74
IN
87 80 78
1 S
15 E*
3
2
6
5
10
11
13
14
BIDIVI_BKL_PWM
MXM_PNL_BL_PWM
BIDIVI_BKL_ON
MXM_PNL_BL_EN
BIDIVI_PNL_PWR_EN
MXM_PNL_PWR_EN
1Y
2Y
3Y
4Y
4
7
9
12
BACKLIGHT_PWM
LCD_BKL_ON_MUX
LCD_PANEL_PWR
OUT
77
OUT
77
OUT
77
81 79 78 77 6
81 79 78 77 6
17
U9510
DP_AUXN_L
1K
10 AUXCH_N_R
3.3K 2
AUXCH_N_STATE
45 81
5%
1/16W
MF-LF
402
7 TSSOP-HF
C9503 1
10%
6.3V 2
CERM
402
1%
1/16W
MF
402 2
PLACE NEAR U6201
1 I1
3 I0
Y 4
MUX
SELECTOR
D9503
SOT23
SOT886
81 79 78 77 6
6
IN
R9506
74LVC14
14
1UF
AUD_SPDIF_IN_CODEC
OUTPUT
OUT
=PP3V3_S0_DP
C9562
20%
10V
2 CERM
402
PP3V3_S0_DP_D
VOLTAGE=3.3V
55
BAT54XG
U9520
74AUP2G14GM
DP_HPD_EXT
R9507
DP_HPD_EXT_L
1M
MUX_CNTRL
14
4.7K 2
U9500
74LVC14
8
14
R9509
1
7 TSSOP-HF
C9504 1
3.3K 2
SMC_DP_HPD
45 81
5%
1/16W
MF-LF
402
1UF
5%
1/16W
MF-LF
402 2
60
DP_HPD_PULS_EAT_L
5%
1/16W
MF-LF
402
R9508
SOT886
80 78
=PP3V3_S0_DP
BAT54XG
GND
81 79 78 77 6
D9502
SOT23
0.1UF
NOSTUFFR9541
AUD_MUX_CNTRL
U9500
14
11
DP_AUXN_DLY_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
55
45 81
=PP3V3_S0_DP
R9505
SPDIF_DP_AUDIO_OUT
AUD_SPDIF_IN
AUXCH_P_STATE
5%
1/16W
MF-LF
402
74AUP2G14GM
DP_EXT_AUXCH_N
R9542
IN
3.3K 2
=PP3V3_S0_DP
81 45
7 TSSOP-HF
BAT54XG
SOT886
87 80 78
VCC
12 AUXCH_P_R
D9501
SOT23
U9524
74LVC1G157
BIDIVI_AUDIO_MUX_SEL 1
R9503
74LVC14
=PP3V3_S0_DP
DisplayPort
AUDIO MUX
IN
U9500
14
5%
1/16W
MF-LF
402
4.75M
IN
14
13
DP_AUXP_DLY_L
1%
1/16W
MF
402 2
1I1
1I0
2I1
2I0
3I1
3I0
4I1
4I0
R95211
77
1K
4.75M
85 59
R95201
DHVQFN
THM
GND PAD
81 79 78 77 6
10%
6.3V
CERM 2
402
R9502
DP_AUXP_L
499K 2
1%
1/16W
MF-LF
402
DP_EXT_AUXCH_P
74LVC157A
BIDIVI_BKL_MUX_SEL
5%
1/16W
MF-LF
402
81 45
PP3V3_S0_DPAUXP_SINK
1UF
BAT54XG
74AUP2G14GM
R9543
C9501
SOT886
=PP3V3_S0_DP
=PP3V3_S0_DP
D9500
SOT23
81 79 78 77 6
10%
6.3V 2
CERM
402
HPD_FILT
OUT
81
5%
1/16W
MF-LF
402
BiDiVi MUX Enable

81 79 78 77 6
=PP3V3_S0_DP
81 79 78 77 6
U9501
81 78 45
IN
81
DPMUX_VIDEO_IN_SEL 7
IN
HPD_FILT
AUX Bias Enable

81 79 78 77 6
74LVC2G32
SOT902
1
DPMUX1_OROUT_L
=PP3V3_S0_DP
DPMUX1_ENABLE
OUT
78
14
81 78 45
IN
DPMUX_VIDEO_IN_SEL
14
7
20%
10V
2 CERM
402
U9500
74LVC14
6
DPMUX_VIDEO_IN_SEL_L
8 74LVC2G08
81 79 78 77 6
77
VIDEO_ON
IN
3.3K
5%
1/16W
MF-LF
402
SMC_VIDEO_ON
45
C9561
U9501
Outputs
81
Default Values
S5/S3
IN
S0
81 45
P21*
P27
DPMUX_VIDEO_IN_SEL
OUT
45 78 81
IN
AUXCH_P_STATE
P22*
PF3
BIDIVI_AUX_TERM_EN
OUT
45 81
81 45
IN
AUXCH_N_STATE
P23*
PF4
BIDIVI_PNL_PWR_EN
OUT
45 81
PF6
BIDIVI_BKL_ON
OUT
45 81
PF7
BIDIVI_BKL_PWM
OUT
45 81
P26
BIDIVI_AUDIO_MUX_SEL
OUT
45 81
IN
HPD_FILT
BIDIVI_AUX_TERM_EN
74LVC2G32
SOT902
5
AUX_TERM_OR_OUT
IN
P25*
R9540
81 74
IN
MXM_PNL_BL_PWM
3.3K 2
SMC_PNL_BL_PWM
45 46
PG0
81 78 45
IN
DPMUX_VIDEO_IN_SEL
5%
1/16W
MF-LF
402
8 74LVC2G08
SOT902
U9502Y 1
B
Display: BiDiVi Support
6 77 78 79 81
DRAWING NUMBER
enables weak sink-like aux termination

so that one bi-directional system can find the other
Apple Inc.
051-8600
DP_SINK_AUX_TERM_EN
OUT
08
81

SIZE
REVISION
A.0.0
PAGE TITLE
=PP3V3_S0_DP
81 45
80
0.1UF
81 45
SMC_DP_HPD
DP_SRC_AUX_TERM_EN OUT
enables 100k dp aux source termination
20%
10V
2 CERM
402
SMC Signals for BiDiVi

SMC
08
=PP3V3_S0_DP
*Some inputs listed below come up as outputs driven low under the SMC flasher
Series R should prevent any issues on the inputs
Ouptuts are OK as low by default
Inputs
SOT902
U9502Y 5
2
TSSOP-HF
R9510
C9560
0.1UF
R9511
5%
1/16W
MF-LF
402
=PP3V3_S0_DP
BRANCH
PAGE
95 OF 110
SHEET
81 OF 92
K60/K61 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
SPACING RULE SET

TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
PHYSICAL CONSTRAINTS
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
STANDARD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
POWER
STANDARD
TABLE_SPACING_RULE_ITEM
DEFAULT
0.1 MM
STANDARD
=DEFAULT
WEIGHT
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DEFAULT
=50_OHM_SE
=50_OHM_SE
100 MM
0 MM
0 MM
STANDARD
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_ASSIGNMENT_ITEM
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
2X_DIELECTRIC
0.150 MM
2X_DIELECTRIC
TOP,BOTTOM
0.160 MM
SPACING_RULE_SET
LAYER
1.5:1_SPACING
0.15 MM
2:1_SPACING
0.2 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
TOP,BOTTOM
0.21 MM
0.085 MM
=STANDARD
35_OHM_SE
0.19 MM
0.085 MM
=STANDARD
=STANDARD
0.220 MM
3X_DIELECTRIC
TOP,BOTTOM
0.240 MM
4X_DIELECTRIC
0.300 MM
4X_DIELECTRIC
TOP,BOTTOM
0.320 MM
5X_DIELECTRIC
0.380 MM
5X_DIELECTRIC
TOP,BOTTOM
0.400 MM
2.5:1_SPACING
0.25 MM
3:1_SPACING
0.3 MM
4:1_SPACING
0.4 MM
5:1_SPACING
0.5 MM
6:1_SPACING
0.6 MM
WEIGHT
=STANDARD
3X_DIELECTRIC
35_OHM_SE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
39_OHM_SE
TOP,BOTTOM
0.175 MM
0.085 MM
=STANDARD
39_OHM_SE
0.16 MM
0.085 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
45_OHM_SE
TOP,BOTTOM
0.135 MM
0.085 MM
=STANDARD
45_OHM_SE
0.12 MM
0.085 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
GND
=STANDARD
GND_P2MM
0.2 MM
1000
PWR_P2MM
0.2 MM
1000
SWITCHNODE
0.8 MM
1000
50_OHM_SE
TOP,BOTTOM
0.1 MM
0.085 MM
15 MM
50_OHM_SE
0.1 MM
0.085 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
55_OHM_SE
TOP,BOTTOM
0.085 MM
0.085 MM
=STANDARD
CONSTRAINTS FOR BGA AREA
SPACING_RULE_SET
LAYER
WEIGHT
55_OHM_SE
0.076 MM
0.075 MM
=STANDARD
=STANDARD
=STANDARD
BGA_P1MM
=DEFAULT
BGA_P2MM
0.2 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL6
0.155 MM
0.085 MM
=STANDARD
0.135 MM
0.1 MM
70_OHM_DIFF
TOP,BOTTOM
0.165 MM
0.085 MM
=STANDARD
0.130 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA_P1MM
BGA_P1MM
MEM_CLK
BGA_P1MM
BGA_P2MM
CLK_PCIE
BGA_P1MM
BGA_P1MM
CLK_LPC
BGA_P1MM
BGA_P1MM
CLK_PCI
BGA_P1MM
BGA_P1MM
85_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
85_OHM_DIFF
ISL3,ISL6
0.115 MM
0.085 MM
=STANDARD
0.2 MM
0.1 MM
85_OHM_DIFF
TOP,BOTTOM
0.125 MM
0.085 MM
=STANDARD
0.2 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL6
0.099 MM
0.085 MM
12 MM
0.200 MM
0.1 MM
90_OHM_DIFF
TOP,BOTTOM
0.110 MM
0.085 MM
=STANDARD
0.200 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL6
0.081 MM
0.085 MM
=STANDARD
0.25 MM
0.1 MM
100_OHM_DIFF
TOP,BOTTOM
0.091 MM
0.085 MM
=STANDARD
0.25 MM
0.1 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
110_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
TOP,BOTTOM
0.075 MM
0.085 MM
=STANDARD
0.320 MM
0.15 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.085 MM
POWER_WIDTH
0.600 MM
0.200 MM
3.0 MM
=STANDARD
=STANDARD
POWER_CTL
0.300 MM
0.200 MM
3.0 MM
=STANDARD
=STANDARD
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
POWER
BGA_P1MM
POWER_CTL
POWER
POWER_WIDTH
TABLE_PHYSICAL_ASSIGNMENT_ITEM
K60/K61 RULE DEFINITIONS
VR_CTL_PHY
BGA_P1MM
DEFAULT
NOTICE OF PROPRIETARY PROPERTY
VR_CTL_PHY
POWER_CTL
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-8600
3.0.0
OF
82
92
Memory Bus Constraints
Memory Net Properties

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_45S
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
MEM_70D
MEM_CLK
MEM_70D
MEM_CLK
MEM_A_CLK_P<3..0>
MEM_A_CLK_N<3..0>
MEM_39S
=39_OHM_SE
=39_OHM_SE
=39_OHM_SE
=39_OHM_SE
=STANDARD
=STANDARD
12 32
12 32
MEM_35S
=35_OHM_SE
=35_OHM_SE
=35_OHM_SE
=35_OHM_SE
=STANDARD
=STANDARD
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_39S
MEM_CTRL
MEM_39S
MEM_CTRL
MEM_39S
MEM_CTRL
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
SPACING_RULE_SET
LAYER
WEIGHT
MEM_CLK2MEM
=4:1_SPACING
MEM_CTRL2CTRL
=2:1_SPACING
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
12 30
12 30
12 30
12 30
12 30
12 30
12 30
12 30
MEM_CTRL2MEM
=2.5:1_SPACING
MEM_CMD2CMD
=1.5:1_SPACING
MEM_CMD2MEM
=3:1_SPACING
MEM_DQ_ODD2DQ_ODD
=3:1_SPACING
MEM_A_DQ<7..0>
MEM_A_DM<0>
MEM_A_DQ<15..8>
MEM_A_DM<1>
12 32
12 32
12 32
12 32
MEM_A_DQ<23..16>
MEM_A_DM<2>
MEM_DQ_ODD2MEM
=3:1_SPACING
MEM_DQ_EVEN2DQ_EVEN
=3:1_SPACING
MEM_DQ_EVEN2MEM
=3:1_SPACING
12 32
12 32
MEM_DQ_EVEN2DQ_ODD
=5:1_SPACING
MEM_DQS2MEM
=3:1_SPACING
MEM_A_DQ<31..24>
MEM_A_DM<3>
MEM_A_DQ<39..32>
MEM_A_DM<4>
12 32
12 32
12 32
12 32
MEM_A_DQ<47..40>
MEM_A_DM<5>
MEM_2OTHER
=3:1_SPACING
Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CLK
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK2MEM
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQ_ODD
MEM_CLK2MEM
MEM_CLK
MEM_DQS
MEM_CLK2MEM
MEM_DQS
MEM_DQ_ODD
MEM_DQS2MEM
MEM_DQS
MEM_DQS
MEM_DQS2MEM
MEM_DQ_EVEN
NET_SPACING_TYPE2
MEM_CLK2MEM
AREA_TYPE
MEM_DQS
MEM_DQ_EVEN
MEM_DQS2MEM
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQ_ODD
MEM_CLK
MEM_DQ_ODD2MEM
MEM_DQ_ODD
MEM_CTRL
MEM_DQ_ODD2MEM
MEM_DQ_ODD
MEM_CMD
MEM_DQ_ODD2MEM
MEM_DQ_ODD
MEM_DQ_ODD
MEM_DQ_ODD2DQ_ODD
MEM_DQ_EVEN
MEM_CLK
MEM_DQ_EVEN2MEM
MEM_DQ_EVEN
MEM_CTRL
MEM_DQ_EVEN2MEM
MEM_DQ_EVEN
MEM_CMD
MEM_DQ_EVEN2MEM
MEM_DQ_EVEN
MEM_DQ_EVEN
MEM_DQ_EVEN2DQ_EVEN
MEM_DQ_EVEN
MEM_DQS
MEM_DQ_EVEN2MEM
MEM_DQ_ODD2MEM
MEM_DQ_ODD
MEM_DQ_EVEN
NET_SPACING_TYPE2
MEM_DQ_EVEN2DQ_ODD
AREA_TYPE
MEM_DQ_EVEN
MEM_DQ_ODD
MEM_CLK
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CTRL
MEM_CTRL2MEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CTRL2CTRL
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_DQ_ODD
MEM_CTRL2MEM
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_CMD
MEM_DQ_ODD
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
MEM_DQ_EVEN
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_CLK
MEM_70D
MEM_CLK
PHYSICAL
SPACING
12 32
12 32
12 32
12 32
12 32
12 32
12 32
I155
MEM_POWER_PHY
MEM_POWER
I154
MEM_POWER_PHY
MEM_POWER
I166
MEM_POWER_PHY
MEM_POWER
I167
MEM_POWER_PHY
MEM_POWER
I169
MEM_POWER_PHY
MEM_POWER
I168
MEM_POWER_PHY
MEM_POWER
CPU_DIMM_VREF_A
CPU_DIMM_VREF_B
VREFMARGIN_DIMMA_DQ
VREFMARGIN_DIMMB_DQ
CPU_DIMM_VREF_A_SW
CPU_DIMM_VREF_B_SW
MEM_B_CLK_P<3..0>
MEM_B_CLK_N<3..0>
MEM_39S
MEM_CTRL
MEM_39S
MEM_CTRL
MEM_39S
MEM_CTRL
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_35S
MEM_CMD
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_EVEN
MEM_B_DQ<7..0>
MEM_B_DM<0>
MEM_CTRL2MEM
MEM_CMD
MEM_DQ_EVEN
MEM_CMD2MEM
NET_SPACING_TYPE1
MEM_CLK
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_B_DQ<15..8>
MEM_B_DM<1>
MEM_2OTHER
MEM_B_DQ<23..16>
MEM_B_DM<2>
MEM_CTRL
MEM_2OTHER
MEM_45S
MEM_CMD
MEM_2OTHER
MEM_DQ_ODD
MEM_2OTHER
MEM_DQS
MEM_DQ_EVEN
MEM_2OTHER
MEM_2OTHER
Need to support MEM_*-style wildcards!
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_EVEN
MEM_45S
MEM_DQ_ODD
MEM_45S
MEM_DQ_ODD
MEM_B_DQ<31..24>
MEM_B_DM<3>
MEM_B_DQ<39..32>
MEM_B_DM<4>
MEM_B_DQ<47..40>
MEM_B_DM<5>
MEM_B_DQ<55..48>
MEM_B_DM<6>
MINIMUM LINE WIDTH
28
28
28
12 32
12 32
12 32
12 32
Memory Net Properties
12 32
NET_TYPE
12 32
PHYSICAL
SPACING
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
CPU_SM_RCOMP0
CPU_SM_RCOMP1
CPU_SM_RCOMP2
12 31
12 31
12 31
MEM_70D
MEM_DQS
12 31
MEM_70D
MEM_DQS
12 31
MEM_70D
MEM_DQS
12 31
MEM_70D
MEM_DQS
12 31
MEM_70D
MEM_DQS
12 31
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
12 32
12 32
MEM_70D
MEM_DQS
12 32
MEM_70D
MEM_DQS
12 32
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
I160
MEM_RCOMP_PHY
MEM_RCOMP
I159
MEM_RCOMP_PHY
MEM_RCOMP
I161
MEM_RCOMP_PHY
MEM_RCOMP
I162
MEM_70D
MEM_DQS
I163
MEM_70D
MEM_DQS
I164
MEM_70D
MEM_DQS
I165
MEM_70D
MEM_DQS
12 32
12 32
12 32
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
12 32
11
11
11
12 32
12 32
12 32
ALLOW ROUTE
ON LAYER?
28
12 32
LAYER
12 28
12 32
PHYSICAL_RULE_SET
12 28
12 32
MEM_CTRL
MEM_DQS
MEM_70D
MEM_CTRL2MEM
MEM_CTRL
MEM_DQS
MEM_70D
NET_TYPE
VOLTAGE
12 32
SPACING_RULE_SET
MEM_CTRL
MEM_70D
SPACING_RULE_SET
MEM_DQS
MEMORY POWER PROPERTIES
12 32
MEM_DQ_EVEN2DQ_ODD
MEM_CTRL
MEM_70D
12 32
NET_SPACING_TYPE1
MEM_DQS
12 32
12 32
MEM_70D
12 32
12 32
MEM_DQS
MEM_DQS
MEM_DQ_ODD
MEM_70D
NET_SPACING_TYPE1
MEM_DQS
MEM_CLK
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_CLK
MEM_A_DQ<63..56>
MEM_A_DM<7>
MEM_CLK
MEM_A_DQ<55..48>
MEM_A_DM<6>
12 32
12 32
TP_MEM_B_DQS_P<8>
TP_MEM_B_DQS_N<8>
TP_MEM_A_DQS_P<8>
TP_MEM_A_DQS_N<8>
12 32
8 12
8 12
8 12
8 12
ADD RULES TO NC_DQS<8>

TO CLEAR CHECK_PLUS ERRORS
12 32
12 32
MEM_POWER_WIDTH
0.500 MM
0.175 MM
=STANDARD
=STANDARD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
MEM_POWER_PHY
MEM_POWER_WIDTH
=STANDARD
MEM_B_DQ<63..56>
MEM_B_DM<7>
12 32
12 32
SPACING_RULE_SET
LAYER
WEIGHT
0.2 MM
MEM_POWER
PAGE TITLE
Memory Constraints
DRAWING NUMBER
Apple Inc.
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
051-8600
0.175 MM
0.175 MM
=STANDARD
=STANDARD
=STANDARD

SPACING_RULE_SET
LAYER
WEIGHT
0.2 MM
MEM_RCOMP
A.0.0
R
MEM_RCOMP_PHY
SIZE
REVISION
BRANCH
PAGE
101 OF 110
SHEET
83 OF 92
PCI-Express
NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
PHYSICAL
SPACING
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PCIE
=4X_DIELECTRIC
PCIE GRAPHICS
=100_OHM_DIFF
0.5 MM
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
D
CPU
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
MXM_PCIE_R2D_P<15..0>
MXM_PCIE_R2D_N<15..0>
MXM_PCIE_D2R_P<15..0>
MXM_PCIE_D2R_N<15..0>
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_MINI_R2D_L_P
PCIE_MINI_R2D_L_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
CPU_AGTL
=STANDARD
?
CPU_ITP
0.2 MM
CPU_RCOMP
0.2 MM
9 75
9 75
9 75
9 75
73 75
73 75
73 75
73 75
PCIE I/O
PHYSICAL_RULE_SET
PCIE
PCIE_85D
CLK_PCIE
PCIE_85D
33
33
18 33
18 33
18 33
18 33
33
33
39
39
18 39
18 39
18 39
18 39
39
39
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
SPACING_RULE_SET
LAYER
WEIGHT
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
ENET_100D
ENET_MII
ENET_100D
ENET_MII
18 42
SATA_85D
SATA
42
SATA_85D
SATA
SATA
=5X_DIELECTRIC
DMI
WEIGHT
SATA
TOP,BOTTOM
=5X_DIELECTRIC
DMI_S2N_P<3..0>
DMI_S2N_N<3..0>
DMI_N2S_P<3..0>
DMI_N2S_N<3..0>
10 19
10 19
10 19
10 19
FDI
FDI_DATA_N<7..0>
FDI_DATA_P<15..0>
PCIE REF CLOCKS

NET_TYPE
PHYSICAL
SPACING
FDI_MISC
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
FDI_FSYNC<1..0>
FDI_LSYNC<1..0>
FDI_INT
SATA SSD
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_SSD_R2D_C_P
SATA_SSD_R2D_C_N
SATA_SSD_R2D_P
SATA_SSD_R2D_N
SATA_SSD_D2R_P
SATA_SSD_D2R_N
SATA_SSD_D2R_C_P
SATA_SSD_D2R_C_N
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
9
9
33
33
18 33
18 33
18 39
18 39
18 36
18 36
SATA
18 42
42
SATA_85D
SATA
18 42
SATA_85D
SATA
18 42
SATA_85D
SATA
42
SATA_85D
SATA
42
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
SATA_85D
SATA
CLOCKS
CLK_PCIE_100D
GPU_CLK100M_PCIE_P
GPU_CLK100M_PCIE_N
PCIE_CLK100M_MINI_CON_P
PCIE_CLK100M_MINI_CON_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
10 18
10 18
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
18 42
18 42
42 92
42 92
18 42
18 42
42 92
42 92
18 42
18 42
42 92
42 92
18 42
18 42
42 92
42 92
CLOCKS
CPU ITP
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
XDP_BPM_L<7..0>
CPU_CFG<17..0>
XDP_OBSDATA_A<3..0>
CLK_PCIE_100D
CLK_PCIE
11 25
CLK_PCIE_100D
CLK_PCIE
10 15 25
CLK_PCIE_100D
CLK_PCIE
25
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CPU_MISC
CPU_50S
CPU_RCOMP
CPU_50S
CPU_RCOMP
CPU_50S
CPU_RCOMP
CPU_50S
CPU_RCOMP
CPU_50S
CPU_RCOMP
CPU_50S
CPU_RCOMP
CPU_PEG_COMP
CPU_PEG_RBIAS
CPU_COMP3
CPU_COMP2
CPU_COMP1
CPU_COMP0
10
10
11
FSB_CLK133M_CPU_P
FSB_CLK133M_CPU_N
FSB_CLK133M_ITP_P
FSB_CLK133M_ITP_N
PCIE_CLK100M_CPU_P
PCIE_CLK100M_CPU_N
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
11 21
11 21
11 18
11 18
11 25
11 25
11 18
11 18
18 26
18 26
11
11
11
FSB_CLK133M_PCH_P
FSB_CLK133M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
18 26
18 26
18 26
18 26
PAGE TITLE
PCIE/DMI/FDI/SATA CONSTRAINTS
DRAWING NUMBER
18 26
Apple Inc.
ANY OTHER LYNNFIELD CONSTRAINTS NOT COVERED ON PAGES 101 AND 107 SHOULD GO ON THIS PAGE TOO
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
102 OF 110
SHEET
84 OF 92
PCH
CONSTRAINTS
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCH_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_PCH_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
CLK_PCH
0.2 MM
COMP_PCH
0.2 MM
D
PCI Bus Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
PCI
=STANDARD
CLK_PCI
0.2 MM
PHYSICAL
NET_TYPE
SPACING
PCI_55S
PCI_55S
CLK_PCI_55S
LPC Bus Constraints
CLK_PCI_55S
LPC_55S
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
NET_TYPE
PCI
PCI_REQ0_L
PCI_REQ1_L
PCI
CLK_PCI
CLK_PCI
LPC
PCH_CLK33M_PCIOUT
PHYSICAL
SPACING
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
20
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
SPI_MLB_CS_L
SPI_ALT_CS_L
SPIROM_USE_MLB
SPI_ALT_MOSI
SPI_ALT_MISO
SPI_ALT_CLK
HDA_BIT_CLK
20
20 27
PCH_CLK33M_PCIIN
18 27
LPC_AD<3..0>
18 45 47
LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
LPC_55S
LPC
LPC_FRAME_L
18 45 47
SPACING_RULE_SET
LAYER
WEIGHT
0.15 MM
LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC
0.2 MM
CLK_LPC_55S
USB 2.0 Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
PM
CLK_LPC_55S
PM
CLK_LPC_55S
CLK_LPC
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
USB_90D
USB
USB_90D
USB
USB_90D
USB
SPACING_RULE_SET
LAYER
WEIGHT
USB
USB
USB
TOP,BOTTOM
=4x_DIELECTRIC
SMBus Interface Constraints
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_90D
USB
USB_90D
USB
USB_90D
USB
SPACING_RULE_SET
LAYER
WEIGHT
USB_90D
SMB
=2x_DIELECTRIC
HD Audio Interface Constraints
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
HDA
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
SPI Interface Constraints
USB
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_EXTA_P
USB_EXTA_N
USB_PORT0_P
USB_PORT0_N
USB_EXTB_P
USB_EXTB_N
USB_PORT1_P
USB_PORT1_N
USB_EXTC_P
USB_EXTC_N
USB_PORT2_P
USB_PORT2_N
USB_EXTD_P
USB_EXTD_N
USB_D_MUXED_P
USB_D_MUXED_N
USB_PORT3_P
USB_PORT3_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_L_P
USB_CAMERA_L_N
USB_BT_P
USB_BT_N
USB_BT_L_P
USB_BT_L_N
USB_IR_P
USB_IR_N
USB_IR_L_P
USB_IR_L_N
USB_SDCARD_P
USB_SDCARD_N
USB_SDCARD_L_P
USB_SDCARD_L_N
USB_WM_P
USB_WM_N
USB_WM_L_P
USB_WM_L_N
USB_MINI_P
USB_MINI_N
USB_BRCRYPT_P
USB_BRCRYPT_N
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
CLK_XTAL
XTAL
CLK_XTAL
XTAL
CLK_XTAL
XTAL
CLK_XTAL
XTAL
CK505_XTAL_IN
CK505_XTAL_OUT
CLK_PCH_55S
CLK_PCH
PCH_CLK14P3M_REFCLK
USB_90D
USB
USB_90D
USB
PHYSICAL_RULE_SET
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
20 27
27 45
27 47
18 47 54
54
18 47 54
54
18 47 54
54
18 47
47
47 54
47
21 47
47
47
47
18 55
9 19 91
9 45 91
HDA_BIT_CLK_R
HDA_RST_L
HDA_RST_R_L
HDA_SDOUT
HDA_SDOUT_R
HDA_SYNC
HDA_SYNC_R
HDA_SDIN0
AUD_SDI_R
AUD_SPDIF_IN
AUD_SPDIF_OUT
AUD_SPDIF_CHIP
20 27
34 43
34 43
43
43
35 43
35 43
43
HDA
43
HDA
34 43
HDA
34 43
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
43
43
35 43
35 43
43
43
43
18
18 55
18
18 55
18
18 55
18
18 55
55
59 81
55 59
55
57 59 92
57 59 92
57 59 92
57 59 92
58 59 92
58 59 92
58 59 92
58 59 92
43
34 44
34 44
CLK_XTAL
XTAL
CLK_XTAL
XTAL
35 44
PCH_55S
COMP_PCH
35 44
PCH_55S
COMP_PCH
44 92
PCH_55S
COMP_PCH
44 92
PCH_55S
COMP_PCH
44 92
44 92
PCH_CLK25M_XTALOUT
PCH_CLK25M_XTALIN
18 27
18 27
PCH_USB_RBIAS
PCH_SATAICOMP
PCH_XCLK_RCOMP
PCH_DMI_COMP
20
18
18
19
34 44
34 44
44 92
44 92
35 44
CLK_XTAL
XTAL
CLK_XTAL
XTAL
PCH_55S
COMP_PCH
USB_HUB1_XTAL1
USB_HUB1_XTAL2
34
34
USB_HUB1_RBIAS
34
35 44
44 92
44 92
20 44
20 44
CLK_XTAL
XTAL
CLK_XTAL
XTAL
PCH_55S
COMP_PCH
USB_HUB2_XTAL1
USB_HUB2_XTAL2
35
35
USB_HUB2_RBIAS
35
44
44
20 44
20 44
SPACING_RULE_SET
LAYER
WEIGHT
0.2 MM
SPI
PCH_CLK32K_RTCX1
PCH_CLK32K_RTCX2
18 27
18 27
26
26
PAGE TITLE
XTAL Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CLK_XTAL
SPACING_RULE_SET
LAYER
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
WEIGHT
XTAL
=4X_DIELECTRIC
IBEX PEAK CONSTRAINTS
18 26
DRAWING NUMBER
USB_BRCRYPT_L_P
USB_BRCRYPT_L_N
Apple Inc.
44
44
051-8600
USB_HUB2_UP_P
USB_HUB2_UP_N
20 34
20 34
20 35
20 35

A.0.0
USB_HUB1_UP_P
USB_HUB1_UP_N
SIZE
REVISION
BRANCH
PAGE
103 OF 110
SHEET
85 OF 92
CAESAR II (ETHERNET) CONSTRAINTS

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
SPACING
SPACING_RULE_SET
LAYER
WEIGHT
ENET_50S
ENET_SE
ENET_50S
BUF0_CLK
ENET_50S
BUF0_CLK
ENET_50S
BUF0_CLK
ENET_100D
ENET_DIFF
ENET_100D
ENET_DIFF
ENET_100D
ENET_DIFF
ENET_100D
ENET_DIFF
ENET_100D
ENET_MII
ENET_100D
ENET_MII
ENET_100D
ENET_MII
ENET_100D
ENET_MII
ENET_100D
ENET_MII
ENET_100D
ENET_MII
ENET_100D
ENET_MII
ENET_100D
ENET_MII
BUF0_CLK
=3:1_SPACING
ENET_RDAC
ENET_CLK25M_XTALI
ENET_CLK25M_XTALO
ENET_CLK25M_XTAL
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
36
36
36
36
36 38
36 38
ENET_MII
0.3 MM
ENET_SE
=STANDARD
SOURCE:BROADCOM 5764M-DS04-RDS. PAGE 38
CAESAR II (ETHERNET) CONSTRAINTS
ENET_MDI_T_P<3..0>
ENET_MDI_T_N<3..0>
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
38
38
36
36
18 36
18 36
18 36
18 36
36
36
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
0.6 MM
ENET_DIFF
SOURCE: BROADCOM 5764-DS04-RDS. PAGE 38
FireWire Interface Constraints
FireWire Net Properties

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
PHYSICAL
SPACING
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
=3:1_SPACING
FW_PORT0_TPA_P
FW_PORT0_TPA_N
FW_PORT0_TPB_P
FW_PORT0_TPB_N
40 41
40 41
40 41
40 41
PORT 1 & 2 NOT USED
FW_P0_TPA_L_P
FW_P0_TPA_L_N
FW_P0_TPB_L_P
FW_P0_TPB_L_N
40
40
40
40
UNUSED FW NETS PHYSICAL PROPERTIES

FireWire Interface Constraints
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_110D
FW_TP
FW_P1_TPA_P
FW_P1_TPA_N
39 40
39 40
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
AUDIO_PHY
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
FW_P2_TPA_P
FW_P2_TPA_N
39 40
39 40
SPACING_RULE_SET
LAYER
WEIGHT
AUDIO
=STANDARD
AUDIO MIC PHYSICAL PROPERTIES

AUDIO_PHY
AUDIO
AUDIO_PHY
AUDIO
AUD_MIC1_IN_N
AUD_MIC1_IN_P
59 60
59 60
PAGE TITLE
ENET/FIREWIRE CONSTRAINTS
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
FIT;
BRANCH
PAGE
104 OF 110
SHEET
86 OF 92
NET_TYPE
PHYSICAL
SPACING
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
ASSINGED IN CONT. MGR.
DIFFPAIR NECK GAP

DP_85D
=85_OHM_DIFF
=85_OHM_DIFF
0.08MM
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DISPLAYPORT
=3:1_SPACING
PAIRS SHOULD BE WITHIN 100 MILS OF CLOCK LENGTH.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
DP_INT_LINK_CONN_P<3..0>
DP_INT_LINK_CONN_N<3..0>
DP_INT_LINK_P<3..0>
DP_INT_LINK_N<3..0>
DP_INT_AUXCH_P
DP_INT_AUXCH_N
DP_EXT_LINK_P<3..0>
DP_EXT_LINK_N<3..0>
DP_EXT_AUXCH_P
DP_EXT_AUXCH_N
DP_EXT_LINK_C_P<3..0>
DP_EXT_LINK_C_N<3..0>
MXM_DP_A_ML_P<3..0>
MXM_DP_A_ML_N<3..0>
MXM_DP_A_AUX_C_P
MXM_DP_A_AUX_C_N
MXM_DP_A_AUX_P
MXM_DP_A_AUX_N
MXM_DP_C_ML_P<3..0>
MXM_DP_C_ML_N<3..0>
MXM_DP_C_AUX_P
MXM_DP_C_AUX_N
MXM_DP_C_AUX_C_P
MXM_DP_C_AUX_C_N
DP_MUX_P<3..0>
DP_MUX_N<3..0>
DP_MUX_AUXCH_P
DP_MUX_AUXCH_N
DP_EQLZ_AUXCH_P
DP_EQLZ_AUXCH_N
MXM_DP_A_ML_C_P<3..0>
MXM_DP_A_ML_C_N<3..0>
MXM_DP_C_ML_C_P<3..0>
MXM_DP_C_ML_C_N<3..0>
DP_TX_EQ_AUXCH_P
DP_TX_EQ_AUXCH_N
MXM_DP_A_ML_EQ_P<3..0>
MXM_DP_A_ML_EQ_N<3..0>
80
80
77
77
77 79
77 79
77 79
77 79
78 80
78 80
78 80 81
78 80 81
78
78
73 78
73 78
78
78
73 78
73 78
73 79
73 79
73 79
73 79
79
79
78 79
78 79
78 79
78 79
79
79
78
78
79
79
78
78
78
78
UNUSED VIDEO NET PHYSICAL CONSTRAINTS
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
MXM_DP_B_AUX_P
MXM_DP_B_AUX_N
MXM_DP_D_AUX_P
MXM_DP_D_AUX_N
MXM_LVDS_A_CLK_P
MXM_LVDS_A_CLK_N
MXM_LVDS_B_CLK_P
MXM_LVDS_B_CLK_N
MXM_DP_B_ML_P<3..0>
MXM_DP_B_ML_N<3..0>
MXM_DP_D_ML_P<3..0>
MXM_DP_D_ML_N<3..0>
MXM_LVDS_A_DATA_P<3..0>
MXM_LVDS_A_DATA_N<3..0>
MXM_LVDS_B_DATA_P<3..0>
MXM_LVDS_B_DATA_N<3..0>
73 76
73 76
73 76
73 76
74 76
74 76
74 76
74 76
73 76
73 76
73 76
73 76
74 76
74 76
74 76
74 76
PAGE TITLE
GRAPHICS CONSTRAINTS
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
105 OF 110
SHEET
87 OF 92
SMC SMBus Net Properties
2
SMC VOLTAGE/CURRENT NET PROPERTIES
NET_TYPE
PHYSICAL
NET_TYPE
SPACING
SMB_55S
SMB
I136
SMB_55S
SMB
I135
SMB_55S
SMB
I160
SMB_55S
SMB
I161
SMB_55S
SMB
I137
SMB_55S
SMB
I139
SMB_55S
SMB
I138
SMB_55S
SMB
I140
SMB_55S
CLK_XTAL
SMB
XTAL
CLK_XTAL
XTAL
SMC_XTAL
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
SMB_55S
SMB
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SMB
=2x_DIELECTRIC
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMBUS_PCH_S0_CLK
SMBUS_PCH_S0_DATA
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
SMC_EXTAL
SMBus Interface Constraints
I197
I196
PHYSICAL
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
THERMAL
4:1_SPACING
I97
THERM_DIFF
THERMAL
48
I98
THERM_DIFF
THERMAL
48
I99
THERM_DIFF
THERMAL
48
I100
THERM_DIFF
THERMAL
48
I148
THERM_DIFF
THERMAL
48
I149
THERM_DIFF
THERMAL
48
I150
THERM_DIFF
THERMAL
48
I151
THERM_DIFF
THERMAL
48 88
I152
THERM_DIFF
THERMAL
48 88
I153
THERM_DIFF
THERMAL
48 88
I181
THERM_DIFF
THERMAL
48 88
I182
THERM_DIFF
THERMAL
48
I183
THERM_DIFF
THERMAL
48
I184
THERM_DIFF
THERMAL
PWR_P2MM
THERMAL
GND
GND_P2MM
PHYSICAL_RULE_SET
THERM_DIFF
1:1_DIFFPAIR
SNS_DIFF
1:1_DIFFPAIR
THERM_DIFF
I87
I162
THERMAL
45 46
I124
THERMAL
I123
THERMAL
I122
THERMAL
I163
THERMAL
I164
THERMAL
I165
THERMAL
I166
THERMAL
I167
THERMAL
I168
THERMAL
I128
THERMAL
SPACING
THERMAL
I88
THERM_DIFF
THERMAL
I89
THERM_DIFF
THERMAL
I90
THERM_DIFF
THERMAL
I200
THERM_DIFF
THERMAL
THERM_DIFF
I201
PHYSICAL
THERMAL
I93
THERM_DIFF
THERMAL
I94
THERM_DIFF
THERMAL
I101
THERM_DIFF
THERMAL
I102
THERM_DIFF
THERMAL
I103
THERM_DIFF
THERMAL
I105
THERM_DIFF
THERMAL
I104
THERM_DIFF
THERMAL
I106
THERM_DIFF
THERMAL
I198
THERM_DIFF
THERMAL
I199
THERM_DIFF
THERMAL
I109
THERM_DIFF
THERMAL
I110
THERM_DIFF
THERMAL
I111
THERM_DIFF
THERMAL
I112
THERM_DIFF
THERMAL
I194
THERM_DIFF
THERMAL
I195
THERM_DIFF
THERMAL
I115
THERMAL
I133
THERMAL
I134
THERMAL
I132
THERMAL
SNS_T_DP1_DN6
SNS_T_DN1_DP6
SNS_T_DP2_DN3
SNS_T_DN2_DP3
SNS_T_DN1_DP6
SNS_T_DP1_DN6
SNS_T_DP4_DN5
SNS_T_DN4_DP5
SNS_LCD_P
SNS_LCD_N
SNS_ODD_P
SNS_ODD_N
SNS_CPU_H_P
SNS_CPU_H_N
SNS_SKIN_P
SNS_SKIN_N
SNS_AMB_P
SNS_AMB_N
SNS_MXM_P
SNS_MXM_N
SNS_CPU_THERMD_P
SNS_CPU_THERMD_N
HDD_OOB_TEMP_FILT
HDD_OOB_TEMP
HDD_OOB_TEMP_R
SMC_HDD_OOB_TEMP
49
49
49
49
49
49
18 48
45 46
NET_TYPE
49
18 48
SMC THERMAL NET PROPERTIES
49
18 48
I113
VID_PHY
VR_CTL
I131
THERM_DIFF
THERMAL
I130
THERM_DIFF
THERMAL
AREA_TYPE
50
18 48
NET_PHYSICAL_TYPE
50
18 48
POWER
MXM_ISENSE_P
MXM_ISENSE_N
SENSE_CPU_1V5_S3_P
SENSE_CPU_1V5_S3_N
SENSE_CPU_1V5_S0_P
SENSE_CPU_1V5_S0_N
SENSE_CPU_1V5_P
SENSE_CPU_1V5_N
SENSE_CPU_VTT_P
SENSE_CPU_VTT_N
SENSE_CPU_VTT1_P
SENSE_CPU_VTT1_N
SENSE_CPU_VTT2_P
SENSE_CPU_VTT2_N
18 48
THERMAL
SPACING
48
NET_SPACING_TYPE1
51 88
51 88
I129
THERMAL
I114
THERMAL
I169
THERMAL
I171
THERMAL
I172
THERMAL
I173
THERMAL
I174
THERMAL
I178
THERMAL
I179
THERMAL
I180
THERMAL
GND_SMC_AVSS
SMC_CPU_1V5_ISENSE
SMC_CPU_1V5_ISENSE_R
SMC_CPU_1V5_VSENSE
SMC_CPU_VTT_ISENSE
SMC_CPU_VTT_ISENSE_R
SMC_CPU_VTT_VSENSE
SMC_CPU_1V8_ISENSE
SMC_CPU_1V8_ISENSE_R
SMC_CPU_1V8_VSENSE
SMC_CPU_VSENSE
VR_CPU_IOUT
VR_ISNS_CPU_P
VR_ISNS_CPU_N
SNS_PS_CPU_ISNS
SMC_CPU_ISENSE
SMC_CPU_INPUT_ISENSE
51
51
51 88
51 88
45 46 49 50
46 49
49
46 49
46 49
49
46 49
46 49
46 49
45 49
13 64
49
49
45 49
46
SMC_CPU_INPUT_VSENSE
SMC_DIMM_1V5_ISENSE
SMC_1V5_S3_ISENSE_R
SMC_DIMM_1V5_VSENSE
46
46 50
46 50
51
51
51 92
51 92
SMC_GPU_ISENSE
SMC_MXM_ISENSE_R
SMC_GPU_VSENSE
45 50
50
45 50
51 92
51 92
51
51
51 92
51 92
51 92
51 92
51
51
10 51
10 51
51 92
51
51
51
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
051-8600

SIZE
REVISION
A.0.0
49
BRANCH
PAGE
106 OF 110
SHEET
88 OF 92
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
SWITCHNODE
SWITCHNODE
BGA_P1MM
BGA_P2MM
SWITCHNODE
POWER
BGA_P1MM
BGA_P2MM
SWITCHNODE
GND
BGA_P1MM
BGA_P2MM
SWITCHNODE
BGA_P1MM
BGA_P2MM
SWITCHNODE
POWER
6:1_SPACING
SWITCHNODE
GND
6:1_SPACING
SWITCHNODE
SWITCHNODE
POWER NET PROPERTIES
I216
I218
I217
NET_TYPE
PHYSICAL
I128
I129
I130
I131
I132
I133
I134
I135
I136
I137
I138
I139
I140
I141
I142
I143
I144
I585
I145
I146
I147
I148
I149
I175
I174
I173
I604
I605
I178
I150
I276
I277
I264
I267
I270
I544
I549
I551
I259
I258
I563
I564
I565
I254
I177
I179
I182
I181
I180
I185
I184
I183
I186
I188
I187
I599
I598
I614
I192
I574
I269
I555
I268
I613
I190
I194
I193
I587
I198
I575
SPACING
POWER
SWITCHNODE
POWER
SWITCHNODE
POWER
POWER
SWITCHNODE
SWITCHNODE
POWER
POWER
SWITCHNODE
SWITCHNODE
POWER
POWER
SWITCHNODE
SWITCHNODE
POWER
SWITCHNODE
POWER
SWITCHNODE
POWER
POWER
SWITCHNODE
SWITCHNODE
POWER
SWITCHNODE
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
I219
I222
VOLTAGE
1.5V
1.5V
1.5V
1.5V
3.3V
5V
1.1V
1.1V
3.4V
1.05V
1.05V
1.5V
1.8V
VR_CPU_PHASE1
VR_CPU_PHASE2
VR_CPU_PHASE3
VR_CPU_PHASE4
P3V3S5_REG_PHASE
P5VS3_REG_PHASE
VTT_REG_PHASE1
VTT_REG_PHASE2
P3V42G3H_SW
PCHCORE_REG_PHASE
P1V05_S5_REG_PHASE
DDR_REG_PHASE
P1V8_REG_PHASE
65
I576
I611
65
66
I612
69
69
I223
I225
67
67
I226
I224
71
68
POWER
POWER
70
I557
70
12V
12V
12V
12V
12V
12V
12V
12V
12V
PP12V_S0_CPUVTT_FLTD
PP12V_LCD
77
PP12V_LCD_CONN
77
PP12V_S0
6 63
PP12V_S0_CPU_FLTRD 64 65
PP12V_S0_FAN0_L
52 92
PP12V_S0_FAN1_L
52 92
PP12V_S0_FAN2_L
53 92
12V
12V
12V
PP12V_G3H
PP12V_G3H_R
PP12V_S5
P12V_S0_FW
P12V_S0_FW_CL
P12V_S0_FW_D
P12V_S0_FW_R
FW_PORT0_VP
FW_PORT0_VP_F
PPVP_FW_PHY_CPS
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
12V
12V
1.1V
1.1V
1.1V
1.1V
1.1V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
I230
28 30
I550
28 31
28 30
I235
I273
I274
6 71
I265
I266
I262
I610
41
I257
40 41
I207
I209
44
I212
I211
PPVCORE_S0_CPU
6
PPVCORE_S0_CPU_REG1
PPVCORE_S0_CPU_REG2
PPVCORE_S0_CPU_REG3
PPVCORE_S0_CPU_REG4
I210
65
65
I215
I214
65
66
17 22
PP1V05_S0_PCH_VCCADPLLB_F
PP1V05_S0_PCH_VCCAPLL_EXP 22 24
PP1V05_S0_PCH_VCCAPLL_FDI 22 24
PP1V05_S0_PCH_VCCAPLL_SATA 22 24
22 24
PP1V05_S0_PCH_VCCA_CLK_F 24
PP1V05_S0_CIO_VDD1P0_DP
PP1V05_S0_CIO_VDD1P0_DP_PLL
I231
I606
I609
I577
I234
I238
POWER
POWER
1.1V
PPVTT_S0_CPU
6 49
1.5V
1.5V
PPVTT_S0_DDR
PP0V75_S0
PP1V2_S5_ENET
PP1V5_S3
PP1V5_CPU_MEM
I603
I245
I242
I536
I243
I601
I600
37
I246
I244
26
I588
26
6 49
I247
I248
I251
I203
I204
I206
I208
I162
I164
I165
POWER
POWER
POWER
POWER
3.3V
3.3V
PP3V3_S3_BT_FLT
PP3V3_S3_SDCARD_FLT
POWER
POWER
3.3V
PP3V3_S3_WM_FLT
POWER
POWER
3.3V
PP3V3_S5
I167
44
I168
44
I169
44
I170
I566
POWER
POWER
POWER
POWER
3.3V
3.3V
PPVTT_S3_DDR_BUF
PPV_S0_MXM_PWRSRC
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
SNS_DIFF
SNS_DIFF
THERMAL
THERMAL
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
THERMAL
SNS_DIFF
SNS_DIFF
THERMAL
THERMAL
SNS_DIFF
THERMAL
VR_CPU_ISNS1_P
VR_CPU_ISNS1_N
VR_CPU_ISNS1_R_P
VR_CPU_ISNS1_R_N
VR_CPU_ISNS2_P
VR_CPU_ISNS2_N
VR_CPU_ISNS2_R_P
VR_CPU_ISNS2_R_N
VR_CPU_ISNS3_P
VR_CPU_ISNS3_N
VR_CPU_ISNS3_R_P
VR_CPU_ISNS3_R_N
VR_CPU_ISNS4_P
VR_CPU_ISNS4_N
VR_CPU_ISNS4_R_P
VR_CPU_ISNS4_R_N
VR_CPU_ISNS1_XW_P
VR_CPU_ISNS1_XW_N
VR_CPU_ISNS2_XW_P
VR_CPU_ISNS2_XW_N
VR_CPU_ISNS3_XW_P
VR_CPU_ISNS3_XW_N
VR_CPU_ISNS4_XW_P
VR_CPU_ISNS4_XW_N
64 65
I338
64 65
I339
64
I340
I341
64
I342
64 65
I343
I344
64 65
64
I345
I346
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
3.3V
3.3V
3.3V
3.3V
3.3V
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
64
64 65
64 65
I347
I348
I349
64
I350
64
I353
64 66
I352
I351
64 66
64
64
65
65
I354
I356
I355
I357
I358
65
I359
I360
65
I363
65
I361
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
SWITCHNODE
SWITCHNODE
VR_CPU_PH1_SNUB
VR_CPU_PH2_SNUB
VR_CPU_PH3_SNUB
VR_CPU_PH4_SNUB
VR_CPU_PWM1
VR_CPU_PWM2
VR_CPU_PWM2_R
VR_CPU_PWM3
VR_CPU_PWM3_R
VR_CPU_PWM4
VR_CPU_PWM4_R
VR_CPU_REF
VR_CPU_SS
VR_CPU_TCOMP
VR_CPU_TM
VR_CPU_BOOT1_RC
VR_CPU_BOOT2_RC
VR_CPU_BOOT3_RC
VR_CPU_COMP
VR_CPU_COMP_R
VR_CPU_COMP_RC
VR_CPU_DAC
VR_CPU_DRV1_BOOT
VR_CPU_DRV1_GDSEL
VR_CPU_DRV1_LGATE
VR_CPU_DRV1_UGATE
65
65
65
66
I437
I595
I439
I596
64 65
I443
I442
64
I441
64 65
I444
64 65
66
I365
I367
I368
70
50
PPVOUT_S0_PCH_DCPSST
22
PPVOUT_S5_PCH_DCPSUS
22
PPVOUT_S5_PCH_DCPSUSBYP 22
PPVOUT_G3_PCH_DCPRTC
22
PPVOUT_SO_PCH_VCCRTC_NCTF
64
64
64
I449
I450
I452
65
I451
I453
65
I455
64
I454
65
I371
I374
64
64
65
65
65
I376
VR_CPU_DRV2_BOOT
65
VR_CPU_DRV2_GDSEL
VR_CPU_DRV2_LGATE
65
SWITCHNODE
VR_CPU_DRV2_UGATE
65
VR_CPU_DRV3_BOOT
VR_CPU_DRV3_GDSEL
VR_CPU_DRV3_LGATE
65
VR_CTL
SWITCHNODE
POWER
POWER
POWER
POWER
1.5V
1.5V
PP1V5_FW_VDDA
39
POWER
POWER
POWER
POWER
1.5V
1.8V
PP1V8_S0
PP1V8_S0_CPU
POWER
POWER
POWER
POWER
1.96V
1.96V
PP1V96_FW_PLLVDD
PP1V95_FW_FWPHY
22 24
I252
I253
I255
I545
I546
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
P1V8_REG_POR
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL
SWITCHNODE
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
I458
I457
I459
I461
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
PPVBATT_G3_RTC
PPVBATT_G3_RTC_R
PP3V3_AUDIO_SPDIF_JACK
PP3V3_FW_AVDD
PP3V3_FW_ESD
PP3V3_FW_PLLVDD
PP3V3_FW_VDDA
PP3V3_G3_RTC
PP_ENET_CTRL12
I377
27
POWER
POWER
3.4V
POWER
POWER
3.3V
POWER
POWER
POWER
POWER
3.42V
3.42V
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
4.5V
4.5V
PP3V3_G3H_SMC_AVCC
PP3V3_G3H_AVREF_SMC
PP3V42_G3H
PP3V42_G3H_R
4V5_REG_IN
PP4V5_AUDIO_ANALOG
39
I578
41
39
I579
39
I56
I57
18 22 24 27
I172
37
45
I153
I154
45 46
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
SNS_DIFF
CPU_VCC_PKG_SENSE_P
CPU_VCC_PKG_SENSE_N
CPU_VTTSENSE_P
CPU_VTTSENSE_N
CPU_VTTSENSE_R_P
CPU_VTTSENSE_R_N
VR_CPU_VSEN
VR_CPU_RGND
VR_CPU_VSNS_R_N
VR_CPU_VSNS_R_P
VR_CPU_VSNS_XW_P
VR_CPU_VSNS_XW_N
13 49 64
I382
13 64
13 49 67
I384
13 67
I387
67
I388
I389
POWER
POWER
POWER
POWER
POWER
POWER
65
67
I390
I393
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
SWITCHNODE
SWITCHNODE
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
PP5V_USB2_PORT0
PP5V_USB2_PORT0_F
PP5V_USB2_PORT1
PP5V_USB2_PORT1_F
PP5V_USB2_PORT2
PP5V_USB2_PORT2_F
PP5V_USB2_PORT3
PP5V_USB2_PORT3_F
DDR_REG_PGND
DDR_REG_CSGND
65
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
SWITCHNODE
VR_CTL_PHY
VR_CTL_PHY
SWITCHNODE
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CPU_DRV4_BOOT
VR_CPU_DRV4_GDSEL
VR_CPU_DRV4_LGATE
66
VR_CPU_DRV4_UGATE
66
VR_CPU_FAN
VR_CPU_FB
VR_CPU_FB_R
VR_CPU_FS
VR_CPU_IMON
64
I391
64
I394
I396
64
I395
64
64
I397
I398
I400
I403
I402
55
55
I401
I404
I406
I405
6 92
64
70
70
70
70
P3V3S5_REG_BOOT
P3V3S5_REG_BOOT_R
P3V3S5_REG_FB
P3V3S5_REG_ISEN
P3V3S5_REG_LGATE
P3V3S5_REG_OCSET
I462
I463
I466
SWITCHNODE
P3V3S5_REG_UGATE
P3V3S5_REG_SNUB
P5VS3_REG_BOOT
P5VS3_REG_FB
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
SWITCHNODE
VR_CTL
P5VS3_REG_ISEN
P5VS3_REG_LGATE
P5VS3_REG_OCSET
VR_CTL_PHY
SWITCHNODE
P5VS3_REG_UGATE
69
69
69
69
69
69
69
69
69
69
69
69
69
69
VR VID NET PROPERTIES

NET_TYPE
65
66
66
64
SPACING
I491
I492
I521
I522
I523
I524
I525
I526
I554
VID_PHY
VID_PHY
VR_CTL
VR_CTL
VID_PHY
VID_PHY
VR_CTL
VR_CTL
VID_PHY
VID_PHY
VR_CTL
VR_CTL
VID_PHY
VID_PHY
VR_CTL
VR_CTL
VID_PHY
VR_CTL
PULL-UP STUB
< 1-INCH
VID LENGTH SKEW < 1-INCH
VID LENGTH RANGE< 1 TO 15-INCH
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
CPU_VID<7>
CPU_PSI_L
13 16 64
13 16 64
13 16 64
13 16 64
13 16 64
13 16 64
13 16 64
13 16 64
13 16 64
64
64
64
VR_CPU_IOUT_PD
PCHCORE_REG_UGATE
PCHCORE_REG_LGATE
PCHCORE_REG_VFB
49 64
64
68
68
68
PCHCORE_REG_TON 68
PCHCORE_REG_TRIP 68
PCHCORE_REG_BOOT 68
PCHCORE_REG_BOOT_R 68
6
71
PP5V_S0_SATA_FET
42
PP5V_S3
6
PP5V_S3_DDR_REG_V5FILT 70
PP5V_S3_CAMERA_FLT
44
PP5V_S3_IR_FLT
44
5V
5V
5V
5V
5V
5V
5V
5V
VR_CPU_DRV3_UGATE
70
64
I399
I594
5V
5V
5V
5V
5V
5V
5V
PP5V_S5
PP5V_CPUVTT_VR
I380
I383
59
PP5V_S0
PP5V_S0_PCH_V5REF
5V
5V
5V
SWITCHNODE
70
70
65
27
5V
5V
5V
VREFMARGIN_DIMMA_P5V
VREFMARGIN_DIMMB_P5V
VR_CTL_PHY
70
70
VR_CTL_PHY
VR_CTL_PHY
PHYSICAL
6
6 49
SWITCHNODE
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
65
VR_CTL
SWITCHNODE
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
DDR_REG_CS
DDR_REG_FB
DDR_REG_LGATE
DDR_REG_UGATE
DDR_REG_BOOT
DDR_REG_BOOT_R
DDR_REG_VDDQSNS
DDR_REG_VTTSNS
64
VR_CTL_PHY
VR_CTL
VR_CTL
SWITCHNODE
64
64
VR_CTL_PHY
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
64 66
I464
VR_CTL
VR_CTL_PHY
64
66
VR_CTL_PHY
SPACING
PHYSICAL
65
VTT_REG_BOOT1
VTT_REG_BOOT2
VTT_REG_COMP
VTT_REG_FB
VTT_REG_FS
VTT_REG_ICOMP
VTT_REG_IREF
67
67
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
VID_PHY
39_OHM_SE
67
67
67
67
67
SPACING_RULE_SET
67
VR_CTL
LAYER
WEIGHT
0.2MM
22 24
I409
I408
I407
I410
I411
I412
I413
I414
28
28
I415
I416
6
22 24
I418
67
I417
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
VTT_REG_ISUM
VTT_REG_LGATE1
VTT_REG_LGATE2
VTT_REG_OCSET
VTT_OFST
VTT_REG_REF
VTT_REG_RGND
VTT_SEL
VTT_REG_UGATE2
VTT_REG_UGATE1
VTT_REG_PH1_SNUB
VTT_REG_PH2_SNUB
VTT_REG_VSEN
VR_CTL_PHY
VR_CTL
P1V05S5_REG_VFB
71
VR_CTL_PHY
VR_CTL
71
VR_CTL_PHY
VR_CTL
P3V42G3H_BOOST
P3V42G3H_FB
VR_CTL_PHY
VR_CTL_PHY
VR_CTL
SWITCHNODE
VR_CTL_PHY
SWITCHNODE
I249
I195
POWER
PP3V3_S0_PCH_VCCA_DAC 17 22
PP3V3_S0_PCH_VCCA_DAC_F
PP3V3_S0_TSENS_R
51
PP3V3_S3
6 92
THERMAL
SNS_DIFF
I419
I250
I205
POWER
I163
3.3V
3.3V
3.3V
3.3V
I152
I236
POWER
POWER
POWER
I161
I151
POWER
POWER
POWER
POWER
33
36 37
I59
PPVTT_S0
POWER
POWER
I159
17 22
1.1V
POWER
POWER
I58
POWER
POWER
POWER
POWER
POWER
PP3V3_S0M
PP3V3_MINI
PP3V3_ENET
I171
PP1V05_SM_SOURCE
72
PP1V05_S0
6
PP1V05_S0_CK505_F
26
PP1V05_S0_PCH_VCCADPLLA_F
POWER
POWER
POWER
POWER
3.3V
3.3V
3.3V
THERMAL
SNS_DIFF
NET_TYPE
SPACING
41
PP12V_S3
PP12V_S3_WM_FLT
PP1V5_S0
PP1V5_S0_CK505_F
PP1V5_S0_CK505_R
POWER
SNS_DIFF
I278
I370
I263
POWER
1.5V
1.5V
1.5V
POWER
PHYSICAL
SPACING
71
6
POWER
POWER
I160
I573
I237
I239
POWER
I158
66
1.2V
I157
80
I572
PP1V05_S5
PP1V05_SM
POWER
80
61
I571
1.05V
1.05V
POWER
I156
I570
POWER
0.75V
I155
80
I569
POWER
0.75V
POWER
POWER
6
26
I568
PP1V05_SM_PCH_LAN
POWER
POWER
POWER
PP3V3_S0
PP3V3_S0_CK505_F
PP3V3_S0_DPAUX
PP3V3_S0_DPFUSE
PP3V3_S0_DPPWR
PP3V3_S0_HS_F
57 58 60
1.05V
POWER
POWER
POWER
PHYSICAL
I567
POWER
POWER
POWER
POWER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
28 31
POWER
POWER
POWER
POWER
NET_TYPE
VOLTAGE
I166
I260
POWER
POWER
POWER
71
1.5V
1.5V
1.5V
1.5V
12V
12V
12V
12V
12V
12V
12V
I221
65
SPACING
VR CTRL NET PROPERTIES
NET_TYPE
NET_TYPE
PHYSICAL
VR CTRL NET PROPERTIES
SENSING NET PROPERTIES
POWER NET PROPERTIES
I597
43
43
43
I607
43
I608
67
67
67
67
67
67
67
67
67
67
67
71
43
43
43
43
70
PAGE TITLE
70
39
POWER CONSTRAINTS
DRAWING NUMBER
39 40
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
107 OF 110
SHEET
89 OF 92
PAGE TITLE
BLANK PAGE
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
108 OF 110
SHEET
90 OF 92
PM NET PROPERTIES
(PM, RESET, EN, PGOOD)
NET_TYPE
SPACING
PHYSICAL
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PM
2:1_SPACING
PM_VTT
PM_VTT
2:1_SPACING
PM_VTT
3:1_SPACING
PM_VTT
GND
DEFAULT
PM
GND
DEFAULT
PM
I2
PM_VTT
I1
PM
I4
PM
I3
PM
I5
PM
I7
PM
I6
PLT_RESET_L
PLT_RESET_LS1V1_L
PM_ACDC_PS_ON
PM_BATLOW_L
PM_CLK32K_SUSCLK
PM_CLK32K_SUSCLK_R
PM_CLKRUN_L
20 27
I82
11
I81
I84
15 19 45
I83
9 45 85
I85
9 19 85
I86
15 19 45 47
I87
PM
I10
PM
I9
PM
I12
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
PM_LAN_PWRGD
I88
11 46
I89
11 46
I90
15 19
I91
PM_VTT
I117
PM
I123
FSB_CPURSTOUT_L
USB_HUB_RESET_L
11 25
I92
I93
34 35
I94
I95
I97
I96
PM_VTT
I25
PM
I24
PM
I27
PM
I26
PM
I28
PM
I30
PM
I29
PM
I31
PM
I33
PM
I32
PM
I35
PM
I34
PM
I36
PM
I38
PM
I37
PM
I40
PM
I120
PM
I119
PM
I118
PM
I39
PM
I41
PM
I43
PM_VTT
I42
PM
I122
PM
I45
PM
I44
PM_VTT
I46
PM
I48
PM
I47
PM_VTT
I50
PM
I49
PM
I51
PM
I53
PM
I52
PM
I54
PM
I56
PM
I55
PM
I58
PM
I57
PM
I59
PM
I61
PM
I60
PM
I63
PM
I62
PM
I64
PM
I66
PM
I65
PM
I67
PM
I68
PM
I69
PM
I71
PM
I70
PM
I72
PM
I74
PM
I73
PM
I76
PM
I75
PM
I77
PM
I79
PM
I78
PM
I80
PM_MEM_PWRGD
11 19
PM_ME_PWRGD
19 63
PM_ME_S0_EN_G
72
PM_ME_S0_EN_G1
72
PM_ME_S0_EN_R
72
PM_MXM_PGOOD
63 74
PM_PCH_PWRGD
19 63
PM_PGOOD_DDRREG_S3
5 62 70
PM_PGOOD_PVCORE_CPU
5 26 63 64
PM_PWRBTN_L
19 25 45
PM_RSMRST_L
45 62
PM_RSMRST_PCH_L
19 62
PM_SLP_M_L
5 19 62
PM_SLP_M_R
PM_SLP_S3_L
5 19 32 33
PM_SLP_S3_L_AND_S0_RDY
PM_SLP_S4_1_L
PM_SLP_S4_2_L
PM_SLP_S4_3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SUS_PWR_ACK
PM_SYNC
SDCARD_PLT_RST_L
PM_SYSRST_L
PM_SYS_PWRGD
PM_THRMTRIP_L
RSMRST_PWRGD
RTC_RESET_L
CPU_PWRGD
CPU_RESET_L
PGOOD_1V05ME_G1
PGOOD_1V05ME_G2
PGOOD_1V8_S0_G1
PGOOD_1V8_S0_G2
PGOOD_CPU_GFX_DDR
PGOOD_P12V_S3
PGOOD_P1V05_ME_S5
PGOOD_P1V5_S0
PGOOD_P1V8_S0
PGOOD_P3V3_ME
PGOOD_P3V3_S0
PGOOD_P3V3_S3
PGOOD_P5V_S0
PGOOD_PCH_AND_P1V8
PGOOD_PCH_S0
PGOOD_SYSPWROK
PGOOD_SYSPWROK_R
RTC_RESET_L
P12V_S3_EN
P1V05_ME_SM_EN
P1V5_S0_EN
P3V3ME_EN
P3V3S0_EN
P3V3S3_EN
P5VS0_EN
P5VS3_EN
PCHCORE_REG_EN
PCHCORE_REG_PGOOD
PEG_RESET_L
SDCARD_RESET
I98
I100
I99
I102
I101
I103
I104
SPACING
PM
PM
PM
PM
PM
PM_VTT
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM_VTT
PM_VTT
PM_VTT
NET PHYSICAL FOR NC NETS
NET_TYPE
PHYSICAL
4V5_REG_EN
ALL_SYS_PWRGD_R
ALL_SYS_PWRGD_SMC
CK505_27MHZ_EN
CPUVTT_REG_EN
CPUVTT_REG_PGOOD
CPU_MEM_RESET_L
DDRVTT_EN
DEBUG_RESET_L
FWPHY_RESET_L
FWXIO_SNOOP_EN
FW_RESET_L
GFX_VR_EN
GFX_VR_PGOOD
LAN_RESET_L
MEM_RESET_L
MINI_RESET_L
SMC_DELAYED_PWRGD
SMC_LRESET_L
SMC_RESET_L
T28_RESET_L
XDP_CPUPWRGD
XDP_DBRESET_L
XDP_PWRGD
REMOVE WHEN CHECKPLUS IS FIXED
55
6 25 32 63
45 63
26
NET_TYPE
62 67
PHYSICAL
SPACING
11 62 63 67
11 32
PCIE GRAPHICS
32 62 70
27 47
39
39
27 39
I105
PCIE_85D
PCIE
I106
PCIE_85D
PCIE
I107
PCIE_85D
PCIE
I108
PCIE_85D
PCIE
I109
PCIE_85D
PCIE
I110
PCIE_85D
PCIE
NC_PCIE_CLK100M_EXCARD_N
NC_PCIE_CLK100M_EXCARD_P
NC_PCIE_EXCARD_D2R_N
NC_PCIE_EXCARD_D2R_P
NC_PCIE_EXCARD_R2D_C_N
NC_PCIE_EXCARD_R2D_C_P
27 36
30 31 32
I112
27 33
I111
46 63
I114
27 45
I113
45 46 47
I116
I115
11 25
NO_TEST=TRUE
USB_90D
USB
NO_TEST=TRUE
USB_90D
USB_90D
USB
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_USB_EXCARD_N
NC_USB_EXCARD_P
NC_USB_EXTE_N
NC_USB_EXTE_P
NC_USB_TPAD_N
NC_USB_TPAD_P
11 25 27
25
37 46 62 63
19 62
19 45 46
5 19
19 32
19 45
19
11 19
27 44
19 27 45
19 32 63
11 21 46
45 63
18 91
11 21 25
11 27
63
63
63
63
63
72
63
72
48 63 72
34 72
62 72
63
63
63
63
18 91
62 72
62 72
62 72
62 72
62 72
62 72
62 72
62 69
62 68
5 62 63 68
9 27
21 25 44 92
PAGE TITLE
PM RESETS ENABLES PGOOD CONST

DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
109 OF 110
SHEET
91 OF 92
FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

J4700 USB CAMERA
IN
PP5V_S3_CAMERA
85 44
IN
85 44
IN
USB_CAMERA_L_P
USB_CAMERA_L_N
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
J5520 ANALOG LCD TEMP SENSOR

88 51
IN
88 51
IN
SNS_LCD_P
SNS_LCD_N
59
IN
FUNC_TEST=TRUE
59
IN
59
IN
1 PP5V_S3_REG Testpoint near J4700

2 Ground Testpoints near J4700
IN
85 44
IN
91 44 25 21
IN
USB_SDCARD_L_P
USB_SDCARD_L_N
SDCARD_RESET
J5521 AMBIENT TEMP SENSOR
FUNC_TEST=TRUE
88 51
IN
FUNC_TEST=TRUE
88 51
IN
85 44
IN
IN
SNS_AMB_P
SNS_AMB_N
85 59 58
IN
FUNC_TEST=TRUE
85 59 58
IN
85 59 57
IN
85 59 57
IN
USB_BT_L_P
USB_BT_L_N
FUNC_TEST=TRUE
85 59 58
IN
FUNC_TEST=TRUE
85 59 58
IN
85 59 57
IN
85 59 57
IN
J5551 ODD TEMP SENSOR
FUNC_TEST=TRUE
FUNC_TEST=TRUE
1 PP3V3_S3 Testpoint near J4720

88 51
IN
88 51
IN
SNS_ODD_P
SNS_ODD_N
GND
16 TPS
FUNC_TEST=TRUE
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=16
FUNC_TEST=TRUE
FUNC_TEST=TRUE
J6602 AUDIO RIGHT SPEAKER
FUNC_TEST=TRUE
FUNC_TEST=TRUE
1 PP3V3_S3 Testpoint near J4750

J4720 USB BLUETOOTH
85 44
AUD_MIC_IN1_N_CONN
GND_AUDIO_MIC1_CONN
AUD_MIC_IN1_P_CONN
1 Ground Testpoint near J6601
J4750 USB CARD READER

85 44
J6601 AUDIO MICROPHONE
FUNC_TEST=TRUE
AUD_SPKR_OUTLO2R_POUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO2R_NOUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO1R_POUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO1R_NOUTFUNC_TEST=TRUE
89 6
IN
PP3V3_S3
2 TPS
69 6
IN
PP5V_S3_REG
2 TPS
89 6
IN
PP5V_S0
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=2
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
J6603 AUDIO LEFT SPEAKER

AUD_SPKR_OUTLO2L_POUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO2L_NOUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO1L_POUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO1L_NOUTFUNC_TEST=TRUE
J4780 IR BOARD
85 44
IN
85 44
IN
USB_IR_L_P
USB_IR_L_N
FUNC_TEST=TRUE
J5600 ODD FAN
FUNC_TEST=TRUE
1 PP5V_S3_REG Testpoint near J4780

52
IN
52
IN
89 52
IN
52
IN
FAN_0_PWR_L
FAN_TACH0_L
PP12V_S0_FAN0_L
FAN_0_GND
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
J5700 CPU FAN

J4520 SATA ODD (HIGH SPEED)
84 42
84 42
IN
IN
84 42
IN
84 42
IN
45 42
IN
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
SMC_ODD_DETECT
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
53
IN
53
IN
89 53
IN
53
IN
FUNC_TEST=TRUE
52
IN
FAN_1_PWR_L
FAN_TACH1_L
PP12V_S0_FAN1_L
FAN_1_GND
88 51
IN
HDD_OOB_TEMP_FILT
88 51
IN
88 51
IN
SNS_SKIN_P
SNS_SKIN_N
52
IN
52
IN
89 52
IN
J4510 SATA HDD (HIGH SPEED)

84 42
IN
84 42
IN
84 42
IN
84 42
IN
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
J5550 HDD TEMP SENSOR
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
J5601 HD FAN
FUNC_TEST=TRUE
1 PP5V_S0 Testpoint near J4520

FAN_2_PWR_L
FAN_TACH2_L
PP12V_S0_FAN2_L
FAN_2_GND
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
J5560 SKIN TEMP SENSOR
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PAGE TITLE
K22/K23 ICT/FCT
DRAWING NUMBER
Apple Inc.
051-8600

A.0.0
SIZE
REVISION
BRANCH
PAGE
110 OF 110
SHEET
92 OF 92

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

System Block Diagram

Power Block Diagram

PROTO 0 DEBUG LEDS

Power Conn / Alias

UNUSED SIGNAL ALIAS

CPU DDR3 INTERFACES

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

CPU NON-GFX DECOUPLING

CPU/PCH GFX DECOUPLING

EXTENDED DEBUG PORT(XDP)

DDR3 VREF MARGINING

DDR3 SO-DIMMs 0 & 2

DDR3 SO-DIMM CONNECTOR B

DDR3 SUPPORT AND BITSWAPS

PCI-E Wireless Connector

ETHERNET (CAESAR II)

FireWire LLC/PHY (XIO2213B)

FW: 1394B MISC

EXTERNAL USB CONNECTORS

Internal USB Connections

LPC+SPI Debug Connector

LAST_MODIFIED=Thu Apr 15 11:21:16 2010

CPU POWER SENSE

GRAPHICS / DIMM POWER SENSE

AUDIO: Tweeter Amp 1

AUDIO: Woofer Amp

Audio: MLB to I/O Conn.

POWER SEQUENCING ENABLES

POWER SEQUENCING PGOOD

VREG: CPU CORE - PHASES 1-3

VREG: CPU CORE - PHASE 4

CPU VTT REGULATOR

IBEX PEAK CORE

5V_S3 / 3V3_S5 VREGS

1.5V / 1.8V VREGS

MXM PCIe, DP & Power

MXM PCIE CAPS

Display: Int DP Connector

Display: BiDiVi Mux1

Display: Ext DP Connector

Display: BiDiVi Support

K60/K61 RULE DEFINITIONS

IBEX PEAK CONSTRAINTS

PM RESETS ENABLES PGOOD CONST

NOTICE OF PROPRIETARY PROPERTY:

X16 PCI-E GEN2

TEMP, CURRENT SENSE

CONTROL LOGIC FROM SMC

USB 96MHZ/PCIE 100MHZ/SATA 100MHZ/BCLK 133MHZ.

J5600, J5601, J5700

FAN CONN AND CONTROL

SATA 2.0 3GHZ.

X1 PCIE GEN1 LANE 2.5GBITPS

X1 PCIE GEN1 LANE 2.5GBITPS

DIGITAL VIDEO OUTPUT

DIGITAL VIDEO OUTPUT

DIGITAL VIDEO OUTPUT