The document discusses the operation of a 6-transistor SRAM cell. The SRAM cell contains a pair of cross-coupled inverters to store true and complementary data values. An access transistor is used for each bit line as a read/write port. The word line is used to read from or write to the cell by raising the appropriate word line and driving the bit lines. Reading a large SRAM array can be slow due to the capacitance of the cells sharing the bit lines.
The document discusses the operation of a 6-transistor SRAM cell. The SRAM cell contains a pair of cross-coupled inverters to store true and complementary data values. An access transistor is used for each bit line as a read/write port. The word line is used to read from or write to the cell by raising the appropriate word line and driving the bit lines. Reading a large SRAM array can be slow due to the capacitance of the cells sharing the bit lines.
The document discusses the operation of a 6-transistor SRAM cell. The SRAM cell contains a pair of cross-coupled inverters to store true and complementary data values. An access transistor is used for each bit line as a read/write port. The word line is used to read from or write to the cell by raising the appropriate word line and driving the bit lines. Reading a large SRAM array can be slow due to the capacitance of the cells sharing the bit lines.
The document discusses the operation of a 6-transistor SRAM cell. The SRAM cell contains a pair of cross-coupled inverters to store true and complementary data values. An access transistor is used for each bit line as a read/write port. The word line is used to read from or write to the cell by raising the appropriate word line and driving the bit lines. Reading a large SRAM array can be slow due to the capacitance of the cells sharing the bit lines.
and both true and complementary bit-lines. Figure 2.
2 shows the circuit diagram of a
6T SRAM.
The cell contains a pair of cross-coupled inverters and an access-
transistor for each bit-line as combination read/write port. True and complementary versions of the data are stored on the cross-coupled inverters. If the data is disturbed slightly, positive feedback around the loop will restore it to VDD or GND. The wordline in inserted to read or to write the cell.
Figure 2.2: Six-transistor SRAM cell.
2.2 SRAM Cell Operation:
SRAM operation can be divided into two phases, phase 1 - 1 and phase 2 - 2, which can be generated from clk and its complement clkb signals. Assume that the SRAM is pre-charged in phase 2. In phase 1, the SRAM is written, or read by raising the appropriate word line and either driving the bit lines to the value that should be written or leaving the bit lines floating and observing which one is pull down. The row and column are selected by row or column decoders. Reading a large SRAM array can be slow due the capacitance of the SRAM cells which are sharing the same bit line.
