International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org

Volume 4, Issue 4, July - August 2015

ISSN 2278-6856

Design and implementation of GDI based

compressor
A.Rajitha1, Mrs. Rani Rajesh2, Mrs. C.V.Keerthilatha3
1

Dept. of Electronics & Communication,

Asso. Professor VLSI Systems, Dept. of Electronics & Communication,

3

Assistant Professor, Dept. of Electronics & Communication,

Abstract
Multiplier is one of the most commonly used circuits in the
digital devices. Multiplication is one of the basic functions
used in digital signal processing. Most high performance DSP
systems rely on hardware multiplication to achieve high data
throughput. In this paper we are implementing Gate Diffusion
Input (GDI) based Compressor. And Here we compare CMOS
with GDI 5-3 compressor & design and implementation of 154 compressor. Here the simulation results give better
performance in terms of power and delay. The simulations are
run in Modelsim 10.1 and schematics and layouts are
generated in DSCH & Microwind tools.

Keywords: CMOS, GDI, Low Power, Power, compressor.

1. Introduction
Multiplier is one of the most commonly used circuits in the
digital devices. Multiplication is one of the basic functions used
in digital signal processing. Most high performance DSP
systems rely on hardware multiplication to achieve high data
throughput. The various types of multipliers available depending
upon the application in which they are used. Full adder is the
main block of power dissipation in multiplier. So reducing the
power dissipation of full adder ultimately reduces the power
dissipation of multiplier. A compressor is simply an adder
circuit. It takes as inputs a number of equally-weighted bits,
adds them, and produces as output the sum, in the form of a bit
with the same weight as the inputs and one or more bits that
have a value greater than that of the inputs. Compressors are
commonly used to reduce a large number of inputs to a smaller
number, such as in a multiplier, where they are used to reduce
the many partial products to a final summed value. The
reduction in the number of individual bits representing the value
leads to the name compressor.
For higher order multiplications, a huge number of adders or
compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits
per decade. These adders are called compressors. Compressors
are major components of the present multiplier designs. In
multipliers maximum amount of power is consumed during the
partial product addition. Using compressor adders, that can add
four, five , six or seven bits at a time, the number of full adders
and half adders can be reduced and thus area and power
consumed also gets reduced. There are many compressors
available e.g. 3-2 compressors, 4-2 compressor, 5-2 compressor,
5-3 compressors in many applications like partial product
summation in multiplier. In this project Full adder 5-3
compressor is used. Full adder 5-3 compressor is faster and
consumes less power. For such operations using small

Volume 4, Issue 4, July August 2015

compressors like 5-2 and 7-2 would not give better performance
in terms of speed and power. To overcome its drawback Gate
diffusion input technology is used. In this paper, conventional

5-3 compressor is presented in section II. In section III, a

proposed 5-3 compressor is presented. Section IV shows
the design of 15-4 compressor. Section V consists of
simulation results and section VI has conclusion.

2. CONVENTIONAL 5-3 COMPRESSOR

The conventional 5-3 compressor architecture is showed
in fig 1.Conventional 5-3 compressor has five inputs and
three outputs. It will compress five partial products into
three outputs.
It has five XOR gates and two MUX and one AND gate.
In order to generate O0 three XOR gates are required.
XOR gate has more critical delay than any other gate. So
conventional 5-3 compressor has more delay and
consumes more power. Further optimization of this
compressor is possible. The proposed design gives better
performance than conventional structure.

Fig. 1.Conventional 5-3 compressor

3. PROPOSED 5-3 COMPRESSOR

Conventional 5-3 compressor has five XOR gates to generate
the output. The circuit has been rearranged so that the use of
XOR gates is reduced. Proposed 5-3 compressor is designed
with the help of three 4-1 MUX. Three partial products from
partial product array are given as input and two partial
products are given as control signal for multiplexer. D and E
are given as control signals which are readily available. So
generation of output (O1, O2 and O3) is faster. As we know
multiplexer is faster and consumes less power because only

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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org
Volume 4, Issue 4, July - August 2015
one input is active at any instant of time based on control
signals(D&E).This idea is used to design a proposed 5-3
compressor.
The equation of proposed 5-3 compressor is given below.
Based on the modified equation new 5-3 architecture is
proposed. Proposed 5-3 compressor is shown in the fig 2.
Truth table of the 5-3 compressor is given in table 1
Conventional 5-3 compressor has five XOR gates to generate
the output. The circuit has been rearranged so that the use of
XOR gates is reduced. Proposed 5-3 compressor is designed
with the help of three 4-1 MUX. Three partial products from
partial product array are given as input and two partial
products are given as control signal for multiplexer. D and E
are given as control signals which are readily available. So
generation of output (O1, O2 and O3) is faster. As we know
multiplexer is faster and consumes less power because only
one input is active at any instant of time based on control
signals(D&E).This idea is used to design a proposed 5-3
compressor.
The equation of proposed 5-3 compressor is given below.
Based on the modified equation new 5-3 architecture is
proposed. Proposed 5-3 compressor is shown in the fig 2.
Truth table of the 5-3 compressor is given in table 1

Fig. 2. Proposed 5-3 compressor

Volume 4, Issue 4, July August 2015

ISSN 2278-6856

TABLE 1 TRUTH TABLE OF 5-3 COMPRESSOR

Proposed 5-3 compressor will count the number of ones in the

given five inputs and generate output according to the inputs.
The proposed 5-3 compressor is faster because based on control
signals it needs to calculate only one input e.g. for D=E=0,
O1=A^B^C;
But
in
conventional
5-3
compressor
O0=X1^X2^X3^X4^X5;

4. DESIGN OF 15-4 COMPRESSOR

4.1 GATE DIFFUSION INPUT
1). The GDI (Gate Diffusion Input) method is based on
the use of simple cell. At first fleeting look, the basic cell
reminds one of the standard CMOS inverter, however
there are a few important differences. The GDI (Gate
Diffusion Gate) cell contains three inputs: (common gate
input of NMOS and PMOS), P (input to the source/drain
of PMOS), and N (input to the source/drain of NMOS).
2). Bulks of both NMOS and PMOS are connected to N or
P (respectively), so it can be arbitrarily biased at contrast
with a CMOS inverter.

Figure: 4.1(a) Gate Diffusion Input Basic Cell

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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org
Volume 4, Issue 4, July - August 2015
It must be remarked that not all of the functions are
possible in standard p-well CMOS process but can be
successfully implemented in twin-well CMOS or silicon
on insulator (SOI) technologies. How
a simple
change of the input configuration of the simple GDI (Gate
Diffusion Input) cell corresponds to very different Boolean
functions. Most of these functions are complex (6-12
transistors) in CMOS, at the same time in criterion PTL
implementations, but very simple (only 2 transistors per
function) in the GDI (Gate Diffusion Input) design
process. The most of designed circuits were based on the
F1 and F2 functions.
The reasons for this are as follows. 1) Both F1 and F2 are
complete logic families (allows understanding of any
possible two input logic function). 2) F1 is the only GDI
function that can be realized in a standard p-well CMOS
process, because the bulk of any NMOS is constantly and
equally biased. 3) When N input is driven at high logic
level and P input is at low logic level, the diodes stuck
between NMOS and PMOS bulks to out are directly
polarized and there is a short between N and P, resulting
in static power dissipation.

ISSN 2278-6856

4.3 PROPOSED 15-4 COMPRESSOR

The basic architecture of 15-4 compressor [2] is shown in
fig 3.This will compress 15 partial products into four
outputs. It has five full adders and two 5-3 compressors
and one parallel adder. Each full adder is used to
compress three partial products into sum and carry. All
the sums from five full adders are compressed with the
help of proposed 5-3 compressor and carry outputs are
compressed with the help of proposed 5-3 compressor.
Parallel adder is used to add the output of 5-3
compressors. Inputs of 4 bit parallel adder (B3 and A0)
are grounded. Parallel adder circuit is shown in fig 4.

Fig. 3. Architecture of 15-4 Compressor

Fig: 4.1(b) General block diagram of GDI

4.2 PROPOSED GDI 5-3 COMPRESSOR

Fig. 4.Parallel adder

The proposed 5-3 compressor is implemented in 15-4
compressor which will result increased speed and reduced
power consumption.

5. SIMULATION RESULTS

Fig 4.2 proposed GDI 5-3 compressor

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Programming is done using Verilog HDL. Xilinx software

is used to verify the functionality of the architecture.
Cadence RTL compiler is used to calculate the delay (in
pico second) and power consumption (in nano watts).
Random test vector is applied to get power consumption
from cadence. Schematic diagram of proposed 5-3
compressor and 15-4 compressor is shown in fig 5a and
fig 5b.
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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org
Volume 4, Issue 4, July - August 2015
Table 2 shows the comparison result of 5-3 compressor
and table 3 shows comparison result of 15-4 compressor.
Comparison results are shown in graphs.

ISSN 2278-6856

Microwind is a tool for designing and simulating circuits

at layout level. The tool features full editing facilities
(copy, cut, past, duplicate, move), various views (MOS
characteristics, 2D cross section, 3D process viewer), and
an analog simulator. DSCH is software for logic design.
Based on primitives, a hierarchical circuit can be built and
simulated. It also includes delay and power consumption
evaluation.

Fig: 5.1(a) Simulation result of full adder 5-3 compressor

Fig. 5a. Schematic diagram of 5-3 compressor,

Fig. 5b.Schematic diagram of 15-4 compressor

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Fig. 5.1(a) shows the Simulation Result of full adder 5-3

compressor. It will compress five partial products into
three outputs. When all the inputs a, b, c, d and e are 1
then the output o1, o2, o3 are 101 and power is observed
75.144w.

Fig: 5.1(b) simulation result of proposed GDI 5-3

compressor
Fig 5.1(b) shows the simulation result of proposed system
GDI 5-3 compressor. It will compress five partial products
into three outputs. When all the inputs a, b, c, d and e are
1 then the output o1, o2 and o3 are 101 and power is
observed 67.491w.

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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org
Volume 4, Issue 4, July - August 2015

Fig: 5.1(c) simulation result of 15-4 compressor

This will compress 15 partial products into four outputs. It
has 15 inputs x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10,
x11, x12, x13and x14 are 011011011101101 then the
output o0, o1, o2 and o3 are 0101.
5.1 comparison of power calculations of 5-3compressor
From table it is observed that power required is less for
proposed system GDI 5-3 compressor. It is compared for
all technology.
Table 8 Comparison of full adder 5-3 compressor and
GDI 5-3 compressor

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Alta Freq,vol. 34, 1965, pp. 349356.

[4] C.S.Wallace, A Suggestion For a Fast Multiplier,
IEEE Transon Electronic Computers, vol. EC-13, pp.
1417, 1964.
[5] Sreehari Veeramachaneni, Kirthi Krishna M,
Lingamneni Avinash, Sreekanth Reddy Puppala ,
M.B. Srinivas," Novel Architectures for High-Speed
and Low-Power 3-2, 4-2 and 5-2 Compressors, 20th
International Conference on VLSI Design. 2007
[6] Mateus Beck Fonseca, Joao Baptista S. Martins,
Eduardo A. Cesar da Costa, Design of power
efficient butterflies from Radix-2 DIT FFT using
adder compressors with a new XOR gate topology,
Analog Integr Circ Sig Process (2012) 73:945954.
[7] Manohar Ayinala, Keshab K. Parhi,Parallel
Pipelined FFT Architectures with Reduced Number of
Delays, GLSVLSI12, May 34, 2012.
[8] Mayur Mehta and Vijay Parmar, Earl Swartzlander,
Jr, High-speed Multiplier Design Using Multi-Input
Counter and Compressor Circuits, Computer
Arithmetic, 1991. Proceedings, 10th IEEE
Symposium. pp 43 50.
[9] Shyh-Jye Jou and Hui-Hsuan Wang, Fixed-Width
Multiplier for DSP Application, Computer Design,
Proceedings. 2000 International Conference, pp 318
322, 2000.

6. Conclusion
The architecture of 5-3 compressor is analyzed. New 5-3
compressor architectures using multiplexer have been
proposed and implemented in 15-4 compressor which is
useful for multiplier which performs large size
multiplication. Simulations have been performed for
proposed 5-3 and 15-4 compressor and conventional 5-3
and 15-4 compressor. Proposed compressors (5-3 and 154) design gives better result than conventional
compressors. This 15-4 compressor can be useful to
design of large multiplier.

REFERENCES
[1] Ohsang Kwon,Kevin Nowka, Earl E. Swartzlander,
Jr, A 16-Bit by 16-Bit MAC Design Using Fast 5:3
Compressor Cells , Journal of VLSI Signal
Processing 31, 7789, 2002 .
[2] Shubhajit Roy Chowdhury, Aritra Banerjee,
Aniruddha Roy, Hiranmay Saha, Design, Simulation
and Testing of a High Speed Low Power 15-4
Compressor for High Speed Multiplication
Applications First International Conference on
Emerging Trends in Engineering and Technology.
434 438, 2008.
[3] L. Dadda, Some Schemes for Parallel Multiplier,

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