MCQ Digital Electronics - 1
MCQ Digital Electronics - 1
MCQ Digital Electronics - 1
7.IC s are
a. analog b. digital
c. both analog and digital d. mostly analog
8.The rate of change of digital signals between High and Low Level is
a. very fast b. fast
c. slow d. very slow
10.Logic pulser
a. generates short duration pulses
b. generate long duration pulses
c. generates long and short duration
d. none of above
11.What is the output state of an OR gate if the inputs are 0 and 1?
a.0 b.1
c.3 d.2
12.What is the output state of an AND gate if the inputs are 0 and 1?
a.0 b.1
c.3 d.2
18.A NAND gate is equivalent to an AND gate plus a .... gate put together.
a. NOR b. NOT
c. XOR d. none
25.. A Kb corresponds to
a. 1024 bits b. 1000 bytes
c.210 bytes d. 210 bits
36.1111+11111=
a.101111 b.101110
c.111111 d.011111
38.110012 -100012=
a.10000 b.01000
c.00100 d.00001
39.10112*1012=
a.55 b.45
c.35 d.25
40.1110112*100012=
a.111101101 b.111101100
c.111110 d.1100110
43. The contents of these chips are lost when the computer is switched off?
a. ROM chips b. RAM chips
c. DRAM chips d. none of above
46.How many bits of information can each memory cell in a computer chip hold?
a. 0 bits b. 1 bit
c. 8 bits d. 2 bits
54. In CCD
a. small charge is deposited for logical 1
b. small charge is deposited for logical 0 or 1
c. small charge is deposited for logical 0 and large charge for logical 1
d. none of above
60.A counter is a
a. Sequential ckt b. Combinational ckt
c. both combinational and sequential ckt d. none of above
69.In a 4 input AND gate,the total number of High outputs for the 16 input states are
a.16 b.8
c.4 d.1
70.a buffer is
a. always non-inverting b.always inverting
c. inverting or non-inverting d.none of above
71.An AND gate has two inputs A and B and ine inhibits input S.Output is 1 if
a.A=1,B=1,S=1 b. A=1,B=1,S=0
c. A=1,B=0,S=1 d. A=1,B=0,S=0
72. An AND gate has two inputs A and B and ine inhibits input S.Out of total 8 input states,Output is 1
in
a. 1 states b. 2 states
c. 3 states d. 4 states
76. A XOR gate has inputs A and B and output Y.Then the output equation is
a.Y=A+B b.Y=AB+A’B
c.AB+ AB’ d.AB’+A’B’
81. A+(B.C)=
a. A.B+C b. A.B+A.C
c. A d.(A+B).(A+C)
82.A.0=
a. 1 b. A
c. 0 d. A or 1
83.A+A.B=
a. B b. A.B
c. A d. A or B
90. In the expression A+BC, the total number of min terms will be
a.2 b. 3
c.4 d. 5
97.In a karnaugh map for an expression having ‘don’t care terms’ the don’t cares
can be treated as
a. 0 b. 1
c. 1 or 0 d. none of above
110.CD 4010 is a
a. inverting buffer b. non inverting hex buffer
c. NOR IC d. NAND IC
114. The inputs to a 3 bit binary adder are 1112 and 1102. The output will be
a.101 b.1101
c.1111 d.1110
121. In 2’s complement addition, the carry generated in the last stage is
a. added to LSB b. neglected
c. added to bit next to MSB d. added to the bit next to LSB
123.In a 7 segment display the segments a,c,d,f,g are lit. The decimal number
displayed will be
a. 9 b. 5
c. 4 d. 2
124. In a 7 segment display the segments b and c are lit up. The decimal number
displayed will be
a. 9 b. 7
c. 3 d. 1
132. It is desired to route data from many registers to one register. The device needed is
a. decoder b. multiplexer
c. demultiplexer d. counter
136. I n a D latch
a. data bit D is fed to S input and D’ to R input
b. data bit D is fed to R input and D’ to S input
c. data bit D is fed to both R and S inputs
d. data bit D’ is not fed to any input
137. I n a D latch
a. a high D sets the latch and low D resets it
b. a low D sets the latch and high D resets it
c. race can occur
d. none of above
138.In a positive edge triggered JK flip flop
a. High J and High K produce inactive state
b. Low J and High K produce inactive state
c. High J and Low K produce inactive state
d. Low J and Low K produce inactive state
144.A counter has N flip flops. The total number of states are
a. N b. 2N
c. 2 N d. 4N
145.A counter has modulus of 10. The number of flip flops are
a. 10 b. 5
c. 4 d. 3
154. Shifting digits from left to right and vice versa is needed in
a. storing numbers b. arithmetic operations
c. counting d. storing and counting
160. An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock
pulses required is
a. 1 b. 2
c. 4 d. 8
Q. Power diode is generally made from
a) Silicon
b) Germanium
c) Both
d) None of these
Q. When the both junction of NPN diode is reverse biased, then the diode is in which mode
a) Active
b) Cutoff
c) Saturation
d) inverted
Q. Multivibrater Produces
a) Sine wave
b) Square wave
c) Smooth wave
d) sawtooth
Ans: 55
Q. 10 in BCD
a) 10100
b) 1100
c) 010111
d) None of these
Ans: 16
Ans: 4
Q. which logic gate has the output is compliment of its input ----------
a) OR
b) AND
c) NOT
d) X-OR
Ans: NOT
Ans: X-OR
Ans: 3
Q. Which logic gate has output high if and only if all inputs are low ---------?
a) NOR
b) NAND
c) X-NOR
d) AND
Ans: NAND
Ans: 1
Ans: 1
Q.2 in 4 bit number one bit indicates sign of the number then the locations are from
a) -8 to 8
b) -7 to 7
c) -16 to 16
d) None
Q.some non zero DC voltage is to RC low pass circuit then the DC voltage in the output contains
a) Same as in input
b) Higher than input
c) Zero
d) Slightly increases
Q.if the output of the gate is always high then the gates applied to this logic are 0,0
a) NAND and EX-NOR
b) NAND and NOR
c) AND and X-NOR
d) OR and XOR
Ans:a
Q.which of the following is/are true about 1's and 2's compements:
i)In 1's complement form. 0 has two representations
ii)in 1's complement, the magnitude of lowest number is equal to the magnitude of highest number
iii)In 2's complement, 0 has two representations
a) i only
b) i and ii
c) iii only
d) all of these
Q.In the hybrid parameter model of a transistor reverse transfer voltage ratio and forward transfer
current ratio are respectively given by:
a) h11 and h21
b) h12 and h11
c) h21 and h11
d) None of these
Q.The largest negative no can be represented with 8 bits in 2's compliment representation?
a)-256
b)-255
c)-127
d)-128
Ans: -128
Ans: 4
Ans: D FF
ANS: Flash/Parallel
Ans: Flash
Q. The maximum time allowed time for each flip flop for a mod 10 synchronous counter if each flip
flop delay is 25ns.
a) 25 ns
b) 50 ns
c) 100 ns
d) none
Q. The resolution for a DAC is given by 0.4% then no. of bits of DAC is
a) 8- bits
b) 16- bits
c) 32- bits
d) none
Ans: 8- bits
41) The chip capacity is 256 bits, then the no.of chips required to build 1024 B memory Is
a) 32
b) 16
c) 15
d) 4
a) 1,2,3
b) 1,3,4
c) 1,2,4
d) 2,3,4
Ans: 1,2,4
ANS: 0
Ans: 2
Ans: IV A
Ans: 0.0978%
Ans: 45%
4. How many steps are there in the output of10-bit D/A converter?
(a) 1023
(b) 1024
(c) 10
(d) 100
5. Which one of the following can be used to change data from spatial code to temporal code?
(a) Shift registers
(b) Counters
(c) A/D converters
(d) Combinational Circuits
6.For a six bit ladder D/A converter which has digital input of 101001, the analog value is
(assume 0 = 0 Vand 1 = + 10 V)
(a) 0.423
(b) 0.522
(c) 0.641
(d) 0.923
8.If the memory chip size is 256 x l bits, then the number of chips required to
make up 1K (1024) bytes of memory is
(a)32
(b)24
(c)12
(d)8
10, The greatest negative number which can be store in a computer that has 8-bit word length and uses
2’s complement arithmetic is
(a) -256
(b)-255
(c) – 128
(d) – 127
12. A carry look ahead adder is frequently used for addition because, it
(a) is faster
(b) is more accurate
(c) uses fewer gates
(d) costs less
13. When signed numbers are used in binary arithmetic, then which one of the following notations
would have unique representation for zero? -
(a) Sign-magnitude
(b) l’s complement
(c) 2’s complement
(d) 9’s complement
15. The gate whose output is LOW if and only if all the inputs are HIGH, is
(ä)NAND
(b)NOR
(c) OR
(d) AND
17. A unit pulse input is given to a single-pole stable digital filter. Its output response will be?
(a) constant pulses
(b) exponentially decaying pulses
(c) impulse
(d) exponentially rising pulses
19. A square wave with a period of 10 micro sec drive a flip flop. The period of.the output signal.will
be
(a)100 micro sec
(b)20 micro sec
(c) 10 micro sec
(d) 5 micro sec
20.A digital Voltmeter has 4 and 1/3 digits display .The 1 volt range can read upto
(a)1.0000
(b) 1.1111
(c)1.9999
(d) 19999
22. In PCM system if the quantization levels are increased from 2 to 8, the relative bandwidth
requirement will
(a) remain same
(b) be doubled
(c) be tripled
(d )be four times
23. The 7-bit Hamming code (even parity check) 001 for a BCD digit is known to have a single error.
Therefore, encoded BCD digit is
(a) 9
(b) 5
(c) 3
(d) 0
26. The number of comparators required to build a 5-bit Analog to Digital Converter (ADC)is
(a) 5
(b) 11
(c)21
(d)31
27. A 555 timer can be used as
(a) an astable multivibrator only
(b) a monostable multivibrator only
(c) a frequency divider only
(d) an astable multivibrator or a monostable muttivibrator or a frequency divider
28. A synchronous sequential circuit is to be designed which will produce an output ‘1’ when previous
two and present input represent an even number, with present input being least significant bit. The
minimum number of states of the machine will be
(a)2
(b)3
(c) 4
(d)5
29. The specification for a standard 74 series TFL gate reads propagation delay as 35 ns and power
dissipation as I mW. This circuit is
(a) high speed TTL
(b) low power TTL
(c) standard Schottky TTL
(D) low power Schottky TTL
Directions : The following question consists of two statements, one labelled as the ‘Assertion (A) ‘and
the other as ‘Reason (R) “. You are to examine these two statements carefully and select the answer’ to
this question using the code given below.
Assertion (A) The modernization process has challenged the hold caste system in India.
Reason (R) Mobility as a phenomenon of change in caste system does not challenge the basic structure
of caste.
Code:
(a) Both A and R are individually true and R is the correct explanation of A
(b) Both A and R are individually true, but R is not the correct explanation of A
(c) A is true, but R is. false
(d) A is false, but R is true
32. Assertion (A) : In analog computation only summing amplifiers and integrators
Reason (R) : The differentiators using operational amplifiers cannot be designed.
37. Assertion (A) : The basic operation of a micro-processor consists of fetching and execution of
instructions one by one
Reason (R) The instruction set of a microprocessor is stored inside the ALU
.
38. Assertion (A) In a heterodyne digital counter, the input signal is heterodyned to a lower frequency
Reason (R) The gating and counting circuits of a digital counter cannot handle GHz signals.
39. Assertion (A) Dual-slope A/D converter is the most preferred A/D conversion approach in digital
multimeters.
Reason (R) Dual-slope A/D converter,provides high accuracy in A/D conversion while at the same
time
suppressing the hum effect on the input signal.
40. Assertion (A) A digital multiplexer can also be used to implement combinational logic function
Reason (R) In a combinational circuit, the current output depends on the previous outputs also.
41. Assertion (A) The sampled data system with its characteristic equation
Z2- 4z + 4 = 0 is unstable
Reason (R) : Sampled data systems with positive roots of the characteristic equation are unstable.
42. Assertion (A) Fast events can be captured and displayed by a real-time spectrum analyzer.
Reason (R) All components of a signal are presented simultaneously in the frequency domain. In swept
type spectrum analyzer, frequencies are supplied one at a time at a particular rate.
43. Assertion (A) Among RAM and ROM, ROM is used as firmware memory
Reason (R) ROM can be accessed for alteration.
1) Angelo marconi
2) Anno median
3) Amplitude modulation
4) Amperes
1) 100 kHz
2) 1 GHz
3) 30 to 300 MHz
4) 3 to 30 MHz
1) Angelo marconi
2) Anno median
3) Amplitude modulation
4) Amperes
1) 100 kHz
2) 1 GHz
3) 30 to 300 MHz
4) 3 to 30 MHz
2) Series motor
4) Synchronous motor
Question: The sampling rate, (how many samples per second are stored) for a CD is...?
1) 48.4 kHz
2) 22,050 Hz
3) 44.1 kHz
4) 48 kHz
Question: Compact discs, (according to the original CD specifications) hold how many minutes of
music?
1) 74 mins
2) 56 mins
3) 60 mins
4) 90 mins
Question: Sometimes computers and cash registers in a foodmart are connected to a UPS system. What
does UPS mean?
Question: Which consists of two plates separated by a dielectric and can store a charge?
1) Inductor
2) Capacitor
3) Transistor
4) Relay
Question: Made from a variety of materials, such as carbon, which inhibits the flow of current...?
1) Choke
2) Inductor
3) Resistor
4) Capacitor
Question: The FFT, a mathematical process, is used extensively in digital signal processing (DSP). For
what word does the second "F" in FFT stand?
1) Fast
2) Fourier
3) Ford
4) Footed
1) Flash
2) Flange
3) Fury
4) FRAM
Question: A given signal's second harmonic is twice the given signal's __________ frequency...?
1) Fourier
2) Foundation
3) Fundamental
4) Field
1) Field
2) Factor
3) Flash
4) Force
Question: "FET" is a type of transistor, Its full name is ________ Effect Transistor...?
1) Field
2) Factor
3) Flash
4) Force
Question: When measuring the characteristics of a small-signal amplifier, say for a radio receiver, one
might be concerned with its "Noise..."?
1) Fundamental
2) Fall
3) Force
4) Figure