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    Lab 2 - 2 Bit Logical Shifter W/ Cadence

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    acormier
    The document contains a truth table, schematic diagrams, logic simulation scripts and results, calculations, and layout for a 2-bit shifter circuit. It includes a truth table showing the inputs and outputs for all possible combinations of input bits. It also includes schematic diagrams of the gate-level and transistor-level implementations of a 2-1 multiplexer used in the shifter design. Simulation waveforms demonstrate the circuit operating at different speeds and failing at too fast a rate. Calculations determine the worst-case propagation delay through the circuit. The layout places the transistors while adhering to the metal layers M1 and M2.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Lab 2 - 2 Bit Logical Shifter W/ Cadence

    Uploaded by

    acormier
    184 views9 pages
    The document contains a truth table, schematic diagrams, logic simulation scripts and results, calculations, and layout for a 2-bit shifter circuit. It includes a truth table showing the inputs and outputs for all possible combinations of input bits. It also includes schematic diagrams of the gate-level and transistor-level implementations of a 2-1 multiplexer used in the shifter design. Simulation waveforms demonstrate the circuit operating at different speeds and failing at too fast a rate. Calculations determine the worst-case propagation delay through the circuit. The layout places the transistors while adhering to the metal layers M1 and M2.

    Original Description:

    Design of a 2 bit logical shifter

    Original Title

    Lab 2 - 2 Bit Logical Shifter w/ Cadence

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    © Attribution Non-Commercial (BY-NC)

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    The document contains a truth table, schematic diagrams, logic simulation scripts and results, calculations, and layout for a 2-bit shifter circuit. It includes a truth table showing the inputs and outputs for all possible combinations of input bits. It also includes schematic diagrams of the gate-level and transistor-level implementations of a 2-1 multiplexer used in the shifter design. Simulation waveforms demonstrate the circuit operating at different speeds and failing at too fast a rate. Calculations determine the worst-case propagation delay through the circuit. The layout places the transistors while adhering to the metal layers M1 and M2.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    184 views9 pages

    Lab 2 - 2 Bit Logical Shifter W/ Cadence

    Uploaded by

    acormier
    The document contains a truth table, schematic diagrams, logic simulation scripts and results, calculations, and layout for a 2-bit shifter circuit. It includes a truth table showing the inputs and outputs for all possible combinations of input bits. It also includes schematic diagrams of the gate-level and transistor-level implementations of a 2-1 multiplexer used in the shifter design. Simulation waveforms demonstrate the circuit operating at different speeds and failing at too fast a rate. Calculations determine the worst-case propagation delay through the circuit. The layout places the transistors while adhering to the metal layers M1 and M2.

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    You are on page 1of 9

    1 - Truth Table

    In1 In0 M1 M0 D Out1 Out0


    0 0 0 0 0 0 0
    0 0 0 0 1 0 0
    0 0 0 1 0 0 0
    0 0 0 1 1 0 0
    0 0 1 0 0 0 0
    0 0 1 0 1 0 0
    0 0 1 1 0 X X
    0 0 1 1 1 X X
    0 1 0 0 0 0 1
    0 1 0 0 1 0 1
    0 1 0 1 0 0 0
    0 1 0 1 1 1 0
    0 1 1 0 0 0 0
    0 1 1 0 1 0 0
    0 1 1 1 0 X X
    0 1 1 1 1 X X
    1 0 0 0 0 1 0
    1 0 0 0 1 1 0
    1 0 0 1 0 0 1
    1 0 0 1 1 0 0
    1 0 1 0 0 0 0
    1 0 1 0 1 0 0
    1 0 1 1 0 X X
    1 0 1 1 1 X X
    1 1 0 0 0 1 1
    1 1 0 0 1 1 1
    1 1 0 1 0 0 1
    1 1 0 1 1 1 0
    1 1 1 0 0 0 0
    1 1 1 0 1 0 0
    1 1 1 1 0 X X
    1 1 1 1 1 X X

    Lab2 Page 1
    2 - Image of Schematic

    Gate Level, 2-bit Shifter

    Transistor Level, 2-1 MUX

    Lab2 Page 2
    3 - Logic Simulation

    Sample script to generate waveform:

    stepsize 25
    analyzer IN<1> IN<0> M<1> M<0> D OUT<1> OUT<0>
    vector in IN<1> IN<0>
    vector mag M<1> M<0>
    vector d D

    set in 00
    ld
    set mag 00
    s
    set mag 01
    s
    set mag 10
    s
    hd
    s
    set mag 00
    s
    set mag 01
    s
    set mag 10
    s
    set in 01
    s
    ld
    ...

    Lab2 Page 3
    4 - Hand Calculations

    Worst case path through shifter

    nm

    Lab2 Page 4
    5 - Simulation - symmetric rise and fall

    Lab2 Page 5
    5 - Simulation - Slow Speed

    Lab2 Page 6
    5 - Simulation - Faster Rate

    Lab2 Page 7
    5 - Simulation - Failure

    From the simulations, a switch time of 2ns produces the most solid output waveform while still pushing
    the circuit.

    1/2ns = 500Mhz. Very, very close to my crude calculation!

    Lab2 Page 8
    6 - Layout Image

    It wasn't easy wiring the MUX's while keeping to M1 and M2, but I managed to pull it off.

    Lab2 Page 9

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