Chapter 3 Logic Gates

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Logic Gates

KIM Tinal

Digital Design
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Overview
What is Gate? The BUF Gate The NOT Gate The OR Gate Truth Table The AND Gate The NOR Gate The NAND Gate The XOR Gate The XNOR Gate IEEE/ANSI Symbols for Logic Gates Implementation Technology

Gate

The BUF Gate


A Y Boolean Expression Y=A A 0 1 Y 0 1

The NOT Gate


A

A
Y Y = A

A 0 1

Y 1 0

Boolean Expression

HIGH HIGH LOW LOW HIGH LOW


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The OR Gate
A Y B

A B
Y=A+B

A 0 0 1 1

B 0 1 0 1

Y 0 1 1 1

Boolean Expression

Two-Input Truth Table A Y 0 0 1 1 B 0 1 0 1 Y Y Y Y Y=A+B = = = = 0 0 1 1 + + + + 0 1 0 1 = = = = 0 1 1 1

A B C

Boolean Expression Y=A+B+C

Truth Table
Number of input combinations The input combinations or binary words will start at the top of the truth table with binary o and then count up to a maximum value that always one less than the maximum number n mber of combination

n 2 n=2x

Count max=2x -1 max 2 1

n= number of input combinations 2 is included because we are dealing with a base-2 base 2 number system x= number of inputs

Truth Table
n n A B Y 0 1 2 3 0 0 1 1 0 1 0 1 0 1 1 1 n A B C Y 0 0 0 1 0 0 2 0 1 3 0 1 4 1 0 5 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

n=22=4 cmax=4-1=3

6 1 1 7 1 1

cmax=8-1=7

n=23=8

n=24=16 cmax=16-1=15 =16 1=15


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The AND Gate


A B Y

A B
Boolean Expression Y=A.B

A 0 0 1 1

B 0 1 0 1

Y 0 0 0 1

Two-Input Truth Table B 0 1 0 1 Y Y Y Y Y=A.B = = = = 0 0 1 1 . . . . 0 1 0 1 = = = = 0 0 0 1

A B C Boolean Expression Y = ABC

A 0 0 1 1

The NOR Gate

A B
Boolean Expression Y = (A + B)

A 0 0 1 1

B 0 1 0 1

Y 1 0 0 0

A 0 0 1 1

B 0 1 0 1

Y = (A + B) Y = (0 + 0) = 0 = 1 Y = (0 + 1) = 1= 0 Y = (1 + 0) = 1 = 0 Y = (1 + 1) = 1= 0 1
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The NAND Gate

A B
Y = (A . B)

Boolean Expression

A 0 0 1 1

B 0 1 0 1 Y Y Y Y = = = =

Y = (A . B) B) (0 (0 ( (1 (1 . . . . 0) 1) 0) ) 1) = = = = 0 0 0 1 = = = = 1 1 1 0

A 0 0 1 1

B 0 1 0 1

Y 1 1 1 0
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The XOR Gate


A B A 0 0 1 1 A 0 0 1 1 B 0 1 0 1 B 0 1 0 1 Y Y Y Y = = = = (0.0) (0.1) (1 0) (1.0) (1.1) + + + + Y Y Y Y Y=A = = = = 0 0 1 1 0 1 0 1 B = = = = 0 1 1 0 A 0 0 1 1 B 0 1 0 1 Y 0 1 1 0 Y

A B
Boolean Expression Y=A B

Y = AB + AB (0.0) (0.1) (1.0) (1 0) (1.1) = = = = (1.0) (1.1) (0.0) (0 0) (0.1) + + + + (0.1) (0.0) (1.1) (1 1) (1.0) = = = = 0 1 0 0 + + + + 0 0 1 0 = = = = 0 1 1 0
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The XNOR Gate

A B
A 0 0 1 1 B 0 1 0 1 Y Y Y Y = = = = Y = (A (0 (0 (1 (1 0) 1) 0) 1) B) B) = = = = 0 1 1 0 = = = = 1 0 0 1 A 0 0 1 1 B 0 1 0 1 Y 1 0 0 1 Y = (A

Y
Boolean Expression B)

A 0 0 1 1

B 0 1 0 1 Y Y Y Y = = = = (0.0) (0.1) (1.0) (1.1) + + + +

Y = AB + AB (0.0) (0.1) (1.0) (1.1) = = = = (1.1) (1.0) (0.1) (0.0) + + + + (0.0) (0.1) (1.0) (1.1) = = = = 1 0 0 0 + + + + 0 0 0 1 = = = = 1 0 0 1
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IEEE/ANSI Symbols for Logic Gates


Traditional Logic Gate Symbol NOT Gate OR Gate AND Gate NOR O Gate NAND Gate G t XOR Gate XNOR Gate IEEE/ANSI Logic Gate Symbol

A A B A B A B A B A B A B

Y Y Y Y Y Y Y
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Implementation Technology

7400

7402

7404

7408

7432

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Thank You

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