Maharashtra State Board of Technical Education (ISO/IEC - 27001 - 2005 Certified)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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(ISO/IEC - 27001 - 2005 Certified)
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Subject Code:
Q. 1. a) ATTEMPT ANY SIX OF THE FOLLOWING. 12 MARKS
12116
SUMMER 12 EXAMINATIONS Model Answer
i) Encoder is a combinational circuit which accepts digital input and converts it in equivalent binary /BCD word. (1 mark)
Example any one of the following 1) Priority encoder. 2) Octal to binary encoder. 3) Decimal to BCD encoder. 4) Hexadecimal to binary encoder.
ii) Carry Propagated Accumulator= 56H 010101 = 10 Register B = ABH 101010 = 1 1+ Result 1000000 01 111111
(1 mark)
Carry is generated from D7 to next stage therefore CY = 1. Carry is generated from D3 to D4 therefore AC = 1 Result is non zero therefore Z = 0 D7 bit is 0 therefore S =0 iii) Generation of Control Signals
mark. mark mark mark 2 marks
(2 marks to given to any 1 figure)
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iv) (Any 2 point - 02 marks (01x2)
Sr. EPROM No 1 Erasing can be done by doing exposure to ultraviolet light 2 Selective erasing is not possible 3 Time required to erase is 10 to 15 min. 4 It is necessary to remove the PROM from circuit 5 Less expensive
EEPROM Erasing is done by applying voltage of 20 to 25 volts. Selective erasing is possible Time required to erase is short i.e. 10ms Not necessary to remove PROM from circuit Very expensive.
v) FEATURES of IC 74LS244 (any 4 points-2 marks (1/2 x 4)) 1) 3- state outputs drive bus lines directly 2) PNP inputs reduce DC loading on bus lines. 3) Hysteresis at data inputs improves noise margins. 4) Typical IOL (sink current) 24mA. 5) Typical IO4 (sink current) 15mA. 6) Typical propagation delay times inverting 10.5 ns, non-inverting 12ns 7) Typical enable /disable time 18ns. 8) Typical power dissipation (enabled) Inverting 130 mw non-inverting - 135 mw. vi) 1) IC 74LS245 Tristate octal Bus Transceiver. 2) IC 74181 4 bit ALU (Arithmetic logic unit) vii) Logic symbol of IC 7483 (1 mark) (1 mark) (2 marks)
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viii) (01 mark for each, even if definition. is given) Static RAM:- Static RAM cells are basically flip-flops which retain the stored information as long as power supply is on. No refreshing is required. Dynamic Ram:- Dynamic Ram cells are basically a MOSFEET and capacitor which loses its stored information in a few milliseconds even though its power supply is on . DRAM stores information in the form of charge on a capacitor, which leaks away in very short time. Therefore refreshing is required.
Q. 1. b) i)Evolution of Microprocessors (4 marks) The first microprocessor was developed in the year 1971 Intel-4004 which is a 4 bit PMOS microprocessor. After this enhanced version was developed i. e. Intel-4040 , IN 1972, Intel introduced the first 8 bit microprocessor Intel 8008 which also uses PMOS technology the microprocessor using PMOS technology were slow and not compatible with TTL logic, & IN 1973, INTEL introduced a more powerful and faster 8 bits NMOS microprocessor Intel 8080 which is TTL compatible also but it required three power supplies IN 1975, Intel developed Improved NMOS microprocessor, Intel 8085 which uses only one +5 V supply. The 8 bit microprocessors other manufacturers are zilogs Z80 and Z800, Motorolas 6800 and 6809 etc. In year 1978, Intel introduced 16 bit microprocessor 8086 & 8088 after 80186 and 80188 microprocessor were developed , besides CPU they contain some additional components like programmable interrupt controller, timer / counter, DMA channels etc. In 1983, 80286 has been designed for multi user system, In 1985, Intel introduced a more powerful 32 bit microprocessor, Intel 80386 which has widely used in desktop computer. Other 32 bit Intels microprocessors are the 486, Pentium, Pentium Pro, Pentium MMX, Pentium II, Pentium II Xeon, Pentium 3 and 4 etc.
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ii) Interfacing diagram for 8KX8 by using 8KX4 chips (4 marks for diagram with address decoding logic ) Address map A15 A1 A1 A1 A1 A1 A A A A A A A A 4 3 2 1 0 9 8 7 6 5 4 3 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Used for chip select Decoder logic 1 1 1 1 1 1 1 1 1 1 1 Connected to A0 A12 pins of 8KX4 RAM
correct
A 1 0 1
A 0 0 1
Addre ss 2000 H 3fffH
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Q. 1. b) contd. iii) 4 bit adder using full adder and half adder 4 marks
Q. 2) Attempt any four of following a) Addressing modes of 8085 (04 marks are given even if 4 addressing modes are explained) 1) Direct addressing:- In this mode of addressing the address of the operand ( data) is given in the instruction itself. (1/2 mark for def. 1/2 for ex.) Example:any one suitable example 2) Register addressing: - In this addressing mode the operand is in one of the general purpose registers or accumulator. (1/2 mark for def. 1/2 for ex.) Example :any one suitable example
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3) Register indirect Addressing: - In this mode of addressing the address of the operand is specified by a register pair. (1/2 mark for def. 1/2 for ex.) Example:- any one suitable example 4) Immediate Addressing: - In immediate addressing mode of the operand is specified within the instruction itself. (1/2 mark for def. 1/2 for ex.) Example:- any one suitable example 5) Implicit Addressing: - There are certain instructions which operate on the content of accumulator, they do not require the address of the operand. (1/2 mark for def. 1/2 for ex.) Example:- any one suitable example
b) OPERATION PERFORMED BY THE FOLLOWING INSTRUCTION. i) ADD C The content of Register C is added to the contents of the accumulator and sum is placed in the accumulator. (01 mark) ii) LXI H, 2500H This instruction is used to load the data 2500H into register pair HL. L = 00H, H= 25H. (01 mark) iii) MOV A, M. The content of memory location whose address is in HL pair is moved to accumulator. (01 mark) iv) INX DThe content of the register pair DE is incremented by one. (01 mark) Q. 2) c) Read operation performed by ROM (02 mark)
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ROM is an array of selectively open and closed unidirectional contacts. The address decoder is divided into two parts decoder DL and DH, DL is used to activate row lines and DH is used to activate column line which is two dimensional addressing. A unidirectional switch along with diode is used at the junction of every row and column. To select any one of the 16 bits a 4 bit address is required. The lower order two bits are decoded by DL and o/p is used to select any one row. The higher order two bits are decoded by the decoder DH which activates one of four column sense amplifiers. A ROM is programmed by selectively opening and closing the switches connected in the series with the diodes in diode matrix by connecting CS=0. To read content from ROM, address decoders DL &DH are used to select the address and chip select CS=1, so that data o/p is enabled and contents can be read. (02 marks) Q. 2) d) timing diagram for MVI A, 8 bit data (4 mark= 2 marks for OPCODE FETCH + 2 marks for Memory Read )
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Q. 2) e) Function of Following Blocks 1) ALU:- The arithmetic and logic unit performs the arithmetical operations such as addition, subtraction, increment, decrement and logical operations such as AND, OR, EX-OR, complement (NOT) (01 mark) 2) Program counter- It is a 16 bit special propose register which is used to hold the memory address of the next instruction to be executed. It keeps the track of memory address of the instructions in a program while they are being executed. (01 mark) 3) Instruction decoder- The instruction decoder decodes the instruction and establishes the sequence of the events to follow. (01 mark) 4) Accumulator- the accumulator is 8 bit reg. It is used to hold one of the operands of an arithmetic or logical operations. It serve one i/p to the ALU. The final result of an arithmetic or logical operation is placed in the accumulator. (01 mark) Q. 2) f) De-multiplexing of address and data bus with examples (04marks)(1 for diagram, 1 for explain, 01 for any suitable example)
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In the 8085 higher order address lines A8 A15 are directly available. The lower order address lines are multiplexed with data bus. i.e. AD0- AD7. The de-multiplexing of address / data bus can be implemented by using tristate octal latch 74LS373 and the latch is controlled by ALE signal. When ALE goes high the address signals will be latched in octal latch 74LS373 and the o/p of latch will be A0 A7. When ALE goes low the latch will be disabled and the data is available on data bus D0-D7 for example. Address = 2005 H & Data = 4f H
3. Attempt any four of the following

a.
(2 marks for diagram)
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(2 marks for description) b) RESOLUTION 1 mark, *2 Resolution of a DAC can be defined in two different ways: 1. Resolution is the number of different analog output voltage values that can be provided by a DAC. For an n-bit DAC Resolution= 2n 2. Resolution is defined as the ratio of change in analog output voltage resulting from a change of 1 LSB at the digital input
VFS is defined as the full scale analog output voltage i.e the analog output voltage when all the digital input with all digits 1. ACCURACY 1 mark, mark even if 1st one line written Accuracy indicates how close the analog output voltage is to its theoretical value. In short it indicates the deviation of actual output from the theoretical value. Accuracy depends on the accuracy of the resistors used in the ladder, and the precision of the reference voltage used. Accuracy is always specified in terms of percentage of the full scale output that means maximum output voltage SETTLING TIME 1 mark, mark even if 1st one line written The analog output voltage should change instantaneously to the change in digital input.
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Practically the analog output of a D -A converter does not change instantaneously. Due to the resistors and OP-AMP in the circuit, oscillations are observed at the output. The settling time should be as short as possible.
SPEED 1 mark mark even if 1st one line written It is defined as the time needed to perform a conversion from digital to analog. It is also defined as the number of conversions that can be performed per second. The speed of DAC should be as high as possible. c . Classify the instructions on Sr. No Instruction 1 MVI A,35H 2 STA 2500 3 CMA 4 ADD M Note:- 1 mark for each instruction the basis of number of bytes Number of Bytes 2 byte 3 byte 1 byte 1 byte
d. Write any four instruction to set the ZERO flag? Ans (1 mark for each instruction) 1. SUB A 2. XRA A 3. ANI 00h 4. CMP A e) ( 1 mark for each pin description)
This is an active low, output control signal. It is used to read data from memory or an I/O device depending on IO/M To read data from device microprocessor selects a device, make data bus available for data transfer & then generates signal RD to read data from selected device. HOLD:- HOLD is an active high, input signal used by other controller to request microprocessor about use of address, data & control signals. When the microprocessor receives HOLD request signal, it completes current machine cycle and will relinquish use of the bus.
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To implement this the microprocessor will instate its address, data & control signals (RD, WR & IO/M) & stop using them. The microprocessors in response to HOLD generates HLDA signal. When HLDA is active it indicates that microprocessor has received HOLD request & will relinquish the buses in next clock cycle. READY o This is an active high input control signal. o It is used by microprocessor to detect whether a peripheral has completed (READY) the data transfer or not. o If READY pin is high the microprocessor will complete the operation and proceed for next operation. But if ready pin is low (i.e. peripheral has not yet completed) microprocessor will wait until it goes high. o The main function of this pin is to synchronize slower peripheral to the faster microprocessor. Serial Input Data (SID) o This is an active high, serial input port pin, used to accept serial 1 bit data under software control. o When a RIM instruction is executed the SID pin data is loaded in bit D7 of accumulator.
4. Attempt any FOUR of the following a. marks for diagram 2 for working) BLOCK DIAGRAM of SINGLE SLOPE ADC
(2
The single slope ADC consists of a counter with display unit. The display unit consists of 7-segment decoder and 7 segment display. The circuits also contain a Control block, Ramp generator and OP-AMP as a comparator.
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The output of ramp generator is fed to comparator which compares the same with analog input voltage. Vc (output of comparator) controls the gating to the clock and also informs control circuit about completion of the conversion WORKING 1. Manual RESET, will reset ramp generator as well as counter. 2. The analog voltage VA has to be positive. Hence the RAMP begins at 0V. 3. Since VAX < VA , the output of the comparator Vc = 1 (HIGH). 4. This will enable CLOCK gate allowing the CLK input, to be applied to the counter. 5. The ramp generator may make use of counter type ADC or simple integrator. 6. As counter receives clock pulses, it will count up; and the RAMP continues upward. RAMP voltage rises till it reaches to VA input voltage. 7. When the ramp voltage reaches the input analog voltage, the output Vc= 0 (LOW) and it will disable CLOCK gate and counter cease to advance. 8. The negative transition of Vc simultaneously generates a strobe signal in the CONTROL box that shifts the contents of the three decade counters into the three 4 FF latch circuit. 9. After the generation of STROBE signal, a reset pulse is generated by the CONTROL box that resets the RAMP and clears the decade counter to 0s (ZEROS) and another conversion cycle begins. 10.During this time the contents of the previous conversion, are contained in the latches and are displayed on the seven segment display. b. Flash Memory (1mark for each for any four points) 1. This is a variation of EE-PROM 2. It makes use of 1 transistor memory cell. 3. It has a high packing density, low cost and high reliability 4. It is non volatile memory and it can be electrically erased and reprogrammed 5. The data is stored in for of large blocks 6. Since the data is written in block it is easy to update it. 7. It must be erased entirely or in blocks 8. It can be erased and programmed at least a million times 9. The power supply requirement for programming these chips was 12 V but now can be programmed using as low as 1.8 V. So ideal for low power system c. Define Stack and Stack Pointer. State the contents of SP and HL registers after execution of following instructions. LXI SP,2050H LXI H,2500H PUSH B PUSH D POP D SPHL
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Ans. The stack is a sequence of memory locations set aside by a programmer to store/retrieve the contents of accumulator, flags, program counter and general purpose registers during the execution of a program. The stack pointer controls addressing of the stack. The SP holds the address of the top element of data stored in the stack. (01 mark) INSTRUCT ION LXI SP,2050H LXI H,2500H PUSH B
S PH S PL Re g H Re g L
mark
2 0
5 0 25 00
Save the contents of Register Pair BC onto the stack. SP= SP -1 Reg B Stack memory pointed by SP SP= SP -2 Reg C Stack memory pointed by SP Save the contents of Register Pair DE onto the stack. SP= SP -1 D Stack memory pointed by SP Reg SP= SP -2 Reg E Stack memory pointed by SP Retrieve the contents of the stack memory to the Register specified Reg E Stack memory pointed by SP SP= SP +1 Reg D Stack memory pointed by SP SP= SP +2 Copy the contents of HL onto the stack pointer
2 0
4 E
PUSH D
2 0
4 C
POP D
2 0
4 E
SPHL
2 5
0 0
After the execution of the instructions SP= 2500h HL= 2500h
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d. Describe RIM instruction of 8085 microprocessor. (1m - format, 1m - M7.5-M5.5, 1m -I7.5-I5.5, 1/2m - IE, 1/2m - SID) Ans.
Instruction RIM is Read Interrupt Mask. This is a 1-byte instruction that can be used to read interrupt masks. This instruction loads the accumulator with 8 bits indicating the current status of the interrupt masks To identify the pending interrupts bits D4, D5 and D6 are used. To receive serial data bit D7 is used.
e. PUSH explanation, 1 m for example) Push, Push register pair onto stack Opcode PUSH Operand Reg-pair Bytes M-Cycles T-States 1 3 10
(1m for
Description: - The contents of the register pair designated in the operand are copied into the stack in the following sequence. The stack pointer register is decremented by1 and the contents of the high order register(B, D, H, A) are copied into that location. The stack pointer register is decremented by 1 again and the contents of the low-order register (C, E, L, flags) are copied to that location.
Example:Initial state:-
Regs/Mem
Flags
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Instruction :Result :-
SP = 2099H BC = 3257H PUSH B Regs/Mem SP = 2097 [2097] = 57H [2098] = 32H Flags
Comments: - Operand PSW (Program Status Word) represents the contents of the accumulator and the flag, the accumulator is the high-order register and the flags are the low-order register. The contents of the source register are not altered after the PUSH instruction. POP explanation, 1 m for example) POP, Pop off stack to register pair Opcode POP Operand Reg-pair Bytes M-Cycles T-States 1 3 10 (1m for
Description:The contents of the memory location pointed out by the stack pointer register are copied to the low-order register(such as C,E,L, and flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high order register (B,D,H,A) of the operand. The stack pointer register is again incremented by 1. Flag:- No flags are modified. Example:Initial state:- Regs/Mem SP = 2090H [2090] = F5H [2091] = 01H Instruction :Result :POP H Flags
Flags
Regs/Mem SP = 2092H HL= 01F5H
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Comments:- Operand PSW (Program Status Word) represents the contents of the accumulator and the flag, the accumulator is the high-order register and the flags are the low-order register. The contents of the source, stack locations, are not altered after the POP instruction. f. carries 1 mark) Sr. No Memory mapped I/O 1 In this technique I/O and memory both are treated as Memory. 2 In this case both I/O and memory have a 16 bit address. All memory related instructions are applicable for I/O devices and memory. Size of memory is reduced Arithmetic and logical operations can be directly performed on the I/O ports Can interface maximum memory of 64 KB which also includes the I/O ports. The data transfer is possible between any register and I/O port (Any 4 points. Each point I/O mapped I/O In this technique I/O is treated as I/O and memory is treated as Memory In this case I/O has an 8 bit address and memory has a 16 bit address. IN and OUT instructions are used for I/O devices and memory related instructions for memory. Size of Memory is not reduced. Arithmetic and logical operations cannot be directly performed on the I/O ports Can interface maximum memory of 64 KB and 256 I/O ports. The data transfer is possible only between Acc and I/O port.
4 5
Q5 a) R -2R ladder DAC uses two resistors R & 2R. The input is applied through digitally
controlled switches.
(2 m) For example if the digital input is 001
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(1/2 m) Applying Thevenins theorem at XX
(1/2 m) Applying Thevenins theorem at yy
(1/2 m) Applying Thevenins theorem at zz
(1/2 m) Similarly for digital input 010 and 100 the equivalent voltages are VR/22 And VR/21 respectively. The equivalent resistance is 3R in each case. So the simplified circuit of 3bit R-2R ladder DAC is
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(1 m) The analog output voltage for a given digital input is given by Vout = - (RF/3R VR*b0/23 + RF/3R VR*b1/22 + RF/3R VR*b2/21) = - (RF/3R) (VR/23) (22b2 + 21b1 + 20 b0) = - (RF/3R) (VR/23) (4b2 + 2b1 + b0)
(1m)
Advantages :(2mark for any 2 advantages) i) Resistors of only two values are required so building the circuit is easy.
ii) Bits can be increased easily by adding more R-2R sections iii) Due to small resistance spread, R-2R ladder can be accurately fabricated
monolithically. Q5 b) FEATURES OF IC 2716:i) 2048 X 8 organization.
(02m for any four features i.e * 4 = 2)
ii) 525mW max active power, 132mW max standby power. iii) Access time iv) v) Static no clock required. vi) Inputs & output TTL compatible during both read and program modes. vii) Extended temperature range viii) Programming voltage : 25V ix) Three state output with tied or capability.
MODES OF OPERATION: (2 marks=1/2m for the names of modes, 1/2 m for each mode explanation) 2716 has 3 modes of operation 1. Read mode :a. Read operation requires G =VIL , EP =VIL and address is stabilized b. Valid data will appear on the output pins after time tAVQV or tELQV 19 M 2716-1 is 450 ns. M 2716 is 350 ns. Single 5V supply voltage
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2. Deselect Mode a. 2716 is deselected by G = VIH. This is independent of EP and condition of addresses b. Outputs of high impedance (Hi-Z) when G = VIH. This allows tied-OR of two or more ICs 3. Stand-by Mode (Power Down) a. 2716 is powered down by EP =VIH. b. Independent of G automatically puts the output in Hi-Z state. Power is reduced by 25% of normal operating power. PROGRAMING MODE: (2 marks=1/2m for the names of modes, 1/2 m for each mode explanation ) 2716 has 3 programming modes a. Program Mode 1. All bits of 2716 are high initially or after full eraser 2. It is programmed by introducing 0s at desired location 3. Any individual address or sequential address or random address can be programmed. 4. Any or all 8 bits of a location can be programmed with a single program pulse to EP pin b. Program Verify Mode 1. Program can be verified one byte at a time during programming or entirely at the end of the program 2. This is done with Vpp = 25V or 5V in either case. c. Program Inhibit Mode 1. This mode allows several 2716 to be programmed simultaneously with different data for each. 2. All similar inputs may be paralleled. Pulsing the program pin will program a unit, inhibiting the program pulse will keep it from being programmed 2716 is a 2048X 8 memory, so 4 ICs are required to get 8 KB memory ( 2mark)
Q5 c) i)
ii)
Hexadecimal to Binary priority encoder:(02m for encoder (1/2 for IC no. for inputs, for outputs, for EI, EO, GS) (02m for encoder (1/2 for IC no. for A0-A3 & B0-B3, for Y0-Y3, for Select & Strobe) 20
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Given : N=4 VFS = 5V Resolution = VFS/2n-1 = 5V/ 24- 1 = 0.333 V (02m) Input change of 1 LSB causes output to change by So input change of (1011)2 = (11)10 causes output to change by OR
iii)
0.333V 11* 0.333V = 3.663V (02m)
Analog output when all inputs are 1 (1111)2 i.e VFS = 05 V Also analog output for (1111)2 = VR * (2n - 1) / 2n So 15VR/16 =5V 21
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or So
VR = 5*16/15 = 5.33V Vo = VR [ (b3*2-1) + (b2 * 2-2) + (b1* 2-3) + (b0 * 2-4)] Vo for 1011 is Vo = 5.33 [ (1*2-1) + (0 * 2-2) + (1* 2-3) + (1 * 2-4)] = 5.33 (0.5 +0 +0.125 + 0.0625) = 5.33 * 0.6875 = 3.664 V OR
(01m) (01m)
(02m)
Say K = 1, VFS = VR. Vo = VR [ (b3*2-1) + (b2 * 2-2) + (b1* 2-3) + (b0 * 2-4)] = 5[ (1*2-1) + (0 * 2-2) + (1* 2-3) + (1 * 2-4)] = 5* 0.6875 = 3.44V (01m) (03m)
Q6
a) Microprocessor has 5 interrupt input TRAP, RS 7.5, RST 6.5 , RST 5.5 and INTR .These interrupt have priorities ,input triggering ,masking and vector location as stated below (01 mark each for Input triggering, Priority, Masking, Vector location) Input triggering Priority Masking Vector location Interrupt TRAP Edge and level 1st Non 0024H triggering maskable RST 7.5 RST 6.5 RST 5.5 INTR Positive edge triggering Level triggering Level triggering Level triggering 2nd 3rd 4th 5th Maskable Maskable Maskable Maskable 003CH 0034H 002CH From RST n (n = 0-7) RST 0 0000H RST 1- 0008H RST 2 -0010H RST 3 0018H RST 4 0020H RST 5 0028H 22
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RST 6 0030H RST 7 0038H 04 marks for diagram
Q6 b) (Data can either be transmitted on SOD pin or received on SID pin so marks should be given for any of the two programs. 04 marks for flow chart and 04 marks for program) Program to transmit B registor 8- bits of data using SOD pin mark start bit Flow chart :23 D0 D1 D2 D3 D4 D5 D6 D7 EP Data bits Asynchronous data format Parity stop bit bit mark
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Program:-
UP
LXI SP, FFFFH MVI C,08H MVI A,40H SIM CALL Delay MOV A,B RRC MOV B, A ANI 80H ORI 40H SIM CALL Delay DCR C
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DWN BELOW
JNZ UP MOV A,B ORA A JPE DWN MVI A, C0H SIM JMP BELOW MVI A,40H SIM CALL Delay MVI A, C0H SIM CALL Delay HLT
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OR Program to receive 8- bits of data using SID pin
Result reg and
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Program :LXI SP, FFFFH MVI B, 08H MVI D, 00H UP : RIM ANI 80H JNZ UP CALL Delay 1 RIM ANI 80H JNZ UP UP 1 : CALL Delay RIM ANI 80H ORA D RRC MOV D, A DCR B JNZ UP 1 RLC STA 2000H ORA A JPO Error RIM ANI 80H 27

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CZ Error CALL Delay RIM ANI 80H CZ Error CALL Delay HLT Q6 c) Functional block diagram of ADC 0809 (3m for diagram)
Explanation: (03m for explanation) ADC 0809 operates on Successive Approximation method of conversion .There are 8 analog input IN0 IN7.The 8 channel mux selects one of the eight input for conversion .This selection is done with the help of 3 address pins A, B, C and ALE signal .These three pins A, B, C can generate eight inputs IN0 IN7 . When a start of conversion (SOC) signal is received, the analog voltage at the selected input starts converting into digital value using Successive Approx. method. It uses the reference voltage VRFF(+) or VREF(-). The converted values i.e digital value is obtained at the tristate output latch. ADC sends an end of conversion (EOC) signal and the 8 bit binary output is obtain , -1 2 represents MSB and 2-8 represents LSB . ALE:01m ALE is the address latch enable pin .Ale input enables the address latch to store the address of the analog input on A, B ,C lines . SOC :01m SOC is the start of conversion signal sent by the microprocessor and received by ADC. When ADC receives the SOC pulse , it starts analog to digital conversion.
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Maharashtra State Board of Technical Education (ISO/IEC - 27001 - 2005 Certified)

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MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

(ISO/IEC - 27001 - 2005 Certified)

Q. 1. a) ATTEMPT ANY SIX OF THE FOLLOWING. 12 MARKS

SUMMER 12 EXAMINATIONS Model Answer

mark. mark mark mark 2 marks

(2 marks to given to any 1 figure)