QUADRATURE PHASE SHIFT KEYING MODULAT ION TECHNIQUES OBJECTIVE: Study of Carrier Modulation Techniques by Quadrature Phase Shift

t Keying method. EQUIPMENT: Experimentor Kit ADCL-02-03. Connecting Chords. Power supply. e-Lab THEORY: In this modulation, called Quadrature PSK (QPSK) or 4 PSK the sine carrier takes 4 phase values, separated of 90 deg. and determined by the combinations of bit pair (Dibit) of the binary data signal. The data are coded into Dibit by a circuit generating: A) A data signal I (in phase) consisting in voltage levels corresponding to the value of the first bit of the considered pair, for duration equal to 2 bit intervals. B) A data signal Q (in quadrature) consisting in voltage levels corresponding to the value of the second bit of the pair, for duration equal to 2 bit intervals. The block diagram of the modulator used on the module is shown in the block diagram. Four 500KHz sine carriers, shifted between them of 90 deg, are applied to modulator. The data (signal I and Q) reach the modulator from the Dibit generator. The instantaneous value of I and Q data bit generates a symbol. Since I and Q can take either 0 or 1 value, maximum 4 possible symbols can be generated (00, 01, 10, and 11). According to the symbol generated one of the four-sine carrier will be selected. The relation between the symbol generated and sine carrier is shown in table. A receiver for the QPSK signal is shown in fig. Synchronous detection is required and hence it is necessary to locally regenerate the carriers. The scheme for carrier regeneration is similar to that employed in BPSK. In that earlier case we squared the incoming the signal, extracted the waveform at twice the carrier frequency by filtering, and recovered the carrier by frequency dividing by two. In the present case, it is required that the incoming signal be raised to the fourth power after which filtering recovers a waveforms at four times the carrier. A receiver for the QPSK signal is shown in fig. Synchronous detection is required and hence it is necessary to locally regenerate the carriers. The scheme for carrier regeneration is similar to that employed in BPSK. In that earlier case we squared the incoming the signal, extracted the waveform at twice the carrier frequency by filtering, and recovered the carrier by frequency dividing by two. In the present case, it is required that the incoming signal be raised to the fourth power after which filtering recovers a waveforms at four times the carrier.

1 1 0

2 4

5 8

7
SW1

[ADCL-02]
OFF
CLK IN

SF1
ON
I BIT
C1

CL OCK & DAT A GENERATOR

SC LOCK

DIBIT CONVERSION

1 4

NR Z-L CODER
SDATA DATA IN
NRZ -L DATA

Q BIT

C2 MOD

DA T A IN

SIN1 SIN2 CAR RIER GENERATOR SIN3 SIN4

IN1 IN2

CARRIER MOD ULATOR

OUT

IN3 IN4

DE M1

SAMP LER SA MPLING F/4

PLL SQUARER VCO 2 SQ UARER 1

DATA OUT

I BIT IN

I BIT Q BIT

ENVE LO PE DE TEC TOR1 ADDER 180 ENVE LO PE

CLO CK GEN ERATO R

MOD IN

DATA DECODER

Q BIT IN

CLK IN

CLK

DE TEC TOR 2 DEM0 2

RK CLK 2

SF1
OFF ON 1 2 4 3

CLO CK RECOVE RY QP SK /DQP SK DEMODU LATION

PHASE SYNC

RST

[ADCL-03]

BLOCK DIAGRAM FOR QUADRATURE PHASE SHIFT KEYING MODULATION TECHNIQUE.

PROCEDURE: Refer to Block Diagram & Carry out the following connections and switch settings. Connect power supply in proper polarity to the kit ADCL-02/03 & switch it on. Select Data pattern of simulated data using switch SW1. Connect SDATA generated to DATA IN of NRZ-L CODER. Connect the coded data NRZ-L DATA to the DATA IN of the DIBIT CONVERSION.

Connect the SCLOCK to CLK IN of DIBIT CONVERSION.

Connect the dibit data I bit to control input C1 of CARRIER MODULATOR

Connect the dibit data Q bit to control input C2 of CARRIER MODULATOR.

Connect carrier component to input of CARRIER MODULATOR as follows: SIN 1 to IN 1

SIN 2 to IN 2

SIN 3 to IN 3

SIN 4 to IN 4

Connect QPSK modulated signal MOD OUT on ADCL-02 to the MOD IN of the QPSK DEMODULATOR on ADCL-03.

Observe the output of first squarer at SQUARER 1.

Observe the output of second squarer at SQUARER 2.

Observe four sampling clocks at the output of SAMPLING CLOCK GENERATOR.

Observe the output of ADDER 1.

Observe the output of ADDER 2.

Observe the recovered data bit I at the output of ENVELOPE DETECTOR 1.

Observe the recovered data bit Q at the output of ENVELOPE DETECTOR 2.

Connect I BIT, Q BIT & CLK OUT outputs of QPSK Demodulator to I BIT IN, Q BIT IN & CLK IN posts of Data Decoder respectively. Observe the recovered NRZ-L data from I & Q bits at the output of DATA DECODER.

Use RESET switch if delay occurs at data out post and use PHASE SYNC switch if there is mismatch in the pattern of data at output with respect to the transmitter data.

OBSERVATIONS: ON KIT ADCL-02 Input NRZ-L Data at DATA INPUT.

Carrier frequency SIN 1 to SIN 4

Dibit pair generated data I bit & Q bit at DIBIT CONVERSION.

ON KIT ADCL-03 QPSK modulated signal at MOD OUT.

Output of first squarer at SQUARER 1.

Output of second squarer at SQUARER 2.

Four sampling clocks at the output of SAMPLING CLOCK GENERATOR.

Two adder outputs at the output of ADDER.

Recovered data bits (I & Q bits) at the output of ENVELOPE DETECTORS.

Recovered NRZ-L data from I & Q bits at the output of DATA DECODER.

CONCLUSION : In BPSK we deal individually with each bit of duration Tb. In QPSK we lump two bits together to form a SYMBOL. The symbol can have any one of four possible values corresponding to two-bit sequence 00, 01, 10, and 11. We therefore arrange to make available for transmission four distinct signals. At the receiver each signal represents one symbol and, correspondingly, two bits. When bits are transmitted, as in BPSK, the signal changes occur at the bit rate. When symbols are transmitted the changes occur at the symbol rate which is one-half the bit rate. Thus the symbol time is Ts = 2Tb.