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CSE 120 SALESH ASWANI ID: -993-70-9953 PROFESSOR: - MR.
MATAR CLASS: - MWF 8:40 SIMULATION LAB #3: - (ALU ) ARITHEMETIC AND LOGIC UNIT
INTRODUCTION In this simulation lab we have to build on the combinational logic circuits that we built in the simulation labs 1 and 2 to form more complex combinational logic subcircuit: the arithmetic and logic unit (ALU). The ALU in a microprocessor is the unit that performs all of the arithmetic operations (such as ass, subtract, negate, etc) and all of the logical operations (such as 1s complement, AND, OR, etc). The ALU that I will design will not be different form the ALU in the personal computer. Our ALU, like all ALUs, will be a combinational logic circuit. It will have two data input ports (each of which will accept a 4-bit binary data values1) and it will have a carry input. These data values are known as operands. Our ALU will be capable of operating on either one operand (e.g., performing a 1s complement operation), or two operands (e.g., performing the sum, A+B) and will produce a 4-bit result (plus a possible carry). The ALU will be controlled by a set of input control signals. These input control signals will determine which operation the ALU will perform. In this laboratory exercise you will construct the ALU.
Objectives: In this laboratory exercise you will learn how to construct an arithmetic and logic unit (ALU) using subcircuits you built with LogicWorks in simulation labs 1 and 2.
Outcomes: When you have completed the tasks in this experiment you will be able to: Build, test, debug, and imbed in a subcircuit, an elementary arithmetic and logic unit (ALU). Describe the arithmetic and logical operations of which the ALU is capable. Describe the input control line values that correspond to each arithmetic and logical operation of the ALU. Write a top-down description of a complex logic circuit. Calculate the approximate propagation delay time of a combinational-logic circuit.
Task 3-1: Build the NOT/NEG Circuit:
In this task we have to build a circuit by modifying 4_Bit Half Adder that we made in the previous
simulation labs. The circuit that we will build in this lab is a NOT/NEG circuit shown below: INC_4 A3 A3 Y3 Y3
A2
A2
Y2
Y2
A1
A1
Y1
Y1
A0
A0
Y0
Y0
/~Pass NOT/~NEG
Cin
CRY
CRY
The above circuit is made by making modifications in the Half Adder that we built in the previous simulation labs. This circuit performs three things listed below: It can perform the 2s complement operation (i.e. negate arithmetically). It can perform the 1s complement (i.e. logically complement each bit, also known as performing the NOT of each bit). Allow the input argument to pass through unscathed. In the circuit shown above two control signals have been added to effect these controls: the /~Pass and the NOT/~NEG.
The /~Pass and NOT/~NEG signals work together to produce the following operations: 1. /~Pass = 0. Pass-Through Operation With /~Pass = 0, the output of the AND gate in the above figure must be 0, preventing the INC_4 subcircuit from incrementing the incoming signal. The /~Pass = 0 is also fed into each XOR gate. Recall from the definition of the XOR gate that 0.A=A; hence the A input is passed through the XOR gates unscathed and then through the incrementer unscathed. Thus with /~Pass = 0, the A operand is passed unscathed through the NOT/~NEG circuit as indicated in the above figure. 2. /~Pass = 1, NOT/~NEG = 0. Arithmetic Negate Operation
With /~Pass = 1 and NOT/~NEG = 0, both inputs to the AND gate are 1's; hence the output of the AND gate is high, causing the INC_4 circuit to increment the incoming signal. The /~Pass = 1 signal is supplied as one input to each of the XOR gates. Recall from the definition of the XOR gate that 1 A = ; that is, when one input to an XOR gate is a 1, the XOR acts on the other input as an inverter would; hence the input to the INC_4 circuit is the bit-wise complement of A, (or ). Incrementing by 1 is the definition of the two's-complement operation. Thus this control scheme arithmetically negates the A operand as indicated in the figure above.
Under this control scheme the lower input to the AND gate is zero. This causes the output of the AND gate to be low. This in turn causes the INC_4 circuit to pass through the incoming 4-bit operand signal unscathed. The incoming 4-bit operand is (see argument above); hence the output of the INC_4 circuit is the bit-wise complement, or one's complement of A as indicated in the figure above.
The test using the truth table that shows that the NOT/~NEG circuit works perfectly is shown below: A0 0 0 0 0 A1 0 0 0 0 A2 0 0 0 0 A3 0 0 0 0 /~Pass 0 0 1 1 NOT/~NEG CRY 0 0 1 0 0 1 1 0 Y0 0 0 0 1 Y1 0 0 0 1 Y2 0 0 0 1 Y3 0 0 0 1
Task 3-2: Build and Test the XOR/ADD Circuit
In this task we have to build a XOR/ADD circuit by using the Subcircuits contained in our library. After I finish making the circuit I have to test it, the circuit to be made is shown below: XR3 XR2 XR1 XR0
After completing the circuit sown above we have to make a sub circuit of it. And test the sub circuit, the sub circuit and the test showing that the sub circuit works correctly is shown below:
The above truth table shows that when /~PASS and XOR/~ADD are low we get a Pass Through function. And the same happens when /~PASS is low and XOR/~ADD is high. But the circuit performs an arithmetic function when /~PASS is high and XOR/~ADD is low. Hence it ADDs, 0011 (A0,A1,A2,A3) with 0110 (B0,B1,B2,B3). A3 and B3 are the least significant bits. 1100 0110 0010
The addition of the binary numbers shown above proves that the circuit works correctly. The addition that is preformed above gives out a carry (1) too.
Task 3-3: Build and Test the ALU Circuit
In this task we have to build and test a ALU circuit. After we finish making the circuit we have to make the Sub Circuit of it and save it in to the library. I have built the ALU circuit by combining the NOT/NEG and the XOR/ADD sub circuits as shown in the figure below: A3 A2 A1 A0 /~Invert
This ALU contains three input signals: The /~Invert signal, when active, indicates that some type of inversion, either a one's or two's complement is taking place. The /~A_Only signal, when active, indicates that only the A operand is being acted upon by the ALU. The Logic/~Arith signal operates so that when it is low, an arithmetic operation is performed. When Logic/~Arith = 1, a logical operation is performed by the ALU.
ALU function definition table /~A_Only = 0 Logic/~Arit /~Invert h
0 0 1 1 0 1 0 1
Function 2s complement Pass 1s complement Pass
/~A_Only = 1 Logic/~Arit /~Invert h
0 0 0 1
Function Arithmetic Sum Arithmetic
1 1
0 1
Sum XOR XOR
After I figured the function tables I tested the ALU using Binary Switches and Binary Probes, that made me confident that the circuit is working correctly. The truth table that shows all the test that were preformed on the ALU is given below:
The truth table above proves that my circuit works correctly.
Task 4:Calculate the Propagation Delay times of the ALU
In this task we are suppose to calculate the propagation delay times from every input of the ALU to every output. This propagation delay time is measured by bring all inputs to a fixed value then
changing the one input of interest and measuring the time it takes the output of interest to reach and stay at its final value. To estimate the propagation delay from every one of our inputs to every one of our outputs, we will need to determine the path length, measured in gate delays, between every input and every output and then multiply the path length by the propagation delay of a gate.
The Path Length for NOT/NEG Circuit is shown below:
The Path Length for XOR/ADD Circuit is shown below:
From the path lengths for NOT/NEG circuit and for XOR/ADD circuit I found out the total Path Lengths for the ALU, the table that shows the path lengths of the ALU is shown below:
Summary of what was learned: After completing the tasks, I learned to build, test, and imbed in a subcircuit, and elementary arithmetic and logic unit (ALU), describe the arithmetic and logical operations of which the ALU is capable, describe the input control line values that corresponds to each arithmetic and logical operation of the ALU, write a top-down decomposition of a complex logic circuit, and calculate the approximate propagation delay time of a combinational-logic circuit.
