PCE385

PCE385
PCI Express Four Channel T1/E1/J1 Communications Processor Hardware Installation Guide
Performance Technologies 205 Indigo Creek Drive Rochester, NY 14626 585.256.0200 support@pt.com
www.pt.com
2008 2004 Performance Technologies, Inc. Performance Technologies, Inc. All Rights Reserved. All Rights Reserved.
Document Revision History Part Number

126p0489.10 126p0489.11 126p0489.12 126p0489.13 126p0489.14
Date
November 10, 2006 February 22, 2007 March 29, 2007 November 1, 2007 January 31, 2008
Explanation of Changes
Draft Released Corrected CE Certification on page 81. Corrected Safety Compliance on page 82. Clarified up-plugging installation of the PCE335
Copyright Notice Copyright 2008 by Performance Technologies, Inc. All Rights Reserved. The Performance Technologies logo is a registered trademark of Performance Technologies, Inc. All other product and brand names may be trademarks or registered trademarks of their respective owners. This document is the sole property of Performance Technologies Inc. Errors and Omissions Although diligent efforts are made to supply accurate technical information to the user, occasionally errors and omissions occur in manuals of this type. Refer to the Performance Technologies, Inc. Web site to obtain manual revisions or current customer information: http://www.pt.com. Performance Technologies, Inc., reserves its right to change product specifications without notice.
Symbols and Conventions in this Manual The following symbols appear in this document: Caution: There is risk of equipment damage. Follow the instructions. Warning: Hazardous voltages are present. To reduce the risk of electrical shock and danger to personal health, follow the instructions. Caution: Electronic components on printed circuit boards are extremely sensitive to static electricity. Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment. It is recommended that anti-static ground straps and antistatic mats are used when installing the board in a system to help prevent damage due to electrostatic discharge. Additional safety information is available throughout this guide and in Chapter 9, Product Safety Information.
Contents
Chapter 1: About This Guide
13
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Customer Support and Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Product Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2: Introduction
17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Processing on the PCE385 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Processing on the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Processing on the H.100-Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCE385 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Main Board Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Daughter Board Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Front Cover Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCI Express Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PCIe Slot Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 3: Installation
25
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contents
Unpacking the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Installing the PCE385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 4: Development Environment
29
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PCE385 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Main Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mezzanine Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PCI Express Interface Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Peripheral Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Communication Processor Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Physical Layer (Layer 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data Link Layer (Layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Transaction Layer (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Forward Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Nontransparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Features from PEX8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Boot Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 General Boot Flash Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Application Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General Application Flash Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TDM Clock Distribution and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Contents
H.100 DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Internal Reference Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Internal Reference Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CT Clock and Frame Monitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External Reference Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 External Reference Clock Source Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 H.100 Clock Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CT Netreference Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 H.100 Bus and Digital Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MT90866 Digital Switch Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Digital Switch Local TDM Streams Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 E1/T1/J1 Quad Framer and LIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Frame Aligner Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 5: ATM Channel Allocations
55
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ATM Channel Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ATM Receive Cell Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ATM Transmit Cell Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Receive UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Transmit UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MPC8280 Parallel Port Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MPC8280 Port A Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MPC8280 Port B Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MPC8280 Port C Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 MPC8280 Port D Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 6: Pinouts
69
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Main Board Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MPC8280 COPS Header (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 JTAG Testing Port (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Option Jumper Block (P3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Contents
Daughter Board Interface Connector (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 7: Specifications
77
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 8: Data Sheets and Agency Approvals
79
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Data Sheet Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 CompactPCI Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 User Documentation References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Agency Approvals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 CE Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Compliance with RoHS and WEEE Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Emissions Test Regulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Immunity Test Regulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 FCC (USA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Industry Canada (Canada) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 9: Product Safety
85
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Product Safety Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 AC or DC Power Safety Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DC Power Safety Warning (DC Powered Units) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Rack Mount Enclosure Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Glossary Index
89 97
Ta b l e s
Table 1-1: Conventions in This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2-1: Data Flow in Processing on the PCE385 Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2-2: Data Flow in Processing on the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2-3: Data Flow in Processing on the H.100-Compatible Board . . . . . . . . . . . . . . . . . . . . . . . 20 Table 2-4: PCE385 Main Board Component Layout Call Out Definitions . . . . . . . . . . . . . . . . . . . . 20 Table 2-5: PCE385 Daughter Board Component Layout Call Out Definitions. . . . . . . . . . . . . . . . . 22 Table 4-1: Reset Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 4-2: Peripheral Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 4-3: MPC8280 Chip Select Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 4-4: Communication Processor Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 4-5: JTAG P4 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 4-6: PEX8111 PCI Express Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 4-7: H.100 DPLL Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 4-8: Digital Switch Local TDM Streams Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 5-1: MPC8280 Port A Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 5-2: MPC8280 Port B Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 5-3: MPC8280 Port C Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 5-4: MPC8280 Port D Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Tables
Table 6-1: PCE385 Main Board Connector Pinout Call Out Definitions . . . . . . . . . . . . . . . . . . . . . 70 Table 6-2: JTAG/BDM Debug Port (P1) Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 6-3: Mezzanine Master/Slave PCM Expansion Connector (P2) Pinout . . . . . . . . . . . . . . . . . 72 Table 6-4: Option Jumper Block (P3) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 6-5: Mezzanine Telecom Line Interface J1 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 7-1: Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 7-2: Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 8-1: Safety Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 8-2: Emissions Test Regulations Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 8-3: Immunity Test Regulations Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10
Figures
Figure 2-1: Operational Overview Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 2-2: PCE385 Main Board Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2-3: PCE385 Daughter Board Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 2-4: PCE385 Front Cover Plate Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 2-5: Types of PCI and PCI Express Slots on a PC Main Board . . . . . . . . . . . . . . . . . . . . . . 24 Figure 3-1: PCE385 Insertion Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 4-1: PCE385 Architectural Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 4-2: JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 4-3: Application Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 4-4: External Clock Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 4-5: Quad Framer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 5-1: ATM Channel Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 5-2: MPC8280 ATM Transmission Convergence (TC) Layer Overview . . . . . . . . . . . . . . . . 58 Figure 6-1: PCE385 Main Board Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11
Figures
12
Chapter
1
About This Guide
Overview
This guide provides the PCE385, Version 1.0 installation and configuration procedures intended for the installer, and the product architecture description intended for the application developer of this board. Here is a brief description of the information in this Guide: Chapter 2, Introduction on page 17 provides an overview of the PCE385 and a summary of the interaction between the board components. Chapter 3, Installation on page 25 provides the information required to install the PCE385. Chapter 4, Development Environment on page 29 provides information about the board memory, interface, features, flash memory, operating modes, and Framer and Line Interface Unit (LIU) information required to develop applications. This chapter also provides information about the Joint Test Action Group/Bund Deutscher Mdel (JTAG/BDM) debug port and the console port. Chapter 5, ATM Channel Allocations on page 55 provides information about Time Division Multiplexing (TDM) data flow, frame pulse, and the TDM clock. This chapter also provides information about how the signals are routed to the MPC8280 TDM inputs and outputs. Chapter 6, Pinouts on page 69 provides information about the JTAG/BDM port, the nine-pin subminiature connector, and the P3 eight-pin header that is used to set the board configuration and operation mode. Chapter 7, Specifications on page 77 provides information about the system requirements including the environmental requirements and the power requirements.
13
Chapter 8, Data Sheets and Agency Approvals on page 79 provides information about the data sheets, standards, and specifications for the technology designed into PCE385. This chapter also provides the agency approvals for the PCE385. Chapter 9, Product Safety on page 85 provides information about safety precautions for the PCE385.
Related Documents
The PCE385 assembly should be used in conjunction with the Performance Technologies software package that you have chosen, for example:
NexusWare Core NexusWare C7 HDLC Frame Relay X.25
This product is compatible with the complete suite of Performance Technologies software. Documentation to support the additional components that you purchased from Performance Technologies is available on the documentation CD. The most current documentation can be located at http://www.pt.com under the product you are inquiring about.
Text Conventions
Table 1-1: Conventions in This Guidedescribes the text conventions and the graphic conventions that are used in this guide. Table 1-1: Conventions in This Guide Convention
Monospace font
Bold font
Used For
Monospace font represents sample code. Bold font represents: paths file names UNIX commands user input.
Italic font
Italic font represents: notes that supply useful advice supplemental information referenced documents.
$ARCH <> ALL CAPITALS
This symbol represents the processor architecture, currently this architecture is ppc, mips, arm, and i386. Angle brackets represent variables such as file names and passwords. All capitals represent keys on the keyboard (for example, ENTER, TAB, and SPACEBAR keys).
14
Customer Support and Services
Customer Support and Services

Performance Technologies offers a variety of standard and custom support packages to ensure customers have access to the critical resources that they need to protect and maximize hardware and software investments throughout the development, integration and deployment phases of the product life cycle. If you encounter difficulty in using this Performance Technologies, Inc. product, you may contact our support personnel by:
1. EMAIL (Preferred Method) Email us at the addresses listed below or our online email support form. Outline your problem in detail. Please include your return email address, and a telephone number. 2. TELEPHONE Contact us via telephone at the number listed below, and request Technical Support. Our offices are open Monday to Friday, 8:00 a.m. and 8:00 p.m. (Eastern Standard Time).
Performance Technologies Support Contact Information Embedded Systems and Software (Includes Platforms, Blades, and Servers) Email Email Form Phone
support@pt.com http://www.pt.com/support/ emailtechsupport.html +1 (585) 256-0248 (Monday to Friday, 8 a.m. to 8 p.m. Eastern Standard Time) +1 (585) 256-0248 (Monday to Friday, 8 a.m. to 8 p.m. Eastern Standard Time)
SS7 Systems (Includes SEGway)

ss7support@pt.com
If you are located outside North America, we encourage you to contact the local Performance Technologies distributor or agent for support. Many of our distributors or agents maintain technical support staffs.
Customer Support Packages

Our configurable development and integration support packages help customers maximize engineering efforts and achieve time-to-market goals. To find out more about our Customer Support packages, visit http://www.pt.com/support/.
Other Web Support

Support for existing products including manuals, release notes, and drivers can be found on specific product pages at http://www.pt.com. Use the product search to locate the information you need.
Return Merchandise Authorization (RMA)

To submit a return merchandise authorization (RMA) request, complete the online RMA form at http://www.pt.com/support/RMA_Request_Form.doc and follow the instructions on the form. You will be notified with an RMA number if your return request has been approved. Shipping information for returning the unit to Performance Technologies will be provided once the RMA is issued.
15
Product Warranty
Performance Technologies, Incorporated, warrants that its products sold hereunder will at the time of shipment be free from defects in material and workmanship and will conform to Performance Technologies applicable specifications or, if appropriate, to Buyers specifications accepted by Performance Technologies in writing. If products sold hereunder are not as warranted, Performance Technologies shall, at its option, refund the purchase price, repair, or replace the product provided proof of purchase and written notice of nonconformance are received by Performance Technologies within 12 months of shipment, or in the case of software and integrated circuits within ninety (90) days of shipment and provided said nonconforming products are returned F.O.B. to Performance Technologiess facility no later than thirty days after the warranty period expires. Products returned under warranty claims must be accompanied by an approved Return Material Authorization number issued by Performance Technologies and a statement of the reason for the return. Please contact Performance Technologies, or its agent, with the product serial number to obtain an RMA number. If Performance Technologies determines that the products are not defective, Buyer shall pay Performance Technologies all costs of handling and transportation. This warranty shall not apply to any products Performance Technologies determines to have been subject to testing for other than specified electrical characteristics or to operating and/or environmental conditions in excess of the maximum values established in applicable specifications, or have been subject to mishandling, misuse, static discharge, neglect, improper testing, repair, alteration, parts removal, damage, assembly or processing that alters the physical or electrical properties. This warranty excludes all cost of shipping, customs clearance and related charges outside the United States. Products containing batteries are warranted as above excluding batteries. THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES WHETHER EXPRESS, IMPLIED OR STATUTORY INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS. IN NO EVENT SHALL PERFORMANCE TECHNOLOGIES BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES DUE TO BREACH OF THIS WARRANTY OR ANY OTHER OBLIGATION UNDER THIS ORDER OR CONTRACT.
16
Chapter
2
Introduction
Overview
The PCE335 is a four-channel T1/E1/J1 communications processor for Peripheral Component Interconnect (PCI) Express based systems.This product uses the PCI Express bus for host processor communications and control. The product provides a high performance, fully channelized platform for use in both datacom and Telecom applications. The PCE385 can run protocols such as Frame Relay, Integrated Services Digital Network (ISDN), or any protocol using High-Level Data Link Control (HDLC) in Internet/Wide Area Network (WAN) environments. In Telecom applications, the PCE385 supports Message Transfer Part (MTP) level two on all four links. Time Division Multiplexing (TDM) line interface connections are made using four RJ-48C connectors on the front panel. The core of the PCE335 is a Freescale MPC8280 PowerQUICC II communications microprocessor running at 450 MHz. This microprocessor includes an embedded Communications Processor Module (CPM) that uses a 32-bit Reduced Instruction Set Computer (RISC) controller residing on a separate local bus. The CPM instruction set is optimized for communications, moving the task of handling lower level communications and Direct Memory Access (DMA) activity off of the PowerPC core Central Processing Unit (CPU). Topics in this chapter include:
Operational Overview on page 18 PCE385 Board Layout on page 20 PCI Express Slots on page 24
17
Operational Overview
The PCE385 supports the following three modes of processing (see Figure 2-1: "Operational Overview Diagram"):
Processing on the PCE385 Board Processing on the Host Processing on the H.100-Compatible Board
Figure 2-1: Operational Overview Diagram
PCE385
In/Out
Optional Configurations
RJ-48
Hardware Determined In/Out
RJ-48 T1/E1/J1 LIU/Framer

In/Out
H.100 Switch
H.110 Bus through Cable
Other H.100-Compatible Card
RJ-48
Power PC Processor DMA
PCI to PCI Express Bridge
Application Determined
In/Out
RJ-48 Board SDRAM Host PC
Processing on the PCE385 Board

Processing on the PCE385, where the processing of packets takes place solely on the PCE385, is the normal configuration. Table 2-1: Data Flow in Processing on the PCE385 Board describes the flow of the data. Table 2-1: Data Flow in Processing on the PCE385 Board Number
1 2 3 4 5
Path / Operation
Line-in to LIU/Framer LIU/Framer to H.100 Switch H.100 Switch to PowerPC Processor PowerPC Processor to SDRAM SDRAM to PowerPC Processor
Output Data Type / Description

Line data TDM data (Framer converts line data to TDM data) TDM data 1 TDM data (processor sets up peripherals and sends data for storage) TDM data (data returns to processor when SDRAM buffer is full)
18
Operational Overview
Table 2-1: Data Flow in Processing on the PCE385 Board (Continued) Number
6 7 8
Path / Operation
PowerPC to H.100 Switch H.100 Switch to LIU/Framer LIU/Framer to Line-out

TDM data TDM data Line data (Framer converts TDM data to line data as T1/ E1/J1)
1. The H.100 switch can either send it, using an H.100 cable, over the H.100 bus to another H.100-compatible board or forward it to the PowerPC Processor.
For a visual representation of this process, see Figure 2-1, Operational Overview Diagram on page 18.
Processing on the Host

The PCE385 processing on the host computer, where some processing of packets takes place on the Host computer, uses both the PCE385 board and the Host computer. Table 2-2: Data Flow in Processing on the Host describes the flow of the data. Table 2-2: Data Flow in Processing on the Host Number
1 2 3 4 5 6 7 8 9
Path / Operation
Line-in to LIU/Framer LIU/Framer to H.100 Switch H.100 Switch to PowerPC Processor PowerPC Processor to SDRAM SDRAM to PowerPC Processor DMA SDRAM to PowerPC Processor DMA PowerPC DMA to PCI Bridge PCI Bridge to Host PC Host PC to Ethernet or Other On-host action 1

Line data TDM data (Framer converts line data to TDM data) TDM data TDM data (processor sets up peripherals and sends data for storage) TDM data (data returns to processor when SDRAM buffer is full) TDM data TDM data Line data (Framer converts TDM data to line data Line data
1. Other On-host action might include, transfer to other board, pass to alternative location with packets or return trip back to originating Line-in/Line-out.
19
Processing on the H.100-Compatible Board

The PCE385 processing on the H.100-compatible board, where the processing of packets takes place on the H.100-compatible board, uses both the PCE385 board and the H.100compatible board. Table 2-3: Data Flow in Processing on the H.100-Compatible Board describes the flow of the data. Table 2-3: Data Flow in Processing on the H.100-Compatible Board Number
1 2 3
Path / Operation
Line-in to LIU/Framer LIU/Framer to H.100 Switch H.100 Switch to H.100-compatible board

Line data TDM data (Framer converts line data to TDM data) TDM data over H.100 cable (H.100 bus)
PCE385 Board Layout

Warning: Use anti-static grounding straps and anti-static mats when you are handling the PCE335 to help prevent damage due to electrostatic discharge. Electronic components on printed circuit boards are extremely sensitive to static electricity. Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment. The PCE385 includes the following two boards:
Main Board Component Layout Daughter Board Component Layout
Main Board Component Layout

This section describes the principal components of the PCE385 main board (see Table 2-4: PCE385 Main Board Component Layout Call Out Definitions and Figure 2-2, PCE385 Main Board Component Layout on page 21). Table 2-4: PCE385 Main Board Component Layout Call Out Definitions Call Out Letter
A B C D E 20
Item
PowerQUICC II MPC SDRAM Chips Daughter Board Interface Connector JTAG Testing Port PCI6466
Description
PowerPC 455 MHz CPU, 300 MHz CPM, 100 MHz Bus 64-bit data width, 128 MB,7.5 ns Electronic connection point for the daughter and main board JTAG port for the on board In-system Programmable CPLD. PCI/PCI express nontransparent bridge
PCE385 Board Layout
Table 2-4: PCE385 Main Board Component Layout Call Out Definitions (Continued) Call Out Letter
F G H I
Item
MPC8280 COPS Header Option Jumper Block Boot Prom PEX8111
Description
COPS Header for JTAG debugging of the CPU Configuration header (see Table 6-4, Option Jumper Block (P3) Pinout on page 73) 512 K x 8 Flash memory device that contains the CPU bootstrap code PCI/PCI express transparent bridge
Figure 2-2: PCE385 Main Board Component Layout
21
Daughter Board Component Layout

This section describes the principal components of the PCE385 daughter board (see Table 2-5: PCE385 Daughter Board Component Layout Call Out Definitions and Figure 2-3, PCE385 Daughter Board Component Layout on page 22. Table 2-5: PCE385 Daughter Board Component Layout Call Out Definitions Call Out Letter
A B C D E F G H
Item
Framer TDM Switch User Defined Switches H.100 Connection Micro 9-pin D Console Port Connection JTAG Connection Main Board Interface Connector RJ-48C Connectors
Description
T1/E1/J1 Framer H.100 TDM Compatible Switch Application assigned values Connection for H.100 cable Console port for hardware, software and application statuses Programs PALs and Runs JTAG test for Hardware debug Electronic connection point for the daughter and main board T1 Interface Connections
Figure 2-3: PCE385 Daughter Board Component Layout
22
PCE385 Board Layout
Front Cover Plate

Installing and setting up the PCE385 requires working with the front cover plate (see Figure 2-4, PCE385 Front Cover Plate Components on page 23.) Figure 2-4: PCE385 Front Cover Plate Components
RJ-48C Jacks
Console Port Connection
23
PCI Express Slots

The PCI Express vertical card-edge connectors are specified for Link widths of x1, x4, x8 and x16. These are not compatible with prior PCI interface standards such as PCI and PCI-X. Figure 2-5: "Types of PCI and PCI Express Slots on a PC Main Board" provides examples of the different types of PCI and PCI Express slots. The PCE385 edge connector utilizes an X1 lane interface. This is capable of up-plugging; that is, it may be inserted into an X2, X4, X8 or X16 slot. Installation is not restricted to an X1 slot. Further details are provided in PCI Express Interface on page 37 Figure 2-5: Types of PCI and PCI Express Slots on a PC Main Board
PCIe Slot Details

PCIe is a high-speed bidirectional peripheral interconnect that includes both a protocol and a layered architecture that has higher data transfer rates than the original PCI bus. PCIe carries data in packets along two pairs of point-to-point data lanes, compared to the single parallel data bus of traditional PCI that routes data at a set rate. Bit rates for PCI Express reach 1.25 Gbps per lane direction, which equates to data transfer rates of approximately 400 MBps per lane. The PCIe bus replaced the standard PCI bus when computer processor speeds started to exceed the capabilities of the PCI architecture. The PCI is a shared parallel bus architecture, the PCIe is a high speed serial switched architecture.
Note: Sometimes abbreviated PCX, PCI Express is not the same as PCI-X. Because the abbreviations can be confusing, the accepted usage is PCI-E or PCIe.
24
Chapter
3
Installation
Overview
This chapter provides information required to install the PCE385 in a PCIe slot on a PC. Topics in this chapter include:
Unpacking the System on page 25 Installing the PCE385 on page 25
Unpacking the System

Caution: If the packing container looks damaged, immediately contact the company responsible for the shipping and report the damage before opening and unpacking the container. It is recommended that you also notify Performance Technologies Customer Support (see Customer Support and Services on page 15).
Before you connect your system and install the software, verify using the packing slip that you received all the components. If you are missing any of the components shown on the packing slip, contact your Performance Technologies Sales Representative immediately.
Installing the PCE385

This section contains installation information for the PCE385 board.
25
Warning: Make sure that the computer is turned off and the power cord is detached from the host chassis prior to installing the PCE385 board. Attempting to install the PCE385 in a computer chassis that has the power still active could result in electrical shock causing serious injury or death. Warning: Use anti-static grounding straps and anti-static mats when you are handling the PCE335 to help prevent damage due to electrostatic discharge. Electronic components on printed circuit boards are extremely sensitive to static electricity. Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment.
Use the following procedure to install the PCE385 in a computer chassis. 1. Turn off the power for the computer on which you are installing the PCE385. 2. Remove the rear cover or side panel that allows access to the inside of the computer by removing the retaining screws or other cover lock down devices. 3. Locate an empty PCI Express slot and remove the corresponding slot cover plate from the outside of the PC chassis. Note that the PCE385 is capable of up-plugging. See PCI Express Slots on page 24 for information about PCIe slots and up-plugging. 4. Line the PCE385 board up with the slot and press the PCE385 into the PCI Express slot with the cover plate end of the board over the edge of the main board. Use caution when pressing so you do not snap the board (see Figure 3-1, PCE385 Insertion Diagram on page 27). 5. Use the retaining screw that was with the cover plate and screw the board cover plate to the chassis.
This step secures the board to the chassis and prevents the board from moving. When you are finished this step, the PCE385 is installed. You can now apply power to the PC and the PCE385 is ready for application development.
26
Installing the PCE385
Figure 3-1: PCE385 Insertion Diagram
27
28
Chapter
4
Development Environment
Overview
This chapter provides information about the board memory, interface, features, flash memory, operating modes, and Framer and LIU information required to develop applications. This chapter also provides information about the JTAG/BDM Debug port and the Console port.
Note: The information contained in this chapter should be used in conjunction with the software you purchased from Performance Technologies.
Topics in this chapter include:

PCE385 Architectural Overview on page 30 Reset Logic on page 32 Memory Map on page 34 Communication Processor Interrupt Sources on page 35 JTAG Support on page 36 SDRAM on page 36 PCI Express Interface on page 37 Features from PEX8111 on page 38 Boot Flash Memory on page 41 H.100 Clock Operating Modes on page 48 E1/T1/J1 Quad Framer and LIU on page 52
29
PCE385 Architectural Overview

The PCE385 is composed of a PCI Main Board and a Mezzanine Board. See Main Board on page 31 and Mezzanine Board on page 31. See Figure 4-1. Figure 4-1: PCE385 Architectural Block Diagram
Mezzanine Card
Jx
H.100 CT Bus
QUAD RJ48C for T1/E1/J1 On Front Panel
Port 1
Port 2
Port 3
Port 4
T1-1 to T1-4 Part of Micro-DB9 Connector
Ext LVDS Pair
Clock Mux Logic
Termination and Line Fault Protection
/16
1.544 MHz Precision Clock Source
ZARLINK MT90866 H.100 Switch
Port 1
Port 2
Port 3
Port 4
Payload Data 192/256 192/256 T1/E1/J1 Quad LIU and Framer
Switches
/8 Board Mount Status LED

/8 or /16 Bit Buffered Bus
General Purpose Logic and Registers
SMC1
Console RS232 port
Fron Panel Micro-DB9 Connector
192/256 192/256
/8
General Inputs
General Purpose Logic and Registers MPC8280 450/300/100 !POR
/8
Boot FLASH 512K x 8 Power Control Logic ee-PROM Non-Volatile Storatge PCI 32 Bit 50MHz 64 bit 100 MHz 60x Bus
Power On Reset and Control Logic
/8
Application FLASH 16M x 8
60x to Local Bus Buffer
ee-PROM Boot code
ee-PROM Boot code
PLX PCI6466 Non-Transparent PCI Bridge
Local PCI Bus
Board Mounted SDRAM up to 128Mbytes
PLX PEX8111 PCI Express to PCI Bridge
PCI Express
30
PCE385 Architectural Overview
Main Board
The PCE385 main board contains all of the active components relating to PowerQUICC II communications microprocessor core operations, including the:
Communication processor SDRAM memory Boot and Application Flash PCI bus interface General control and option register logic
For information about the logic on this board, refer to the Freescale MPC8280 Users Manual.
Mezzanine Board
The PCE385 mezzanine I/O board provides the:
T1/E1 LIU and Framer H.100 Controller receiver and transmitter metallic connectors (RJ-48C) passive components including the telephony line protection
T1/E1 LIU and Framer

The on-board T1/E1 LIU and Framer receives and transmits framed serialized T1/E1/J1 bit streams, recover timing information, and demultiplex the T1/E1 data directly to the DS-0 level. The result is that 192/256/192 T1/E1/J1 DS-0 timeslots can be terminated in different manners. The data can be passed to the PCI bus as terminated data or to the H.100 bus as DS-0s in a TDM stream. During receive, the LIU and Framers accept T1/E1 or J1 bipolar signals, perform equalization, convert the signals into binary digital data streams, receive frame synchronization, data recovery, frame overhead extraction, and provide data connection paths to the various onboard terminating interfaces using the H.100 controller. During transmit, the LIU and Framers accept digital data from one of the terminating interfaces through the H.100 controller. The LIU and Framers perform frame generation overhead insertion, and convert the digital clock and data to the appropriate wave shapes for transmission as bipolar T1/E1 or J1 streams.
H.100 Controller
The H.100 controller interfaces the T1/E1 LIU and Framers to the TDM of the MPC8280 processor. Each local time slot can be assigned to any of the possible 4096 H.100 external time slots or reassigned to any other local time slot. These possible time slots are based on the memory locations in the TDM switch to accommodate all of the time slots (DS0s) on the H.100 backplane (ribbon cable). The calculation is derived from 32 DS0s max per frame x 4 individual T1 or E1 connections muxed to the backplane per H.110/H.100 data bit x 32 data bits per H.100/H.110 backplane.
31
The PowerQuicc II CPM implements channel routing and time division multiplexing (TDM) to its internal communications controllers using its Internal Timeslot Assigner (TSA). Data can be routed to and from the various CPM communications controllers. The controllers used in the PCE385 application include:
Two multi-channel communications controllers (MCC) One fast communications controller (FCC) Advanced CPM protocol specific functions, controlled by internal and downloadable firmware
Reset Logic
The reset logic for the PCE385 includes five major resets caused by the external PCI Express bus. They are:
Power On Reset Hard Reset Soft Reset PCI Express Interface Resets Peripheral Resets
Table 4-1: Reset Priorities describes the priorities for the on-board resets. Table 4-1: Reset Priorities PORESET PORESET HRESET SRESET PCIEXPRST PCI6466RST
------X ---
HRESET
X ----X X
SRESET
X X --X X
PCIRST
------X ---
H100RST
X X X X X
QFALCRST
X X X X X
Power On Reset
The power on reset signal, PORESET#, is asserted by the baseboard Control Logic PAL in response to a PCI Express reset.
Hard Reset
The hard reset signal, PQ_HRESET#, is generated by the PowerQUICC II communications microprocessor. The communication processor generates PQ_HRESET# in response to any of the following (when enabled):
Power on reset Software watchdog reset Bus monitor reset Checkstop reset
32
Reset Logic
Soft Reset
The soft reset signal is accomplished by asserting the PQ_SRESET# signal. The signal is distributed to the MPC8280, Control logic PAL, the P9-A2 Analyzer Connector and the COP8 JTAG header for the debug port. The signal sources for PQ_SRESET# include the MPC8280 and the debugger port. The MPC8280 asserts this signal in response to any power on reset or hard reset condition. The effect of soft reset on the processor differs from the power on reset or hard reset and it is outlined in the Freescale MPC8280 Users Manual in the Reset chapter.
PCI Express Interface Resets

The PEX8111 receives primary resets from the PCI Express Root Complex on the PCI Express bus by the PCE_PERST# signal. This reset input is buffered on the board, and sent to the mainboard Control Logic PAL and the PEX8111. The PEX8111 interprets this signal as a Fundamental Reset. The Fundamental Reset resets all of the PEX8111 internal logic and it initializes the rest of the PCE385 logic to the Power On Reset condition. This condition remains on the MPC8280 as long as the PCE_PERST# signal is asserted to the board. The PEX8111 supports Hot Reset due to Link training Control Reset, which is a primary reset due to the physical layer mechanism. This reset causes all transactions on the PCI Express side of the interface to stop and all of the cycle state machines to reset. The PEX8111 also supports Primary Reset due to Data Link Down in a similar manner. All of these reset conditions generate a primary PCI Reset (PRI_PLX_PCIRST#) downstream to the PCI6466. For a complete description of the primary PCI Express reset on the PEX8111, refer to the PLX PEX 8111 PCI Express-to-PCI Bridge Data Book. The PCI6466 has primary and secondary PCI resets. The primary PCI reset (PRI_PLX_PCIRST#) is driven into the PCI6466 by the PEX8111. Receipt of this signal by the PCI6466 causes the PCI6466 primary PCI bus to take a fundamental reset. In addition, the PCI6466 issues a secondary PCI reset (S_PCI_RSTOUT#) as long as the primary input is true. The S_PCI_RSTOUT# signal is connected to the Control Logic PAL and it causes a power on reset pulse to be applied to the MPC8280. This reset is caused by receipt of the primary PCI reset and by a bit in one of two registers in the PCI6466. The registers are the Diagnostic Control register Chip Reset and Bridge Control Secondary Reset (Nontransparent mode DCNTRL[0]=1; PCI:D9h and BCNTRL[6]=1; PCI:42h, respectively). S_RSTOUT# remains asserted until the SecondaryReset Output Mask bit is cleared (Nontransparent mode DCNTRL[3]=0; PCI:D9h). This method is the preferred method to cause a Software Reset of the PCE385.
Peripheral Resets
Each peripheral chip on the PCE385 has an individual reset line. The peripheral resets are driven by the daughter board PAL logic. The resets are all set to a reset state by anything that creates PQ_SRESET # on the PCE385 board. The devices are held in reset until the appropriate bit in the general-purpose registers is set. Table 4-2, Peripheral Resets on page 34 describes the individual peripheral reset signals, the power up reset state and the bit that controls the device in the general-purpose registers.
33
The PCE385 has a Freescale MPC8280 Communications Processor Unit (CPU) on the main board portion of the assembly. This CPU is the primary controller on the PCE385. The CPU provides the PowerPC CPU core, the Communications Processor Module (CPM), and the 60X bus processor bus controller. The CPU controls the Synchronous DRAM (SDRAM) and the PCI side of the PEX8111 PCI Express Interface Controller by its direct connections. The CPU also controls all of the on-board peripheral chips by a buffered data and address bus. Table 4-2: Peripheral Resets Peripheral
H.100 Switch Quad FALC 1
Reset Signal Name

!H100_RST !QFALC1_RST
PQ_SRESET# State
0 0
Register Bit Name

h100_rst-n qfalc1_rst_n
Memory Map
The memory map is defined by the PCE385 Address Decode Scheme. There are several levels of Address Decode built into the PCE385. The first level and primary decode is performed by the System Interface Unit (SIU) of the communication processor. One of the SIU subsections is the memory controller. The memory controller is responsible for controlling a maximum of twelve memory banks shared by a high performance SDRAM machine, a General-Purpose Chip-select Machine (GPCM). This GPCM supports several types of interface to Synchronous DRAM (SDRAM), EPROM, Flash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals. This flexible memory controller allows the implementation of memory systems with very specific timing requirements.
The SDRAM machine provides an interface to synchronous DRAMs, using SDRAM pipelining, bank interleaving, and back-to-back page mode to achieve the highest performance. The GPCM provides interfacing for simpler, lower-performance memory resources and memorymapped devices. The GPCM has inherently lower performance because it does not support bursting. For this reason, GPCM-controlled banks are used primarily for boot loading and access to lowperformance memory-mapped peripherals.
The primary control of the devices served by the memory controller is through the communication processor external Chip Select lines. The specific memory controller set ups are defined for each type of device in the section of the specification that describes the device. Table 4-3: MPC8280 Chip Select Assignments represents the primary address decode of the external chip select lines. Table 4-3: MPC8280 Chip Select Assignments Chip Select Line
CS#0 CS#1 CS#2 CS#3 CS#4
Controlled Device
Flash Boot PROM SDRAM Not Used Application Flash PAL General Purpose Registers
Address Range
FFF0_0000 to FFF7_FFFF h 0000_0000 to 07FF_FFFF h
1000_0000 to 10FF_FFFF h 2000_0000 to 2000_00ff h
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Communication Processor Interrupt Sources
Table 4-3: MPC8280 Chip Select Assignments (Continued) Chip Select Line
CS#5 CS#6 CS#7 CS#8 CS#9 CS#11 None
Controlled Device
QUAD FALC H.100 Switch Chip Not Used Not Used Not Used Not Used PEX8111 mapped space
Address Range
2010_0000 to 2010_7FFF h 2020_0000 to 2020_7FFF h
2030_0000 to 2030_7FFF h 2040_0000 to 2040_7FFF h
Communication Processor Interrupt Sources

Several multifunction pins are used to supply the communication processor with the interrupts from the various direct-connect board peripherals. The !IRQ0 to !IRQ7 lines are used along with some of the port C interrupt-capable pins. The interrupt sources, for the most part, have multiple interrupt conditions. For complete information about interrupt causes, refer to the individual component subsections or the component user manual. Table 4-4: Communication Processor Interrupt Sources provides information about the connections from the peripheral devices to the communication processor. Table 4-4: Communication Processor Interrupt Sources IRQ Level
!IRQ0 !IRQ1 !IRQ2 !IRQ3 !IRQ4 !IRQ5 !IRQ6 !IRQ7 PC0 PC1 PC2 PC3
Pin Number
T1 A22 E21 D21 C21 B21 A21 E20 AB26 AD29 AE29 AE27
Controlled Device
NMI Interrupt from the Abort Jumper P3-4 to P3-5 Quad FALC 1 General Interrupt Not Used Not Used PEX8111 General Interrupt H.100 Switch FAIL_A, FAIL_B, LREF0 and LREF1 Fail Not Used Not Used Not Used Not Used Not Used Not Used
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JTAG Support
The JTAG testing port on the MPC8280 supports the EST Common On-chip Processor (COP) debugger on the P4 connector. This connector supports the extended 16-pin COP debugger signaling, but the basic 10-pin signaling devices can be used with an interposing adapter. Table 4-5: JTAG P4 Pinouts provides information about JTAG P4 pinouts. Table 4-5: JTAG P4 Pinouts Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Signal Name
PQ_TDO - JTAG Test Data Out Signal !PQ_QACK- Quiescent State Acknowledge, not supported PQ_TDI- JTAG Test Data In signal !PQ_TRST- JTAG Reset and Tristate signal !PQ_QREQ - Quiescent State RequestV3V PQ_TCK - JTAG Test Clock No Connection PQ_TMS-JTAG Test Mode Select No Connection PQ_SRESET# - MPC8280 Soft Reset Ground PQ_HRESET# - MPC8280 Hard Reset No Connection !CHKSTPO - Checkstop output, Not supported Ground
Note: All of the control signals are terminated to prevent false assertion when no JTAG controller is connected.
SDRAM
The Synchronous Dynamic Random Access Memory (SDRAM) memory bank has individual chips mounted on the component and circuit sides of the base board. The SDRAM architecture provides the ability to:
burst data, synchronously, at a high data rate with automatic column address generation interleave between internal banks in order to hide PRECHARGE time randomly change column addresses on each clock cycle during a burst access
The total SDRAM memory is 128 MB. This SDRAM memory is arranged in four parallel bytes to give the data bus a 64-bit total width. The integral SDRAM controller takes care of all low level SDRAM operations including row and column multiplexing, precharge times, and refresh.
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PCI Express Interface

The PCE385 uses a PCI to PCI Express Bridge to gain connectivity to the PCI Express Root Complex. This Root Complex connects through the PCI Express connector located on the lower edge of the assembly. The PCI Express interface, a PLX PEX8111, is used in its forward mode relative to the PCI Express Root Complex. The interface is also configured in the Transparent mode relative to the root complex. The PEX8111 translates all accesses to and from the Root Complex into local 32-bit PCI accesses. These accesses are passed to a nontransparent PCI-PCI bridge (PCI6466) before they are presented to the MPC8280 on-board CPU. The nontransparent bridge allows the board assembly to hide the fact that there is a private PCI bus behind the bridge. The nontransparent mode also allows the PCE385 to identify itself to the ROOT complex with a PTI Device and Vendor ID. This configuration allows the operating system to recognize the board and load the correct system drivers. The following sections describe the interface, the two bridge connections, and the modes of operation:
Physical Layer (Layer 1) Data Link Layer (Layer 2) Transaction Layer (Layer 3) Forward Mode Transparent Mode Nontransparent Mode
Physical Layer (Layer 1)

Layer 1, the Physical Layer (PHY) defines the electrical characteristics of PCI Express. This layer is the basic transmission unit, which consists of two pairs of wires, called a lane. Each pair allows for unidirectional data transmission 1.25 Gbps, so the two pairs combined provide 2.5 Gbps full-duplex communication, without the risk of transmission collision.
Data Link Layer (Layer 2)

Layer 2, the Data Link Layer (DLL) defines the data control for PCI Express. This data link layer provides link management and data integrity, including error detection and correction. The layer calculates and appends a Cyclic Redundancy Check (CRC) and a sequence number to the information sent from the data packet. The CRC verifies that data has been transmitted correctly from link to link. The sequence number allows proper ordering of the data packets.
Transaction Layer (Layer 3)

Layer 3, the Transaction Layer (TL) connects the lower protocols to the upper layers. This Transaction Layer appears to the upper layers of the PCI. The Transaction Layer packetizes and then pre-appends a header to the payload data. This layer also includes the read and write commands and prior sideband signals (for example, interrupts and power management requests). To achieve code compatibility with PCI, PCI Express does not modify the transaction layer.
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Forward Mode
In Forward Mode, the configuration cycles originate from the PCI Express link through the bridge chip and then to the PCI Bus segment.
Transparent Mode
In addition to operating as a forward bridge, PEX8111 also operates as a transparent bridge (through pin strap). In Transparent Mode, the bridge electrically isolates the two domains (PCI Express and PCI) while preserving the command and addressing functions of the transaction.
Nontransparent Mode
The PCI6466 bridge operates as a nontransparent bridge (through pin strap). In Nontransparent Mode, the bridge isolates processor domains on each side by providing a Type 0 Configuration Header to each CPU on either side of the bridge. Data is transferred between the domains through the bridge using address translation. This transfer can occur in either the upstream or downstream direction. As a nontransparent bridge, configuration accesses occur on both the PCI bus and the PCI Express port. There are two hosts in this configuration and each can access or send data to devices on both sides of the bridge. Each host has its own memory map for the devices to which it has access.
Features from PEX8111

In the PCE385 implementation the PEX8111 supports these features:
PCI Express Interface (one port and one lane interface) 2.5 Gbps transfer rate external RefClk input external PERST# input one-lane status indicators PCI interface JTAG interface 32-bit support clock rates of up to 66 MHz
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Features from PEX8111

The PCE385 is configured as x1 interface on the PEX8111 PCI Express board interface connector. Table 4-6: PEX8111 PCI Express Connections describes the interface signals that are supported on the PCI Express connector. Table 4-6: PEX8111 PCI Express Connections PCI Express Pin Number
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
Signal
PRSNT1# +12v +12v GND JTAG2# JTAG3# JTAG4# JTAG5# 3.3V 3.3V PERST# GND REFCLK+ REFCLKGND PERp0 PERn0 GND +12v +12v RSVD GND SMCLK SMDAT GND 3.3V JTAG1# 3.3Vaux
Description
Hot Plug presence detect +12V power +12V power Ground TCK, Test Clock, not used TDI, Test Data Input, not used, looped to TDO TDO, Test Data Output, not used looped to TDI TMS, Test Mode Select, not used 3.3V Power 3.3V Power PCI Express Fundamental Reset Ground Reference Clock differential pair
Ground Receiver differential pair, Lane 0
Ground +12V Power +12V Power Reserved Ground SMBus clock SMBus data Ground 3.3V Power JTAG Test Reset, not used. 3.3V auxiliary power, not used. 39
Table 4-6: PEX8111 PCI Express Connections (Continued) PCI Express Pin Number
B11 B12 B13 B14 B15 B16 B17 B18
Signal
WAKE# RSVD GND PETp0 PETn0 GND PRSNT2# GND
Description
Signal for Link Reactivation, not used. Reserved Ground Transmitter Differential Pair Lane 0
Ground Hot Plug Presence Detect Ground
JTAG Interface
The JTAG interface (see Figure 4-2: "JTAG Interface") on the PEX8111 is bypassed on the connector to preserve the remaining external chain. Figure 4-2: JTAG Interface
BUF_A[0-18]
BOOT FLASH EPROM 29LV040-90 512Kx8

BUF_AD[0-7] !CS_FLASHB !BUF_WR !BUF_RD
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Boot Flash Memory
Boot Flash Memory

The Boot Flash Erasable Programmable Read Only Memory (EPROM) is used to store the initial startup code for the CPU of the PCE385 (the MPC8280). This EPROM is socketed and mounted on the base board at position U11. The Boot Flash is a nonvolatile memory that has the following general characteristics. The Boot Flash EPROM is a single power supply, 4 Mbit, 3.0 Volt-only Flash memory device organized as 524,288 bytes. The data appears on DQ0-DQ7 of the buffered memory bus.
The device is in a 32-pin PLCC package. All read, erase, and application operations are accomplished using only a single power supply. Internally generated and regulated voltages are provided for the application and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
The Boot Flash EPROM is accessed by the MPC8280 through the Buffered Data bus. This Buffered Data bus supplies a buffered MPC8280 address and a bidirectional 8-bit or 16-bit data bus. The MPC8280 provides the CS_FLASHB#, which acts as the device chip enable. The Control Logic PAL logic provides the !BUF_RD, which acts as the device output enable and !BUF_WR, which acts as the write enable. The PCE385 has a write protect feature that does not allow the !BUF_WR signal to activate unless the flash_wp bit is set in the General Purpose registers. After a reset, writing to the Boot Flash EPROM is disabled, by default. The the GCPM wait state programming provides the timing for the read and write cycle. The Boot Flash EPROM does not generate any cycle termination signal. This section provides information about:
General Boot Flash Information Application Flash Memory General Application Flash Information TDM Clock Distribution and Control H.100 DPLL Internal Reference Clock Sources Internal Reference Monitors CT Clock and Frame Monitor Circuits External Reference Clock Sources External Reference Clock Source Monitor
General Boot Flash Information

Flash access in the Read mode is done as any normal PROM device. The programming or write operations are entirely command set compatible with the Joint Electron Device Engineering Council (JEDEC) single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data required for the programming and erase operations. Device programming occurs by executing the program command sequence. This sequence initiates the Embedded Program algorithm, which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.
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Device erasure occurs by executing the erase command sequence. This command initiates the Embedded Erase algorithm, an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During an erase operation, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data/Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors using programming equipment. Device hardware data protection measures include a low Common Collector Voltage (VCC) detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. The Erase Suspend feature enables the user to put the erase operation on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
Application Flash Memory

The Application Flash PROM (see Figure 4-3, Application Flash Memory on page 43) stores application code that is not executed at boot time. This Application Flash PROM is permanently mounted to the main board at position U23. The Application Flash is a nonvolatile memory that has the following general characteristics:
A single power supply, 32 MB, 3.0 Volt-only Flash memory device. DQ0-DQ7 on the buffered data bus for Read accesses to the device. 256 blocks of byte wide data storage for writing purposes. Each storage blocks has 128 KB of storage. Common Flash Interface (CFI) and a Scalable Command Set (SCS) blocks perform the writing and erasing. Internally generated and regulated voltages for the program and erase operations. A 64-pin FBGA.
42
Boot Flash Memory
Figure 4-3: Application Flash Memory
General Application Flash Information

Flash access in the read mode is done as any normal PROM device. Selecting, writing and erasing the blocks is done by using a Common Flash Interface (CFI) and a Scalable Command Set (SCS). For information about the command set and the programming strategy, refer to the Intel Spansion S29GL256N MirrorBit Flash Family Datasheet.
TDM Clock Distribution and Control

The TDM clock distribution is centralized about the Zarlink MT90866 H.100 TDM switch located on the mezzanine I/O board. This MT90866 generates all of the local TDM Frame Pulses and data clocks. The MT90866 uses a variety of clock sources to lockup its internal Digital Phase Locked Loop (DPLL) to a system reference. This DPLL lockup ability ensures that the data stays in synchronization with the system and no timing slips occur during data transfers on the board.
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H.100 DPLL
The DPLL is the core of the MT90866. This DPLL is directly driven by a 20 MHz 25 ppm signal as its primary clock input. The DPLL accuracy allows the H.100 switch to function as a Stratum 4 Enhanced clock source when it runs in a free-run mode. In a normal integration into a Telephony system, synchronized timing is maintained by locking the PLL to a system-supplied reference. Table 4-7: H.100 DPLL Operating Specifications provides information about some of the significant DPLL operating specifications. Table 4-7: H.100 DPLL Operating Specifications Parameter
Acceptable Reference Clock Input Frequencies Skew Control
Value
1.544 MHz, 2.048 MHz or 8 kHz per AT&T TR62411 8 taps @ 1.9 ns each, allows 0 to13.3 ns total skew adjustment between reference input and clock outputs. This adjustment translates to static phase offset of 1.28 us to 1.293 us for reference clock input of 1.544 MHz. For a reference clock input of 8 kHz or 2.048 MHz, the static phase offset is 960 ns to 973 ns. For 1.544 MHz reference clock, maximum phase offset +/- 1.28 us, minimum phase adjustment 10 ns. For 8 kHz or 2.048 MHz reference clock, maximum phase offset +/- 0.96 us, minimum phase adjustment 7.5 ns. Maximum phase slope response for input transient 4.6 ns per 125 us. Meets AT&T TR62411 standard. Equivalent to a first order low pass filter with 1.52 Hz cutoff. 6.25 nspp for the 80 MHz master clock. Rate limited by Phase Slope Limiter to 4.6 ns/125 us. Jitter Transfer Function Cutoff frequency 1.52 Hz with slope of 20 db/decade. For the actual curves and the UI calculations, refer to the Zarlink MT90866 Data Sheet Master Clock/ppm + DPLL/ppm= 25+.03=25.03 ppm of selected frequency. Master Clock/ppm + DPLL/ppm= 25+.03=25.03 ppm of selected frequency. +/- 273 ppm 21 ns for every reference switch. Maintained to within 4.6 ns at the instance (over one frame) of all reference switches. Less than 25 seconds
Phase Offset, dependent on reference clock frequency
Phase Slope Limiter Loop Filter Intrinsic Jitter Jitter Transfer
Frequency Accuracy Holdover accuracy Locking Range Maximum Time Interval Error (MTIE) Phase Continuity Phase Lock Time
The DPLL can choose from several input sources to obtain the signal it needs to lock to. This mechanism supplies the system synchronization. These clock sources can be selected either internally using the reference multiplexer (MUX) internal to the part or externally by the mezzanine board Phase Alternation Line (PAL) logic. For additional information, refer to the Zarlink MT9088 WAN Access Switch Data Sheet.
44
Boot Flash Memory
Internal Reference Clock Sources

The internal reference selector multiplexer for the DPLL has a redundant configuration. The primary and secondary muxes both have access to the same set of clock sources. These sources include any of the six local reference inputs, the A and B Computer Telephony (CT) bus clocks or the CT Netreferences from the CT bus.
Internal Reference Monitors

There are two Reference Monitor circuits: one for the primary reference (PRI_REF) and one for the secondary reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting up the adequate internal fail outputs (FAIL_PRI and FAIL_SEC). These fail signals are used in the auto-detect mode as the internal LOS_PRI and LOS_SEC signals to indicate when the reference has failed. The method of generating the failure depends on the selected reference:
The minimum 90 ns check is done for all references. This check is the requirement by the H.100 specifications. The low level and high level of the reference must last for minimum 90 ns each. The period in the specified range check is done for all references. The length of the period of the selected input reference is checked if it is in the specified range. For the E1 (2.048 MHz clock) or the T1 (1.544 MHz clock) reference, the period of the clock can vary within the range of 1 +/- 1/4 of the defined clock period which is 488 ns for the E1 clock and 648 ns for T1 clock. For the 8 kHz reference, the variation is from 1 +/- 1/32 period. The 64 periods in the specified range check is done if the selected reference is E1 or T1. The selected reference is observed for long period (64 reference clock cycles) and checked if it is within the specified range (from 62 to 66 clock periods)
These reference signal verifications include a complete loss or a large frequency shift of the selected reference signal. When the reference signal returns to normal, the LOS_PRI and LOS_SEC signals return to logic low.
CT Clock and Frame Monitor Circuits

These monitor circuits check the period of the C8_A and the C8_B clocks and the FRAME_A and FRAME_B frame pulses. According to the H.100 signal specification, the C8 period is 122 ns with a tolerance of +/-35 ns measured between rising edges. If C8 falls outside the range (87 ns to157 ns), the clock is rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or FAIL_B) becomes high. These two signals are connected to the mezzanine board PAL logic and are two of the inputs that form the H.100 Interrupt to the MPC8280.
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External Reference Clock Sources

These sources include any of the recovered clocks from the quad Framer and Line- interface Component (FALC) or the dual external Low Voltage Differential Signaling (LVDS) clock receivers. The recovered clocks are connected to the mezzanine board PAL logic, which is internally programmed to select one of four recovered T1 clocks from the framers or the Dual External LVDS Clock receivers. There are two of these selectors and they feed the H100_LREF0 and H100_LREF1 signals to the LREF0 and LREF1 inputs on the H.100 chip. NexusWare has provisions that allow the selection of LREF0 or LREF1 as the received clock source. For more information, refer to the NexusWare Core Reference Manual.
External Reference Clock Source Monitor

There is a set of clock monitors (see Figure 4-4, External Clock Monitors on page 47) in the mezzanine board PAL logic that check the external clock sources for validity. The Clock Timer Timeout Period Register contains a clock count value that is used to check for a valid time period for the local reference clocks, which are fed from the mezzanine board PAL select multiplexer to the H.100 Switch chip. The timer value is the maximum number of 20 MHz clocks that are allowed to elapse during the reference clock period. If the 20 MHz count is exceeded without seeing at least one valid local reference clock, the internal lrefxsts bit is set. This signal is one of the sources for the H.100 interrupt to the MPC8280. NexusWare has provisions to automatically setup the timer. For more information, refer to the NexusWare Core Reference Manual.
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Boot Flash Memory
Figure 4-4: External Clock Monitors
1.544 or 2.048 MHz
PSM521 MUX lref0
EXTERNAL LVDS CLOCK INPUT Quad FALC 1 RXC 1-4 PSM521 MUX lref1 PSM521 LREF0/1 and 3 Clock Monitor LREF0/1 Fail Interrupt
QUAD FALC 1
1.544 MHz TXC PSM521 MUX lref3
To PSM521 Interrupt logic
H110_LFREF0 H110_LREF1 Local Clock Source H110_LREF3 !CLK_CNTL_A
Pullup Termination
0
20Mhz Master Clock and Driver
4-7
CT BUS A CLOCKS 8 Mhz 8 MHz 8 KHz A CT Bus Clock Bypass and Termination
Lref 0-7 inputs 20 Mhz
1.544 MHz 8MHz Data Clock Distribution
H.110 Sw itch MT90866
!CLK_CNTL_B
CT BUS
!H110_STCKO Local TDM CLOCKS !H110_STFPO
CT BUS B CLOCKS CT NETREFERENCE CLOCKS
8 MHz 8 KHz
B CT Bus Clock Bypass and Termination
8KHz Frame Pulse Distribution
1.544 or 2.048 MHz 1.544 or 2.048 MHz NETREFO
CTNR1
CT Bus Netreference Driver
Each Clock is 8 Mhz Each Frame Pulse Is 8 KHz MPC8280 CPU
CREF1_OE
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H.100 Clock Operating Modes

Clock distribution and control circuitry support both master and slave modes of H.100 operation. The H.100 switch provides primary and secondary clock and frame synchronization sources for the local TDM streams. These sources are distributed to the MPC8280, E1/T1/J1 framers, PTMC module and clock monitoring circuitry. H.100 backplane clocks CT_C8_A and CT_C8_B are supported at 8 MHz operation exclusively. The local clocks are supported at 8 MHz operation exclusively. In master mode, the H.100 switch accepts two of several local clock references that can be recovered by the E1/T1/J1 framers or generated by an optional local precision oscillator. These clocks can be divided to create an 8 kHz clock reference. These primary and secondary reference clocks are used to drive CTREF1 or CTREF2 to the H.100 backplane for primary or secondary master operation. The reference clocks are also provided to a PLL that generates and drives the CT_FRAME_A or CT_FRAME_B synchronization, and CT_C8_A or CT_C8_B clock, to the H.100 backplane. The selected local reference clocks are monitored and cause an interrupt upon failure. Local status and masking is provided for these interrupt sources. In slave mode, the H.100 switch accepts CTREF1, CTREF2, CT_C8_A and CT_C8_B clocks. One CTREF and one CT_C8 clock are selected for primary operation, while the alternate pair stand-by as secondary clocks. Support is included to allow A-side and B-side source termination resistors on CT_C8_A/B and CT_FRAME_A/B to be bypassed. The A and B side clock and the frame synchronization are monitored by the H.100 switch and failure causes the corresponding FAIL_A or FAIL_B signal to be asserted. This signal is intercepted and provided as an interrupt to the MPC8280. Local status and masking is provided for this interrupt source. A 20 MHz crystal oscillator is distributed to provide a 20 MHz clock for each of the H.100 switch, E1/T1/J1 framers, and general-purpose logic components. These clocks are dedicated clocks without control options. This section provides information about:
CT Netreference Sources H.100 Bus and Digital Switch MT90866 Digital Switch Overview Digital Switch Local TDM Streams Connection
CT Netreference Sources
The H.100 switch can also source the CT bus Netreference signal. The H100_LREF3 signal is supplied to the switch as the reference input for this function. This signal source includes any of the recovered clocks from the Quad FALC or the Dual External LVDS Clock receivers. The recovered clocks are connected to the mezzanine board PAL logic, which is internally programmed to select one of four recovered T1 clocks from the framers or the Dual External LVDS Clock receivers. These external clock sources are configured in NexusWare API. For more information, refer to the NexusWare Core Reference Manual.
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H.100 Bus and Digital Switch

The PCE385 uses the Zarlink MT90866 digital switch to connect the various Time Division Multiplexing (TDM) interface streams together. This digital switch resides on the mezzanine I/O board. The digital switch has local side connections to the MPC8280 TDM I/O and the Quad FALC TDM bus. It connects to the 32 bit H.100 CT Bus on the backplane. The digital switch features:
3.3V operation with 5V tolerant inputs and I/Os 5V tolerant PCI drivers on CT-Bus I/Os 2,432 x 2,432 non-blocking switching among local streams 4,096 x 2,432 blocking switching between backplane and local streams 2,048 x 2,048 non-blocking switching among backplane streams rate conversion between backplane and local streams rate conversion among local streams backplane interface accepts data rate of 8.192 Mbps local interface accepts data rates of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps sub-rate switching (2 or 4 bits) configuration for local streams at a data rate of 2.048 Mbps per-channel variable or constant throughput delay fully compliant to H.100 timing specification per-stream input delay, programmable for local streams on a per bit basis per-stream output advancement, programmable for backplane and local streams per-channel direction control for backplane streams per-channel message mode for backplane and local streams compatible with Stratum 4 Enhanced clock switching standard integrated PLL conforms to Bellcore Stratum 4 Enhanced switching standard holdover mode with hold over frequency of 0.07 ppm wander attenuation from 1.5 Hz Time Interval Error (TIE) correction H.100 Bus Master and Slave mode operation connection memory block programming for fast device initialization tristate control outputs for external drivers Pseudo-Random Binary Sequence (PRBS) pattern generation and testing for backplane and local streams
MT90866 Digital Switch Overview

The MT90866 digital switch (see Figure 4-5, Quad Framer Block Diagram on page 50) provides switching capacities of 4,096 x 2,432 channels between backplane and local streams, 2,432 x 2,432 channels among local streams and 2,048 x 2,048 channels among backplane streams. This digital switch has local connections to serial inputs and outputs that have 32, 64 and 128 64-kbps channels per frame with data rates of 2.048, 4.096 and 8.192 Mbps respectively. The digital switch has backplane connections to serial inputs and outputs have 128 64-kbps channels per frame with data rate of 8.192 Mbps.
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The MT90866 digital switch also offers a sub-rate switching configuration that allows internal switching of two-bit wide 16 kbps data channels or four-bit wide 32-kbps data channels. This digital switch has features that are programmable on a per-stream or per-channel basis including message mode, input delay offset, output advancement offset, direction control, and high impedance output control. The MT90866 digital switch is connected to the TDM peripherals, the CT Bus and the MPC8280. For more information, see Digital Switch Local TDM Streams Connection on page 50. Figure 4-5: Quad Framer Block Diagram
MUXED TDM DATA Line Side Interface X4 LocalTDM Connections RDO1 XDI1
To RJ-48c Telephony Connector
Softw areSelectable T1/E1/J1 Receive Termination and Overvoltage Protection for Each Channel Softw areSelectable Transmit Termination and Overvoltage Protection fo Each Channel
RX1 Tip and Ring TX1 Tip and Ring RX2 Tip and Ring TX2 Tip and Ring RX3 Tip and Ring TX3 Tip and Ring RX4 Tip and Ring TX4 Tip and Ring
Quad FALC T1 E1 J1 Framer

TDM System Clocks x2 Recovered Receive Clocks Interrupt Timer STCKI STFPI RXC 1 RXC 2 RXC 3 RXC 4 !FALC_INT
1.544Mhz 20 Mhz !FALC_RST
T1 Clock x 4 Master Clock
CPU Interface
Buffered 8 Bit Control Address Buffered Signals Bus Data Bus
Digital Switch Local TDM Streams Connection

The H.100-compatible digital switch serves as the focal point for all of the TDM streams from the various on-board peripherals. Table 4-8, Digital Switch Local TDM Streams Connection on page 51 provides more information about peripheral connections. The digital switch local I/O connections are grouped as inputs and outputs. The inputs and outputs are also sub-grouped in four groups. This grouping allows each sub-group to be run at one of the available data rates, 2.048, 4.096 or 8.192 Mbps. Some of the sub-groups also support two-bit and four-bit sub-rate switching when the group is run at the 2.048 Mbps data rate. The local TDM clock is
50
sourced from the DPLL of the digital switch and it is fixed at 8.192 MHz. The DPLL is locked to a system reference, which is programmable and chosen by the system architect. The local Frame Pulse signal is 8 kHz and is also supplied by the DPLL locked to the system reference. Table 4-8: Digital Switch Local TDM Streams Connection provides information about the peripheral connections for the PCE385 and the data rate at which the link operates. Table 4-8: Digital Switch Local TDM Streams Connection Group
Group 1
Device
Input Pulled up Input Pulled up Input Pulled up Input Pulled up
Switch Connection
STi0/STo0 STi1/STo1 STi2/STo2 STi3/STo3 Sti4/Sto4 Sti5/Sto5 Sti6/Sto6 Sti7/Sto7 Sti8/Sto8 Sti9/Sto9 Sti10/Sto10
TDM Data Rate

8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps
Interleaving Format
Group 2
Group 3
Input Pulled up Input Pulled up MPC8280 TDMA through the B1 TDM Port MPC8280 TDMB through the B2 TDM Port
Each DS-0 in the input stream of 127 channels is defined by the MPC8280. Each DS-0 of the output stream is defined by the connection memory. Each DS-0 in the input stream of 127 channels is defined by the MPC8280. Each DS-0 of the output stream is defined by the connection memory 128 DS-0s Bidirectional
Sti11/Sto11
8.192 Mbps
Group 3
QUAD FALC Data Port 0-3 Input Pulled up Input Pulled up
Sti13/ Sto13 Sti14/Sto14 Sti15/Sto15 Sti16/Sto16 Sti17/Sto17 Sti18/Sto18 Sti19/Sto19 Sti20/Sto20 Sti21/Sto21 Sti22/Sto22 Sti23/Sto23
8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps
Group 4
Input Pulled up Input Pulled up Input Pulled up Input Pulled up Input Pulled up Input Pulled up Input Pulled up Input Pulled up
51
Table 4-8: Digital Switch Local TDM Streams Connection (Continued) Group Device
Switch Connection
Sti24/Sto24 Sti25/Sto25 Sti26/Sto26 Sti27/Sto27
TDM Data Rate

8.192 Mbps 8.192 Mbps 8.192 Mbps 8.192 Mbps
Interleaving Format
E1/T1/J1 Quad Framer and LIU

The PCE385 has an E1/T1/J1 quad framer with an integral Line Interface Unit (LIU, four ports total) located on the mezzanine I/O board. The Quad FALC supports a multitude of features, including:
high density, generic interface for all E1/T1/J1 applications four analog receive and transmit circuits for long and short haul applications E1 or T1/J1 mode selectable for each channel individually data and clock recovery using an integrated digital phase locked loop maximum line attenuation to -43 dB at 1024 kHz (E1) and to -36 dB at 772 kHz (T1/J1) programmable transmit pulse shapes for E1 and T1/J1 pulse masks programmable line build-out for CSU signals according to ANSI T1. 403 and FCC68: 0 dB, -7.5 dB, 15 dB, -22.5 dB (T1/J1) low transmitter output impedances for high transmit return loss tristate function of the analog transmit line outputs transmit line monitor protecting the device from damage receive line monitor mode jitter specifications of ITU-T I.431, G.703, G.736 (E1), G.823 (E1) and AT&T TR62411 (T1/J1) are met crystal-less wander and jitter attenuation/compensation common master clock reference for E1 and T1/J1 (any frequency within 1.02 and 20 MHz) power down function per channel support for automatic protection switching selectable line codes (E1: HDB3, AMI/T1: B8ZS, AMI with ZCS) loss of signal indication with programmable thresholds according to ITU-T G.775, ETS300233 (E1) and ANSI T1.403 (T1/J1) optional data stream muting upon Loss of Signal (LOS) detection programmable receive slicer threshold clock generator for jitter free system and transmit clocks per channel local loop and remote loop for diagnostic purposes low power device, single power supply: 3.3 V with 5 V tolerant digital inputs
52
E1/T1/J1 Quad Framer and LIU
Frame Aligner Features

These are the Frame Aligner features:
frame alignment/synthesis for 2,048 Kbps according to ITU-T G.704 (E1) and for1,544 Kbps according to ITU-T G.704 and JT G.704 (T1/J1) programmable frame formats: E1: Doubleframe, CRC Multiframe (E1)T1: 4-Frame Multiframe (F4,FT), 12-Frame Multiframe (F12, D3/4), Extended Superframe (F24, ESF), Remote Switch Mode (F72, SLC96) selectable conditions for recover/loss of frame alignment CRC4 to Non-CRC4 Interworking according to ITU-T G. 706 Annex B (E1) error checking using CRC4 procedures according to ITU-T G. 706 (E1) error checking using CRC6 procedures according to ITU-T G. 706 and JT G.706 (T1/J1) performs synchronization in ESF format according to NTT requirements (J1) alarm and performance monitoring per second: 16 bit counter for CRC-, framing errors, code violations, error monitoring using E bit and SA6 bit (E1), errored blocks, PRBS bit errors insertion and extraction of alarm indication signals (AIS, remote/yellow alarm,) remote Alarm generation/checking according to ITU JT-G.704 in ESF-format (J1) IDLE code insertion for selectable channels single-bit defect insertion flexible system clock frequency for receiver and transmitter supports programmable system data rates with independent receive/transmit shifts: E1: 2.048, 4.096, 8.192 and 16.384 Mbps (according to H.100 bus). T1/J1: 2.048, 4.096, 8.192, 16.384 Mbps and 1.544, 3.088, 6.176, 12.352 Mbps system interface multiplex mode; multiplexing of four channels into an 8.192 Mbps data stream and vice versa, bit- or byte-interleaved elastic store for receive and transmit route clock wander and jitter compensation; controlled slip capability and slip indication programmable elastic buffer size: two frames, one frame/short buffer/bypass provides different time slot mapping modes supports fractional E1 or T1/J1 access flexible transparent modes programmable in-band loop code detection and generation (TR62411) channel loop back, line loop back, or payload loop back capabilities (TR54016) Pseudo Random Bit Sequence (PRBS) generator and monitor (framed or unframed) clear channel capabilities (T1/J1) loop-timed mode HDLC controller bit stuffing, CRC check and generation, flag generation, flag and address recognition, handling of bit oriented functions supports Signaling System #7 delimitation, alignment and error detection according to ITU-Q.703 processing of fill in signaling units, processing of errored signaling units CAS/CAS-BR controller with last look capability, enhanced CAS-register access and freeze signaling indication DL-channel protocol for ESF format according to ANSI T1.403 specification or according to AT&T TR54016 (T1/J1) DL-bit access for F72 (SLC96) format (T1/J1) generates periodic performance report according to ANSI T1. 403
53
provides access to serial signaling data streams multiframe synchronization and synthesis according to ITU-T G.732 alarm insertion and detection (AIS and LOS in time slot 16) transparent mode FIFO buffers (64 bytes deep) for efficient transfer of data packets time slot assignment: any combination of time slots selectable for data transfer independent of signaling mode (useful for fractional T1/J1 applications) time-slot 0 Sa8...4-bit handling using FIFOs (E1) HDLC access to any Sa-bit combination (E1) extended interrupt capabilities one-second timer (internal or external timing reference)
54
Chapter
5
ATM Channel Allocations
Overview
The PCE385 supports Asynchronous Transfer Mode (ATM) termination. Two full channels of eight MHz Time Division Multiplexed (TDM) data are fed from the H.100 TDM switch on the PCE385 daughter board along with the frame pulse and the TDM clock. The signals are routed into the baseboard control and logic PAL for buffering and distribution of the data, control pulses and TDM clocks to the MPC8280 TDM inputs and outputs. Topics in this chapter include:
ATM Channel Allocations on page 56 ATM Receive Cell Functions on page 58 ATM Transmit Cell Functions on page 59 Receive UTOPIA Interface on page 59 Transmit UTOPIA Interface on page 59 MPC8280 Parallel Port Pin Assignments on page 60 MPC8280 Port A Pin Assignments on page 60 MPC8280 Port B Pin Assignments on page 62 MPC8280 Port C Pin Assignments on page 64 MPC8280 Port D Pin Assignments on page 66
55

Figure 5-1: "ATM Channel Allocations" provides an overview of ATM channel allocations. Figure 5-1: ATM Channel Allocations
TDMA1_RX PQTDMRXA TDMB1_RX TDMC1_RX TDMD1_RX TDMA1_RX_SYNC TDMB1_RX_SYNC TDMC1_RX_SYNC TDMD1_RX_SYNC TDMA1_TX TDMB1_TX TDMC1_TX TDMD1_TX
PQTDMTXa
MPC_TDM_STFPI#
MPC8280 CPM TDM1
MPC8280 CPM COMMONCLOCKING

MPC_TDM_STCKI# CLK1 CLK3 CLK5 CLK15 TDMA1RX/TDMD2RX TDMB1RX/TDMC2RX TDMC1RX/TDMA2RX TDMD1RX/TDMB2RX
PAL Input Buffering
TDMA2_RX_SYNC TDMB2_RX_SYNC TDMC2_RX_SYNC TDMD2_RX_SYNC
MPC8280 CPM TDM2
TDMA2_RX TDMB2_RX PQTDMRXB TDMC2_RX TDMD2_RX
TDMA2_TX TDMB2_TX TDMC2_TX TDMD2_TX
PQTDMTXB
PQTDMRXA and PQTDMRXB are the multiplexed 8.192 MHz TDM data from the on-board TDM switch. MPC_TDM_STCKI# is the synchronized 8.192 MHz TDM clock from the on-board switch. MPC_TDM_STFPI# is the TDM frame pulse from the on-board TDM switch. These signals are buffered by the PAL and connected directly to the appropriate TDM inputs. TDM connections A1, B1, C1, D1, A2, B2, C2, and D2 can be used as inputs. Because the TDM inputs can share clocking, they are grouped together to reduce the number of common clock connections inputted to the part. The grouping is as follows:
CLK1 is mapped to TDMA1 Rx CLK and TDMD2 Rx CLK. CLK3 is mapped to TDMB1 Rx CLK and TDMC2 Rx CLK CLK5 is mapped to TDMC1 Rx CLK and TDMA2 Rx CLK CLK15 is mapped to TDMD1 Rx CLK and TDMB2 Rx CLK
In the SI setup, the transmit clock for each TDM channel is then set to be sourced from its own Rx CLK input. The Frame pulse sync inputs are made to each individual Rx SYNC input of the TDM channels. The SI setup is then configured to source the Tx SYNC input from its own Rx SYNC input. For information about the data, frame pulse and clocking connections for each port, see MPC8280 Parallel Port Pin Assignments on page 60.
56
The Switch TDM data is byte grouped so that the SI can decode it appropriately for each TDM input and pass it on the Transmission Convergence (TC) layer block in the MPC8280. The TC layer block separates ATM functions into its receive and transmit sub-blocks (see Figure 5-2, MPC8280 ATM Transmission Convergence (TC) Layer Overview on page 58). Primary features of the TC layer include the following:
eight TDM channels routed in hardware to eight TC layer blocks - protocol-specific overhead bits can be discarded or routed to other controllers by the SI - performing ATM TC layer functions (according to ITU-T I.432) - transmit (Tx) updates are as follows: cell Header Error Control (HEC) generation payload scrambling using self synchronizing scrambler (programmable by the user) coset generation (programmable by the user) cell rate by inserting idle cells - receive (Rx) updates are as follows: cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA parameters for the delineation state machine payload de-scrambling using self synchronizing scrambler (programmable by the user) coset removing (programmable by the user) filtering idle/unassigned cells (programmable by the user) performing HEC error detection and single bit error correction (programmable by the user) generating loss of cell delineation status/interrupt (LOC / LCD) operates with FCC2 (UTOPIA 8) serial loop back mode cell echo mode supports both FCC transmit modes: - external rate modeIdle cells are generated by the FCC (microcode) to control data rate - internal rate mode (sub-rate)FCC transfers only the data cells using the required data rate. The TC layer generates idle/unassigned cells to maintain the line bit rate supports the TC layer and Physical Medium Dependent (PMD) WIRE interface (according to the ATM-Forum AF-PHY-0063.000)
Cell counters for performance monitoring include:

16-bit counters count: - HEC error cells - HEC single bit error and corrected cells - idle/unassigned cells filtered - idle/unassigned cells transmitted - transmitted ATM cells - received ATM cells - maskable interrupt sent to the host when a counter expires overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt can be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps are supported.
57
Figure 5-2: MPC8280 ATM Transmission Convergence (TC) Layer Overview
ATM Receive Cell Functions

The ATM Receive Cell Functions (RCF) block performs the receive functions of the TC block. This block performs cell delineation, cell payload descrambling, Header Error Check (HEC) verification and correction, and idle/unassigned cell filtering. Cell delineation is the process of framing data to ATM cell boundaries using the HEC received in the ATM cell header. The HEC is a CRC-8 calculation over the first four octets of the ATM cell header. The cell delineation algorithm assumes that repetitive correct HEC calculations over consecutive cells indicate valid ATM cell boundaries. The receive First In, First Out (FIFO) provides FIFO management and an interface to the Universal Test and OPerations Interface for ATM (UTOPIA) receive cell interface. The receive FIFO can hold two ATM cells, thereby providing the cell rate decoupling function between the transmission system physical layer and the ATM layer. FIFO management includes filling the FIFO, indicating to the UTOPIA interface that it contains cells, maintaining the FIFO read and write pointers, and detecting FIFO overrun (TCER[OR]) conditions.
58
ATM Transmit Cell Functions
ATM Transmit Cell Functions

The ATM Transmit Cell Functions (TCF) block performs the ATM cell payload scrambling and is responsible for the HEC generation and the idle cell generation. The TCF scrambles (programmable by the user) the cell payload using the self-synchronizing scrambler with polynomial x43 + 1. The HEC is generated using the polynomial x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) (programmable by the user) to the calculated HEC octet. The result overwrites the HEC octet on the transmitted cell. When the transmit FIFO is empty, the TCF inserts idle cells, which are counted in the Idle Cell Counter (ICC). The TCF accumulates the number of transmitted assigned cells in a counter (TCC). The transmit FIFO provides FIFO management and an interface to the UTOPIA transmit interface. The FIFO provides the cell rate decoupling between the transmission system physical layer and the ATM layer. The FIFO management includes emptying cells from the transmit FIFO, indicating to the UTOPIA interface that it is full, maintaining the FIFO read and write pointers, and detecting FIFO underrun (TCER[UR]) conditions.
Receive UTOPIA Interface

The receive UTOPIA block performs the receive interface with the FCC using the UTOPIA bus. This block implements the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface.
Transmit UTOPIA Interface

The transmit UTOPIA block performs the transmit interface with the FCC using the UTOPIA bus. This block implements the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface. The remainder of the setup for the ATM block is internal to the MPC8280s FCC2 and the TC Layer. The incoming data is received by FCC2 and at this point, the data can be terminated into memory or sent to another TDM port. The transmit path is also through FCC2. For additional informations, refer to the Freescale MPC8280 PowerQUICC II Family Reference Manual Rev.0.
59
MPC8280 Parallel Port Pin Assignments

The program settings for the parallel port pins can be found in the files init.inc and hardware.c.
Note: All unassigned channels on all ports should be programmed to be data register outputs wherever no conflicts or limitations in the part exist. This configuration prevents unwanted current draw on the unused channels.
MPC8280 Port A Pin Assignments

Table 5-1: MPC8280 Port A Pin Assignments describes the MPC8280 port A pin assignments. Table 5-1: MPC8280 Port A Pin Assignments Pin Function Pin PPARA = 1 PSORA = 0 PDIRA = 1 Out
PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 60
PSORA = 1 PDIRA = 1 Out PDIRA = 0 In
PPARA = 0 PDIRA = 1 Out PDIRA = 0 In
PDIRA = 0 In
Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned
MPC8280 Port A Pin Assignments
Table 5-1: MPC8280 Port A Pin Assignments (Continued) Pin Function Pin PPARA = 1 PSORA = 0 PDIRA = 1 Out
PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 EE_DO
PSORA = 1 PDIRA = 1 Out PDIRA = 0 In
PPARA = 0 PDIRA = 1 Out PDIRA = 0 In
PDIRA = 0 In
Default = Unassigned Default = Unassigned TDMA1_TX TDMA1_RX Default = Unassigned TDMA1_RX_ SYNC Default = Unassigned Default = Unassigned EE_CS EE_SCL EE_DI
61
MPC8280 Port B Pin Assignments

Table 5-2: MPC8280 Port B Pin Assignments describes the MPC8280 port B pin assignments. Table 5-2: MPC8280 Port B Pin Assignments Pin Function Pin PPARB = 1 PSORB = 0 PDIRB = 1 Out
PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 62
PSORB = 1 PDIRB = 1 Out PDIRB = 0 In

TDMB2_TX TDMB2_RX TDMB2_RX_ SYNC Default = Unassigned TDMC2_TX TDMC2_RX Default = Unassigned TDMC2_RX_ SYNC TDMD2_TX TDMD2_RX Default = Unassigned TDMD2_RX_ SYNC Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned TDMC1_TX TDMC1_RX Default = Unassigned TDMC1_RX_ SYNC TDMD1_TX TDMD1_RX Default = Unassigned
PPARB = 0 PDIRB = 1 Out PDIRB = 0 In
PDIRB = 0 In
MPC8280 Port B Pin Assignments
Table 5-2: MPC8280 Port B Pin Assignments (Continued) Pin Function Pin PPARB = 1 PSORB = 0 PDIRB = 1 Out
PB31 PB8 PB7 PB6 PB5 PB4
PSORB = 1 PDIRB = 1 Out PDIRB = 0 In

TDMB2_TX TDMD1_RX_ SYNC TDMA2_TX TDMA2_RX Default = Unassigned TDMA2_RX_ SYNC
PPARB = 0 PDIRB = 1 Out PDIRB = 0 In
PDIRB = 0 In
63
MPC8280 Port C Pin Assignments

Table 5-3: MPC8280 Port C Pin Assignments describes the MPC8280 port C pin assignments. Table 5-3: MPC8280 Port C Pin Assignments Pin Function Pin PPARC = 1 PSORC = 0 PDIRC = 1 Out
PC31
PSORC = 1 PDIRC = 1 Out PDIRC = 0 In
PPARC = 0 PDIRC = 1 Out PDIRC = 0 In
PDIRC = 0 In
CLK1 ASSIGNED TO TDMA1_RX_ CLK AND TDMD2_RX_ CLK
PC30 PC29 CLK3 ASSIGNED TO TDMB1_RX_ CLK AND TDMC2_RX_ CLK
Default = Unassigned
PC28 PC27 CLK5 ASSIGNED TO TDMC1_RX_ CLK AND TDMA2_RX_ CLK
Default = Unassigned
PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18
Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned
64
MPC8280 Port C Pin Assignments
Table 5-3: MPC8280 Port C Pin Assignments (Continued) Pin Function Pin PPARC = 1 PSORC = 0 PDIRC = 1 Out
PC17
PSORC = 1 PDIRC = 1 Out PDIRC = 0 In
PPARC = 0 PDIRC = 1 Out PDIRC = 0 In
PDIRC = 0 In
CLK15 ASSIGNED TO TDMB2_RX_ CLK AND TDMD1_RX_ CLK
PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned
65
MPC8280 Port D Pin Assignments

Table 5-4: MPC8280 Port D Pin Assignments describes the MPC8280 port D pin assignments. Table 5-4: MPC8280 Port D Pin Assignments Pin Function Pin PPARD = 1 PSORD = 0 PDIRD = 1 Out
PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 SMC1: SMTXD TDM_B1: L1RSYNC
PSORD = 1 PDIRD = 1 Out PDIRD = 0 In
PPARD = 0 PDIRD = 1 Out PDIRD = 0 In
PDIRD = 0 In
Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned TDM_B1: L1TXD TDM_B1: L1RXD
66
MPC8280 Port D Pin Assignments
Table 5-4: MPC8280 Port D Pin Assignments (Continued) Pin Function Pin PPARD = 1 PSORD = 0 PDIRD = 1 Out
PD8 PD7 PD6 PD5 PD4
PSORD = 1 PDIRD = 1 Out PDIRD = 0 In
PPARD = 0 PDIRD = 1 Out PDIRD = 0 In
PDIRD = 0 In
SMC1: SMRXD
Default = Unassigned Default = Unassigned Default = Unassigned Default = Unassigned
67
68
Chapter
6
Pinouts
Overview
This chapter provides information about the pinouts and ports on the PCE385. To identify the port locations on the boards, see Figure 2-2, PCE385 Main Board Component Layout on page 21 and Figure 2-3, PCE385 Daughter Board Component Layout on page 22. Topics in this chapter include:
Main Board Pinouts on page 70 MPC8280 COPS Header (P1) on page 71 JTAG Testing Port (P2) on page 72 Option Jumper Block (P3) on page 73 Daughter Board Interface Connector (J1) on page 74
69
Chapter 6: Pinouts
Main Board Pinouts

This section describes the pinouts of the connectors on the PCE385 main board (see Table 6-1: PCE385 Main Board Connector Pinout Call Out Definitions and Figure 6-1: "PCE385 Main Board Connector Pinouts"). Table 6-1: PCE385 Main Board Connector Pinout Call Out Definitions Call Out Letter
A B C D
Connector
MPC8280 COPS Header (P1) JTAG Testing Port (P2) Option Jumper Block (P3) Daughter Board Interface Connector (J1)
Figure 6-1: PCE385 Main Board Connector Pinouts
70
Main Board Pinouts
MPC8280 COPS Header (P1)

The JTAG testing port on the MPC8280 is used to support the EST Common On-chip Processor (COP) debugger on the P1 connector. This connector is set up to support the extended 16-pin COP debugger signaling, but the basic 10-pin signaling devices can be used with an interposing adapter. Table 6-2: JTAG/BDM Debug Port (P1) Pinouts describes the P1 pinouts. Table 6-2: JTAG/BDM Debug Port (P1) Pinouts Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Signal Name
PQ_TDO - JTAG Test Data Out Signal !PQ_QACK- Quiescent State Acknowledge, not supported PQ_TDI - JTAG Test Data In signal !PQ_TRST - JTAG Reset and Tristate signal !PQ_QREQ - Quiescent State Request V3V PQ_TCK - JTAG Test Clock No Connection PQ_TMS - JTAG Test Mode Select No Connection PQ_SRESET# - MPC8280 Soft Reset Ground PQ_HRESET# - MPC8280 Hard Reset No Connection !CHKSTPO - Checkstop output, Not supported Ground
All the control signals are pulled to V3V with a minimum 10K resistor to prevent false acutation when no JTAG controller is connected. The mechanical requirements 16-pin Motorola connector are specified as follows.
vertical, 16 (2 X 8) pin header 0.10 in. between centers of adjacent pins 0.025 in. square pins 0.23 in. height of each post
71
Chapter 6: Pinouts
JTAG Testing Port (P2)

Two PCE385 boards can be configured as a master/slave pair using the H.100 bus provided at board edge connector P2. Connect the two boards together (in adjacent PCI slots) using the ribbon cable assembly described in Table 6-3: Mezzanine Master/Slave PCM Expansion Connector (P2) Pinout. Table 6-3: Mezzanine Master/Slave PCM Expansion Connector (P2) Pinout Pin Number
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53
Signal Name
reserved CT_D31 CT_D29 GND CT_D26 CT_D24 CT_D23 CT_D21 GND CT_D18 CT_D16 CT_D15 CT_D13 GND CT_D10 CT_D8 CT_D7 CT_D5 GND CT_D2 CT_D0 CT_FRAME_A CT_C8_A CTNR1 CT_FRAME_B CT_C8_B reserved
Signal Name
reserved CT_D30 CT_D28 CT_D27 CT_D25 GND CT_D22 CT_D20 CT_D19 CT_D17 GND CT_D14 CT_D12 CT_D11 CT_D9 GND CT_D6 CT_D4 CT_D3 CT_D1 GND GND GND GND GND GND GND
Pin Number
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54
72
Main Board Pinouts
Table 6-3: Mezzanine Master/Slave PCM Expansion Connector (P2) Pinout (Continued) Pin Number
55 57 59 61 63 65 67
Signal Name
reserved reserved reserved reserved reserved reserved GND
Signal Name
GND GND GND GND GND reserved reserved
Pin Number
56 58 60 62 64 66 68
Option Jumper Block (P3)

The P3 eight-pin header is used to set the board configuration and the mode of operation. Table 6-4: Option Jumper Block (P3) Pinout describes the P3 pinouts. Table 6-4: Option Jumper Block (P3) Pinout Pin Number
1 2 3 4 5 6
Signal Name
RSTCONF GND PORESET NMI GND BREAK_DET
Operational Mode
Jumper 1-2 No Connect No Connect
Description
Tells CPU to follow normal Reset configuration procedure by reading settings from FLASH When momentarily grounded this pin will force the card to take a power-on reset. When momentarily grounded this pin will force the CPU to take a non-maskable interrupt. This jumper selection can be made to allow the serial console port to send a break signal to the board to reset it. It is usually only used during the debug process. This function is not normally enabled in an operational mode. This jumper signals the boot code to load the run time software from the on board application FLASH. If the jumper is not present the boot loader will stop and display the ok> prompt.
No Connect
7 8
GND FACTORY_JMP Jumper 7-8
Notes: RSTCONF is grounded for normal operation. Jumper open uses default hardware configuration where the reset of the 60x bus components will not be configured. BREAK_DET provides a hardware reset with a serial break detect sequence. FACTORY_JMP for factory default initialization.
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Chapter 6: Pinouts
Daughter Board Interface Connector (J1)

The PCE385 is connected to the media using a shielded four position RJ-48C connector on the mounting bracket. The mating plug (not supplied) can be a shielded or unshielded eightposition modular jack. Use the shielded version when you require maximum noise immunity. Table 6-5: Mezzanine Telecom Line Interface J1 Pinout describes the J1 pinouts. Table 6-5: Mezzanine Telecom Line Interface J1 Pinout Pin Number
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6 C7 C8 D1 D2 D3
Signal Name
RRING_4 RTIP_4 nc TRING_4 TTIP_4 nc nc nc RRING_3 RTIP_3 nc TRING_3 TTIP_3 nc nc nc RRING_2 RTIP_2 nc TRING_2 TTIP_2 nc nc nc RRING_1 RTIP_1 nc
74
Main Board Pinouts
Table 6-5: Mezzanine Telecom Line Interface J1 Pinout (Continued) Pin Number
D4 D5 D6 D7 D8
Signal Name
TRING_1 TTIP_1 nc nc nc
75
Chapter 6: Pinouts
76
Chapter
7
Specifications
Overview
This chapter provides information about the system requirements for the PCE385.
Caution: Use anti-static grounding straps and anti-static mats when you are handling the PCE335 to help prevent damage due to electrostatic discharge. Electronic components on printed circuit boards are extremely sensitive to static electricity. Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment.
System Requirements
This section describes the PCE385 environmental and power requirements (see Table 7-1: Environmental Requirements and Table 7-2: Power Requirements). Table 7-1: Environmental Requirements Temperatures
Operating: 0C to 50C (32F to 122F) Non-operating: -20C to 80C (-4F to 176F)
Air Flow
Standard PC chassis airflow is acceptable.
77
Chapter 7: Specifications
Table 7-2: Power Requirements Voltage

2.46A @ 3.3V 3.36 @ 12V
Maximum (W)
8.1 3.63
78
Chapter
8
Data Sheets and Agency Approvals
Overview
This chapter provides references to data sheets, standards, and specifications for the technology designed into PCE385. This chapter also provides the agency approvals for the PCE385. Topics in this chapter include:
Data Sheet Reference on page 79 Agency Approvals on page 81 Compliance with RoHS and WEEE Directives on page 81 Regulatory Information on page 83
Data Sheet Reference

This section provides links to data sheets, standards, and specifications for the technology designed into the PCE385 board, including:
CompactPCI Specifications User Documentation References
CompactPCI Specifications
Current CompactPCI Specifications can be purchased from PICMG (PCI Industrial Computers Manufacturers Group) for a nominal fee. Short form specifications in Adobe Acrobat format (PDF) are also available on PICMGs website at: http://www.picmg.org
79
User Documentation References

This guide has been created for the installation, maintenance, configuration, and use of the PCE385. The latest PCE385 product information and manuals are available on the Performance Technologies Website at http://www.pt.com. Refer to the following manuals for more information about the software components that might be used with your system.
NexusWare Core NexusWare Core is a comprehensive, highly integrated, Linux-based development, integration and management environment, for system engineers using Performance Technologies' embedded products to build packet-based wireless and IP telephony systems. NexusWare Core is the foundation environment for Performance Technologies' existing and future value-add NexusWare software packages, including NexusWare C7, NexusWare Wide Area Network (WAN), NexusWare Information Systems Management (ISM). WAN Protocol Software Our suite of Wide Area Networking (WAN) protocols provides all the critical pieces required for timely application development. With a wide range of WAN protocols, high performance controllers and servers and comprehensive operating system support, we provide a complete application solution for Original Equipment Manufacturer (OEM). All of our WAN protocols adhere to a common Application Programming Interface (API). The API contains information useful to programmers developing applications that interact with Performance Technologies' Executive for STREAMS Applications (xSTRa) or its NexusWare Service Layer (NWSL). This software architecture ensures customer investments in application development will be fully portable across industry-standard hardware bus architectures, TCP/IP and operating systems. This portability represents a significant reduction in WAN application development efforts, system integration costs and time-to-market. NexusWare C7 NexusWare C7 is a comprehensive, highly-integrated Linux-based development, integration and management environment. This environment is intended for system engineers using Performance Technologies' embedded products to build packet-based systems, including nextgeneration wireless and Internet Protocol (IP) telephony platforms. In the past, systems depended on the conventional Peripheral Component Interconnect (PCI) bus for system integration, forcing a low-level and time-consuming process for developing IP telephony, datacom, and telecom systems. The Ethernet capabilities of Performance Technologies' IPnexus hardware products, coupled with the strong Linux operating system (OS) foundation of NexusWare C7, offers a simple and rapid path to newer, IP-based PCI PICMG 2.16 systems, while providing developers with a simplified way to design-in current, PCI-based systems. NexusWare C7, which is a loadable module within NexusWare Core, provides SS7 MTP2 layer data processing above the NexusWare Core API. ChanneLink T1/E1/J1 Driver (Solaris) Our ChanneLink T1/E1/J1 Driver provides users of our high performance family of T1/E1 communications adapters an easy way to run a variety of SunSoft communications protocols in either a channelized or non-channelized mode. ChanneLink is architected to provide a totally transparent link between the SunSoft protocols and our T1/E1 communications adapters. ChanneLink is capable of transmitting and receiving T1/E1 data, and sustaining high speed data rates for a variety of protocols used in telecommunications and data communications applications. ChanneLink can also be used as a standard API and Solaris driver for non-SunSoft applications. Users of Sun's suite of communication protocols, such as X.25, Frame Relay, PPP, Internetwork Router (IR), and so on, can quickly and easily integrate our communications adapters for PCI, CompactPCI/PICMG 2.16, or PMC based systems with the desired SunSoft protocol.
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Agency Approvals
Agency Approvals
This section presents agency approval and certification information for the PCE385:
CE Certification Compliance with RoHS and WEEE Directives Safety Emissions Test Regulations Immunity Test Regulations
CE Certification
The PCE385 meets the intent of Directive 89/336/EEC for electromagnetic compatibility (amended by 92/31/EEC, 93/68/EEC, 98/13/EEC, 2004/108/EC), R&TTE Directive 1999/5/EC, and the Low-Voltage Directive 72/23/EEC for product safety (amended by 73/23/EEC, 93/68/ EEC, 2006/95/EC). Compliance was demonstrated to the following specifications as listed in the Official Journal of the European Communities:
Compliance with RoHS and WEEE Directives

In February 2003, the European Union issued Directive 2002/95/EC about the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment (RoHS) and Directive 2002/96/EC about Waste Electrical and Electronic Equipment (WEEE). This product is compliant with Directive 2002/95/EC. It may also fall under the Directive 2002/ 96/EC. Performance Technologies complete position statements on the RoHS and WEEE Directives can be viewed on the Web at http://www.pt.com/rohs/position.html.
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Safety
Table 8-1: Safety Compliance Specification
EN/IEC 60950 CB Report Scheme CSA C22.2 No. 950-1
Compliance
Safety of Information Technology Equipment with UL Certification CB certificate and Report Safety of Information Technology Equipment
Emissions Test Regulations

Table 8-2: Emissions Test Regulations Compliance Specification
FCC EN 55022 EN 55022 EN 61000-3-2 EN 61000-3-3
Compliance
Part 15, Subpart B, Class A Class A Radiated Class A Conducted Emissions Power Line Harmonics Power Line Flicker
Immunity Test Regulations

Table 8-3: Immunity Test Regulations Compliance Specifications
EN 61000 4-2 EN 61000 4-3 EN 61000 4-4 EN 61000 4-5 EN 61000 4-6 EN 61000 4-11 ETSI EN 300 386 V1.3.1
Compliance
Electrostatic Discharge (ESD) Radiated Immunity Electrical Fast Transient Burst Immunity Surge Immunity Radio -frequency common mode Voltage dips, and Interrupt Immunity Electromagnetic Compatibility and Radio Spectrum Matters (ERM)
Note: Additional Radiated Emissions and ESD test limits were tested in accordance with GR-1089core, issue 3.
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Regulatory Information
Regulatory Information
This section provides regulatory information for the PCE385 including:
FCC (USA) Industry Canada (Canada)
FCC (USA)
This product has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This product generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.
Note: This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: This device may not cause harmful interference. This device must accept any interference received, including interference that may cause undesired operation. Caution: If you make any modification to the equipment not expressly approved by Performance Technologies, you could void your authority to operate the equipment.
Industry Canada (Canada)

Cet appareil numrique respecte les limites bruits radiolectriques applicables aux appareils numriques de Classe B prescrites dans la norme sur le matriel brouilleur: Appareils Numriques, NMB-003 dicte par le Ministre Canadien des Communications. This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled: Digital Apparatus, ICES-003 of the Canadian Department of Communications.
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Chapter
9
Product Safety
Overview
This chapter provides safety information for the PCE3285 product.
Product Safety Information

This section provides safety information for the PCE385 including:
Safety Precautions on page 85 AC or DC Power Safety Warning on page 87 DC Power Safety Warning (DC Powered Units) on page 87 Rack Mount Enclosure Safety on page 88
Safety Precautions
Review the following precautions to avoid injury and prevent damage to this product, or any products to which it is connected. To avoid potential hazards, use the product only as specified. Read all safety information provided in the component product user manuals and understand the precautions associated with safety symbols, written warnings, and cautions before accessing parts or locations within the unit. Save this document for future reference.
Caution: To Avoid Electric Overload: To avoid electrical hazards (heat shock and/or fire hazard), do not make connections to terminals outside the range specified for that terminal. Refer to the product user manual for correct connections.
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Caution: To Avoid the Risk of Electric Shock: When supplying power to the system, always make connections to a grounded main. Always use a power cable with a grounded plug (third grounding pin). Do not operate in wet, damp, or condensing conditions. Caution: System Airflow Requirements: Platform components such as processor boards, Ethernet switches, etc., are designed to operate with external airflow. Components can be destroyed if they are operated without external airflow. Chassis fans normally provide external airflow when components are installed in compatible chassis. Filler panels must be installed over unused chassis slots so that airflow requirements are met. Please refer to the product data sheet for airflow requirements if you are installing components in custom chassis. Caution: Microprocessor Heatsinks May Become Hot During Normal Operation: To avoid burns, do not allow anything to touch processor heatsinks. Caution: Do Not Operate Without Covers: To avoid electric shock or fire hazard, do not operate this product with any removed enclosure covers or panels. Caution: To Avoid the Risk of Electric Shock: Do not operate in wet, damp, or condensing conditions. Caution: Do Not Operate in an Explosive Atmosphere: To avoid injury, fire hazard, or explosion, do not operate this product in an explosive atmosphere. Caution: If Your System Has Multiple Power Supply Sources: Disconnect all external power connections before servicing. Warning: Power Supplies Must Be Replaced by Qualified Service Personnel Only. Caution: Lithium Batteries Are Not Field-Replaceable Units: There is a danger of explosion if a battery is incorrectly replaced or handled. Do not disassemble or recharge the battery. Do not dispose of the battery in fire. When the battery is replaced, the same type or an equivalent type recommended by the manufacturer must be used. Used batteries must be disposed of according to the manufacturers instructions. Return the unit to Performance Technologies for battery service.
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Product Safety Information
AC or DC Power Safety Warning

The AC or DC power cord is your units main AC or DC disconnecting device, and must be easily accessible at all times. Auxiliary AC or DC On/Off switches or circuit breaker switches are for power control functions only (NOT THE MAIN DISCONNECT). For your safety, use only a power cord with a grounded plug. The enclosure is also provided with a separate earth ground connection/stud. The earth ground connection should be installed prior to the application of power or peripheral connections and should never be disconnected while power or peripheral connections exist. To reduce the possibility of electric shock from a telephone or Ethernet system, plug your enclosure into the power source before making these connects. Disconnect these connections before unplugging your enclosure from the power source.
Warning: Verify Power Cord and Outlet Compatibility. Check to ensure you are using the appropriate power cords for your power outlet configurations. Visit the following website for additional information: http:// kropla.com/electric2.htm. Caution: Hot surface. Avoid contact: Surfaces are hot and may cause personal injury if touched.
DC Power Safety Warning (DC Powered Units)

Caution: This equipment has a connection between the earthed conductor of the DC supply circuit and the earthing conductor. 1. This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode is connected. 2. This equipment shall be located in the same immediate area (such as, adjacent cabinets) as any other equipment that has a connection between the earthed conductor of the same DC supply circuit and the earthing conductor, and also the point of earthing of the DC system. The DC system shall not be earthed elsewhere. 3. The DC supply source is to be located within the same premises as the equipment. 4. Switching or disconnecting devices shall not be in the earthed circuit conductor between the DC source and the point of connection of the earthing electrode conductor.
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Rack Mount Enclosure Safety

Your enclosure may be intended for stationary rack mounting. Mount in a rack designed to meet the physical strength requirements of NEBS GR-63-CORE and NEBS GR 487. Your system may have multiple power sources. Disconnect all power sources and external connections/cables prior to installing or removing your system from a rack frame.
Caution: Avoid Electric Overload: To avoid electric shock or fire hazard, only connect your system to an input voltage source as specified in the product user manual.
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Glossary
A
Term address ANSI architecture asynchronous transmission Definition
Address is a sequence of digits that uniquely identify an endpoint. American National Standards Institute is an organization of American industry groups. ANSI works with the standards committees of other nations to develop standards to facilitate international trade and telecommunications. Architecture is system specification of how subcomponents interconnect, interact, and interoperate. Asynchronous transmission is a type of synchronization where there is no defined time relationship between transmission of frames.
B
Term bit bit rate bps byte Definition
Bit is the smallest unit of information that a computer can process. Typically, a bit represents two states: 1 or 0. Bit rate is the number of bits transmitted over a telephone line for each second. Bit Per Second is a data transmission speed measurement unit. Byte is a group of bits and is a unit that represents a character in some coding system. Eight bits equal one bite.
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Glossary
C
Term central office CO Definition
Central office is a building that houses switching equipment and serves as the primary operating and service center for all telephones in its geographical area. Sometimes used interchangeably with exchange. See central office. Compact Peripheral Component Interface is a combination of the PCI bus contained on a Eurocard form factor. The Eurocard provides more rugged packaging and a more secure plug and socket for embedded systems than the standard PCI board used in desktop computers. This interface supports hot swapping and provides higher performance (32-bit, 33MHz) than the ISA bus in the PC/104 architecture. CompactPCI also provides modularity as Eurocard comes in several sizes.
CompactPCI
D
Term database Definition
Database is a collection of related information on a computer that is arranged for ease of retrieval.
E
Term E1 Ethernet Definition
E1 is the European equivalent to the North American T1. E1 carries information at the rate of 2.048 million bits per second (E1 supports 30 channels, 2.048 Mbps). Ethernet is a 10 Mbps Local Area Network (LAN) medium-access method that uses Carrier Sense Multiple Access to allow the sharing of a bus-type network. IEEE 802.3 is the standard that specifies Ethernet.
F
Term FCC flag Definition
Federal Communications Commission is a USA federal regulatory agency charged with regulation of frequency spectrum use. Flag is variable such as a symbol, character or digit in software used for identification.
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Glossary
I
Term ID IP IP address ITU ITU-T Definition
Identifier is one or more characters used to specify or identify a user, a network element, managed object, and others. Internet Protocol is a standardized method of transporting information across the Internet in packets of data. This data contains a network address and is used to route a message to a different network or subnetwork. IP address is a numerical designation of a network node. Under IP version 4 (IPv4), this is a 32-bit number that is typically written as four byte values separated by periods (for example, 127.0.0.1). International Telecommunication Union is a United Nations organization that co-ordinates global telecommunications activities. International Telecommunications Union-Telecommunication Standardization Sector is one of three sectors of ITU, and is an international body that develops worldwide standards for telecommunication technologies.
J
Term J1 Definition
J1 is Japanese version of the T1 carrier system of North America (J1 supports 24 channels, 1.544 Mbps).
K
Term kbps Definition
Kilo Bits Per Second is a unit of measurement for data transfer. One kbps is equal to 1000 bits transmitted for each second.
L
Term LED link Definition
Light Emitting Diode is a display technology that uses a semiconductor diode to emit infrared or visible light when this diode is charged. LEDs require very little power and are often used as indicator lights. Link (or circuit) is the physical connection of channels, conductors, and equipment between two given signaling points through which electrical current can be established. A link has both sending and receiving capabilities.
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Glossary
M
Term Mbps MTP Definition
Megabits Per Second is a unit measure of data transmission speed (one million bits per second). Message Transfer Part is a component of the SS7 protocol stack that provides SS7 routing and is divided into three levels: Message Transfer Part Level 1 (MTP1), MTP2, MTP3, and MTP4. Message Transfer Part Level 1 is a protocol layer that defines the physical, electrical, and functional characteristics of the digital signaling link. Physical interfaces defined include E-1 (2048 kbps; 32 64 kbps channels), DS-1 (1544 kbps; 24 64kbps channels), DS-0 (64 kbps), and DS-0A (56 kbps). Message Transfer Part Level 2 is a protocol layer that provides end-to-end transmission of a message across a signaling link. Level 2 implements flow control, message sequence validation, and error checking. When an error occurs on a signaling link, the message(s) is retransmitted. Message Transfer Part Level 3 is a protocol layer that provides message routing between signaling points in the SS7 network. MTP Level 3 reroutes traffic away from failed links and signaling points and controls traffic when congestion occurs.
MTP1
MTP2
MTP3
N
Term NEBS Definition
Network Equipment Building System is a standard issued by Telcordia (formerly Bellcore) that defines central office standards for grounding and cabling, power and operations interfaces, and techniques for surviving fire and earthquake. Network is a group of interconnected computers that can exchange information. These computers can be connected at the same physical location (LAN) or at different locations connected by modem, telephone lines, or other form of long distance communication method. Node is a point of communication on a data network and refers to a specific interface or address on a specific host.
network node
O
Term OEM Definition
Original Equipment Manufacturer
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Glossary
P
Term packet path Definition
Packet is a logical grouping of information that includes a header. This header contains control information and (usually) user data. Packets most often are used to refer to network layer units of data. Path is the route data travels through a network. Paths are usually characterized by their speed, latency, the number of hops and the rate of packet loss. Peripheral Component Interconnect is an interface used on computer backplanes to connect interface cards and peripheral devices to the processor bus. PCI is typically used for video display cards, network interfaces such as Ethernet, and peripheral interfaces such as Small Computer System Interface (SCSI) or universal serial bus (SB). PCI Industrial Computer Manufacturers Group 2.16 is a specification that overlays a packet-based switching architecture on top of CompactPCI, enabling an Ethernet-based dual-star topology to exist within the CompactPCI chassis. PCI Mezzanine Board is a board adapted to VME bus, CompactPCI and PCI cards. Small and compact (74 mm x 149 mm) and providing 32- or 64-bit data paths, PMC cards enable a large variety of PCI products to be retrofitted to other bus environments. Protocol is a set of communication rules that govern the format of sending and receiving data.
PCI
PICMG 2.16
PMC protocol
R
Term router Definition
Router is a device or a piece of software that connects two or more networks. A router functions as a sorter and interpreter as it looks at addresses and passes bits of information to their proper destinations. Software routers are sometimes referred to as gateways.
S
Term SCCP SI signaling SS7 Definition
Signaling Connection Control Part is a signaling protocol that provides connectionless and connection-oriented network services above MTP3. Signaling Indicator shows the level of service relevant to a particular message. Valid options are: ISUP or SCCP. Signaling is the exchange of information in a network for call setup, control, and termination. Signaling System 7, defined by the ITU-T, provides a suite of protocols that enables circuit and non-circuit related information to be routed about and between networks.
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Glossary
Term subnetwork switch
Definition (Continued)
Subnetwork or subnet is the part of a network that shares a common address component. These networks are segmented to provide a hierarchical routing structure while shielding the subnetwork form the addressing complexities of the attached networks. Switch is a device that connects segmented elements within a LAN.
T
Term T1 Definition
T1 is a 1.544 Mbps point-to-point dedicated, digital circuit provided by the North American telephone companies. T1supports 24 channels. See E1 and J1 for European and Japanese counterparts, respectively. Transmission Control Protocol is a protocol that enables two hosts to establish a connection and exchange streams of data. TCP guarantees delivery of data and also guarantees that packets will be delivered in the same order in which they were sent. Transmission Control Protocol over Internet Protocol is a set of rules that establish the method for transmitting data between two computers over the Internet. Telecommunication is long distance communication using systems that transmit messages electronically (radio, satellite, Internet, and others).
TCP
TCP/IP telecommunication
U
Term UDP/IP Definition
User Datagram Protocol is a rudimentary transport protocol built on top of IP. UDP adds the functionality of port numbers to distinguish between different applications on the same host. All systems that support TCP/IP also support UDP/IP.
V
Term Definition
Voice over Internet Protocol is a term used in IP telephony for a set of facilities for managing the delivery of voice information using the IP. This means sending voice information in digital form in discrete packets rather than in the traditional circuit-committed protocols of the public switched telephone network (PSTN). A major advantage of VoIP and Internet telephony is that it avoids the tolls charged by ordinary telephone service.
VoIP
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Glossary
W
Term WAN Definition
Wide-Area Network is a network that connects computers over long distances using telephone lines or satellite links. In a WAN, the computers are physically and sometimes geographically far apart.
95
Glossary
96
Index
Numerics
9 pin d subminiature connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
clock monitors external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 clock operating modes H.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 clock sources internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 communication processor interrupt . . . . . . . . . . . . . . . . . . . . 35 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 connector pinout 9 pin d subminiature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 controller H.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CT clock and frame monitor circuits . . . . . . . . . . . . . . . . . . . . . 45 netreference sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Customer Support and Services . . . . . . . . . . . . . . . . . . . . . . . 15
A
air flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 application flash information general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 application flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 42, 43 architectural block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .30 ATM cell functions receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 ATM channel allocations . . . . . . . . . . . . . . . . . . . . . . . . . 55, 56 ATM TC layer block diagram MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
B
block diagram architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 board configuration header . . . . . . . . . . . . . . . . . . . . . . . . . . .73 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 board operation H.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 boot flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 bus and digital switch H.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
D
daughter board call out definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 daughter board component layout . . . . . . . . . . . . . . . . . . . . . 22 daughter board interface connector (j1) . . . . . . . . . . . . . . . . . 74 digital switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 digital switch local TDM streams connection . . . . . . . . . . . . . . . . . . . . . . . 50, 51 DPLLl H.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DPLLl operating specifications H.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
C
chip select assignments MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 clock and frame monitor circuits CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
E
E1/T1/J1 quad framer and line interface unit (LIU) . . . . . . . . . 52 environmental requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 77 external
97
Index
clock monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 reference clock source monitor . . . . . . . . . . . . . . . . . . . . . .46
L
logic reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 logic, types of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
F
flash information general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 frame aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 frame aligner features, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 front cover plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M
main board component layout . . . . . . . . . . . . . . . . . . . . . 20, 70 call out definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 70 main board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 master/slave PCM expansion connector pin assignments . . . 72 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 mezzanine p2 PCM expansion connector . . . . . . . . . . . . . . . . . . . . . . 72 mezzanine board PCE385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 modular jack pin assignments . . . . . . . . . . . . . . . . . . . . . . . . 74 monitors internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MPC8280 ATM TC layer block diagram . . . . . . . . . . . . . . . . . . . . . . . chip select assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . parallel port pin assignments . . . . . . . . . . . . . . . . . . . . . . . port a pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . port b pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . port c pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . port d pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 34 60 60 62 64 66
G
general application flash information . . . . . . . . . . . . . . . . . . . . . . . .43 flash information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
H
H.100 board operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 bus and digital switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 clock operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DPLLl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DPLLl operating specifications . . . . . . . . . . . . . . . . . . . . . . .44 H.100 compatible board operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 header pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 host processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MT90866 digital switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I
insertion diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 interaction block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 interface JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 PCI express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 internal reference clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
N
netreference sources CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
O
on-board reset priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 operation on the H.100 compatible board . . . . . . . . . . . . . . . . . . . . . 20 overview diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PCE385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 operation overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 overview diagram operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
J
j1 connector pinout daughter board interface . . . . . . . . . . . . . . . . . . . . . . . . . . .74 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 71 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 testing port support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 JTAG/BDM debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
P
p2 PCM expansion connector mezzanine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 parallel port pin assignments MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PCE385 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 daughter board call out definitions . . . . . . . . . . . . . . . . . . . 22
98
Index
front cover plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 insertion diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 interaction block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .30 main board component layout call out definitions . . . . . . . . . . . . . . . . . . . . . . . . 20, 70 main board components . . . . . . . . . . . . . . . . . . . . . . . . . . .31 mezzanine board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PCI express interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PCI express connections PEX8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PCI express interface resets PEX8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PCI6466 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PCIe x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 peripheral resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 34 PEX8111 PCI express connections . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PCI express interface resets . . . . . . . . . . . . . . . . . . . . . . . .33 pinout JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 71 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 port a pin assignments MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 port b pin assignments MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 port c pin assignments MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 port d pin assignments MPC8280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 priorities reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 processing on the H.100 compatible board . . . . . . . . . . . . . . . . . . . . . .20 on the host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Product Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 requirements power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic, types of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI6466 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, PEX8111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . soft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 32 32 33 34 33 32 32 33
S
SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 slots PCI express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 sources communication processor interrupt . . . . . . . . . . . . . . . . . . 35 support JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
T
TDM clock distribution and control . . . . . . . . . . . . . . . . . . . . . 43 TDM streams connection digital switch local . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 51 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 testing port support JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 text conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 transmit utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 types of PCI and PCI express slots . . . . . . . . . . . . . . . . . . . . 24
U
unpacking the system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 utopia interface receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Q
quad framer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .50
W
Warranty, Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
R
receive ATM cell functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 reference clock source monitor external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
99
Index
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Document Revision History Part Number

Chapter 1: About This Guide

Unpacking the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Installing the PCE385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Chapter 4: Development Environment

Chapter 5: ATM Channel Allocations

Daughter Board Interface Connector (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 8: Data Sheets and Agency Approvals

Chapter 9: Product Safety

Chapter 1: About This Guide

$ARCH <> ALL CAPITALS

Customer Support and Services

Customer Support and Services

SS7 Systems (Includes SEGway)

Customer Support Packages

Other Web Support

Return Merchandise Authorization (RMA)

Chapter 1: About This Guide

Figure 2-1: Operational Overview Diagram

RJ-48 T1/E1/J1 LIU/Framer

H.110 Bus through Cable

Other H.100-Compatible Card

Power PC Processor DMA

PCI to PCI Express Bridge

RJ-48 Board SDRAM Host PC

Processing on the PCE385 Board

Output Data Type / Description

Output Data Type / Description

Processing on the Host

Output Data Type / Description

Processing on the H.100-Compatible Board

Output Data Type / Description

PCE385 Board Layout

Main Board Component Layout

PCE385 Board Layout

Figure 2-2: PCE385 Main Board Component Layout

Daughter Board Component Layout

Figure 2-3: PCE385 Daughter Board Component Layout

PCE385 Board Layout

Front Cover Plate

Console Port Connection

PCI Express Slots

PCIe Slot Details

Unpacking the System

Installing the PCE385

Installing the PCE385

Figure 3-1: PCE385 Insertion Diagram

Topics in this chapter include:

Chapter 4: Development Environment

PCE385 Architectural Overview

QUAD RJ48C for T1/E1/J1 On Front Panel

T1-1 to T1-4 Part of Micro-DB9 Connector

Ext LVDS Pair

Clock Mux Logic

Termination and Line Fault Protection

1.544 MHz Precision Clock Source

ZARLINK MT90866 H.100 Switch

Payload Data 192/256 192/256 T1/E1/J1 Quad LIU and Framer

/8 Board Mount Status LED