Safety Seminar Silkeborg Day-1 2012
Safety Seminar Silkeborg Day-1 2012
Safety Seminar Silkeborg Day-1 2012
Agenda Day 1
Introduction in Functional Safety Systematic and Random Failures Hazard and Risk Analysis IEC EN 61508 ISO 26262 Hercules (TMS570, RM4x and TMS470M) Overview Hercules Safety Concept and Peripherals Development Kits, SW Tools Safety Critical Motor Control Example
Agenda Day 2
TMS570 Introduction and Roadmap Development Tools: Hardware kits, Software tools Safety Overview and Modules TMS570LS Architecture: Memory Map, Clocking, Exceptions Embedded Flash Memory tools: nowECC, nowFlash, API
Demo:TMS570 Safety MCU Demos
Real Time Interrupt (RTI) Vectored Interrupt Manager (VIM) Direct Memory Access (DMA) General-purpose I/O (GIO) Programmable Timer Unit with Transfer Unit (NHET/HTU)
Demo: Using NHET as GIO
Multi-Buffered Serial Peripheral Interface (MibSPI) Controller Area Network (DCAN) FlexRay Interface with Transfer Unit (ERAY/FTU) Local Interconnect Network (LIN) / Serial Communication Interface (SCI)
Demo: PC to SCI Communication
External Memory Interface (EMIF) / Parameter Overlay (POM) Multi-buffered Analog-to-Digital Converter (MibADC) Support Structure: Web, Forum, WIKI
3
Motivation
Safety Concerns
Space Shuttle Challenger disaster (1986)
Space Shuttle broke apart (deaths of 7 crew members) Unqualified O-ring seal No victims (unmanned flight), but loss of over 370 million $ SW design error (protection of integer overflow)
Safety Standards
EN 50128 EN 50129
(railway)
DO-178B
(aerospace)
DO-254
(medical equipment)
IEC 60601
Hercules MCU
TM
(furnaces)
IEC 50156
(process industry)
IEC 61511
IEC 60880
(nuclear power stations)
IEC 61508
(safety)
ISO 26262
(automotive)
What is a System?
Environment System
+
Output Circuit Sensor Input Circuit Logic Solver
Common Circuitry
Actuator
Final Element
PE Component
MCU HW MCU SW
E/E/PE Component
E/E/PE Component
10
Concept Design Prototype Release for Manufacturing Field Implementation Removal from Field Usage
11
Error
Discrepancy between expected and actual value.
Failure
Result of a fault which leads to an inability to execute safety critical functionality.
Fault
Error
Failure
12
Transient
Occur for a short time. Disappears automatically or by reset.
13
Random Failures
Result from random defects. Can not be reduced, must be detected and handled by Application. Hazard and risk analyses.
Systematic Failures
Result from a failure in design or manufacturing. Reducible through quality management. Often a result of failure to follow best practices.
14
Dependent Failures
Root Cause
Failure
Cascading Failures:
Fault Error Failure Fault Failure
Error
15
Dangerous
May cause a hazard.
Operational
Run in a degraded mode.
16
System
Sub-System
E/E/PE Component
E/E/PE Component
17
Availability
Probability that a device will perform its required function under stated conditions for a specific point of time.
18
TBF tU+1
MTBF Mean Time Between Failures MTTF Mean Time To Failure MTTR Mean Time To Restoration (Detect and repair time)
19
Failure Rate
The failure rate can be calculated as follows for a device with a constant failure rate
0.00000005 failures per hour x 8760 hours per year = 0.000438 failures per year
20
What is a Hazard?
Hazard
21
22
What is Risk?
Risk is a combination of
Frequency probability of hazardous event Consequence
Accident Hazardous Event1 Hazardous Eventn
Hazard
Risk = f x C
23
Qualitative Analysis
Qualitative Analyses
Use word like probable, frequent, unlikely, etc. to describe the likelihood of an hazardous event. Use words like minor, major, catastrophic, etc. to describe the severity of an hazardous event. Qualitative numbers are introduced on how to interpret these words.
E.g. Unlikely may be defined: once every 10 to 100 years Risk Graph FMEA
Analyze technics
24
Quantitative Analysis
Quantitative Analysis
Use numbers to describe the likelihood and severity of a hazardous event.
E.g. Likelihood of frequency hazardous event is: < 10-3 per year. E.g. Likelihood of potential loss of life is: < 10-5 per year
Analyze technics
26
27
Risk Graph
Decision tree in which a team considers some risk parameters to determine a safety integrity level. Remember: R = f x C
C may be considered as
Consequence risk parameter (C) Frequency and exposure time risk parameter (F) Possibility of failing to avoid hazard risk parameter (P) Probability of the unwanted occurrence (W)
f may be considered as
28
29
Risk Graph
W3
C1 P1 F1 C2 Start F2 P2 F1 C3 F2 C4 P2 P1
W2 1 2 3 4 5 6 7
W1 1 2 3 4 5 6 Requirement Classes
1 2 3 4 5 6 7 8
Risk
Necessary risk reduction
High
(Re-)Spec/(Re-)Design of function
Quality Management Maturity Processes and Methods SPICE, CMMI, ISO 9001,
31
Safety Functions
Additional functionality to avoid or control hazards. Separated from system to protect.
Accident Hazardous Event1 Hazardous Eventn
Hazard
Risk = f x C
32
Action:
Maximum time to react How to react
Hazardous Event
Time
Diagnostic Action
Hazard
33
Safety Integrity
34
Risk Graph
W3 1
P1 F1 C2 Start F2 P2 F1 C3 F2 C4 P2 P1
C1
W2 1 2 3 4 5 6 7
W1 1 2 3 4 5 6
SIL
No safety requirements No special safety requirements SIL 1 SIL 2 SIL 3 SIL 4 An E/E/PE SRS is not sufficient
2 3 4 5 6 7 8
36
37
FMEDA
FMEDA = FMEA extension to identify:
Online diagnostic techniques and Failure modes relevant to safety instrumented system design.
38
Actuator
Final Element
40
Airbag systems 32-bit main and 8-bit secondary MCU used to energize squib charges. +
Actuator
Final Element
41
Sensor
Input Circuit
Actuator
Final Element
42
A C
B C
Voting Circuit
Actuator
Final Element
43
Diagram
CHK CPU
Advantages
Relatively low cost Safety through diverse hardware
Disadvantages
SIL may be limited by processing capacity of simple checker micro Processing power limited by frequent on-line diagnostics Increased complexity for safety SW synchronization Additional cost, board space
Dual devices with external compare of safety outputs and optional SW message passing
Compare
CPU
CPU
SIL3 generally possible Can double performance for nonsafety critical tasks Simplicity of sourcing Potential for redundancy SIL3 generally possible Reduction in board space Reduced S/W complexity
CPU
Compare
CHK CPU
CPU 1 M
CPU 2
44
HFT = 1 (redundant)
2 or multiple faults needed to loss of safety function. 1oo2, 2oo3
45
IEC 61508
Distinguish between:
Systems with continues or high demand and Systems with low demand
47
Standard Documentation
Part 0: Overview of Functional Safety Part 1: General requirements. Part 2: Requirements for E/E/PE safety-related systems. Part 3: Software requirements Part 4: Definitions and abbreviations. Part 5: Examples of methods for the determination of SILs. Part 6: Guidelines on the application of part 2 and 3. Part 7: Overview of techniques and measures.
48
49
A s s e s s m e n t
D o c u m e n t a t i o n
M a n a g e m e n t
V e r i f i c a t i o n
E/E/PES safety requirement specification E/E/PES safety validation planning E/E/PES design and development E/E/PES integration E/E/PES safety validation E/E/PES operation and maintenance procedures
50
A s s e s s m e n t
D o c u m e n t a t i o n
M a n a g e m e n t
V e r i f i c a t i o n
SW safety requirement specification SW safety validation planning SW design and development PE integration (HW/SW) SW safety validation SW operation and modification procedures
51
52
53
Exercise SFF
= 20 FIT and
= 2000FIT
Improved System:
DU
= 10 FIT and
= 200FIT
Optimized System:
DU
= 10 FIT and
= 20FIT
54
Solution SFF
= 20 FIT and
= 2000 FIT
Improved System:
DU
= 10 FIT and
= 200 FIT
Optimized System:
DU
= 10 FIT and
= 20 FIT
55
56
Probability of Failure
Probability of failure due to random hardware failures must be quantified for each safety function. PFD Probability of Failure on Demand
Assumes low demand for safety function.
PFD depends on repair time and test interval.
57
2,6 * 103 0,087 * 103 0,044 * 103 0,0087 * 103 2,6 * 103 5, 34 * 103
PFDAvg_System
Actuator
Final Element
58
Exercise PFDAvg
59
Solution PFDAvg
60
ISO 26262
Adapted for common automotive lifecycle ISO 26262 has hazard and risk analysis, failure rates and metrics adapted for Automotive use cases. Work products are clearly defined
62
ISO 26262 categories of risk are Automotive Safety Integrity Levels ASILs.
ISO 26262 ASIL QM SIL 1 SIL 2 ASIL A ASIL B ASIL C SIL 3 SIL 4 ASIL D SIL 2 is not fully equivalent ASIL B SIL 2 Development requirements SIL 3 Verification requirements SIL 3 is not fully equivalent ASIL D Description
Hazard
Risk = S x (E * C)
Safety Goal1 Safety Goaln
64
Severity Classification
Class S0 S1 S2 S3 No injuries Light and moderate injuries Severe and life-threatening injuries (survival probable) Life-threatening injuries (survival uncertain), fatal injuries Description
65
66
Controllability Classification
Class C0 C1 C2 C3 Controllable in general Simply controllable Normally controllable Difficult to control or uncontrollable Description
67
ASIL Determination
C1 E1 S1 E2 E3 E4 E1 S2 E2 E3 E4 E1 S3 E2 E3 E4 QM QM QM QM QM QM QM ASIL A QM QM ASIL A ASIL B C2 QM QM QM ASIL A QM QM ASIL A ASIL B QM ASIL A ASIL B ASIL C C3 QM QM ASIL A ASIL B QM ASIL A ASIL B ASIL C ASIL A ASIL B ASIL C ASIL D
68
HW Failures Modes
Failure Modes of HW
Safety Related
Safe Fault
Safe Fault
69
70
Metrics
Metrics
71
Hercules Overview
What is Hercules?
Hercules Platform
TMS470M TMS570 RM4x
73
73
RM4x
RM4x
2MB, 192kB
RM4x
Transportation
TMS570
2*R4F LS 2MB, 160kB 160MHz
TMS570
TMS570
TMS570
1MB, 160kB
2MB, 192kB
TMS570
TMS470M
Value
TMS470M
TMS470M
TMS470M
Production
Sampling
Development
Lockstep CPUs
61508 SIL3
26262 support
74
75
TMS570LS31x
76
RM48x
77
78
CRC
ECLK
CRC
CMON DWWD
Self Test
IO Loopback
Timing Protection
Once a known safe region can be guaranteed, logic in this region can be used to provide diagnostic coverage on other regions.
80
Safe Island Hardware diagnostics (RED) Blended HW diagnostics (BLUE) Non Safety Critical Functions (BLACK)
Power, Clock, & Safety OSC PLL POR CRC PBIST/LBIST ESM RTI/DWWD
ARM CortexR4F
ARM
CortexCPU CoreR4F
Memory BIST on all RAMS allows fast memory test at startup On-Chip Clock and Voltage Monitoring Error Signaling Module w/ External Error Pin IO Loop Back, ADC Self Test, Dual ADC Cores with shared channels
Serial Interfaces
81
ARM Cortex-R4F
up to 220 MHz
Single / double precision IEEE 754 floating-point Floating point and integer instructions operate in parallel Superscalar, SIMD, 8 stage pipeline delivers 1.6 DMIPS/MHz Scalable ARM Based Solutions from TI: Stellaris, TMS470M, TMS570 & Sitara
Over 350 DMIPS of performance High performance floating point ARM-based: broad industry adoption
83
Compare Error
CCM
Self Test
Advantages to SW solution:
Faster fault detection. Better fault coverage. Little to no performance impact. Minimal memory impact. Easy to integrate in application. Proven, easy to justify diagnostic coverage.
Cortex R4
Spatial separation
Cycle Delay
Input + Control
Cortex R4
84
Advantages to SW solution:
Easy integration. Faster test execution. Proven, easy to justify diagnostic coverage. Better fault coverage. Minimal memory impact.
Clock controller
ROM
ROM interface
Clock cntrl
FSM
CPU_nRESET
Test controller
CPU1
DBIST CNTRL misr_in1 DBIST CNTRL
STC
PCR
VBUSP interface
CCM
misr_in2
CPU2
ESM
85
Errors
Error Handling
87
88
Peripheral
Master Core
Diagnostic Core
IRQ
NFIQ
ESM
VIM
89
Confidentiality
Availability
Removed from circulation after release to market due to availability of Safety Manual Available
NDA required
Safety Manual Safety Analysis Report Summary Detailed Safety Analysis Report Safety Case Report Safety Case Database
NDA required
Available
NDA required
In development
NDA required
In development
NDA required
In development
91
Early Development
$99
Control Card
$99
$199
TMS570 MDK
TMS470M HDK
TMS570 HDK
RM4x HDK
Evaluation
$79
$79
$79
$99
TMS570LS2x
TMS470M
TMS570LS3x
RM4x
Order: http://focus.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2836&familyId=1931&toolTypeId=1
93
More: http://focus.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2836&familyId=1931&toolTypeId=1
94
Safety Consulting
Safety Assessment
95
Download: http://focus.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2836&familyId=1931&toolTypeId=1
96
HALCoGen
HALCoGen
Hardware Abstraction Layer Code Generator
Download: http://focus.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2836&familyId=1931&toolTypeId=1
97
NHET - Simulator
Graphical Programming Environment Output Simulation Tool Generates CCS-ready SW modules Includes functional examples from TI
Graphical Waveform Viewer Input Generation Tool Seamless interface to coding tool Upgradable to Full SynaptiCAD
Algorithm Library Drag & Drop Instructions NHET ASM Code Waveform View Pin Selection NHET Registers
Download: http://focus.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2836&familyId=1931&toolTypeId=1
98
Support
Web Page:
Hercules: www.ti.com/hercules
Data sheets Technical reference manual Application notes Software & tools downloads and updates. Order evaluation and development Kits.
E2E Forums:
Hercules: http://www.ti.com/hercules-support
News and announcements. Useful links. Ask technical questions. Search for technical content.
WIKI:
Hercules: www.ti.com/hercules-wiki How to guides, intro videos and general information.
100
Answer Known ? NO YES Forward Question to World Wide Team World Wide Apps Team: -United States - Europe -India
Forum Guidelines: At least one person will monitor the forum at all times (work days) All questions posted in the forum will have a response in 24hrs or less
101
3-Day Training
102
6V asynch switch-mode pre-regulator, integrated current limit 4.5V to 36V Operating Range
3.3V9.5V Sensor Supply
Temp Prot.
Current Limit
5V Supply
5V linear regulator (internal FET) with temp protection and current limit Multiple supply rails to power the MCU, CAN/FlexRay, and external sensor Reset circuit for the MCU integrated in power supply Window or Q/A watchdog support
Multi-Rail Supply
TPS65381
Clock Monitor BIST Voltage Monitor CRC
Clock monitoring on internal oscillators Voltage monitoring on all Power Supplies and internal supply voltages
104
EPS Chipset
DRV3201/TPIC7312
105
107
Thank You
Who to contact
Frank Forster Josef Mieslinger Marcus Frech f-forster@ti.com +49 8161804270 TMS570 Marketing & SysApps j-mieslinger@ti.com +49 8161803077 TMS570 Marketing m-frech2@ti.com +49 8161803431 TMS570 SysApps
108