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Using the 24LC21 Dual Mode Serial EEPROM

Author: Bruce Negley Memory Products Division

TRANSMIT ONLY MODE (DDC1)

The 24LC21 will always power-up in the transmit only mode. In this mode, the 24LC21 will output one bit of data at the SDA pin for every rising edge on the VCLK pin. The data will be transmitted in 8-bit words, with each word followed by a 9th null bit. This null bit will always be high. A timing diagram for transmit only mode is shown in Figure 1. As long as VCLK is present and no falling edges on SCL are received, the 24LC21 will repeatedly cycle through the entire memory array.

INTRODUCTION
The Microchip Technology Inc. 24LC21 is a 1K-bit (128 x 8) dual mode serial EEPROM that was developed primarily for use in computer monitors. This part was developed with inputs from several computer monitor manufacturers, in accordance with the VESA (Video Electronics Standards Association) monitor committee. This committee has developed a serial communication protocol called Data Display Channel (DDC) which was created to eliminate the need to change dip switches when conguring a new system or adding a new monitor or video card. The 24LC21 device is used in the monitor to store and transmit the EDID (extended display ID) table which contains all set-up parameters needed by the video card to operate with a particular monitor. With this system, the user can now plug any compatible monitor into any compatible graphics board and the graphics board will automatically know what type of monitor is being used and congure itself accordingly. This automatic conguration is the cornerstone for Microsofts Plug and Play capability being built into the new Windows 95 release.

PACKAGE TYPE

NC NC NC VSS

1 2 3 4

5 6 7 8

VCC VCLK SCL SDA

DEVICE OPERATION
The 24LC21 can operate in two modes of operation. These two modes of operation are the transmit only mode and bi-directional mode. Upon power-up, the device will always be in the transmit-only mode. Transmit only mode is also referred to as DDC1 mode. The transmit only mode only allows the video card to read the contents of the 24LC21 in a sequential manner, one bit at a time. Writing to the device is not possible in transmit only mode. The device will automatically transition to the bi-directional mode whenever a falling edge is seen on the SCL pin. Bi-directional mode is also referred to as DDC2 mode, and is implemented as the standard I2C protocol. This allows a controller to read and write specic addresses in the device like a standard I2C Serial EEPROM device. Once the device has transitioned to the bi-directional mode, there is no way to return to transmit only mode other than to reset (power-down) the device.

Upon power-up, the device will not output valid data until it has been initialized. This initialization procedure (Figure 1) data will not be available until after the rst 9 clocks are sent to the device. The exact memory location that the 24LC21 begins to transmit data is unknown at power-up, and the initialization procedure only initializes the device, not the starting address or bit location. In order to for a controller to determine what address is being read, a framing or syncing procedure must be executed by the video card.

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A framing procedure involves looking for the header portion of the EDID table which is a byte of 00H followed by 6 bytes of FFH and another byte of 00H. A framing routine would continue to clock data from the 24LC21 until this unique header has been found. At this point, the current location in the EDID table has been determined and the controller has now synchronized itself with the device. Care must be taken while using the device in the transmit only mode to prevent noise on the SCL pin, as a falling edge seen on this pin will immediately send the part into the bi-directional mode. In a DDC1-only monitor, SCL is not connected to the VGA connector, but must still be terminated to VCC through a pullup resistor.

FIGURE 1:

TRANSMIT ONLY MODE

SCL
Bit8 (MSB)

SCL must remain high for transmit-only mode

SDA VCLK

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1 (LSB)

Null Bit

Bit8

Bit7

FIGURE 2:

DEVICE INITIALIZATION FOR TRANSMIT-ONLY MODE

VCC SCL
SDA at high impedance for 9 clock cycles Valid data begins on 10th clock
Bit8 Bit7 Bit6 Bit5 Bit4

SDA VCLK 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15

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BI-DIRECTIONAL MODE (DDC2)
Bi-directional mode is essentially the standard I C protocol and allows the controller to read and write to the device. The 24LC21 supports byte and page writes and byte and sequential reads in the bi-directional mode. This mode will be used primarily before the monitor leaves the factory to load the EDID table into the device, but it also provides a means of updating the table if necessary. It is also used for faster (up to 100 kHz) data transmission, or transmission of only specic requested data in a DDC2 system. (The I2C protocol allows the host to request data from a specic portion of the EDID table rather than waiting for the entire table.) When writing to the device, the VCLK pin must be held high while the write command is being loaded or the write will be aborted and no data will be written. Note that this is the opposite of the 24LC01B, where the WP pin must be held low for the device to be written.
2

EDID TABLE
The EDID table is the Extended Display ID table, specied by VESA, that will be stored in the 24LC21 and contains information about what type of display it is and the capabilities of the display. The basic EDID table consists of 128 bytes of data. A breakdown of the table is shown below in Table 1. A complete description of the table can be found in the VESA DDC Specication.

TABLE 1:
Bytes 8 10 2 15 19 72 1 1

EDID TABLE DESCRIPTION

Description Header Vendor/Product Description EDID Version/Revision Basic Display Parameters/Features Established/Standard Timings Detailed Timing Descriptions (18 bytes each) Extension Flag Checksum

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USING THE 24LC21 IN A SYSTEM
In order to use the 24LC21 in a monitor system, it must be programmed with a proper EDID table and then properly connected to the signals coming from the video controller card. The VESA committee has specied that the connections for DDC transmission can be part of the standard 15-pin VGA connector. A table of pinouts for this connector are shown in Table 2. Signals that pertain to the use of the 24LC21 are highlighted. Programming of the 24LC21 can be accomplished via Microchip Technologys SEEVAL programming and evaluation system or by any nal test system at the customer site which can communicate over the I2C bus.

TABLE 2:
Pin 1 2 3 4 5 6 7 8 9 10 11 12

VGA CONNECTOR DESCRIPTION

Standard VGA DDC1 Host Red Video Green Video Blue Video Monitor ID Bit2 Return Red Video Return Green Video Return Blue Video Return +5V Supply (optional) Sync Return Monitor ID Bit0 Data from Display (SDA) DDC2 Host Red Video Green Video Blue Video Monitor ID Bit2 Return Red Video Return Green Video Return Blue Video Return +5V Supply (optional) Sync Return Monitor ID Bit0 Bi-directional Data (SDA) DDC1.2 Display Red Video Green Video Blue Video Return Return Red Video Return Green Video Return Blue Video Return +5V Supply (optional) Sync Return Optional Bi-directional Data (SDA) Horizontal Sync Vertical Sync (VCLK) Data Clock (SCL)

Red Video Green Video Blue Video Monitor ID Bit2 Test (Ground) Red Video Return Green Video Return Blue Video Return No Connection Sync Return Monitor ID Bit0 Monitor ID Bit1

13 14 15

Horizontal Sync Vertical Sync Monitor ID Bit3

Horizontal Sync Vertical Sync (VCLK) Monitor ID Bit3

Horizontal Sync Vertical Sync Data Clock (SCL)

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SYSTEM CONFIGURATION
A typical system conguration is shown below. The DDC specication states that a 47 k pull-up resistor is required on the SDA line at the monitor end. It also states that a 15K pullup resistor is needed on both the SCL and SDA lines at the video controller end.

FIGURE 3:

USE OF 24LC21 IN VIDEO SYSTEM

Video Monitor System Video Controller Card 15K VGA Controller

VCC Pin 14 (VSYNC) 15K Pin 15 (SCL) Pin 12 (SDA) VCC 47K* 47K Monitor Controller Card

VCC SDA SCL 6

* 47 k resistor is recommended on SCL line at the monitor end although it is not required by the VESA specication.

VCLK

CRT 24LC21 1

GND

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POTENTIAL PROBLEMS CAUSED BY NOISE IN A VIDEO SYSTEM
Because the typical application for the 24LC21 is in a computer monitor where electronic noise is prevalent, some precautions may need to be made in order for this device (or any other CMOS device) to work properly. The diagram below (Figure 4) shows a lter circuit that can be used to reduce the amount of noise seen by the device on the SCL and VCLK pins.

FIGURE 4:

RECOMMENDED FILTER CIRCUIT FOR MONITOR APPLICATIONS

VCC

CBP

RS VCLK RPD CR1 CS 24LC21 RPU RS SCL CS SCL VSYNC

CBP = 1 F RS = 100 - 300 RPD = 4.7 k CS = 100 - 1000 pF RPU = 47 k

CBP RPD

Bypass capacitor Can be as a termination resistor on VGA cable. Also will discharge the series capacitor going to the MCU and horizontal/Vertical processor.

CS and RS on VCLK Acts as low pass lter to clean-up noise on VSYNC line CS and RS on SCL Acts as low pass lter to clean-up noise and dampen power transient spikes that may cause accidental mode switching from DDC1 to DDC2 RPU on SCL Keeps SCL pulled high, although a high enough value is used that the host will not power the 24LC21. Lets the 24LC21 reset when the monitor power is turned off Eliminates undershoot on VSYNC

CR1

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NOTES:

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All rights reserved. 1995, Microchip Technology Incorporated, USA.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

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1995 Microchip Technology Inc.