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    Spi Slave Uart I2c Master Gpio

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    Yuvaraja
    I2c Spi Master slave

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    Spi Slave Uart I2c Master Gpio

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    Yuvaraja
    311 views2 pages
    I2c Spi Master slave

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    Spi.slave.uart.i2c.master.gpio

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    © Attribution Non-Commercial (BY-NC)

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    I2c Spi Master slave

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    311 views2 pages

    Spi Slave Uart I2c Master Gpio

    Uploaded by

    Yuvaraja
    I2c Spi Master slave

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    NXP I2C master bridges SC18IS600/601 and SC18IM700

    Low-power bridges for SPI slave or UART to I2C master or GPIO


    These compact protocol converters create seamless, low-power, low-voltage interface connections, so they make it quick and easy to add I2C master and GPIO capability to any application that has an SPI bus or UART host interface. The result is increased design flexibility with reduced complexity and software overhead, and faster time-to-market.
    SC18IS600/601 features 4  2.4- to 3.6-V operation with 5-Vtolerant I/O pins 4  High-speed SPI bus slave up to 3 Mbps 4  Fast I2C-bus (up to 400 kbps) with multi-master capability 4  Up to four GPIO and two quasibidirectional I/O pins 4  96-byte transmit and receive buffers 4  Power-down mode with a wake-up pin 4  Active-low interrupt output 4  Industrial temperature range (-40 to +85 C) 4  16-pin TSSOP package SC18IM700 features 4  2.3- to 3.6-V operation with 5-Vtolerant I/O pins 4  UART host interface with baud rates up to 460.8 kbps 4  Fast I2C-bus (up to 400 kbps) with multi-master capability 4  Up to eight GPIO 4  16-byte transmit and receive FIFOs 4  8N1 RS-232 format 4  Sleep mode (power-down) with a wake-up pin 4  Industrial temperature range (-40 to +85 C) 4  16-pin TSSOP package These low-power bridge ICs simplify design and reduce system cost by making it easy to add devices to an application. They provide an I2C master interface control to the I2C bus without a remote host processor. They also provide access to GPIO, so its easy to expand the host system to support additional functions: 4  System monitoring 4  Diagnostics 4  LCD display control 4  Fan control 4  LED lighting/blinking 4  Button/keypad press detection 4  Status information 4  EEPROM data storage SC18IS600/601 The NXP I2C master bridges SC18IS600 and SC18IS601 let a host with a SPI bus communicate transparently with I2C-bus devices like LCD displays, temperature/voltage sensors, and EEPROM data storage. The I2C-bus controller has multi-master capability, so it can share the bus with a microcontroller or another

    I2C master. The high-speed SPI bus slave operates at up to 3 Mbps. Both devices support 2.4- to 3.6-V operation and offer up to four GPIO and two quasi-bidirectional I/O pins. The I/O pins are tolerant to 5 V. They have 96-byte on-chip transmit and receive buffers, use a wake-up pin to support power-down mode, and provide active-low interrupt output. It operates in the industrial temperature range and is available in a 16-pin TSSOP package. SC18IM700 The NXP I2C master bridge SC18IM700 lets a host with an RS-232 connection communicate with remote I2C devices such as temperature sensors, LCD displays, A/D converters, and smart card readers. The same RS-232 connection can also be used to let the host communicate with remote GPIO. The device supports 2.3- to 3.6-V operation and offers up to eight GPIO. The UART host interface delivers baud rates up to 460.8 kbps and the fast I2C-bus, which supports multi-master capability, operates up to 400 kbps. It has 16-byte on-chip transmit and receive FIFOs, supports the 8N1 RS232 format, and uses a wake-up pin to support sleep mode (power-down). It operates in the industrial temperature range and is available in a 16-pin TSSOP package. For more information, please visit: www.nxp.com/interface For technical support, please send questions to: interface.support@nxp.com

    GPIO0 CS RESET VSS MISO MOSI SDA SCL

    1 2 3 4 5 6 7 8

    16 IO5 15 WAKEUP/IO4 14 INT 13 GPIO3 12 VDD 11 SCLK 10 GPIO2 9 GPIO1

    GPIO0 GPIO1 RESET VSS GPIO2 GPIO3 SDA SCL

    1 2 3 4 5 6 7 8

    16 GPIO7 15 GPIO4 14 GPIO5 13 WAKEUP 12 VDD 11 GPIO6 10 TX 9 RX

    SC18IS600 / 601 pinout diagram

    SC18IM700 pinout diagram

    Smart card ASIC CPU FPGA MCU

    A/D D/A ASIC CPU FPGA MCU UART UART

    Smart card

    A/D D/A

    I2C

    LCD / LED SC18IS60x

    I2C

    SPI

    SPI

    Sensor SC18IM700 Status LED Fan control

    LCD / LED

    Sensor

    Status LED Fan control GPIO Reset signal Push button

    GPIO

    Reset signal Push button

    SC18IS600/601 usage scenario

    SC18IM700 usage scenario

    Feature summary
    Type number SPI speed UART speed I C bus
    2

    SC18IS600IPW 1 Mbps N/A 400 kHz 4 2 Internal TSSOP16 5.0 x 4.4 x 1.1 mm

    SC18IS601IPW 3 Mbps N/A 400 kHz 3 2 External TSSOP16 5.0 x 4.4 x 1.1 mm

    SC18IM700IPW N/A 460.8 kbps 400 kHz 8 0 Internal TSSOP16 5.0 x 4.4 x 1.1 mm

    Number of GPIO Quasi-bidirectional I/O Clock Package Dimensions

    www.nxp.com

    NXP Semiconductors is in the process of being established as a separate legal entity in various countries worldwide. This process will be finalized in the course of 2006. 2006 Koninklijke Philips Electronics N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Date of release: September 2006 Document order number: 9397 750 15674 Printed in the USA

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