IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO.

12, DECEMBER 2006 2765

An Analytical Fringe Capacitance Model for
Interconnects Using Conformal Mapping
Aditya Bansal, Student Member, IEEE, Bipul C. Paul, Senior Member, IEEE, and Kaushik Roy, Fellow, IEEE
AbstractAn analytical model is proposed to compute the
fringe capacitance between two nonoverlapping interconnects in
different layers using a conformal mapping technique. With this
technique, electric eld lines are geometrically approximated
to separately model the different capacitive components. These
components are nally combined to obtain the equivalent fringe
capacitance. Using the aforementioned technique, a model was
developed to compute the capacitances of typical interconnect
geometries using technology-dependent parameters. The proposed
model closely matches with FASTCAP results and signicantly
reduces the computational complexity and time in calculating the
interconnect capacitances.
Index TermsConfocal ellipses, conformal mapping, fringe
capacitance.
I. INTRODUCTION
T
HE ever-increasing demand for high performance requires
aggressive technology scaling and innovative designs.
This results in a less performance margin in integrated circuit
design. Hence, estimation of circuit performance and signal
integrity is necessary in the design phase to ensure proper
reliability. Interconnect capacitances are one of the major
contributors to performance degradation and signal integrity
problems in sub-100-nm circuits. Hence, an accurate modeling
of interconnect capacitances is necessary to predict circuit
performance before fabrication. Due to the complex geometry,
modeling interconnect capacitances is always a challenging
problem.
Fig. 1 shows a typical interconnect geometry in a custom
design layout [1]. Note that typically, interconnects in adja-
cent layers are orthogonal to each other, which is a special
case of the general conguration shown in Fig. 1, with the
top interconnect having a large width and small length. The
capacitance at any metal line or node consists of the following
three components:
1) overlap capacitance C
ov
due to the overlap between two
interconnects in different metal layers;
2) lateral capacitance C
lat
between two intralayer
interconnects;
Manuscript received July 11, 2005; revised November 30, 2005. This work
was supported in part by Semiconductor Research Corporation under Contract
1078 and in part by IBM. This paper was recommended by Associate Editor
W. Schoenmaker.
A. Bansal and K. Roy are with the School of Electrical and Computer
Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail:
bansal@ecn.purdue.edu; kaushik@ecn.purdue.edu).
B. C. Paul is with Toshiba America Research, San Jose, CA 95131 USA
(e-mail: bpaul@tari.toshiba.com).
Digital Object Identier 10.1109/TCAD.2006.882489
Fig. 1. Schematic of a typical interconnect structure.
3) fringe capacitance C
fr
between two interconnects in dif-
ferent metal layers; this fringe capacitance is between the
sidewall of one interconnect and the top (or bottom) of
another interconnect in a different layer.
With scaling, interconnect width W decreases every technology
generation. Consequently, interconnect thickness T is increased
to compensate the increase in resistance. This results in a
signicant increase in the lateral and fringe capacitances [2].
However, estimating the fringe capacitances of complex inter-
connect geometries is extremely difcult.
Several approaches have been used in the literature to model
the capacitances of such complex interconnect geometries.
Efcient numerical methods to compute the capacitances in-
clude the boundary-element method (BEM) [3][7], nite-
element method [8], nite-difference method [9], and some
semianalytical approaches [10], [11]. However, such ap-
proaches are computationally intensive, requiring large mem-
ory and CPU time. To reduce the computational complexity,
several numerically computed closed-form expressions for the
different capacitance components have also been proposed
[12][18]. In this approach, capacitance models for commonly
encountered interconnect geometries are numerically evaluated
and experimentally characterized [21], [22]. These capacitance
models are stored in a library that is coupled to the layout ex-
tractor. The capacitance matrix of a complete layout is extracted
by pattern matching to the precharacterized library patterns.
However, in case of mismatch, either the library is enhanced
by numerically computing the mismatched patterns or the ca-
pacitance is computed by relating to the closely matched pattern
[19], [20]. In order to accurately model all possible interconnect
geometries, the aforementioned approach needs to generate a
large number of library patterns. On the other hand, with a
limited number of patterns, the capacitance for all possible
geometries cannot be computed accurately. Only a geometry-
independent analytical model can reduce the computational
0278-0070/$20.00 2006 IEEE
2766 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006
Fig. 2. Capacitances between two metal lines in different layers.
complexity in computing different components of interconnect
capacitances. To the best of our knowledge, no such models
that can analytically compute the capacitance of multilayer
interconnects are reported in the literature.
In this paper, we propose analytical models to compute
the different capacitive components of a typical interconnect
geometry. These models are derived by analyzing the electro-
statics between interconnects and using technology-dependent
parameters. The major contribution of this paper includes the
following:
1) an accurate analytical model for fringe capacitance be-
tween two interconnects in different layers;
2) an analytical model to compute the capacitances of a
conventional multilayer interconnect structure;
3) our proposed model will signicantly reduce the number
of precharacterized patterns, and in case of mismatch,
it can be easily and accurately modied to compute the
effective capacitance.
The remainder of this paper is organized as follows. We
explain the fringe capacitance model in Section II. Section III
describes the model to compute the capacitance of a typical
interconnect geometry. In this section, we compare our model
with FASTCAP, which uses the BEM with multipole accelera-
tion [4], followed by conclusions in Section IV.
II. MODELING OF FRINGE CAPACITANCE
To formulate the multilevel capacitance model, rst, let us
consider the modeling of all the dominant capacitances between
two interconnects in different metal layers (Fig. 2). We will use
the following notations to describe our model:
H interlayer dielectric thickness;
W width of metal line;
T thickness of metal line;
S nonoverlap distance between two metal lines;

di
dielectric permittivity.
Fig. 2 shows the dominant capacitances between two
nonoverlapped interconnect lines in different layers. Initially,
we assume that these two interconnects are in isolation. All
these capacitances are conventionally grouped together and
called fringe capacitance C
fr
, which is given by
C
fr
= C
corner
+ (C
sw,top1
+C
sw,top2
)
+ (C
top,top1
+C
top,top2
) + (C
sw1,sw2
). (1)
Fig. 3. Electric eld lines between the two metal lines contributing to
C
sw,top
. Dashed lines show fringing electric eld between the corners.
Fig. 4. Electric eld lines contributing to C
top,top
.
Note that in case of overlapped interconnect lines, one more
capacitance (parallel-plate capacitance) will exist in place
of C
corner
. However, analytical expression used to calculate
parallel-plate capacitance is well known; therefore, we consider
nonoverlapped interconnects here.
Analytical expressions used to evaluate the capacitances are
formulated by geometrically modeling the electric eld lines
between the two interconnects. Fig. 3 shows the electric eld
lines between the sidewall of the top interconnect and the top
of the bottom interconnect that contribute to the capacitances
C
sw,top1
and C
corner
in Fig. 2. Note that the electric eld lines
between the sidewall of the bottom interconnect and the bottom
surface of the top interconnect, which contribute to C
sw,top2
,
can be shown in a similar way. The electric-eld lines are
divided into two groups, namely 1) normal to the surface and
2) fringing at the ends of the interconnects (in the ABCD
region). Normal electric-eld lines are shown by the solid lines
in the gure, and fringing eld is shown by the dashed lines.
Fig. 4 shows the electric-eld lines between the top sur-
faces of the two interconnects that contribute to capacitance
C
top,top1
. Note that the electric-eld lines between the bottom
surfaces, left sidewalls, and right sidewalls that contribute to
C
top,top2
, C
sw,sw2
, and C
sw,sw1
, respectively, can be shown in
a similar way.
We separately model the preceding capacitance components
and add them to obtain the overall fringe capacitance C
fr
.
A. Capacitance Between the Sidewall and Top (C
sw,top
)
The modeling approach for this capacitance component is
similar to the one we used to model gate sidewall fringe
capacitance in devices [23]. The problem can be formulated
as determining the electric eld and the potential in the rst
BANSAL et al.: ANALYTICAL FRINGE CAPACITANCE MODEL FOR INTERCONNECTS USING CONFORMAL MAPPING 2767
Fig. 5. (a) Electric eld lines represented by the rst quadrant of an elliptical
system. (b) Electric eld lines after transforming the nonconfocal elliptical
system to a confocal system.
quadrant of an elliptical system, as shown in Fig. 5(a). The
electric eld lines are represented by the boundaries of con-
centric ellipses. To calculate the capacitance, we map these
perpendicular surfaces to an equivalent parallel-plate system
using conformal mapping [24]. This can be done if and only
if the elliptical system is confocal. The elliptical system shown
in the gure, however, may not necessarily be a confocal
system. Hence, we rst transform the elliptical system into an
equivalent confocal one with
f =
_
S
2
H
2
, if S > H

H
2
S
2
, if H > S
(2)
which is the focus of the innermost ellipse. Note that if S = H,
the system transforms to an equivalent concentric circular sys-
tem. The outermost ellipse of the equivalent confocal elliptical
system is represented by
x
2
(S +W

)
2
+
y
2
(H +T

)
2
= 1 (3)
as shown in Fig. 5(b). T

and W

are the equivalent metal-line

thickness and width of the transformed confocal elliptical sys-
tem, respectively. Note that W

can be determined by equating

the foci of the innermost and the outermost ellipses and can be
expressed as
W

=
_
S
2
+T
2
+ 2HT

S. (4)
The electric-eld lines in the transformed system are rep-
resented by the confocal ellipses, and the electric potential
contours are represented by the confocal hyperbolas (Fig. 6).
The system can now be mapped to an equivalent parallel-plate
system (inset of Fig. 6) by transforming the xy coordinates to
uv coordinates as follows:
u +jv = F(x +jy). (5)
Fig. 6. Electric eld lines and equipotential lines in the z plane and after
transforming to the w plane.
From [24], we nd that F = cos
1
is a suitable function to
map elliptical geometry to linear geometry, which provides
x =fcos ucosh v (6)
y = fsinusinhv (7)
where f = (S
2
H
2
)
1/2
is the focus of the confocal elliptical
system. Solving (6) and (7), we get
v =sinh
1
_
x
2
+y
2
1
_
(x
2
+y
2
1)
2
+4y
2
2
_
1/2
(8)
u=cos
1
_
x
2
+y
2
+1
_
(x
2
+y
2
+1)
2
4x
2
2
_
1/2
. (9)
In the uv coordinate system, the capacitance per unit length
is given by
C =
di
v
5
v
1
u
5
u
1
=
di
distance(A, B)
distance(C, D)
(10)
where
di
is the permittivity of the dielectric between the sur-
faces. v
1
corresponds to the inner ellipse and can be computed
by substituting x = S/f and y = 0 in (8), while v
5
corresponds
to the outermost ellipse and can be computed by substituting
x = (S +W

)/f and y = 0. v
1
and v
5
are given by
v
1
= sinh
1
_
S
f
_
1/2
, v
5
= sinh
1
_
S +W

f
_
1/2
.
Similarly, u
1
and u
5
can be computed from (9) and are
given by
u
1
= 0 u
5
=

2
.
Substituting v
1
, v
5
, u
1
, and u
5
in (10), we get
C
sw,top
=

di
/2
ln
_
H +T

+
_
S
2
+T
2
+ 2HT

]
S +H
_
. (11)
2768 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006
Fig. 7. Error in approximating the nonconfocal elliptical system to a confocal
elliptical system with T

= T.
Fig. 8. Percentage error in capacitance estimation assuming T

= T.
The preceding model accurately estimates the capacitance
between the two surfaces, provided that an appropriate value of
T

is known. We represent T

= T, where is an empirical pa-

rameter. = 1 if the original system is confocal. To understand
the dependence of on the device geometry, let us consider the
example shown in Fig. 7. In this example, if we construct the
confocal elliptical system with T

= T, then the electric ux in

the shaded region is not included in the estimation. Fig. 8 shows
the percentage error introduced for different geometries. It can
be observed that the percentage error initially increases sharply
with increase in W from W

(W

corresponds to the confocal

system with T

= T) and then saturates. This is because the

electric ux decreases logarithmically with distance. Based on
this analysis, we empirically represent as
=exp
_
W W

|
T

=T
W
_
=exp
_
W +S

S
2
+T
2
+ 2HT
W
_
(12)
where is a tting parameter and is independent of geometry.
is determined by matching the preceding model with the
simulation results and is found to be 3.7.
Note that the system reduces to a concentric circular system
if S = H and W = T and the model simplies to the equation
given in [25].
Fig. 9. (a) Electric eld lines contributing to C
pi
and C
par
. (b) Circuit model
showing C
pi
and C
par
in series.
Fig. 10. Radial geometry in z plane is mapped to linear geometry in the
w plane to calculate C
pi
.
B. Capacitance Between the Top of Two Metal Lines (C
top,top
Analogous to C
sw,sw
)
Capacitance between the top of two metal lines C
top,top
is modeled by using conformal mapping in a similar way
as explained in the previous subsection. Fig. 9(a) shows the
electric-eld lines that contribute to C
top,top
. The equivalent
capacitance model is shown in Fig. 9(b). Capacitance C
par
is
the parallel-plate capacitance between the top surface of metal
2 (AB) and a horizontal ctitious plane [shown as line CD in
Fig. 9(b)] and is given by
C
par
=
di
W
H +T
. (13)
Capacitance C
pi
, due to radial eld, is modeled by conformal
mapping. The coordinate-transformation technique explained
in the previous section is applied to map the circular geometry
into the equivalent linear geometry, as shown in Fig. 10. A
suitable function for such mapping can be expressed as [26]
u +jv = ln(x +jy)
x +jy =re
j
. (14)
Solving the preceding equations, we get
u =
1
2
ln(x
2
+y
2
)
v = tan
1
y
x
. (15)
BANSAL et al.: ANALYTICAL FRINGE CAPACITANCE MODEL FOR INTERCONNECTS USING CONFORMAL MAPPING 2769
Using the preceding transformation, the radial electric eld
(Fig. 10) in the z plane is mapped into a linear electric eld in
the w plane. In the w plane, the capacitance per unit length is
then given by
C
pi
=
di
distance(C, D)
distance(G, D)
. (16)
Substituting the coordinates of the three points D, C, and G
in (16), we get
C
pi
=

di

ln
_
1 +
2W
S
_
. (17)
Finally, the expression for capacitance C
top,top
(Series
[C
par
, C
pi
]) is derived as
C
top,top
=
di
W ln
_
1 +
2W
S
_
W + (H +T) ln
_
1 +
2W
S
_. (18)
The preceding analytical expression accounts for the
capacitance due to electric-eld lines encompassed in the
ABCEFGHD region, as shown in Fig. 9(a). Note that it does not
include the electric eld lines in the semicircular region GDH
(shown with the dotted lines in the gure). The capacitance
contributed by these eld lines is approximated as
C
(GDH)
=

di

exp
_
(T +S)
3S
_
. (19)
This capacitance is in parallel with C
pi
. Note that for S = 0,
i.e., in case of overlap between two lines, the preceding capaci-
tance is zero.
Further note that a part of the electric-eld lines in the ABCD
region are already included in the earlier derived capacitance
C
sw,top
. Therefore, calculating C
par
in isolation using (13) will
result in overestimation of the total capacitance. Therefore, we
modify (13) using an empirical geometry-dependent factor as
follows:
C
par
=
di
W
H +T
exp
_

H +T
S +W
_
. (20)
The added exponential factor accounts for the exponential
decrease in C
par
with increase in H +T or decrease in S +W.
As can be intuitively seen in Fig. 3, for extremely high S +W
and/or very low H +T, the electric eld in the ABCD region
due to the sidewall of metal 1 and the top of metal 2 decreases;
hence, the introduced factor exp((H +T)/(S +W)) in
C
par
approaches unity.
Combining (17), (19), and (20), the nal expression for
C
top,top
can be obtained as
C
top,top
=Series(C
par
,
_
C
pi
+C
(GDH)
)
_
C
top,top
=

di
W
_
ln
_
1 +
2W
S
_
+e
(
S+T
3S
)
_
W + (H +T)
_
ln
_
1 +
2W
S
_
+e
(
S+T
3S
)
_
(21)
where = exp[(H +T)/(S +W)].
The analytical expression for C
sw,sw
is analogous to C
top,top
and can be similarly expressed as
C
sw,sw
=

di
T
_
ln
_
1 +
2T
H
_
+e
(
H+W
3H
)
_
T + (S +W)
_
ln
_
1 +
2T
H
_
+e
(
H+W
3H
)
_
(22)
where = exp[(S +W)/(H +T)].
C. Capacitance Due to Corner Fringing Field (C
corner
)
Capacitance due to fringing eld C
corner
between the corners
of the two interconnects cannot be modeled in the same way
because the electric-eld lines are not elliptical. C
corner
is mod-
eled based on two characteristics: 1) it is inversely proportional
to distance d between the two corners given by
d =
_
H
2
+S
2
(23)
and 2) it depends on the area of connement. The fringing
electric eld is conned in the rst quarter of an ellipse, and
its area is represented as
Area
con
=

4
HS. (24)
Hence, C
corner
can be represented as follows:
C
corner
= k
di
f(Area
con
, d) (25)
where k is a constant. We found the best representation of
f(Area
con
, d) as
_
HS/(H
2
+S
2
) to make (25) dimension-
ally correct. The value of k is determined by comparing the
model with simulation results and is found to be 1/. The nal
expression of C
corner
can be written as
C
corner
=

di

_
HS
H
2
+S
2
. (26)
By adding C
sw,top
, C
corner
, C
top,top
, and C
sw,sw
, the overall
fringe capacitance C
fr
per unit length can be obtained as
C
fr
=2

di
/2
ln
_
H +T +
_
S
2
+ (T)
2
+ 2HT
S +H
_
+ 2

di
W
_
ln
_
1 +
2W
S
_
+e
(
S+T
3S
)
_
W + (H +T)
_
ln
_
1 +
2W
S
_
+e
(
S+T
3S
)
_
+ 2

di
T
_
ln
_
1 +
2T
H
_
+e
(
H+W
3H
)
_
T + (S +W)
_
ln
_
1 +
2T
H
_
+e
(
H+W
3H
)
_
+

di

_
HS
H
2
+S
2
(27)
2770 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006
Fig. 11. Comparison of the proposed model with FastCap simulation for
different geometries. (a) T
1
= 0.1 m. (b) T
2
= 0.2 m.
where
= exp[(W +S

S
2
+T
2
+ 2HT)/(W)];
= exp[(H +T)/(S +W)];
= exp[(S +W)/(H +T)].
Typically, H/T < 2, and S (the spacing between the two
interconnects in the same layer) can vary. We empirically tted
the parameters, , and in (27) for typical interconnect
distances for the geometry shown in Fig. 2. For empirical t-
ting, the chosen parameter ranges were - 50 nm < T < 300 nm,
0.5 < H/T < 4, and 0 < S < 500 nm.
To verify our proposed model, several test structures of
varying nonoverlapped geometries are created and simulated
using FASTCAP [4]. A typical structure is shown in Fig. 2. It
Fig. 12. Typical interconnect geometry in custom design layout.
can be seen that the dominant capacitance components between
the two metal lines are C
sw,top
, C
corner
, and C
top,top
.
Fig. 11(a) and (b) shows the fringe capacitances obtained for
different geometries using the proposed model and FASTCAP.
It can be observed that the proposed model closely matches
with the simulation results. The error is less than 4%, except for
S = 0. For S = 0, C
pi
[see (17)] is undened, which results in
an overestimation of capacitance.
III. INTERCONNECT CAPACITANCE
Consider a typical interconnect geometry shown in Fig. 12,
where interconnect thicknesses T
1
, T
2
, and T
3
and interlayer
dielectric thicknesses H
12
and H
13
are technology parameters
dened by process. The nonoverlap distances S
1
, S
2
, and
S
3
and metal widths W
1
, W
2
, and W
3
are design-dependent
parameters. The equivalent capacitance C
M21,self
from metal
M21 to ground (Fig. 12) can be represented as
C
M21,self
=C
M21,M1
+C
M21,M3
+C
M21,M22
C
M21,self
=C
M21,M1,fr
+C

M21,M1,fr
+C
M21,M3,fr
+C

M21,M3,fr
+C
M21,M22,lat
(28)
where C
M21,M1
, C
M21,M3
, and C
M21,M22
are the coupling
capacitances between M21 and M1, M21 and M3, and M21
and M22, respectively. C

M21,M1,fr
and C

M21,M3,fr
include the
C
sw,top
, C
corner
, C
top,top
, and C
sw,sw
capacitive components.
C
M21,M1,fr
and C
M21,M3,fr
include only C
sw,top
. C
M21,M22,lat
is the lateral capacitance between two interconnects in the
same layer.
Note that because of our modular approach of separately
modeling the different capacitive components and then calcu-
lating the total capacitance, our proposed model remains valid
for different widths and thicknesses for different layers. For
example, in Fig. 12, if T
1
= T
2
= T
3
and W
1
= W
2
= W
3
,
C
M21,M1,fr
, C
M21,M3,fr
, and C
M21,M22,lat
remain unchanged;
however, C

M21,M1,fr
and C

M21,M3,fr
are modied. Note that
C
corner
is the only component of C

M21,M1,fr
and C

M21,M3,fr
that is independent of T and W.
We use the capacitance model explained in the previous
section to solve the fringe capacitances. However, note that the
model developed for two isolated metal lines cannot be directly
used to solve the preceding problem. The eld lines originating
fromthe right sidewall of M21 will terminate partly on M3, M1,
and M22.
BANSAL et al.: ANALYTICAL FRINGE CAPACITANCE MODEL FOR INTERCONNECTS USING CONFORMAL MAPPING 2771
Fig. 13. Schematic of symmetric (S
1
= S
3
) and asymmetric (S
1
= S
3
)
interconnect geometry.
We solve this problem in two steps.
1) First, nd an analytical solution for capacitance for a
symmetric (S
1
= S
3
) geometry (Fig. 13).
2) Verify the preceding solution obtained with the bench-
mark interconnect geometry from the Predictive Technol-
ogy Model (PTM) [27].
3) Find an analytical solution for asymmetric geometry
(e.g., the structure shown in Fig. 13) using the preceding
solution.
A. Symmetric Geometry
Fig. 13 shows the schematic of a symmetric (S
1
= S
3
)
interconnect geometry. Since the electric ux that originates
from the right sidewall of M21 is distributed among M1, M3,
and M22, the capacitance C
M21,self
can be represented as
C
M21,self
=
0
(C
isolation
M21,M1,fr
+C
isolation
M21,M3,fr
) +
1
(C
isolation
M21,M22,lat
)
+ C

M21,M1,fr
+C

M21,M3,fr
(29)
where C
isolation
M21,M1,fr
and C
isolation
M21,M3,fr
are the normal components
of fringe capacitances between the right sidewall of M21 and
the top surfaces of M1 and between the right sidewall of M21
and the bottom surfaces of M3, respectively, and are obtained
in isolation using (11) and (12). Similarly, C
isolation
M21,M22,lat
is the
lateral capacitance between M21 and M22 in isolation and is
dominated by the parallel-plate capacitance between M21 and
M22 and the capacitance between the top (bottom) surfaces of
M21 and M22.
Note that C

M21,M1,fr
and C

M21,M3,fr
are not affected by
the presence of M22 and can be calculated as explained in
the previous section. Further note that due to the symmetric
structure (H
12
= H
23
= H and W
1
= W
3
= W), C
isolation
M21,M1,fr
and C

M21,M1,fr
are equal to C
isolation
M21,M3,fr
and C

M21,M3,fr
,
respectively. However, calculating the preceding components in
isolation will result in the overestimation of C
M21,self
for the
preceding geometry (Fig. 13).
0
and
1
in (30) are used as the
correction factors to account for the distribution of the electric
eld. We empirically found
0
to be best represented by

0
= exp
_
_

_
S
2
1
+ (H +
1
2
T)
2
+S
1
2S
2
+
1
5
_
_
. (30)
Fig. 14. Variation in (a) C
M21,M1
= C
M21,M3
and (b) C
M21,M22
with
lateral distances (S
2
) for different symmetrical geometries.
The preceding expression is empirically derived from the obser-
vation that
0
increases with increase in distance S
2
between
M21 and M22.
0
also decreases with increase in distance
between the bottom left edge of M3 and M21, which is given
by the expression under the roots. The expression has been
found to be true for the typical range of S
1
and S
2
distances
in very large scale integration (VLSI) circuits. It can be seen
from the preceding equation that as M22 moves away from
M21 (S
2
S
1
), the eld lines will effectively terminate on M1
and M3, making
0
insensitive to S
2
. Similarly, when M22 is
very close to M21 (S
2
S
1
), all the eld lines will effectively
terminate on M22, making
0
0.
The effective lateral capacitance (
1
C
isolation
M21,M22,lat
) depends
on S
2
, S
1
, and W. We track its dependence on these parameters
for different geometries and empirically found
1
as

1
= 2
0
. (31)
Fig. 14 compares our model with simulation results for
different symmetric geometries. It can be observed that
C
M21,M22,lat
[Fig. 14(b)] is inversely proportional to S
2
and
not very sensitive to S
1
(or S
3
). This conrms that (31) is
a good approximation and reduces the computational com-
plexity in calculating
1
signicantly. It can also be observed
2772 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006
Fig. 15. Benchmark interconnect structure from PTM.
Fig. 16. Comparison of the model with the simulation for typical interconnect
geometry parameters for 65- and 130-nm technologies.
from Fig. 14(a) that C
M21,M1
(C
M21,M3
) closely matches with
FASTCAP results. Hence, the proposed analytical model can
be used to estimate the interconnect capacitances for symmetric
geometries.
Note that all the tting parameters are technology dependent
and have to be obtained once, irrespective of interconnect
geometry.
B. Verication With Benchmark
In typical VLSI designs, interconnects in adjacent layers are
orthogonal to each other. We verify our model for the bench-
mark interconnect conguration given by PTM [27]. Fig. 15
shows a benchmark structure that shows line-to-ground and
line-to-line capacitances. The total capacitance of the metal line
M22 can be given as
C
total
= 2C
cpl
+ 2C
gnd
(32)
where C
cpl
is the coupling capacitance between two lines and
C
gnd
is the line-to-ground capacitance. We veried our model
for the interconnect-technology parameters for 65- and 130-nm
nodes. Fig. 16 shows the coupling and ground capacitances for
varying distance S between the adjacent metal lines.
C. General (Asymmetric) Structure
In a general interconnect structure, S
1
, S
2
, and S
3
are inde-
pendent of each other and can vary depending on the design.
In the previous section, we described the analytical model
Fig. 17. Variation in (a) C
M21,M1
, (b) C
M21,M3
, and (c) C
M21,M22
as the
asymmetry (S
3
> S
1
) increases for S
2
= 300 nm.
to calculate the capacitance of a symmetric structure. In this
subsection, we will use the preceding model to calculate the ca-
pacitance of a general interconnect structure. In order to do this,
BANSAL et al.: ANALYTICAL FRINGE CAPACITANCE MODEL FOR INTERCONNECTS USING CONFORMAL MAPPING 2773
we rst calculate the capacitance for the symmetric structure
using (30) with S
1
= S
min
= min(S
1
, S
3
). The asymmetry of
the structure can then be represented as |S
3
S
1
|, where S
3
=
S
max
= max(S
1
, S
3
). Fig. 17 shows the variation in C
M21,M1
,
C
M21,M3
, and C
M21,M22
as the asymmetry increases from
different symmetry points (S
1
= S
3
). The symmetry points
are marked on the plots. It can be observed from the gure
that C
M21,M1
remains almost constant as asymmetry increases
because a fraction of the electric elds terminating on M1
are largely dependent on S
1
and S
3
. However, capacitance
C
M21,M3
(C
M21,M22
) decreases (increases) parabolically from
the symmetry-point capacitance and can be given by
C
M21,M3
=C
M21,M3
|
symmetric
P
1
(s)
C
M21,M22
=C
M21,M22
|
symmetric
+P
2
(s) (33)
where C
M21,M3
|
symmetric
and C
M21,M22
|
symmetric
are the ca-
pacitances of the symmetric structure corresponding to the sym-
metry point and s = S
max
= max(S
1
, S
3
). P
1
(s) and P
2
(s)
are quadratic polynomials and can be obtained uniquely for
technology generation. They can be represented as
P
1
(s) =a
1
s
2
+b
1
s (34)
P
2
(s) =a
2
s
2
+b
2
s (35)
where a
1
, b
1
, a
2
, and b
2
are technology-dependent constants.
For a typical example, we chose TSMC 0.18 m and found
that a
1
= 2.23 10
5
, b
1
= 5 10
12
, a
2
= 1.05 10
4
,
and b
2
= 1.31 10
10
.
It is further observed that the proposed model is signi-
cantly faster than FASTCAP. Matlab was used to calculate
the capacitance matrix of the preceding geometries using our
model and was about 50X faster than FASTCAP on a 750-MHz
UltraSPARC-III with 2-GB memory.
Note that in our model, we only considered the interconnects
in neighboring layers and did not consider the interconnects
in other layers. We assumed that the interaction between the
interconnects in nonadjacent layers is negligible.
IV. CONCLUSION
In this paper, we developed an analytical fringe capacitance
model between two nonoverlapping interconnects that can be
effectively used to calculate the coupling capacitance between
any two interconnects. We also developed an analytical model
to compute the capacitances of typical multilayer interconnect
geometries. These models are derived by analyzing the electro-
statics between interconnects and using technology-dependent
parameters. The proposed model is expected to signicantly
reduce the computational complexity in calculating the in-
terconnect capacitances and can be effectively used in any
interconnect capacitance extraction tool.
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2774 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006
Aditya Bansal (S01) received the B.Tech. degree
in electrical engineering from the Institute of Tech-
nology, Banaras Hindu University, Varanasi, India, in
2001 and the M.S. degree in electrical and computer
engineering from Purdue University, West Lafayette,
IN, in 2003. He is currently working toward the
Ph.D. degree in electrical and computer engineering
at Purdue University.
He is currently working on exploring low-power
and high-performance design issues in nanoscale
bulk CMOS and double-gate MOSFET technologies,
and circuit-based device design in the nanoscale regime.
Bipul C. Paul (S97M01SM05) received the
B.Tech. and M.Tech. degrees in radiophysics and
electronics from the University of Calcutta, Calcutta,
India, and the Ph.D. degree from Indian Institute of
Science (IISc), Bangalore, India.
After his graduation, he joined Alliance Semi-
conductor (India), where he worked on synchronous
dynamic RAM design. In 2000, he joined Purdue
University, West Lafayette, IN, as a Postdoctoral
Fellow, where he worked on low-power electronic
design of nanoscale circuits (both bulk and silicon-
on-insulator technologies), statistical design under process variation, and very
large scale integration testing, verication, and noise analysis. He has also
developed device and circuit optimization techniques for ultralow power dig-
ital subthreshold operation. He is currently with Toshiba America Research,
San Jose, CA, where he is working on postsilicon devices and technology,
and nanoarchitecture. He is also a Visiting Scientist at Stanford University,
Stanford, CA.
Dr. Paul was a recipient of the National Scholarship (India) in 1984, the
Senior Research Fellowship Award from CSIR, India, in 1995, and the Best
Thesis Award in 1999.
Kaushik Roy (S83M83SM95F02) received
the B.Tech. degree in electronics and electrical com-
munications engineering from the Indian Institute of
Technology, Kharagpur, India, and the Ph.D. degree
from the University of Illinois, Urbana-Champaign,
in 1990.
He was with the Semiconductor Process and De-
sign Center, Texas Instruments Incorporated, Dallas,
TX, where he worked on eld-programmable eld
array architecture development and low-power cir-
cuit design. He joined the electrical and computer
engineering faculty, Purdue University, West Lafayette, IN, in 1993, where
he is currently a Professor, the Roscoe H. George Professor of Electrical
and Computer Engineering and a Purdue University Faculty Scholar. He is
also the Chief Technical Advisor of Zenasis Inc., Campbell, CA. He was a
Research Visionary Board Member with Motorola Laboratories in 2002. He
has published more than 350 papers in refereed journals and conferences. He
is a coauthor of two books on Low Power CMOS VLSI Design (Hoboken,
NJ: Wiley, 2000; New York: McGraw-Hill, 2004) and holds eight patents. His
research interests include very large scale integration (VLSI) design/computer-
aided design for nanoscale silicon and nonsilicon technologies, low-power
electronics for portable computing and wireless communications, VLSI testing
and verication, and recongurable computing.
Dr. Roy was a recipient of the National Science Foundation Career Devel-
opment Award in 1995, the IBM Faculty Partnership Award, the ATT/Lucent
Foundation Award, the 2005 SRC Technical Excellence Award, the SRC
Inventors Award, and the Best Paper Awards at the 1997 International Test
Conference, the IEEE 2000 International Symposium on Quality of IC Design,
the 2003 IEEE Latin American Test Workshop, the 2003 IEEE Nano, the
2004 IEEE International Conference on Computer Design, and the 2005
IEEE Circuits and System Society Outstanding Young Author Award (Chris
Kim). He has been on the Editorial Board of the IEEE Design and Test of
Computers, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and the
IEEE TRANSACTIONS ON VLSI SYSTEMS. He was a Guest Editor for the
Special Issue on Low-Power VLSI in the IEEE Design and Test of Computers
(1994), the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000), and the
IEE ProceedingsComputers and Digital Techniques (July 2002).